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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / pinctrl / stm32 / pinctrl-stm32.c
bloba657cd829ce6a6dccf1d5f581de40376c0c3e018
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 2017
5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 *
7 * Heavily based on Mediatek's pinctrl driver
8 */
9 #include <linux/clk.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/hwspinlock.h>
12 #include <linux/io.h>
13 #include <linux/irq.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/of_irq.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinconf-generic.h>
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
26 #include <linux/platform_device.h>
27 #include <linux/regmap.h>
28 #include <linux/reset.h>
29 #include <linux/slab.h>
30
31 #include "../core.h"
32 #include "../pinconf.h"
33 #include "../pinctrl-utils.h"
34 #include "pinctrl-stm32.h"
35
36 #define STM32_GPIO_MODER 0x00
37 #define STM32_GPIO_TYPER 0x04
38 #define STM32_GPIO_SPEEDR 0x08
39 #define STM32_GPIO_PUPDR 0x0c
40 #define STM32_GPIO_IDR 0x10
41 #define STM32_GPIO_ODR 0x14
42 #define STM32_GPIO_BSRR 0x18
43 #define STM32_GPIO_LCKR 0x1c
44 #define STM32_GPIO_AFRL 0x20
45 #define STM32_GPIO_AFRH 0x24
46
47 /* custom bitfield to backup pin status */
48 #define STM32_GPIO_BKP_MODE_SHIFT 0
49 #define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0)
50 #define STM32_GPIO_BKP_ALT_SHIFT 2
51 #define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2)
52 #define STM32_GPIO_BKP_SPEED_SHIFT 6
53 #define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6)
54 #define STM32_GPIO_BKP_PUPD_SHIFT 8
55 #define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8)
56 #define STM32_GPIO_BKP_TYPE 10
57 #define STM32_GPIO_BKP_VAL 11
58
59 #define STM32_GPIO_PINS_PER_BANK 16
60 #define STM32_GPIO_IRQ_LINE 16
61
62 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
63
64 #define gpio_range_to_bank(chip) \
65 container_of(chip, struct stm32_gpio_bank, range)
66
67 #define HWSPINLOCK_TIMEOUT 5 /* msec */
68
69 static const char * const stm32_gpio_functions[] = {
70 "gpio", "af0", "af1",
71 "af2", "af3", "af4",
72 "af5", "af6", "af7",
73 "af8", "af9", "af10",
74 "af11", "af12", "af13",
75 "af14", "af15", "analog",
76 };
77
78 struct stm32_pinctrl_group {
79 const char *name;
80 unsigned long config;
81 unsigned pin;
82 };
83
84 struct stm32_gpio_bank {
85 void __iomem *base;
86 struct clk *clk;
87 spinlock_t lock;
88 struct gpio_chip gpio_chip;
89 struct pinctrl_gpio_range range;
90 struct fwnode_handle *fwnode;
91 struct irq_domain *domain;
92 u32 bank_nr;
93 u32 bank_ioport_nr;
94 u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
95 u8 irq_type[STM32_GPIO_PINS_PER_BANK];
96 };
97
98 struct stm32_pinctrl {
99 struct device *dev;
100 struct pinctrl_dev *pctl_dev;
101 struct pinctrl_desc pctl_desc;
102 struct stm32_pinctrl_group *groups;
103 unsigned ngroups;
104 const char **grp_names;
105 struct stm32_gpio_bank *banks;
106 unsigned nbanks;
107 const struct stm32_pinctrl_match_data *match_data;
108 struct irq_domain *domain;
109 struct regmap *regmap;
110 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
111 struct hwspinlock *hwlock;
112 struct stm32_desc_pin *pins;
113 u32 npins;
114 u32 pkg;
115 u16 irqmux_map;
116 spinlock_t irqmux_lock;
117 };
118
119 static inline int stm32_gpio_pin(int gpio)
120 {
121 return gpio % STM32_GPIO_PINS_PER_BANK;
122 }
123
124 static inline u32 stm32_gpio_get_mode(u32 function)
125 {
126 switch (function) {
127 case STM32_PIN_GPIO:
128 return 0;
129 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
130 return 2;
131 case STM32_PIN_ANALOG:
132 return 3;
133 }
134
135 return 0;
136 }
137
138 static inline u32 stm32_gpio_get_alt(u32 function)
139 {
140 switch (function) {
141 case STM32_PIN_GPIO:
142 return 0;
143 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
144 return function - 1;
145 case STM32_PIN_ANALOG:
146 return 0;
147 }
148
149 return 0;
150 }
151
152 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
153 u32 offset, u32 value)
154 {
155 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
156 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
157 }
158
159 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
160 u32 mode, u32 alt)
161 {
162 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
163 STM32_GPIO_BKP_ALT_MASK);
164 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
165 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
166 }
167
168 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
169 u32 drive)
170 {
171 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
172 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
173 }
174
175 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
176 u32 speed)
177 {
178 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
179 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
180 }
181
182 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
183 u32 bias)
184 {
185 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
186 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
187 }
188
189 /* GPIO functions */
190
191 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
192 unsigned offset, int value)
193 {
194 stm32_gpio_backup_value(bank, offset, value);
195
196 if (!value)
197 offset += STM32_GPIO_PINS_PER_BANK;
198
199 clk_enable(bank->clk);
200
201 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
202
203 clk_disable(bank->clk);
204 }
205
206 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
207 {
208 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
209 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
210 struct pinctrl_gpio_range *range;
211 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
212
213 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
214 if (!range) {
215 dev_err(pctl->dev, "pin %d not in range.\n", pin);
216 return -EINVAL;
217 }
218
219 return pinctrl_gpio_request(chip->base + offset);
220 }
221
222 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
223 {
224 pinctrl_gpio_free(chip->base + offset);
225 }
226
227 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
228 {
229 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
230 int ret;
231
232 clk_enable(bank->clk);
233
234 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
235
236 clk_disable(bank->clk);
237
238 return ret;
239 }
240
241 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
242 {
243 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
244
245 __stm32_gpio_set(bank, offset, value);
246 }
247
248 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
249 {
250 return pinctrl_gpio_direction_input(chip->base + offset);
251 }
252
253 static int stm32_gpio_direction_output(struct gpio_chip *chip,
254 unsigned offset, int value)
255 {
256 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
257
258 __stm32_gpio_set(bank, offset, value);
259 pinctrl_gpio_direction_output(chip->base + offset);
260
261 return 0;
262 }
263
264
265 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
266 {
267 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
268 struct irq_fwspec fwspec;
269
270 fwspec.fwnode = bank->fwnode;
271 fwspec.param_count = 2;
272 fwspec.param[0] = offset;
273 fwspec.param[1] = IRQ_TYPE_NONE;
274
275 return irq_create_fwspec_mapping(&fwspec);
276 }
277
278 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
279 {
280 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
281 int pin = stm32_gpio_pin(offset);
282 int ret;
283 u32 mode, alt;
284
285 stm32_pmx_get_mode(bank, pin, &mode, &alt);
286 if ((alt == 0) && (mode == 0))
287 ret = GPIO_LINE_DIRECTION_IN;
288 else if ((alt == 0) && (mode == 1))
289 ret = GPIO_LINE_DIRECTION_OUT;
290 else
291 ret = -EINVAL;
292
293 return ret;
294 }
295
296 static const struct gpio_chip stm32_gpio_template = {
297 .request = stm32_gpio_request,
298 .free = stm32_gpio_free,
299 .get = stm32_gpio_get,
300 .set = stm32_gpio_set,
301 .direction_input = stm32_gpio_direction_input,
302 .direction_output = stm32_gpio_direction_output,
303 .to_irq = stm32_gpio_to_irq,
304 .get_direction = stm32_gpio_get_direction,
305 };
306
307 static void stm32_gpio_irq_trigger(struct irq_data *d)
308 {
309 struct stm32_gpio_bank *bank = d->domain->host_data;
310 int level;
311
312 /* If level interrupt type then retrig */
313 level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);
314 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
315 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
316 irq_chip_retrigger_hierarchy(d);
317 }
318
319 static void stm32_gpio_irq_eoi(struct irq_data *d)
320 {
321 irq_chip_eoi_parent(d);
322 stm32_gpio_irq_trigger(d);
323 };
324
325 static int stm32_gpio_set_type(struct irq_data *d, unsigned int type)
326 {
327 struct stm32_gpio_bank *bank = d->domain->host_data;
328 u32 parent_type;
329
330 switch (type) {
331 case IRQ_TYPE_EDGE_RISING:
332 case IRQ_TYPE_EDGE_FALLING:
333 case IRQ_TYPE_EDGE_BOTH:
334 parent_type = type;
335 break;
336 case IRQ_TYPE_LEVEL_HIGH:
337 parent_type = IRQ_TYPE_EDGE_RISING;
338 break;
339 case IRQ_TYPE_LEVEL_LOW:
340 parent_type = IRQ_TYPE_EDGE_FALLING;
341 break;
342 default:
343 return -EINVAL;
344 }
345
346 bank->irq_type[d->hwirq] = type;
347
348 return irq_chip_set_type_parent(d, parent_type);
349 };
350
351 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
352 {
353 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
354 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
355 int ret;
356
357 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
358 if (ret)
359 return ret;
360
361 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
362 if (ret) {
363 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
364 irq_data->hwirq);
365 return ret;
366 }
367
368 return 0;
369 }
370
371 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
372 {
373 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
374
375 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
376 }
377
378 static void stm32_gpio_irq_unmask(struct irq_data *d)
379 {
380 irq_chip_unmask_parent(d);
381 stm32_gpio_irq_trigger(d);
382 }
383
384 static struct irq_chip stm32_gpio_irq_chip = {
385 .name = "stm32gpio",
386 .irq_eoi = stm32_gpio_irq_eoi,
387 .irq_ack = irq_chip_ack_parent,
388 .irq_mask = irq_chip_mask_parent,
389 .irq_unmask = stm32_gpio_irq_unmask,
390 .irq_set_type = stm32_gpio_set_type,
391 .irq_set_wake = irq_chip_set_wake_parent,
392 .irq_request_resources = stm32_gpio_irq_request_resources,
393 .irq_release_resources = stm32_gpio_irq_release_resources,
394 };
395
396 static int stm32_gpio_domain_translate(struct irq_domain *d,
397 struct irq_fwspec *fwspec,
398 unsigned long *hwirq,
399 unsigned int *type)
400 {
401 if ((fwspec->param_count != 2) ||
402 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
403 return -EINVAL;
404
405 *hwirq = fwspec->param[0];
406 *type = fwspec->param[1];
407 return 0;
408 }
409
410 static int stm32_gpio_domain_activate(struct irq_domain *d,
411 struct irq_data *irq_data, bool reserve)
412 {
413 struct stm32_gpio_bank *bank = d->host_data;
414 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
415 unsigned long flags;
416 int ret = 0;
417
418 /*
419 * gpio irq mux is shared between several banks, a lock has to be done
420 * to avoid overriding.
421 */
422 spin_lock_irqsave(&pctl->irqmux_lock, flags);
423 if (pctl->hwlock)
424 ret = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
425
426 if (ret) {
427 dev_err(pctl->dev, "Can't get hwspinlock\n");
428 goto unlock;
429 }
430
431 if (pctl->irqmux_map & BIT(irq_data->hwirq)) {
432 dev_err(pctl->dev, "irq line %ld already requested.\n",
433 irq_data->hwirq);
434 ret = -EBUSY;
435 if (pctl->hwlock)
436 hwspin_unlock(pctl->hwlock);
437 goto unlock;
438 } else {
439 pctl->irqmux_map |= BIT(irq_data->hwirq);
440 }
441
442 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
443
444 if (pctl->hwlock)
445 hwspin_unlock(pctl->hwlock);
446
447 unlock:
448 spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
449 return ret;
450 }
451
452 static void stm32_gpio_domain_deactivate(struct irq_domain *d,
453 struct irq_data *irq_data)
454 {
455 struct stm32_gpio_bank *bank = d->host_data;
456 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
457 unsigned long flags;
458
459 spin_lock_irqsave(&pctl->irqmux_lock, flags);
460 pctl->irqmux_map &= ~BIT(irq_data->hwirq);
461 spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
462 }
463
464 static int stm32_gpio_domain_alloc(struct irq_domain *d,
465 unsigned int virq,
466 unsigned int nr_irqs, void *data)
467 {
468 struct stm32_gpio_bank *bank = d->host_data;
469 struct irq_fwspec *fwspec = data;
470 struct irq_fwspec parent_fwspec;
471 irq_hw_number_t hwirq;
472
473 hwirq = fwspec->param[0];
474 parent_fwspec.fwnode = d->parent->fwnode;
475 parent_fwspec.param_count = 2;
476 parent_fwspec.param[0] = fwspec->param[0];
477 parent_fwspec.param[1] = fwspec->param[1];
478
479 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
480 bank);
481
482 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
483 }
484
485 static const struct irq_domain_ops stm32_gpio_domain_ops = {
486 .translate = stm32_gpio_domain_translate,
487 .alloc = stm32_gpio_domain_alloc,
488 .free = irq_domain_free_irqs_common,
489 .activate = stm32_gpio_domain_activate,
490 .deactivate = stm32_gpio_domain_deactivate,
491 };
492
493 /* Pinctrl functions */
494 static struct stm32_pinctrl_group *
495 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
496 {
497 int i;
498
499 for (i = 0; i < pctl->ngroups; i++) {
500 struct stm32_pinctrl_group *grp = pctl->groups + i;
501
502 if (grp->pin == pin)
503 return grp;
504 }
505
506 return NULL;
507 }
508
509 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
510 u32 pin_num, u32 fnum)
511 {
512 int i;
513
514 for (i = 0; i < pctl->npins; i++) {
515 const struct stm32_desc_pin *pin = pctl->pins + i;
516 const struct stm32_desc_function *func = pin->functions;
517
518 if (pin->pin.number != pin_num)
519 continue;
520
521 while (func && func->name) {
522 if (func->num == fnum)
523 return true;
524 func++;
525 }
526
527 break;
528 }
529
530 return false;
531 }
532
533 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
534 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
535 struct pinctrl_map **map, unsigned *reserved_maps,
536 unsigned *num_maps)
537 {
538 if (*num_maps == *reserved_maps)
539 return -ENOSPC;
540
541 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
542 (*map)[*num_maps].data.mux.group = grp->name;
543
544 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) {
545 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
546 fnum, pin);
547 return -EINVAL;
548 }
549
550 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
551 (*num_maps)++;
552
553 return 0;
554 }
555
556 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
557 struct device_node *node,
558 struct pinctrl_map **map,
559 unsigned *reserved_maps,
560 unsigned *num_maps)
561 {
562 struct stm32_pinctrl *pctl;
563 struct stm32_pinctrl_group *grp;
564 struct property *pins;
565 u32 pinfunc, pin, func;
566 unsigned long *configs;
567 unsigned int num_configs;
568 bool has_config = 0;
569 unsigned reserve = 0;
570 int num_pins, num_funcs, maps_per_pin, i, err = 0;
571
572 pctl = pinctrl_dev_get_drvdata(pctldev);
573
574 pins = of_find_property(node, "pinmux", NULL);
575 if (!pins) {
576 dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
577 node);
578 return -EINVAL;
579 }
580
581 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
582 &num_configs);
583 if (err)
584 return err;
585
586 if (num_configs)
587 has_config = 1;
588
589 num_pins = pins->length / sizeof(u32);
590 num_funcs = num_pins;
591 maps_per_pin = 0;
592 if (num_funcs)
593 maps_per_pin++;
594 if (has_config && num_pins >= 1)
595 maps_per_pin++;
596
597 if (!num_pins || !maps_per_pin) {
598 err = -EINVAL;
599 goto exit;
600 }
601
602 reserve = num_pins * maps_per_pin;
603
604 err = pinctrl_utils_reserve_map(pctldev, map,
605 reserved_maps, num_maps, reserve);
606 if (err)
607 goto exit;
608
609 for (i = 0; i < num_pins; i++) {
610 err = of_property_read_u32_index(node, "pinmux",
611 i, &pinfunc);
612 if (err)
613 goto exit;
614
615 pin = STM32_GET_PIN_NO(pinfunc);
616 func = STM32_GET_PIN_FUNC(pinfunc);
617
618 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
619 dev_err(pctl->dev, "invalid function.\n");
620 err = -EINVAL;
621 goto exit;
622 }
623
624 grp = stm32_pctrl_find_group_by_pin(pctl, pin);
625 if (!grp) {
626 dev_err(pctl->dev, "unable to match pin %d to group\n",
627 pin);
628 err = -EINVAL;
629 goto exit;
630 }
631
632 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
633 reserved_maps, num_maps);
634 if (err)
635 goto exit;
636
637 if (has_config) {
638 err = pinctrl_utils_add_map_configs(pctldev, map,
639 reserved_maps, num_maps, grp->name,
640 configs, num_configs,
641 PIN_MAP_TYPE_CONFIGS_GROUP);
642 if (err)
643 goto exit;
644 }
645 }
646
647 exit:
648 kfree(configs);
649 return err;
650 }
651
652 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
653 struct device_node *np_config,
654 struct pinctrl_map **map, unsigned *num_maps)
655 {
656 struct device_node *np;
657 unsigned reserved_maps;
658 int ret;
659
660 *map = NULL;
661 *num_maps = 0;
662 reserved_maps = 0;
663
664 for_each_child_of_node(np_config, np) {
665 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
666 &reserved_maps, num_maps);
667 if (ret < 0) {
668 pinctrl_utils_free_map(pctldev, *map, *num_maps);
669 of_node_put(np);
670 return ret;
671 }
672 }
673
674 return 0;
675 }
676
677 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
678 {
679 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
680
681 return pctl->ngroups;
682 }
683
684 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
685 unsigned group)
686 {
687 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
688
689 return pctl->groups[group].name;
690 }
691
692 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
693 unsigned group,
694 const unsigned **pins,
695 unsigned *num_pins)
696 {
697 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
698
699 *pins = (unsigned *)&pctl->groups[group].pin;
700 *num_pins = 1;
701
702 return 0;
703 }
704
705 static const struct pinctrl_ops stm32_pctrl_ops = {
706 .dt_node_to_map = stm32_pctrl_dt_node_to_map,
707 .dt_free_map = pinctrl_utils_free_map,
708 .get_groups_count = stm32_pctrl_get_groups_count,
709 .get_group_name = stm32_pctrl_get_group_name,
710 .get_group_pins = stm32_pctrl_get_group_pins,
711 };
712
713
714 /* Pinmux functions */
715
716 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
717 {
718 return ARRAY_SIZE(stm32_gpio_functions);
719 }
720
721 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
722 unsigned selector)
723 {
724 return stm32_gpio_functions[selector];
725 }
726
727 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
728 unsigned function,
729 const char * const **groups,
730 unsigned * const num_groups)
731 {
732 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
733
734 *groups = pctl->grp_names;
735 *num_groups = pctl->ngroups;
736
737 return 0;
738 }
739
740 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
741 int pin, u32 mode, u32 alt)
742 {
743 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
744 u32 val;
745 int alt_shift = (pin % 8) * 4;
746 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
747 unsigned long flags;
748 int err = 0;
749
750 clk_enable(bank->clk);
751 spin_lock_irqsave(&bank->lock, flags);
752
753 if (pctl->hwlock)
754 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
755
756 if (err) {
757 dev_err(pctl->dev, "Can't get hwspinlock\n");
758 goto unlock;
759 }
760
761 val = readl_relaxed(bank->base + alt_offset);
762 val &= ~GENMASK(alt_shift + 3, alt_shift);
763 val |= (alt << alt_shift);
764 writel_relaxed(val, bank->base + alt_offset);
765
766 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
767 val &= ~GENMASK(pin * 2 + 1, pin * 2);
768 val |= mode << (pin * 2);
769 writel_relaxed(val, bank->base + STM32_GPIO_MODER);
770
771 if (pctl->hwlock)
772 hwspin_unlock(pctl->hwlock);
773
774 stm32_gpio_backup_mode(bank, pin, mode, alt);
775
776 unlock:
777 spin_unlock_irqrestore(&bank->lock, flags);
778 clk_disable(bank->clk);
779
780 return err;
781 }
782
783 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
784 u32 *alt)
785 {
786 u32 val;
787 int alt_shift = (pin % 8) * 4;
788 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
789 unsigned long flags;
790
791 clk_enable(bank->clk);
792 spin_lock_irqsave(&bank->lock, flags);
793
794 val = readl_relaxed(bank->base + alt_offset);
795 val &= GENMASK(alt_shift + 3, alt_shift);
796 *alt = val >> alt_shift;
797
798 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
799 val &= GENMASK(pin * 2 + 1, pin * 2);
800 *mode = val >> (pin * 2);
801
802 spin_unlock_irqrestore(&bank->lock, flags);
803 clk_disable(bank->clk);
804 }
805
806 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
807 unsigned function,
808 unsigned group)
809 {
810 bool ret;
811 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
812 struct stm32_pinctrl_group *g = pctl->groups + group;
813 struct pinctrl_gpio_range *range;
814 struct stm32_gpio_bank *bank;
815 u32 mode, alt;
816 int pin;
817
818 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
819 if (!ret) {
820 dev_err(pctl->dev, "invalid function %d on group %d .\n",
821 function, group);
822 return -EINVAL;
823 }
824
825 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
826 if (!range) {
827 dev_err(pctl->dev, "No gpio range defined.\n");
828 return -EINVAL;
829 }
830
831 bank = gpiochip_get_data(range->gc);
832 pin = stm32_gpio_pin(g->pin);
833
834 mode = stm32_gpio_get_mode(function);
835 alt = stm32_gpio_get_alt(function);
836
837 return stm32_pmx_set_mode(bank, pin, mode, alt);
838 }
839
840 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
841 struct pinctrl_gpio_range *range, unsigned gpio,
842 bool input)
843 {
844 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
845 int pin = stm32_gpio_pin(gpio);
846
847 return stm32_pmx_set_mode(bank, pin, !input, 0);
848 }
849
850 static const struct pinmux_ops stm32_pmx_ops = {
851 .get_functions_count = stm32_pmx_get_funcs_cnt,
852 .get_function_name = stm32_pmx_get_func_name,
853 .get_function_groups = stm32_pmx_get_func_groups,
854 .set_mux = stm32_pmx_set_mux,
855 .gpio_set_direction = stm32_pmx_gpio_set_direction,
856 .strict = true,
857 };
858
859 /* Pinconf functions */
860
861 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
862 unsigned offset, u32 drive)
863 {
864 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
865 unsigned long flags;
866 u32 val;
867 int err = 0;
868
869 clk_enable(bank->clk);
870 spin_lock_irqsave(&bank->lock, flags);
871
872 if (pctl->hwlock)
873 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
874
875 if (err) {
876 dev_err(pctl->dev, "Can't get hwspinlock\n");
877 goto unlock;
878 }
879
880 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
881 val &= ~BIT(offset);
882 val |= drive << offset;
883 writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
884
885 if (pctl->hwlock)
886 hwspin_unlock(pctl->hwlock);
887
888 stm32_gpio_backup_driving(bank, offset, drive);
889
890 unlock:
891 spin_unlock_irqrestore(&bank->lock, flags);
892 clk_disable(bank->clk);
893
894 return err;
895 }
896
897 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
898 unsigned int offset)
899 {
900 unsigned long flags;
901 u32 val;
902
903 clk_enable(bank->clk);
904 spin_lock_irqsave(&bank->lock, flags);
905
906 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
907 val &= BIT(offset);
908
909 spin_unlock_irqrestore(&bank->lock, flags);
910 clk_disable(bank->clk);
911
912 return (val >> offset);
913 }
914
915 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
916 unsigned offset, u32 speed)
917 {
918 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
919 unsigned long flags;
920 u32 val;
921 int err = 0;
922
923 clk_enable(bank->clk);
924 spin_lock_irqsave(&bank->lock, flags);
925
926 if (pctl->hwlock)
927 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
928
929 if (err) {
930 dev_err(pctl->dev, "Can't get hwspinlock\n");
931 goto unlock;
932 }
933
934 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
935 val &= ~GENMASK(offset * 2 + 1, offset * 2);
936 val |= speed << (offset * 2);
937 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
938
939 if (pctl->hwlock)
940 hwspin_unlock(pctl->hwlock);
941
942 stm32_gpio_backup_speed(bank, offset, speed);
943
944 unlock:
945 spin_unlock_irqrestore(&bank->lock, flags);
946 clk_disable(bank->clk);
947
948 return err;
949 }
950
951 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
952 unsigned int offset)
953 {
954 unsigned long flags;
955 u32 val;
956
957 clk_enable(bank->clk);
958 spin_lock_irqsave(&bank->lock, flags);
959
960 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
961 val &= GENMASK(offset * 2 + 1, offset * 2);
962
963 spin_unlock_irqrestore(&bank->lock, flags);
964 clk_disable(bank->clk);
965
966 return (val >> (offset * 2));
967 }
968
969 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
970 unsigned offset, u32 bias)
971 {
972 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
973 unsigned long flags;
974 u32 val;
975 int err = 0;
976
977 clk_enable(bank->clk);
978 spin_lock_irqsave(&bank->lock, flags);
979
980 if (pctl->hwlock)
981 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
982
983 if (err) {
984 dev_err(pctl->dev, "Can't get hwspinlock\n");
985 goto unlock;
986 }
987
988 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
989 val &= ~GENMASK(offset * 2 + 1, offset * 2);
990 val |= bias << (offset * 2);
991 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
992
993 if (pctl->hwlock)
994 hwspin_unlock(pctl->hwlock);
995
996 stm32_gpio_backup_bias(bank, offset, bias);
997
998 unlock:
999 spin_unlock_irqrestore(&bank->lock, flags);
1000 clk_disable(bank->clk);
1001
1002 return err;
1003 }
1004
1005 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
1006 unsigned int offset)
1007 {
1008 unsigned long flags;
1009 u32 val;
1010
1011 clk_enable(bank->clk);
1012 spin_lock_irqsave(&bank->lock, flags);
1013
1014 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1015 val &= GENMASK(offset * 2 + 1, offset * 2);
1016
1017 spin_unlock_irqrestore(&bank->lock, flags);
1018 clk_disable(bank->clk);
1019
1020 return (val >> (offset * 2));
1021 }
1022
1023 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
1024 unsigned int offset, bool dir)
1025 {
1026 unsigned long flags;
1027 u32 val;
1028
1029 clk_enable(bank->clk);
1030 spin_lock_irqsave(&bank->lock, flags);
1031
1032 if (dir)
1033 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
1034 BIT(offset));
1035 else
1036 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
1037 BIT(offset));
1038
1039 spin_unlock_irqrestore(&bank->lock, flags);
1040 clk_disable(bank->clk);
1041
1042 return val;
1043 }
1044
1045 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
1046 unsigned int pin, enum pin_config_param param,
1047 enum pin_config_param arg)
1048 {
1049 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1050 struct pinctrl_gpio_range *range;
1051 struct stm32_gpio_bank *bank;
1052 int offset, ret = 0;
1053
1054 range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
1055 if (!range) {
1056 dev_err(pctl->dev, "No gpio range defined.\n");
1057 return -EINVAL;
1058 }
1059
1060 bank = gpiochip_get_data(range->gc);
1061 offset = stm32_gpio_pin(pin);
1062
1063 switch (param) {
1064 case PIN_CONFIG_DRIVE_PUSH_PULL:
1065 ret = stm32_pconf_set_driving(bank, offset, 0);
1066 break;
1067 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1068 ret = stm32_pconf_set_driving(bank, offset, 1);
1069 break;
1070 case PIN_CONFIG_SLEW_RATE:
1071 ret = stm32_pconf_set_speed(bank, offset, arg);
1072 break;
1073 case PIN_CONFIG_BIAS_DISABLE:
1074 ret = stm32_pconf_set_bias(bank, offset, 0);
1075 break;
1076 case PIN_CONFIG_BIAS_PULL_UP:
1077 ret = stm32_pconf_set_bias(bank, offset, 1);
1078 break;
1079 case PIN_CONFIG_BIAS_PULL_DOWN:
1080 ret = stm32_pconf_set_bias(bank, offset, 2);
1081 break;
1082 case PIN_CONFIG_OUTPUT:
1083 __stm32_gpio_set(bank, offset, arg);
1084 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
1085 break;
1086 default:
1087 ret = -EINVAL;
1088 }
1089
1090 return ret;
1091 }
1092
1093 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
1094 unsigned group,
1095 unsigned long *config)
1096 {
1097 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1098
1099 *config = pctl->groups[group].config;
1100
1101 return 0;
1102 }
1103
1104 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
1105 unsigned long *configs, unsigned num_configs)
1106 {
1107 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1108 struct stm32_pinctrl_group *g = &pctl->groups[group];
1109 int i, ret;
1110
1111 for (i = 0; i < num_configs; i++) {
1112 ret = stm32_pconf_parse_conf(pctldev, g->pin,
1113 pinconf_to_config_param(configs[i]),
1114 pinconf_to_config_argument(configs[i]));
1115 if (ret < 0)
1116 return ret;
1117
1118 g->config = configs[i];
1119 }
1120
1121 return 0;
1122 }
1123
1124 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
1125 struct seq_file *s,
1126 unsigned int pin)
1127 {
1128 struct pinctrl_gpio_range *range;
1129 struct stm32_gpio_bank *bank;
1130 int offset;
1131 u32 mode, alt, drive, speed, bias;
1132 static const char * const modes[] = {
1133 "input", "output", "alternate", "analog" };
1134 static const char * const speeds[] = {
1135 "low", "medium", "high", "very high" };
1136 static const char * const biasing[] = {
1137 "floating", "pull up", "pull down", "" };
1138 bool val;
1139
1140 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1141 if (!range)
1142 return;
1143
1144 bank = gpiochip_get_data(range->gc);
1145 offset = stm32_gpio_pin(pin);
1146
1147 stm32_pmx_get_mode(bank, offset, &mode, &alt);
1148 bias = stm32_pconf_get_bias(bank, offset);
1149
1150 seq_printf(s, "%s ", modes[mode]);
1151
1152 switch (mode) {
1153 /* input */
1154 case 0:
1155 val = stm32_pconf_get(bank, offset, true);
1156 seq_printf(s, "- %s - %s",
1157 val ? "high" : "low",
1158 biasing[bias]);
1159 break;
1160
1161 /* output */
1162 case 1:
1163 drive = stm32_pconf_get_driving(bank, offset);
1164 speed = stm32_pconf_get_speed(bank, offset);
1165 val = stm32_pconf_get(bank, offset, false);
1166 seq_printf(s, "- %s - %s - %s - %s %s",
1167 val ? "high" : "low",
1168 drive ? "open drain" : "push pull",
1169 biasing[bias],
1170 speeds[speed], "speed");
1171 break;
1172
1173 /* alternate */
1174 case 2:
1175 drive = stm32_pconf_get_driving(bank, offset);
1176 speed = stm32_pconf_get_speed(bank, offset);
1177 seq_printf(s, "%d - %s - %s - %s %s", alt,
1178 drive ? "open drain" : "push pull",
1179 biasing[bias],
1180 speeds[speed], "speed");
1181 break;
1182
1183 /* analog */
1184 case 3:
1185 break;
1186 }
1187 }
1188
1189
1190 static const struct pinconf_ops stm32_pconf_ops = {
1191 .pin_config_group_get = stm32_pconf_group_get,
1192 .pin_config_group_set = stm32_pconf_group_set,
1193 .pin_config_dbg_show = stm32_pconf_dbg_show,
1194 };
1195
1196 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
1197 struct device_node *np)
1198 {
1199 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
1200 int bank_ioport_nr;
1201 struct pinctrl_gpio_range *range = &bank->range;
1202 struct of_phandle_args args;
1203 struct device *dev = pctl->dev;
1204 struct resource res;
1205 struct reset_control *rstc;
1206 int npins = STM32_GPIO_PINS_PER_BANK;
1207 int bank_nr, err;
1208
1209 rstc = of_reset_control_get_exclusive(np, NULL);
1210 if (!IS_ERR(rstc))
1211 reset_control_deassert(rstc);
1212
1213 if (of_address_to_resource(np, 0, &res))
1214 return -ENODEV;
1215
1216 bank->base = devm_ioremap_resource(dev, &res);
1217 if (IS_ERR(bank->base))
1218 return PTR_ERR(bank->base);
1219
1220 bank->clk = of_clk_get_by_name(np, NULL);
1221 if (IS_ERR(bank->clk)) {
1222 dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk));
1223 return PTR_ERR(bank->clk);
1224 }
1225
1226 err = clk_prepare(bank->clk);
1227 if (err) {
1228 dev_err(dev, "failed to prepare clk (%d)\n", err);
1229 return err;
1230 }
1231
1232 bank->gpio_chip = stm32_gpio_template;
1233
1234 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);
1235
1236 if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) {
1237 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
1238 bank->gpio_chip.base = args.args[1];
1239 } else {
1240 bank_nr = pctl->nbanks;
1241 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1242 range->name = bank->gpio_chip.label;
1243 range->id = bank_nr;
1244 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
1245 range->base = range->id * STM32_GPIO_PINS_PER_BANK;
1246 range->npins = npins;
1247 range->gc = &bank->gpio_chip;
1248 pinctrl_add_gpio_range(pctl->pctl_dev,
1249 &pctl->banks[bank_nr].range);
1250 }
1251
1252 if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr))
1253 bank_ioport_nr = bank_nr;
1254
1255 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1256
1257 bank->gpio_chip.ngpio = npins;
1258 bank->gpio_chip.of_node = np;
1259 bank->gpio_chip.parent = dev;
1260 bank->bank_nr = bank_nr;
1261 bank->bank_ioport_nr = bank_ioport_nr;
1262 spin_lock_init(&bank->lock);
1263
1264 /* create irq hierarchical domain */
1265 bank->fwnode = of_node_to_fwnode(np);
1266
1267 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
1268 STM32_GPIO_IRQ_LINE, bank->fwnode,
1269 &stm32_gpio_domain_ops, bank);
1270
1271 if (!bank->domain)
1272 return -ENODEV;
1273
1274 err = gpiochip_add_data(&bank->gpio_chip, bank);
1275 if (err) {
1276 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
1277 return err;
1278 }
1279
1280 dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1281 return 0;
1282 }
1283
1284 static struct irq_domain *stm32_pctrl_get_irq_domain(struct device_node *np)
1285 {
1286 struct device_node *parent;
1287 struct irq_domain *domain;
1288
1289 if (!of_find_property(np, "interrupt-parent", NULL))
1290 return NULL;
1291
1292 parent = of_irq_find_parent(np);
1293 if (!parent)
1294 return ERR_PTR(-ENXIO);
1295
1296 domain = irq_find_host(parent);
1297 if (!domain)
1298 /* domain not registered yet */
1299 return ERR_PTR(-EPROBE_DEFER);
1300
1301 return domain;
1302 }
1303
1304 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1305 struct stm32_pinctrl *pctl)
1306 {
1307 struct device_node *np = pdev->dev.of_node;
1308 struct device *dev = &pdev->dev;
1309 struct regmap *rm;
1310 int offset, ret, i;
1311 int mask, mask_width;
1312
1313 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1314 if (IS_ERR(pctl->regmap))
1315 return PTR_ERR(pctl->regmap);
1316
1317 rm = pctl->regmap;
1318
1319 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
1320 if (ret)
1321 return ret;
1322
1323 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
1324 if (ret)
1325 mask = SYSCFG_IRQMUX_MASK;
1326
1327 mask_width = fls(mask);
1328
1329 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1330 struct reg_field mux;
1331
1332 mux.reg = offset + (i / 4) * 4;
1333 mux.lsb = (i % 4) * mask_width;
1334 mux.msb = mux.lsb + mask_width - 1;
1335
1336 dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
1337 i, mux.reg, mux.lsb, mux.msb);
1338
1339 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1340 if (IS_ERR(pctl->irqmux[i]))
1341 return PTR_ERR(pctl->irqmux[i]);
1342 }
1343
1344 return 0;
1345 }
1346
1347 static int stm32_pctrl_build_state(struct platform_device *pdev)
1348 {
1349 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1350 int i;
1351
1352 pctl->ngroups = pctl->npins;
1353
1354 /* Allocate groups */
1355 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1356 sizeof(*pctl->groups), GFP_KERNEL);
1357 if (!pctl->groups)
1358 return -ENOMEM;
1359
1360 /* We assume that one pin is one group, use pin name as group name. */
1361 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1362 sizeof(*pctl->grp_names), GFP_KERNEL);
1363 if (!pctl->grp_names)
1364 return -ENOMEM;
1365
1366 for (i = 0; i < pctl->npins; i++) {
1367 const struct stm32_desc_pin *pin = pctl->pins + i;
1368 struct stm32_pinctrl_group *group = pctl->groups + i;
1369
1370 group->name = pin->pin.name;
1371 group->pin = pin->pin.number;
1372 pctl->grp_names[i] = pin->pin.name;
1373 }
1374
1375 return 0;
1376 }
1377
1378 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
1379 struct stm32_desc_pin *pins)
1380 {
1381 const struct stm32_desc_pin *p;
1382 int i, nb_pins_available = 0;
1383
1384 for (i = 0; i < pctl->match_data->npins; i++) {
1385 p = pctl->match_data->pins + i;
1386 if (pctl->pkg && !(pctl->pkg & p->pkg))
1387 continue;
1388 pins->pin = p->pin;
1389 pins->functions = p->functions;
1390 pins++;
1391 nb_pins_available++;
1392 }
1393
1394 pctl->npins = nb_pins_available;
1395
1396 return 0;
1397 }
1398
1399 static void stm32_pctl_get_package(struct device_node *np,
1400 struct stm32_pinctrl *pctl)
1401 {
1402 if (of_property_read_u32(np, "st,package", &pctl->pkg)) {
1403 pctl->pkg = 0;
1404 dev_warn(pctl->dev, "No package detected, use default one\n");
1405 } else {
1406 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
1407 }
1408 }
1409
1410 int stm32_pctl_probe(struct platform_device *pdev)
1411 {
1412 struct device_node *np = pdev->dev.of_node;
1413 struct device_node *child;
1414 const struct of_device_id *match;
1415 struct device *dev = &pdev->dev;
1416 struct stm32_pinctrl *pctl;
1417 struct pinctrl_pin_desc *pins;
1418 int i, ret, hwlock_id, banks = 0;
1419
1420 if (!np)
1421 return -EINVAL;
1422
1423 match = of_match_device(dev->driver->of_match_table, dev);
1424 if (!match || !match->data)
1425 return -EINVAL;
1426
1427 if (!of_find_property(np, "pins-are-numbered", NULL)) {
1428 dev_err(dev, "only support pins-are-numbered format\n");
1429 return -EINVAL;
1430 }
1431
1432 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1433 if (!pctl)
1434 return -ENOMEM;
1435
1436 platform_set_drvdata(pdev, pctl);
1437
1438 /* check for IRQ controller (may require deferred probe) */
1439 pctl->domain = stm32_pctrl_get_irq_domain(np);
1440 if (IS_ERR(pctl->domain))
1441 return PTR_ERR(pctl->domain);
1442
1443 /* hwspinlock is optional */
1444 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
1445 if (hwlock_id < 0) {
1446 if (hwlock_id == -EPROBE_DEFER)
1447 return hwlock_id;
1448 } else {
1449 pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
1450 }
1451
1452 spin_lock_init(&pctl->irqmux_lock);
1453
1454 pctl->dev = dev;
1455 pctl->match_data = match->data;
1456
1457 /* get package information */
1458 stm32_pctl_get_package(np, pctl);
1459
1460 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
1461 sizeof(*pctl->pins), GFP_KERNEL);
1462 if (!pctl->pins)
1463 return -ENOMEM;
1464
1465 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
1466 if (ret)
1467 return ret;
1468
1469 ret = stm32_pctrl_build_state(pdev);
1470 if (ret) {
1471 dev_err(dev, "build state failed: %d\n", ret);
1472 return -EINVAL;
1473 }
1474
1475 if (pctl->domain) {
1476 ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1477 if (ret)
1478 return ret;
1479 }
1480
1481 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
1482 GFP_KERNEL);
1483 if (!pins)
1484 return -ENOMEM;
1485
1486 for (i = 0; i < pctl->npins; i++)
1487 pins[i] = pctl->pins[i].pin;
1488
1489 pctl->pctl_desc.name = dev_name(&pdev->dev);
1490 pctl->pctl_desc.owner = THIS_MODULE;
1491 pctl->pctl_desc.pins = pins;
1492 pctl->pctl_desc.npins = pctl->npins;
1493 pctl->pctl_desc.link_consumers = true;
1494 pctl->pctl_desc.confops = &stm32_pconf_ops;
1495 pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1496 pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1497 pctl->dev = &pdev->dev;
1498
1499 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1500 pctl);
1501
1502 if (IS_ERR(pctl->pctl_dev)) {
1503 dev_err(&pdev->dev, "Failed pinctrl registration\n");
1504 return PTR_ERR(pctl->pctl_dev);
1505 }
1506
1507 for_each_available_child_of_node(np, child)
1508 if (of_property_read_bool(child, "gpio-controller"))
1509 banks++;
1510
1511 if (!banks) {
1512 dev_err(dev, "at least one GPIO bank is required\n");
1513 return -EINVAL;
1514 }
1515 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1516 GFP_KERNEL);
1517 if (!pctl->banks)
1518 return -ENOMEM;
1519
1520 for_each_available_child_of_node(np, child) {
1521 if (of_property_read_bool(child, "gpio-controller")) {
1522 ret = stm32_gpiolib_register_bank(pctl, child);
1523 if (ret) {
1524 of_node_put(child);
1525 return ret;
1526 }
1527
1528 pctl->nbanks++;
1529 }
1530 }
1531
1532 dev_info(dev, "Pinctrl STM32 initialized\n");
1533
1534 return 0;
1535 }
1536
1537 static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
1538 struct stm32_pinctrl *pctl, u32 pin)
1539 {
1540 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
1541 u32 val, alt, mode, offset = stm32_gpio_pin(pin);
1542 struct pinctrl_gpio_range *range;
1543 struct stm32_gpio_bank *bank;
1544 bool pin_is_irq;
1545 int ret;
1546
1547 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
1548 if (!range)
1549 return 0;
1550
1551 pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
1552
1553 if (!desc || (!pin_is_irq && !desc->gpio_owner))
1554 return 0;
1555
1556 bank = gpiochip_get_data(range->gc);
1557
1558 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
1559 alt >>= STM32_GPIO_BKP_ALT_SHIFT;
1560 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
1561 mode >>= STM32_GPIO_BKP_MODE_SHIFT;
1562
1563 ret = stm32_pmx_set_mode(bank, offset, mode, alt);
1564 if (ret)
1565 return ret;
1566
1567 if (mode == 1) {
1568 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
1569 val = val >> STM32_GPIO_BKP_VAL;
1570 __stm32_gpio_set(bank, offset, val);
1571 }
1572
1573 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
1574 val >>= STM32_GPIO_BKP_TYPE;
1575 ret = stm32_pconf_set_driving(bank, offset, val);
1576 if (ret)
1577 return ret;
1578
1579 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
1580 val >>= STM32_GPIO_BKP_SPEED_SHIFT;
1581 ret = stm32_pconf_set_speed(bank, offset, val);
1582 if (ret)
1583 return ret;
1584
1585 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
1586 val >>= STM32_GPIO_BKP_PUPD_SHIFT;
1587 ret = stm32_pconf_set_bias(bank, offset, val);
1588 if (ret)
1589 return ret;
1590
1591 if (pin_is_irq)
1592 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
1593
1594 return 0;
1595 }
1596
1597 int __maybe_unused stm32_pinctrl_resume(struct device *dev)
1598 {
1599 struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1600 struct stm32_pinctrl_group *g = pctl->groups;
1601 int i;
1602
1603 for (i = g->pin; i < g->pin + pctl->ngroups; i++)
1604 stm32_pinctrl_restore_gpio_regs(pctl, i);
1605
1606 return 0;
1607 }
Linux with added FPC-III support