drivers/remoteproc/qcom_q6v5_adsp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Qualcomm Technology Inc. ADSP Peripheral Image Loader for SDM845.
   4  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/delay.h>
   9 #include <linux/firmware.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/io.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/kernel.h>
  14 #include <linux/mfd/syscon.h>
  15 #include <linux/module.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pm_domain.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/regmap.h>
  22 #include <linux/remoteproc.h>
  23 #include <linux/reset.h>
  24 #include <linux/soc/qcom/mdt_loader.h>
  25 #include <linux/soc/qcom/smem.h>
  26 #include <linux/soc/qcom/smem_state.h>
  27
  28 #include "qcom_common.h"
  29 #include "qcom_q6v5.h"
  30 #include "remoteproc_internal.h"
  31
  32 /* time out value */
  33 #define ACK_TIMEOUT                     1000
  34 #define BOOT_FSM_TIMEOUT                10000
  35 /* mask values */
  36 #define EVB_MASK                        GENMASK(27, 4)
  37 /*QDSP6SS register offsets*/
  38 #define RST_EVB_REG                     0x10
  39 #define CORE_START_REG                  0x400
  40 #define BOOT_CMD_REG                    0x404
  41 #define BOOT_STATUS_REG                 0x408
  42 #define RET_CFG_REG                     0x1C
  43 /*TCSR register offsets*/
  44 #define LPASS_MASTER_IDLE_REG           0x8
  45 #define LPASS_HALTACK_REG               0x4
  46 #define LPASS_PWR_ON_REG                0x10
  47 #define LPASS_HALTREQ_REG               0x0
  48
  49 #define QDSP6SS_XO_CBCR         0x38
  50 #define QDSP6SS_CORE_CBCR       0x20
  51 #define QDSP6SS_SLEEP_CBCR      0x3c
  52
  53 struct adsp_pil_data {
  54         int crash_reason_smem;
  55         const char *firmware_name;
  56
  57         const char *ssr_name;
  58         const char *sysmon_name;
  59         int ssctl_id;
  60
  61         const char **clk_ids;
  62         int num_clks;
  63 };
  64
  65 struct qcom_adsp {
  66         struct device *dev;
  67         struct rproc *rproc;
  68
  69         struct qcom_q6v5 q6v5;
  70
  71         struct clk *xo;
  72
  73         int num_clks;
  74         struct clk_bulk_data *clks;
  75
  76         void __iomem *qdsp6ss_base;
  77
  78         struct reset_control *pdc_sync_reset;
  79         struct reset_control *restart;
  80
  81         struct regmap *halt_map;
  82         unsigned int halt_lpass;
  83
  84         int crash_reason_smem;
  85
  86         struct completion start_done;
  87         struct completion stop_done;
  88
  89         phys_addr_t mem_phys;
  90         phys_addr_t mem_reloc;
  91         void *mem_region;
  92         size_t mem_size;
  93
  94         struct qcom_rproc_glink glink_subdev;
  95         struct qcom_rproc_ssr ssr_subdev;
  96         struct qcom_sysmon *sysmon;
  97 };
  98
  99 static int qcom_adsp_shutdown(struct qcom_adsp *adsp)
 100 {
 101         unsigned long timeout;
 102         unsigned int val;
 103         int ret;
 104
 105         /* Reset the retention logic */
 106         val = readl(adsp->qdsp6ss_base + RET_CFG_REG);
 107         val |= 0x1;
 108         writel(val, adsp->qdsp6ss_base + RET_CFG_REG);
 109
 110         clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
 111
 112         /* QDSP6 master port needs to be explicitly halted */
 113         ret = regmap_read(adsp->halt_map,
 114                         adsp->halt_lpass + LPASS_PWR_ON_REG, &val);
 115         if (ret || !val)
 116                 goto reset;
 117
 118         ret = regmap_read(adsp->halt_map,
 119                         adsp->halt_lpass + LPASS_MASTER_IDLE_REG,
 120                         &val);
 121         if (ret || val)
 122                 goto reset;
 123
 124         regmap_write(adsp->halt_map,
 125                         adsp->halt_lpass + LPASS_HALTREQ_REG, 1);
 126
 127         /* Wait for halt ACK from QDSP6 */
 128         timeout = jiffies + msecs_to_jiffies(ACK_TIMEOUT);
 129         for (;;) {
 130                 ret = regmap_read(adsp->halt_map,
 131                         adsp->halt_lpass + LPASS_HALTACK_REG, &val);
 132                 if (ret || val || time_after(jiffies, timeout))
 133                         break;
 134
 135                 usleep_range(1000, 1100);
 136         }
 137
 138         ret = regmap_read(adsp->halt_map,
 139                         adsp->halt_lpass + LPASS_MASTER_IDLE_REG, &val);
 140         if (ret || !val)
 141                 dev_err(adsp->dev, "port failed halt\n");
 142
 143 reset:
 144         /* Assert the LPASS PDC Reset */
 145         reset_control_assert(adsp->pdc_sync_reset);
 146         /* Place the LPASS processor into reset */
 147         reset_control_assert(adsp->restart);
 148         /* wait after asserting subsystem restart from AOSS */
 149         usleep_range(200, 300);
 150
 151         /* Clear the halt request for the AXIM and AHBM for Q6 */
 152         regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 0);
 153
 154         /* De-assert the LPASS PDC Reset */
 155         reset_control_deassert(adsp->pdc_sync_reset);
 156         /* Remove the LPASS reset */
 157         reset_control_deassert(adsp->restart);
 158         /* wait after de-asserting subsystem restart from AOSS */
 159         usleep_range(200, 300);
 160
 161         return 0;
 162 }
 163
 164 static int adsp_load(struct rproc *rproc, const struct firmware *fw)
 165 {
 166         struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
 167
 168         return qcom_mdt_load_no_init(adsp->dev, fw, rproc->firmware, 0,
 169                              adsp->mem_region, adsp->mem_phys, adsp->mem_size,
 170                              &adsp->mem_reloc);
 171 }
 172
 173 static int adsp_start(struct rproc *rproc)
 174 {
 175         struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
 176         int ret;
 177         unsigned int val;
 178
 179         qcom_q6v5_prepare(&adsp->q6v5);
 180
 181         ret = clk_prepare_enable(adsp->xo);
 182         if (ret)
 183                 goto disable_irqs;
 184
 185         dev_pm_genpd_set_performance_state(adsp->dev, INT_MAX);
 186         ret = pm_runtime_get_sync(adsp->dev);
 187         if (ret)
 188                 goto disable_xo_clk;
 189
 190         ret = clk_bulk_prepare_enable(adsp->num_clks, adsp->clks);
 191         if (ret) {
 192                 dev_err(adsp->dev, "adsp clk_enable failed\n");
 193                 goto disable_power_domain;
 194         }
 195
 196         /* Enable the XO clock */
 197         writel(1, adsp->qdsp6ss_base + QDSP6SS_XO_CBCR);
 198
 199         /* Enable the QDSP6SS sleep clock */
 200         writel(1, adsp->qdsp6ss_base + QDSP6SS_SLEEP_CBCR);
 201
 202         /* Enable the QDSP6 core clock */
 203         writel(1, adsp->qdsp6ss_base + QDSP6SS_CORE_CBCR);
 204
 205         /* Program boot address */
 206         writel(adsp->mem_phys >> 4, adsp->qdsp6ss_base + RST_EVB_REG);
 207
 208         /* De-assert QDSP6 stop core. QDSP6 will execute after out of reset */
 209         writel(0x1, adsp->qdsp6ss_base + CORE_START_REG);
 210
 211         /* Trigger boot FSM to start QDSP6 */
 212         writel(0x1, adsp->qdsp6ss_base + BOOT_CMD_REG);
 213
 214         /* Wait for core to come out of reset */
 215         ret = readl_poll_timeout(adsp->qdsp6ss_base + BOOT_STATUS_REG,
 216                         val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
 217         if (ret) {
 218                 dev_err(adsp->dev, "failed to bootup adsp\n");
 219                 goto disable_adsp_clks;
 220         }
 221
 222         ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5 * HZ));
 223         if (ret == -ETIMEDOUT) {
 224                 dev_err(adsp->dev, "start timed out\n");
 225                 goto disable_adsp_clks;
 226         }
 227
 228         return 0;
 229
 230 disable_adsp_clks:
 231         clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
 232 disable_power_domain:
 233         dev_pm_genpd_set_performance_state(adsp->dev, 0);
 234         pm_runtime_put(adsp->dev);
 235 disable_xo_clk:
 236         clk_disable_unprepare(adsp->xo);
 237 disable_irqs:
 238         qcom_q6v5_unprepare(&adsp->q6v5);
 239
 240         return ret;
 241 }
 242
 243 static void qcom_adsp_pil_handover(struct qcom_q6v5 *q6v5)
 244 {
 245         struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5);
 246
 247         clk_disable_unprepare(adsp->xo);
 248         dev_pm_genpd_set_performance_state(adsp->dev, 0);
 249         pm_runtime_put(adsp->dev);
 250 }
 251
 252 static int adsp_stop(struct rproc *rproc)
 253 {
 254         struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
 255         int handover;
 256         int ret;
 257
 258         ret = qcom_q6v5_request_stop(&adsp->q6v5);
 259         if (ret == -ETIMEDOUT)
 260                 dev_err(adsp->dev, "timed out on wait\n");
 261
 262         ret = qcom_adsp_shutdown(adsp);
 263         if (ret)
 264                 dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
 265
 266         handover = qcom_q6v5_unprepare(&adsp->q6v5);
 267         if (handover)
 268                 qcom_adsp_pil_handover(&adsp->q6v5);
 269
 270         return ret;
 271 }
 272
 273 static void *adsp_da_to_va(struct rproc *rproc, u64 da, size_t len)
 274 {
 275         struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
 276         int offset;
 277
 278         offset = da - adsp->mem_reloc;
 279         if (offset < 0 || offset + len > adsp->mem_size)
 280                 return NULL;
 281
 282         return adsp->mem_region + offset;
 283 }
 284
 285 static unsigned long adsp_panic(struct rproc *rproc)
 286 {
 287         struct qcom_adsp *adsp = rproc->priv;
 288
 289         return qcom_q6v5_panic(&adsp->q6v5);
 290 }
 291
 292 static const struct rproc_ops adsp_ops = {
 293         .start = adsp_start,
 294         .stop = adsp_stop,
 295         .da_to_va = adsp_da_to_va,
 296         .parse_fw = qcom_register_dump_segments,
 297         .load = adsp_load,
 298         .panic = adsp_panic,
 299 };
 300
 301 static int adsp_init_clock(struct qcom_adsp *adsp, const char **clk_ids)
 302 {
 303         int num_clks = 0;
 304         int i, ret;
 305
 306         adsp->xo = devm_clk_get(adsp->dev, "xo");
 307         if (IS_ERR(adsp->xo)) {
 308                 ret = PTR_ERR(adsp->xo);
 309                 if (ret != -EPROBE_DEFER)
 310                         dev_err(adsp->dev, "failed to get xo clock");
 311                 return ret;
 312         }
 313
 314         for (i = 0; clk_ids[i]; i++)
 315                 num_clks++;
 316
 317         adsp->num_clks = num_clks;
 318         adsp->clks = devm_kcalloc(adsp->dev, adsp->num_clks,
 319                                 sizeof(*adsp->clks), GFP_KERNEL);
 320         if (!adsp->clks)
 321                 return -ENOMEM;
 322
 323         for (i = 0; i < adsp->num_clks; i++)
 324                 adsp->clks[i].id = clk_ids[i];
 325
 326         return devm_clk_bulk_get(adsp->dev, adsp->num_clks, adsp->clks);
 327 }
 328
 329 static int adsp_init_reset(struct qcom_adsp *adsp)
 330 {
 331         adsp->pdc_sync_reset = devm_reset_control_get_optional_exclusive(adsp->dev,
 332                         "pdc_sync");
 333         if (IS_ERR(adsp->pdc_sync_reset)) {
 334                 dev_err(adsp->dev, "failed to acquire pdc_sync reset\n");
 335                 return PTR_ERR(adsp->pdc_sync_reset);
 336         }
 337
 338         adsp->restart = devm_reset_control_get_optional_exclusive(adsp->dev, "restart");
 339
 340         /* Fall back to the  old "cc_lpass" if "restart" is absent */
 341         if (!adsp->restart)
 342                 adsp->restart = devm_reset_control_get_exclusive(adsp->dev, "cc_lpass");
 343
 344         if (IS_ERR(adsp->restart)) {
 345                 dev_err(adsp->dev, "failed to acquire restart\n");
 346                 return PTR_ERR(adsp->restart);
 347         }
 348
 349         return 0;
 350 }
 351
 352 static int adsp_init_mmio(struct qcom_adsp *adsp,
 353                                 struct platform_device *pdev)
 354 {
 355         struct device_node *syscon;
 356         struct resource *res;
 357         int ret;
 358
 359         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 360         adsp->qdsp6ss_base = devm_ioremap(&pdev->dev, res->start,
 361                         resource_size(res));
 362         if (!adsp->qdsp6ss_base) {
 363                 dev_err(adsp->dev, "failed to map QDSP6SS registers\n");
 364                 return -ENOMEM;
 365         }
 366
 367         syscon = of_parse_phandle(pdev->dev.of_node, "qcom,halt-regs", 0);
 368         if (!syscon) {
 369                 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
 370                 return -EINVAL;
 371         }
 372
 373         adsp->halt_map = syscon_node_to_regmap(syscon);
 374         of_node_put(syscon);
 375         if (IS_ERR(adsp->halt_map))
 376                 return PTR_ERR(adsp->halt_map);
 377
 378         ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,halt-regs",
 379                         1, &adsp->halt_lpass);
 380         if (ret < 0) {
 381                 dev_err(&pdev->dev, "no offset in syscon\n");
 382                 return ret;
 383         }
 384
 385         return 0;
 386 }
 387
 388 static int adsp_alloc_memory_region(struct qcom_adsp *adsp)
 389 {
 390         struct device_node *node;
 391         struct resource r;
 392         int ret;
 393
 394         node = of_parse_phandle(adsp->dev->of_node, "memory-region", 0);
 395         if (!node) {
 396                 dev_err(adsp->dev, "no memory-region specified\n");
 397                 return -EINVAL;
 398         }
 399
 400         ret = of_address_to_resource(node, 0, &r);
 401         if (ret)
 402                 return ret;
 403
 404         adsp->mem_phys = adsp->mem_reloc = r.start;
 405         adsp->mem_size = resource_size(&r);
 406         adsp->mem_region = devm_ioremap_wc(adsp->dev,
 407                                 adsp->mem_phys, adsp->mem_size);
 408         if (!adsp->mem_region) {
 409                 dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n",
 410                         &r.start, adsp->mem_size);
 411                 return -EBUSY;
 412         }
 413
 414         return 0;
 415 }
 416
 417 static int adsp_probe(struct platform_device *pdev)
 418 {
 419         const struct adsp_pil_data *desc;
 420         struct qcom_adsp *adsp;
 421         struct rproc *rproc;
 422         int ret;
 423
 424         desc = of_device_get_match_data(&pdev->dev);
 425         if (!desc)
 426                 return -EINVAL;
 427
 428         rproc = rproc_alloc(&pdev->dev, pdev->name, &adsp_ops,
 429                             desc->firmware_name, sizeof(*adsp));
 430         if (!rproc) {
 431                 dev_err(&pdev->dev, "unable to allocate remoteproc\n");
 432                 return -ENOMEM;
 433         }
 434
 435         adsp = (struct qcom_adsp *)rproc->priv;
 436         adsp->dev = &pdev->dev;
 437         adsp->rproc = rproc;
 438         platform_set_drvdata(pdev, adsp);
 439
 440         ret = adsp_alloc_memory_region(adsp);
 441         if (ret)
 442                 goto free_rproc;
 443
 444         ret = adsp_init_clock(adsp, desc->clk_ids);
 445         if (ret)
 446                 goto free_rproc;
 447
 448         pm_runtime_enable(adsp->dev);
 449
 450         ret = adsp_init_reset(adsp);
 451         if (ret)
 452                 goto disable_pm;
 453
 454         ret = adsp_init_mmio(adsp, pdev);
 455         if (ret)
 456                 goto disable_pm;
 457
 458         ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
 459                              qcom_adsp_pil_handover);
 460         if (ret)
 461                 goto disable_pm;
 462
 463         qcom_add_glink_subdev(rproc, &adsp->glink_subdev);
 464         qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name);
 465         adsp->sysmon = qcom_add_sysmon_subdev(rproc,
 466                                               desc->sysmon_name,
 467                                               desc->ssctl_id);
 468         if (IS_ERR(adsp->sysmon)) {
 469                 ret = PTR_ERR(adsp->sysmon);
 470                 goto disable_pm;
 471         }
 472
 473         ret = rproc_add(rproc);
 474         if (ret)
 475                 goto disable_pm;
 476
 477         return 0;
 478
 479 disable_pm:
 480         pm_runtime_disable(adsp->dev);
 481 free_rproc:
 482         rproc_free(rproc);
 483
 484         return ret;
 485 }
 486
 487 static int adsp_remove(struct platform_device *pdev)
 488 {
 489         struct qcom_adsp *adsp = platform_get_drvdata(pdev);
 490
 491         rproc_del(adsp->rproc);
 492
 493         qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
 494         qcom_remove_sysmon_subdev(adsp->sysmon);
 495         qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
 496         pm_runtime_disable(adsp->dev);
 497         rproc_free(adsp->rproc);
 498
 499         return 0;
 500 }
 501
 502 static const struct adsp_pil_data adsp_resource_init = {
 503         .crash_reason_smem = 423,
 504         .firmware_name = "adsp.mdt",
 505         .ssr_name = "lpass",
 506         .sysmon_name = "adsp",
 507         .ssctl_id = 0x14,
 508         .clk_ids = (const char*[]) {
 509                 "sway_cbcr", "lpass_ahbs_aon_cbcr", "lpass_ahbm_aon_cbcr",
 510                 "qdsp6ss_xo", "qdsp6ss_sleep", "qdsp6ss_core", NULL
 511         },
 512         .num_clks = 7,
 513 };
 514
 515 static const struct adsp_pil_data cdsp_resource_init = {
 516         .crash_reason_smem = 601,
 517         .firmware_name = "cdsp.mdt",
 518         .ssr_name = "cdsp",
 519         .sysmon_name = "cdsp",
 520         .ssctl_id = 0x17,
 521         .clk_ids = (const char*[]) {
 522                 "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave", "q6ss_master",
 523                 "q6_axim", NULL
 524         },
 525         .num_clks = 7,
 526 };
 527
 528 static const struct of_device_id adsp_of_match[] = {
 529         { .compatible = "qcom,qcs404-cdsp-pil", .data = &cdsp_resource_init },
 530         { .compatible = "qcom,sdm845-adsp-pil", .data = &adsp_resource_init },
 531         { },
 532 };
 533 MODULE_DEVICE_TABLE(of, adsp_of_match);
 534
 535 static struct platform_driver adsp_pil_driver = {
 536         .probe = adsp_probe,
 537         .remove = adsp_remove,
 538         .driver = {
 539                 .name = "qcom_q6v5_adsp",
 540                 .of_match_table = adsp_of_match,
 541         },
 542 };
 543
 544 module_platform_driver(adsp_pil_driver);
 545 MODULE_DESCRIPTION("QTI SDM845 ADSP Peripheral Image Loader");
 546 MODULE_LICENSE("GPL v2");