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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / scsi / bnx2fc / bnx2fc_hwi.c
blob1f7c58b4c53518a53868e59cafe508f62d2fb392
1 /* bnx2fc_hwi.c: QLogic Linux FCoE offload driver.
2 * This file contains the code that low level functions that interact
3 * with 57712 FCoE firmware.
4 *
5 * Copyright (c) 2008-2013 Broadcom Corporation
6 * Copyright (c) 2014-2016 QLogic Corporation
7 * Copyright (c) 2016-2017 Cavium Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation.
12 *
13 * Written by: Bhanu Prakash Gollapudi (bprakash@broadcom.com)
14 */
15
16 #include "bnx2fc.h"
17
18 DECLARE_PER_CPU(struct bnx2fc_percpu_s, bnx2fc_percpu);
19
20 static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
21 struct fcoe_kcqe *new_cqe_kcqe);
22 static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
23 struct fcoe_kcqe *ofld_kcqe);
24 static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
25 struct fcoe_kcqe *ofld_kcqe);
26 static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code);
27 static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
28 struct fcoe_kcqe *destroy_kcqe);
29
30 int bnx2fc_send_stat_req(struct bnx2fc_hba *hba)
31 {
32 struct fcoe_kwqe_stat stat_req;
33 struct kwqe *kwqe_arr[2];
34 int num_kwqes = 1;
35 int rc = 0;
36
37 memset(&stat_req, 0x00, sizeof(struct fcoe_kwqe_stat));
38 stat_req.hdr.op_code = FCOE_KWQE_OPCODE_STAT;
39 stat_req.hdr.flags =
40 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
41
42 stat_req.stat_params_addr_lo = (u32) hba->stats_buf_dma;
43 stat_req.stat_params_addr_hi = (u32) ((u64)hba->stats_buf_dma >> 32);
44
45 kwqe_arr[0] = (struct kwqe *) &stat_req;
46
47 if (hba->cnic && hba->cnic->submit_kwqes)
48 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
49
50 return rc;
51 }
52
53 /**
54 * bnx2fc_send_fw_fcoe_init_msg - initiates initial handshake with FCoE f/w
55 *
56 * @hba: adapter structure pointer
57 *
58 * Send down FCoE firmware init KWQEs which initiates the initial handshake
59 * with the f/w.
60 *
61 */
62 int bnx2fc_send_fw_fcoe_init_msg(struct bnx2fc_hba *hba)
63 {
64 struct fcoe_kwqe_init1 fcoe_init1;
65 struct fcoe_kwqe_init2 fcoe_init2;
66 struct fcoe_kwqe_init3 fcoe_init3;
67 struct kwqe *kwqe_arr[3];
68 int num_kwqes = 3;
69 int rc = 0;
70
71 if (!hba->cnic) {
72 printk(KERN_ERR PFX "hba->cnic NULL during fcoe fw init\n");
73 return -ENODEV;
74 }
75
76 /* fill init1 KWQE */
77 memset(&fcoe_init1, 0x00, sizeof(struct fcoe_kwqe_init1));
78 fcoe_init1.hdr.op_code = FCOE_KWQE_OPCODE_INIT1;
79 fcoe_init1.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
80 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
81
82 fcoe_init1.num_tasks = hba->max_tasks;
83 fcoe_init1.sq_num_wqes = BNX2FC_SQ_WQES_MAX;
84 fcoe_init1.rq_num_wqes = BNX2FC_RQ_WQES_MAX;
85 fcoe_init1.rq_buffer_log_size = BNX2FC_RQ_BUF_LOG_SZ;
86 fcoe_init1.cq_num_wqes = BNX2FC_CQ_WQES_MAX;
87 fcoe_init1.dummy_buffer_addr_lo = (u32) hba->dummy_buf_dma;
88 fcoe_init1.dummy_buffer_addr_hi = (u32) ((u64)hba->dummy_buf_dma >> 32);
89 fcoe_init1.task_list_pbl_addr_lo = (u32) hba->task_ctx_bd_dma;
90 fcoe_init1.task_list_pbl_addr_hi =
91 (u32) ((u64) hba->task_ctx_bd_dma >> 32);
92 fcoe_init1.mtu = BNX2FC_MINI_JUMBO_MTU;
93
94 fcoe_init1.flags = (PAGE_SHIFT <<
95 FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT);
96
97 fcoe_init1.num_sessions_log = BNX2FC_NUM_MAX_SESS_LOG;
98
99 /* fill init2 KWQE */
100 memset(&fcoe_init2, 0x00, sizeof(struct fcoe_kwqe_init2));
101 fcoe_init2.hdr.op_code = FCOE_KWQE_OPCODE_INIT2;
102 fcoe_init2.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
103 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
104
105 fcoe_init2.hsi_major_version = FCOE_HSI_MAJOR_VERSION;
106 fcoe_init2.hsi_minor_version = FCOE_HSI_MINOR_VERSION;
107
108
109 fcoe_init2.hash_tbl_pbl_addr_lo = (u32) hba->hash_tbl_pbl_dma;
110 fcoe_init2.hash_tbl_pbl_addr_hi = (u32)
111 ((u64) hba->hash_tbl_pbl_dma >> 32);
112
113 fcoe_init2.t2_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_dma;
114 fcoe_init2.t2_hash_tbl_addr_hi = (u32)
115 ((u64) hba->t2_hash_tbl_dma >> 32);
116
117 fcoe_init2.t2_ptr_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_ptr_dma;
118 fcoe_init2.t2_ptr_hash_tbl_addr_hi = (u32)
119 ((u64) hba->t2_hash_tbl_ptr_dma >> 32);
120
121 fcoe_init2.free_list_count = BNX2FC_NUM_MAX_SESS;
122
123 /* fill init3 KWQE */
124 memset(&fcoe_init3, 0x00, sizeof(struct fcoe_kwqe_init3));
125 fcoe_init3.hdr.op_code = FCOE_KWQE_OPCODE_INIT3;
126 fcoe_init3.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
127 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
128 fcoe_init3.error_bit_map_lo = 0xffffffff;
129 fcoe_init3.error_bit_map_hi = 0xffffffff;
130
131 /*
132 * enable both cached connection and cached tasks
133 * 0 = none, 1 = cached connection, 2 = cached tasks, 3 = both
134 */
135 fcoe_init3.perf_config = 3;
136
137 kwqe_arr[0] = (struct kwqe *) &fcoe_init1;
138 kwqe_arr[1] = (struct kwqe *) &fcoe_init2;
139 kwqe_arr[2] = (struct kwqe *) &fcoe_init3;
140
141 if (hba->cnic && hba->cnic->submit_kwqes)
142 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
143
144 return rc;
145 }
146 int bnx2fc_send_fw_fcoe_destroy_msg(struct bnx2fc_hba *hba)
147 {
148 struct fcoe_kwqe_destroy fcoe_destroy;
149 struct kwqe *kwqe_arr[2];
150 int num_kwqes = 1;
151 int rc = -1;
152
153 /* fill destroy KWQE */
154 memset(&fcoe_destroy, 0x00, sizeof(struct fcoe_kwqe_destroy));
155 fcoe_destroy.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY;
156 fcoe_destroy.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
157 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
158 kwqe_arr[0] = (struct kwqe *) &fcoe_destroy;
159
160 if (hba->cnic && hba->cnic->submit_kwqes)
161 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
162 return rc;
163 }
164
165 /**
166 * bnx2fc_send_session_ofld_req - initiates FCoE Session offload process
167 *
168 * @port: port structure pointer
169 * @tgt: bnx2fc_rport structure pointer
170 */
171 int bnx2fc_send_session_ofld_req(struct fcoe_port *port,
172 struct bnx2fc_rport *tgt)
173 {
174 struct fc_lport *lport = port->lport;
175 struct bnx2fc_interface *interface = port->priv;
176 struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface);
177 struct bnx2fc_hba *hba = interface->hba;
178 struct kwqe *kwqe_arr[4];
179 struct fcoe_kwqe_conn_offload1 ofld_req1;
180 struct fcoe_kwqe_conn_offload2 ofld_req2;
181 struct fcoe_kwqe_conn_offload3 ofld_req3;
182 struct fcoe_kwqe_conn_offload4 ofld_req4;
183 struct fc_rport_priv *rdata = tgt->rdata;
184 struct fc_rport *rport = tgt->rport;
185 int num_kwqes = 4;
186 u32 port_id;
187 int rc = 0;
188 u16 conn_id;
189
190 /* Initialize offload request 1 structure */
191 memset(&ofld_req1, 0x00, sizeof(struct fcoe_kwqe_conn_offload1));
192
193 ofld_req1.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN1;
194 ofld_req1.hdr.flags =
195 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
196
197
198 conn_id = (u16)tgt->fcoe_conn_id;
199 ofld_req1.fcoe_conn_id = conn_id;
200
201
202 ofld_req1.sq_addr_lo = (u32) tgt->sq_dma;
203 ofld_req1.sq_addr_hi = (u32)((u64) tgt->sq_dma >> 32);
204
205 ofld_req1.rq_pbl_addr_lo = (u32) tgt->rq_pbl_dma;
206 ofld_req1.rq_pbl_addr_hi = (u32)((u64) tgt->rq_pbl_dma >> 32);
207
208 ofld_req1.rq_first_pbe_addr_lo = (u32) tgt->rq_dma;
209 ofld_req1.rq_first_pbe_addr_hi =
210 (u32)((u64) tgt->rq_dma >> 32);
211
212 ofld_req1.rq_prod = 0x8000;
213
214 /* Initialize offload request 2 structure */
215 memset(&ofld_req2, 0x00, sizeof(struct fcoe_kwqe_conn_offload2));
216
217 ofld_req2.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN2;
218 ofld_req2.hdr.flags =
219 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
220
221 ofld_req2.tx_max_fc_pay_len = rdata->maxframe_size;
222
223 ofld_req2.cq_addr_lo = (u32) tgt->cq_dma;
224 ofld_req2.cq_addr_hi = (u32)((u64)tgt->cq_dma >> 32);
225
226 ofld_req2.xferq_addr_lo = (u32) tgt->xferq_dma;
227 ofld_req2.xferq_addr_hi = (u32)((u64)tgt->xferq_dma >> 32);
228
229 ofld_req2.conn_db_addr_lo = (u32)tgt->conn_db_dma;
230 ofld_req2.conn_db_addr_hi = (u32)((u64)tgt->conn_db_dma >> 32);
231
232 /* Initialize offload request 3 structure */
233 memset(&ofld_req3, 0x00, sizeof(struct fcoe_kwqe_conn_offload3));
234
235 ofld_req3.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN3;
236 ofld_req3.hdr.flags =
237 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
238
239 ofld_req3.vlan_tag = interface->vlan_id <<
240 FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT;
241 ofld_req3.vlan_tag |= 3 << FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT;
242
243 port_id = fc_host_port_id(lport->host);
244 if (port_id == 0) {
245 BNX2FC_HBA_DBG(lport, "ofld_req: port_id = 0, link down?\n");
246 return -EINVAL;
247 }
248
249 /*
250 * Store s_id of the initiator for further reference. This will
251 * be used during disable/destroy during linkdown processing as
252 * when the lport is reset, the port_id also is reset to 0
253 */
254 tgt->sid = port_id;
255 ofld_req3.s_id[0] = (port_id & 0x000000FF);
256 ofld_req3.s_id[1] = (port_id & 0x0000FF00) >> 8;
257 ofld_req3.s_id[2] = (port_id & 0x00FF0000) >> 16;
258
259 port_id = rport->port_id;
260 ofld_req3.d_id[0] = (port_id & 0x000000FF);
261 ofld_req3.d_id[1] = (port_id & 0x0000FF00) >> 8;
262 ofld_req3.d_id[2] = (port_id & 0x00FF0000) >> 16;
263
264 ofld_req3.tx_total_conc_seqs = rdata->max_seq;
265
266 ofld_req3.tx_max_conc_seqs_c3 = rdata->max_seq;
267 ofld_req3.rx_max_fc_pay_len = lport->mfs;
268
269 ofld_req3.rx_total_conc_seqs = BNX2FC_MAX_SEQS;
270 ofld_req3.rx_max_conc_seqs_c3 = BNX2FC_MAX_SEQS;
271 ofld_req3.rx_open_seqs_exch_c3 = 1;
272
273 ofld_req3.confq_first_pbe_addr_lo = tgt->confq_dma;
274 ofld_req3.confq_first_pbe_addr_hi = (u32)((u64) tgt->confq_dma >> 32);
275
276 /* set mul_n_port_ids supported flag to 0, until it is supported */
277 ofld_req3.flags = 0;
278 /*
279 ofld_req3.flags |= (((lport->send_sp_features & FC_SP_FT_MNA) ? 1:0) <<
280 FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT);
281 */
282 /* Info from PLOGI response */
283 ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_EDTR) ? 1 : 0) <<
284 FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT);
285
286 ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_SEQC) ? 1 : 0) <<
287 FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT);
288
289 /*
290 * Info from PRLI response, this info is used for sequence level error
291 * recovery support
292 */
293 if (tgt->dev_type == TYPE_TAPE) {
294 ofld_req3.flags |= 1 <<
295 FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT;
296 ofld_req3.flags |= (((rdata->flags & FC_RP_FLAGS_REC_SUPPORTED)
297 ? 1 : 0) <<
298 FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT);
299 }
300
301 /* vlan flag */
302 ofld_req3.flags |= (interface->vlan_enabled <<
303 FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT);
304
305 /* C2_VALID and ACK flags are not set as they are not supported */
306
307
308 /* Initialize offload request 4 structure */
309 memset(&ofld_req4, 0x00, sizeof(struct fcoe_kwqe_conn_offload4));
310 ofld_req4.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN4;
311 ofld_req4.hdr.flags =
312 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
313
314 ofld_req4.e_d_tov_timer_val = lport->e_d_tov / 20;
315
316
317 ofld_req4.src_mac_addr_lo[0] = port->data_src_addr[5];
318 /* local mac */
319 ofld_req4.src_mac_addr_lo[1] = port->data_src_addr[4];
320 ofld_req4.src_mac_addr_mid[0] = port->data_src_addr[3];
321 ofld_req4.src_mac_addr_mid[1] = port->data_src_addr[2];
322 ofld_req4.src_mac_addr_hi[0] = port->data_src_addr[1];
323 ofld_req4.src_mac_addr_hi[1] = port->data_src_addr[0];
324 ofld_req4.dst_mac_addr_lo[0] = ctlr->dest_addr[5];
325 /* fcf mac */
326 ofld_req4.dst_mac_addr_lo[1] = ctlr->dest_addr[4];
327 ofld_req4.dst_mac_addr_mid[0] = ctlr->dest_addr[3];
328 ofld_req4.dst_mac_addr_mid[1] = ctlr->dest_addr[2];
329 ofld_req4.dst_mac_addr_hi[0] = ctlr->dest_addr[1];
330 ofld_req4.dst_mac_addr_hi[1] = ctlr->dest_addr[0];
331
332 ofld_req4.lcq_addr_lo = (u32) tgt->lcq_dma;
333 ofld_req4.lcq_addr_hi = (u32)((u64) tgt->lcq_dma >> 32);
334
335 ofld_req4.confq_pbl_base_addr_lo = (u32) tgt->confq_pbl_dma;
336 ofld_req4.confq_pbl_base_addr_hi =
337 (u32)((u64) tgt->confq_pbl_dma >> 32);
338
339 kwqe_arr[0] = (struct kwqe *) &ofld_req1;
340 kwqe_arr[1] = (struct kwqe *) &ofld_req2;
341 kwqe_arr[2] = (struct kwqe *) &ofld_req3;
342 kwqe_arr[3] = (struct kwqe *) &ofld_req4;
343
344 if (hba->cnic && hba->cnic->submit_kwqes)
345 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
346
347 return rc;
348 }
349
350 /**
351 * bnx2fc_send_session_enable_req - initiates FCoE Session enablement
352 *
353 * @port: port structure pointer
354 * @tgt: bnx2fc_rport structure pointer
355 */
356 int bnx2fc_send_session_enable_req(struct fcoe_port *port,
357 struct bnx2fc_rport *tgt)
358 {
359 struct kwqe *kwqe_arr[2];
360 struct bnx2fc_interface *interface = port->priv;
361 struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface);
362 struct bnx2fc_hba *hba = interface->hba;
363 struct fcoe_kwqe_conn_enable_disable enbl_req;
364 struct fc_lport *lport = port->lport;
365 struct fc_rport *rport = tgt->rport;
366 int num_kwqes = 1;
367 int rc = 0;
368 u32 port_id;
369
370 memset(&enbl_req, 0x00,
371 sizeof(struct fcoe_kwqe_conn_enable_disable));
372 enbl_req.hdr.op_code = FCOE_KWQE_OPCODE_ENABLE_CONN;
373 enbl_req.hdr.flags =
374 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
375
376 enbl_req.src_mac_addr_lo[0] = port->data_src_addr[5];
377 /* local mac */
378 enbl_req.src_mac_addr_lo[1] = port->data_src_addr[4];
379 enbl_req.src_mac_addr_mid[0] = port->data_src_addr[3];
380 enbl_req.src_mac_addr_mid[1] = port->data_src_addr[2];
381 enbl_req.src_mac_addr_hi[0] = port->data_src_addr[1];
382 enbl_req.src_mac_addr_hi[1] = port->data_src_addr[0];
383 memcpy(tgt->src_addr, port->data_src_addr, ETH_ALEN);
384
385 enbl_req.dst_mac_addr_lo[0] = ctlr->dest_addr[5];
386 enbl_req.dst_mac_addr_lo[1] = ctlr->dest_addr[4];
387 enbl_req.dst_mac_addr_mid[0] = ctlr->dest_addr[3];
388 enbl_req.dst_mac_addr_mid[1] = ctlr->dest_addr[2];
389 enbl_req.dst_mac_addr_hi[0] = ctlr->dest_addr[1];
390 enbl_req.dst_mac_addr_hi[1] = ctlr->dest_addr[0];
391
392 port_id = fc_host_port_id(lport->host);
393 if (port_id != tgt->sid) {
394 printk(KERN_ERR PFX "WARN: enable_req port_id = 0x%x,"
395 "sid = 0x%x\n", port_id, tgt->sid);
396 port_id = tgt->sid;
397 }
398 enbl_req.s_id[0] = (port_id & 0x000000FF);
399 enbl_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
400 enbl_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
401
402 port_id = rport->port_id;
403 enbl_req.d_id[0] = (port_id & 0x000000FF);
404 enbl_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
405 enbl_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
406 enbl_req.vlan_tag = interface->vlan_id <<
407 FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
408 enbl_req.vlan_tag |= 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
409 enbl_req.vlan_flag = interface->vlan_enabled;
410 enbl_req.context_id = tgt->context_id;
411 enbl_req.conn_id = tgt->fcoe_conn_id;
412
413 kwqe_arr[0] = (struct kwqe *) &enbl_req;
414
415 if (hba->cnic && hba->cnic->submit_kwqes)
416 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
417 return rc;
418 }
419
420 /**
421 * bnx2fc_send_session_disable_req - initiates FCoE Session disable
422 *
423 * @port: port structure pointer
424 * @tgt: bnx2fc_rport structure pointer
425 */
426 int bnx2fc_send_session_disable_req(struct fcoe_port *port,
427 struct bnx2fc_rport *tgt)
428 {
429 struct bnx2fc_interface *interface = port->priv;
430 struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface);
431 struct bnx2fc_hba *hba = interface->hba;
432 struct fcoe_kwqe_conn_enable_disable disable_req;
433 struct kwqe *kwqe_arr[2];
434 struct fc_rport *rport = tgt->rport;
435 int num_kwqes = 1;
436 int rc = 0;
437 u32 port_id;
438
439 memset(&disable_req, 0x00,
440 sizeof(struct fcoe_kwqe_conn_enable_disable));
441 disable_req.hdr.op_code = FCOE_KWQE_OPCODE_DISABLE_CONN;
442 disable_req.hdr.flags =
443 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
444
445 disable_req.src_mac_addr_lo[0] = tgt->src_addr[5];
446 disable_req.src_mac_addr_lo[1] = tgt->src_addr[4];
447 disable_req.src_mac_addr_mid[0] = tgt->src_addr[3];
448 disable_req.src_mac_addr_mid[1] = tgt->src_addr[2];
449 disable_req.src_mac_addr_hi[0] = tgt->src_addr[1];
450 disable_req.src_mac_addr_hi[1] = tgt->src_addr[0];
451
452 disable_req.dst_mac_addr_lo[0] = ctlr->dest_addr[5];
453 disable_req.dst_mac_addr_lo[1] = ctlr->dest_addr[4];
454 disable_req.dst_mac_addr_mid[0] = ctlr->dest_addr[3];
455 disable_req.dst_mac_addr_mid[1] = ctlr->dest_addr[2];
456 disable_req.dst_mac_addr_hi[0] = ctlr->dest_addr[1];
457 disable_req.dst_mac_addr_hi[1] = ctlr->dest_addr[0];
458
459 port_id = tgt->sid;
460 disable_req.s_id[0] = (port_id & 0x000000FF);
461 disable_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
462 disable_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
463
464
465 port_id = rport->port_id;
466 disable_req.d_id[0] = (port_id & 0x000000FF);
467 disable_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
468 disable_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
469 disable_req.context_id = tgt->context_id;
470 disable_req.conn_id = tgt->fcoe_conn_id;
471 disable_req.vlan_tag = interface->vlan_id <<
472 FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
473 disable_req.vlan_tag |=
474 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
475 disable_req.vlan_flag = interface->vlan_enabled;
476
477 kwqe_arr[0] = (struct kwqe *) &disable_req;
478
479 if (hba->cnic && hba->cnic->submit_kwqes)
480 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
481
482 return rc;
483 }
484
485 /**
486 * bnx2fc_send_session_destroy_req - initiates FCoE Session destroy
487 *
488 * @port: port structure pointer
489 * @tgt: bnx2fc_rport structure pointer
490 */
491 int bnx2fc_send_session_destroy_req(struct bnx2fc_hba *hba,
492 struct bnx2fc_rport *tgt)
493 {
494 struct fcoe_kwqe_conn_destroy destroy_req;
495 struct kwqe *kwqe_arr[2];
496 int num_kwqes = 1;
497 int rc = 0;
498
499 memset(&destroy_req, 0x00, sizeof(struct fcoe_kwqe_conn_destroy));
500 destroy_req.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY_CONN;
501 destroy_req.hdr.flags =
502 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
503
504 destroy_req.context_id = tgt->context_id;
505 destroy_req.conn_id = tgt->fcoe_conn_id;
506
507 kwqe_arr[0] = (struct kwqe *) &destroy_req;
508
509 if (hba->cnic && hba->cnic->submit_kwqes)
510 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
511
512 return rc;
513 }
514
515 static bool is_valid_lport(struct bnx2fc_hba *hba, struct fc_lport *lport)
516 {
517 struct bnx2fc_lport *blport;
518
519 spin_lock_bh(&hba->hba_lock);
520 list_for_each_entry(blport, &hba->vports, list) {
521 if (blport->lport == lport) {
522 spin_unlock_bh(&hba->hba_lock);
523 return true;
524 }
525 }
526 spin_unlock_bh(&hba->hba_lock);
527 return false;
528
529 }
530
531
532 static void bnx2fc_unsol_els_work(struct work_struct *work)
533 {
534 struct bnx2fc_unsol_els *unsol_els;
535 struct fc_lport *lport;
536 struct bnx2fc_hba *hba;
537 struct fc_frame *fp;
538
539 unsol_els = container_of(work, struct bnx2fc_unsol_els, unsol_els_work);
540 lport = unsol_els->lport;
541 fp = unsol_els->fp;
542 hba = unsol_els->hba;
543 if (is_valid_lport(hba, lport))
544 fc_exch_recv(lport, fp);
545 kfree(unsol_els);
546 }
547
548 void bnx2fc_process_l2_frame_compl(struct bnx2fc_rport *tgt,
549 unsigned char *buf,
550 u32 frame_len, u16 l2_oxid)
551 {
552 struct fcoe_port *port = tgt->port;
553 struct fc_lport *lport = port->lport;
554 struct bnx2fc_interface *interface = port->priv;
555 struct bnx2fc_unsol_els *unsol_els;
556 struct fc_frame_header *fh;
557 struct fc_frame *fp;
558 struct sk_buff *skb;
559 u32 payload_len;
560 u32 crc;
561 u8 op;
562
563
564 unsol_els = kzalloc(sizeof(*unsol_els), GFP_ATOMIC);
565 if (!unsol_els) {
566 BNX2FC_TGT_DBG(tgt, "Unable to allocate unsol_work\n");
567 return;
568 }
569
570 BNX2FC_TGT_DBG(tgt, "l2_frame_compl l2_oxid = 0x%x, frame_len = %d\n",
571 l2_oxid, frame_len);
572
573 payload_len = frame_len - sizeof(struct fc_frame_header);
574
575 fp = fc_frame_alloc(lport, payload_len);
576 if (!fp) {
577 printk(KERN_ERR PFX "fc_frame_alloc failure\n");
578 kfree(unsol_els);
579 return;
580 }
581
582 fh = (struct fc_frame_header *) fc_frame_header_get(fp);
583 /* Copy FC Frame header and payload into the frame */
584 memcpy(fh, buf, frame_len);
585
586 if (l2_oxid != FC_XID_UNKNOWN)
587 fh->fh_ox_id = htons(l2_oxid);
588
589 skb = fp_skb(fp);
590
591 if ((fh->fh_r_ctl == FC_RCTL_ELS_REQ) ||
592 (fh->fh_r_ctl == FC_RCTL_ELS_REP)) {
593
594 if (fh->fh_type == FC_TYPE_ELS) {
595 op = fc_frame_payload_op(fp);
596 if ((op == ELS_TEST) || (op == ELS_ESTC) ||
597 (op == ELS_FAN) || (op == ELS_CSU)) {
598 /*
599 * No need to reply for these
600 * ELS requests
601 */
602 printk(KERN_ERR PFX "dropping ELS 0x%x\n", op);
603 kfree_skb(skb);
604 kfree(unsol_els);
605 return;
606 }
607 }
608 crc = fcoe_fc_crc(fp);
609 fc_frame_init(fp);
610 fr_dev(fp) = lport;
611 fr_sof(fp) = FC_SOF_I3;
612 fr_eof(fp) = FC_EOF_T;
613 fr_crc(fp) = cpu_to_le32(~crc);
614 unsol_els->lport = lport;
615 unsol_els->hba = interface->hba;
616 unsol_els->fp = fp;
617 INIT_WORK(&unsol_els->unsol_els_work, bnx2fc_unsol_els_work);
618 queue_work(bnx2fc_wq, &unsol_els->unsol_els_work);
619 } else {
620 BNX2FC_HBA_DBG(lport, "fh_r_ctl = 0x%x\n", fh->fh_r_ctl);
621 kfree_skb(skb);
622 kfree(unsol_els);
623 }
624 }
625
626 static void bnx2fc_process_unsol_compl(struct bnx2fc_rport *tgt, u16 wqe)
627 {
628 u8 num_rq;
629 struct fcoe_err_report_entry *err_entry;
630 unsigned char *rq_data;
631 unsigned char *buf = NULL, *buf1;
632 int i;
633 u16 xid;
634 u32 frame_len, len;
635 struct bnx2fc_cmd *io_req = NULL;
636 struct bnx2fc_interface *interface = tgt->port->priv;
637 struct bnx2fc_hba *hba = interface->hba;
638 int task_idx, index;
639 int rc = 0;
640 u64 err_warn_bit_map;
641 u8 err_warn = 0xff;
642
643
644 BNX2FC_TGT_DBG(tgt, "Entered UNSOL COMPLETION wqe = 0x%x\n", wqe);
645 switch (wqe & FCOE_UNSOLICITED_CQE_SUBTYPE) {
646 case FCOE_UNSOLICITED_FRAME_CQE_TYPE:
647 frame_len = (wqe & FCOE_UNSOLICITED_CQE_PKT_LEN) >>
648 FCOE_UNSOLICITED_CQE_PKT_LEN_SHIFT;
649
650 num_rq = (frame_len + BNX2FC_RQ_BUF_SZ - 1) / BNX2FC_RQ_BUF_SZ;
651
652 spin_lock_bh(&tgt->tgt_lock);
653 rq_data = (unsigned char *)bnx2fc_get_next_rqe(tgt, num_rq);
654 spin_unlock_bh(&tgt->tgt_lock);
655
656 if (rq_data) {
657 buf = rq_data;
658 } else {
659 buf1 = buf = kmalloc((num_rq * BNX2FC_RQ_BUF_SZ),
660 GFP_ATOMIC);
661
662 if (!buf1) {
663 BNX2FC_TGT_DBG(tgt, "Memory alloc failure\n");
664 break;
665 }
666
667 for (i = 0; i < num_rq; i++) {
668 spin_lock_bh(&tgt->tgt_lock);
669 rq_data = (unsigned char *)
670 bnx2fc_get_next_rqe(tgt, 1);
671 spin_unlock_bh(&tgt->tgt_lock);
672 len = BNX2FC_RQ_BUF_SZ;
673 memcpy(buf1, rq_data, len);
674 buf1 += len;
675 }
676 }
677 bnx2fc_process_l2_frame_compl(tgt, buf, frame_len,
678 FC_XID_UNKNOWN);
679
680 if (buf != rq_data)
681 kfree(buf);
682 spin_lock_bh(&tgt->tgt_lock);
683 bnx2fc_return_rqe(tgt, num_rq);
684 spin_unlock_bh(&tgt->tgt_lock);
685 break;
686
687 case FCOE_ERROR_DETECTION_CQE_TYPE:
688 /*
689 * In case of error reporting CQE a single RQ entry
690 * is consumed.
691 */
692 spin_lock_bh(&tgt->tgt_lock);
693 num_rq = 1;
694 err_entry = (struct fcoe_err_report_entry *)
695 bnx2fc_get_next_rqe(tgt, 1);
696 xid = err_entry->fc_hdr.ox_id;
697 BNX2FC_TGT_DBG(tgt, "Unsol Error Frame OX_ID = 0x%x\n", xid);
698 BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x\n",
699 err_entry->data.err_warn_bitmap_hi,
700 err_entry->data.err_warn_bitmap_lo);
701 BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x\n",
702 err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
703
704
705 if (xid > hba->max_xid) {
706 BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n",
707 xid);
708 goto ret_err_rqe;
709 }
710
711 task_idx = xid / BNX2FC_TASKS_PER_PAGE;
712 index = xid % BNX2FC_TASKS_PER_PAGE;
713
714 io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
715 if (!io_req)
716 goto ret_err_rqe;
717
718 if (io_req->cmd_type != BNX2FC_SCSI_CMD) {
719 printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n");
720 goto ret_err_rqe;
721 }
722
723 if (test_and_clear_bit(BNX2FC_FLAG_IO_CLEANUP,
724 &io_req->req_flags)) {
725 BNX2FC_IO_DBG(io_req, "unsol_err: cleanup in "
726 "progress.. ignore unsol err\n");
727 goto ret_err_rqe;
728 }
729
730 err_warn_bit_map = (u64)
731 ((u64)err_entry->data.err_warn_bitmap_hi << 32) |
732 (u64)err_entry->data.err_warn_bitmap_lo;
733 for (i = 0; i < BNX2FC_NUM_ERR_BITS; i++) {
734 if (err_warn_bit_map & (u64)((u64)1 << i)) {
735 err_warn = i;
736 break;
737 }
738 }
739
740 /*
741 * If ABTS is already in progress, and FW error is
742 * received after that, do not cancel the timeout_work
743 * and let the error recovery continue by explicitly
744 * logging out the target, when the ABTS eventually
745 * times out.
746 */
747 if (test_bit(BNX2FC_FLAG_ISSUE_ABTS, &io_req->req_flags)) {
748 printk(KERN_ERR PFX "err_warn: io_req (0x%x) already "
749 "in ABTS processing\n", xid);
750 goto ret_err_rqe;
751 }
752 BNX2FC_TGT_DBG(tgt, "err = 0x%x\n", err_warn);
753 if (tgt->dev_type != TYPE_TAPE)
754 goto skip_rec;
755 switch (err_warn) {
756 case FCOE_ERROR_CODE_REC_TOV_TIMER_EXPIRATION:
757 case FCOE_ERROR_CODE_DATA_OOO_RO:
758 case FCOE_ERROR_CODE_COMMON_INCORRECT_SEQ_CNT:
759 case FCOE_ERROR_CODE_DATA_SOFI3_SEQ_ACTIVE_SET:
760 case FCOE_ERROR_CODE_FCP_RSP_OPENED_SEQ:
761 case FCOE_ERROR_CODE_DATA_SOFN_SEQ_ACTIVE_RESET:
762 BNX2FC_TGT_DBG(tgt, "REC TOV popped for xid - 0x%x\n",
763 xid);
764 memcpy(&io_req->err_entry, err_entry,
765 sizeof(struct fcoe_err_report_entry));
766 if (!test_bit(BNX2FC_FLAG_SRR_SENT,
767 &io_req->req_flags)) {
768 spin_unlock_bh(&tgt->tgt_lock);
769 rc = bnx2fc_send_rec(io_req);
770 spin_lock_bh(&tgt->tgt_lock);
771
772 if (rc)
773 goto skip_rec;
774 } else
775 printk(KERN_ERR PFX "SRR in progress\n");
776 goto ret_err_rqe;
777 break;
778 default:
779 break;
780 }
781
782 skip_rec:
783 set_bit(BNX2FC_FLAG_ISSUE_ABTS, &io_req->req_flags);
784 /*
785 * Cancel the timeout_work, as we received IO
786 * completion with FW error.
787 */
788 if (cancel_delayed_work(&io_req->timeout_work))
789 kref_put(&io_req->refcount, bnx2fc_cmd_release);
790
791 rc = bnx2fc_initiate_abts(io_req);
792 if (rc != SUCCESS) {
793 printk(KERN_ERR PFX "err_warn: initiate_abts "
794 "failed xid = 0x%x. issue cleanup\n",
795 io_req->xid);
796 bnx2fc_initiate_cleanup(io_req);
797 }
798 ret_err_rqe:
799 bnx2fc_return_rqe(tgt, 1);
800 spin_unlock_bh(&tgt->tgt_lock);
801 break;
802
803 case FCOE_WARNING_DETECTION_CQE_TYPE:
804 /*
805 *In case of warning reporting CQE a single RQ entry
806 * is consumes.
807 */
808 spin_lock_bh(&tgt->tgt_lock);
809 num_rq = 1;
810 err_entry = (struct fcoe_err_report_entry *)
811 bnx2fc_get_next_rqe(tgt, 1);
812 xid = cpu_to_be16(err_entry->fc_hdr.ox_id);
813 BNX2FC_TGT_DBG(tgt, "Unsol Warning Frame OX_ID = 0x%x\n", xid);
814 BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x",
815 err_entry->data.err_warn_bitmap_hi,
816 err_entry->data.err_warn_bitmap_lo);
817 BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x",
818 err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
819
820 if (xid > hba->max_xid) {
821 BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n", xid);
822 goto ret_warn_rqe;
823 }
824
825 err_warn_bit_map = (u64)
826 ((u64)err_entry->data.err_warn_bitmap_hi << 32) |
827 (u64)err_entry->data.err_warn_bitmap_lo;
828 for (i = 0; i < BNX2FC_NUM_ERR_BITS; i++) {
829 if (err_warn_bit_map & ((u64)1 << i)) {
830 err_warn = i;
831 break;
832 }
833 }
834 BNX2FC_TGT_DBG(tgt, "warn = 0x%x\n", err_warn);
835
836 task_idx = xid / BNX2FC_TASKS_PER_PAGE;
837 index = xid % BNX2FC_TASKS_PER_PAGE;
838 io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
839 if (!io_req)
840 goto ret_warn_rqe;
841
842 if (io_req->cmd_type != BNX2FC_SCSI_CMD) {
843 printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n");
844 goto ret_warn_rqe;
845 }
846
847 memcpy(&io_req->err_entry, err_entry,
848 sizeof(struct fcoe_err_report_entry));
849
850 if (err_warn == FCOE_ERROR_CODE_REC_TOV_TIMER_EXPIRATION)
851 /* REC_TOV is not a warning code */
852 BUG_ON(1);
853 else
854 BNX2FC_TGT_DBG(tgt, "Unsolicited warning\n");
855 ret_warn_rqe:
856 bnx2fc_return_rqe(tgt, 1);
857 spin_unlock_bh(&tgt->tgt_lock);
858 break;
859
860 default:
861 printk(KERN_ERR PFX "Unsol Compl: Invalid CQE Subtype\n");
862 break;
863 }
864 }
865
866 void bnx2fc_process_cq_compl(struct bnx2fc_rport *tgt, u16 wqe,
867 unsigned char *rq_data, u8 num_rq,
868 struct fcoe_task_ctx_entry *task)
869 {
870 struct fcoe_port *port = tgt->port;
871 struct bnx2fc_interface *interface = port->priv;
872 struct bnx2fc_hba *hba = interface->hba;
873 struct bnx2fc_cmd *io_req;
874
875 u16 xid;
876 u8 cmd_type;
877 u8 rx_state = 0;
878
879 spin_lock_bh(&tgt->tgt_lock);
880
881 xid = wqe & FCOE_PEND_WQ_CQE_TASK_ID;
882 io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
883
884 if (io_req == NULL) {
885 printk(KERN_ERR PFX "ERROR? cq_compl - io_req is NULL\n");
886 spin_unlock_bh(&tgt->tgt_lock);
887 return;
888 }
889
890 /* Timestamp IO completion time */
891 cmd_type = io_req->cmd_type;
892
893 rx_state = ((task->rxwr_txrd.var_ctx.rx_flags &
894 FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE) >>
895 FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT);
896
897 /* Process other IO completion types */
898 switch (cmd_type) {
899 case BNX2FC_SCSI_CMD:
900 if (rx_state == FCOE_TASK_RX_STATE_COMPLETED) {
901 bnx2fc_process_scsi_cmd_compl(io_req, task, num_rq,
902 rq_data);
903 spin_unlock_bh(&tgt->tgt_lock);
904 return;
905 }
906
907 if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
908 bnx2fc_process_abts_compl(io_req, task, num_rq);
909 else if (rx_state ==
910 FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
911 bnx2fc_process_cleanup_compl(io_req, task, num_rq);
912 else
913 printk(KERN_ERR PFX "Invalid rx state - %d\n",
914 rx_state);
915 break;
916
917 case BNX2FC_TASK_MGMT_CMD:
918 BNX2FC_IO_DBG(io_req, "Processing TM complete\n");
919 bnx2fc_process_tm_compl(io_req, task, num_rq, rq_data);
920 break;
921
922 case BNX2FC_ABTS:
923 /*
924 * ABTS request received by firmware. ABTS response
925 * will be delivered to the task belonging to the IO
926 * that was aborted
927 */
928 BNX2FC_IO_DBG(io_req, "cq_compl- ABTS sent out by fw\n");
929 kref_put(&io_req->refcount, bnx2fc_cmd_release);
930 break;
931
932 case BNX2FC_ELS:
933 if (rx_state == FCOE_TASK_RX_STATE_COMPLETED)
934 bnx2fc_process_els_compl(io_req, task, num_rq);
935 else if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
936 bnx2fc_process_abts_compl(io_req, task, num_rq);
937 else if (rx_state ==
938 FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
939 bnx2fc_process_cleanup_compl(io_req, task, num_rq);
940 else
941 printk(KERN_ERR PFX "Invalid rx state = %d\n",
942 rx_state);
943 break;
944
945 case BNX2FC_CLEANUP:
946 BNX2FC_IO_DBG(io_req, "cq_compl- cleanup resp rcvd\n");
947 kref_put(&io_req->refcount, bnx2fc_cmd_release);
948 break;
949
950 case BNX2FC_SEQ_CLEANUP:
951 BNX2FC_IO_DBG(io_req, "cq_compl(0x%x) - seq cleanup resp\n",
952 io_req->xid);
953 bnx2fc_process_seq_cleanup_compl(io_req, task, rx_state);
954 kref_put(&io_req->refcount, bnx2fc_cmd_release);
955 break;
956
957 default:
958 printk(KERN_ERR PFX "Invalid cmd_type %d\n", cmd_type);
959 break;
960 }
961 spin_unlock_bh(&tgt->tgt_lock);
962 }
963
964 void bnx2fc_arm_cq(struct bnx2fc_rport *tgt)
965 {
966 struct b577xx_fcoe_rx_doorbell *rx_db = &tgt->rx_db;
967 u32 msg;
968
969 wmb();
970 rx_db->doorbell_cq_cons = tgt->cq_cons_idx | (tgt->cq_curr_toggle_bit <<
971 FCOE_CQE_TOGGLE_BIT_SHIFT);
972 msg = *((u32 *)rx_db);
973 writel(cpu_to_le32(msg), tgt->ctx_base);
974
975 }
976
977 static struct bnx2fc_work *bnx2fc_alloc_work(struct bnx2fc_rport *tgt, u16 wqe,
978 unsigned char *rq_data, u8 num_rq,
979 struct fcoe_task_ctx_entry *task)
980 {
981 struct bnx2fc_work *work;
982 work = kzalloc(sizeof(struct bnx2fc_work), GFP_ATOMIC);
983 if (!work)
984 return NULL;
985
986 INIT_LIST_HEAD(&work->list);
987 work->tgt = tgt;
988 work->wqe = wqe;
989 work->num_rq = num_rq;
990 work->task = task;
991 if (rq_data)
992 memcpy(work->rq_data, rq_data, BNX2FC_RQ_BUF_SZ);
993
994 return work;
995 }
996
997 /* Pending work request completion */
998 static bool bnx2fc_pending_work(struct bnx2fc_rport *tgt, unsigned int wqe)
999 {
1000 unsigned int cpu = wqe % num_possible_cpus();
1001 struct bnx2fc_percpu_s *fps;
1002 struct bnx2fc_work *work;
1003 struct fcoe_task_ctx_entry *task;
1004 struct fcoe_task_ctx_entry *task_page;
1005 struct fcoe_port *port = tgt->port;
1006 struct bnx2fc_interface *interface = port->priv;
1007 struct bnx2fc_hba *hba = interface->hba;
1008 unsigned char *rq_data = NULL;
1009 unsigned char rq_data_buff[BNX2FC_RQ_BUF_SZ];
1010 int task_idx, index;
1011 unsigned char *dummy;
1012 u16 xid;
1013 u8 num_rq;
1014 int i;
1015
1016 xid = wqe & FCOE_PEND_WQ_CQE_TASK_ID;
1017 if (xid >= hba->max_tasks) {
1018 pr_err(PFX "ERROR:xid out of range\n");
1019 return false;
1020 }
1021
1022 task_idx = xid / BNX2FC_TASKS_PER_PAGE;
1023 index = xid % BNX2FC_TASKS_PER_PAGE;
1024 task_page = (struct fcoe_task_ctx_entry *)hba->task_ctx[task_idx];
1025 task = &task_page[index];
1026
1027 num_rq = ((task->rxwr_txrd.var_ctx.rx_flags &
1028 FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE) >>
1029 FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT);
1030
1031 memset(rq_data_buff, 0, BNX2FC_RQ_BUF_SZ);
1032
1033 if (!num_rq)
1034 goto num_rq_zero;
1035
1036 rq_data = bnx2fc_get_next_rqe(tgt, 1);
1037
1038 if (num_rq > 1) {
1039 /* We do not need extra sense data */
1040 for (i = 1; i < num_rq; i++)
1041 dummy = bnx2fc_get_next_rqe(tgt, 1);
1042 }
1043
1044 if (rq_data)
1045 memcpy(rq_data_buff, rq_data, BNX2FC_RQ_BUF_SZ);
1046
1047 /* return RQ entries */
1048 for (i = 0; i < num_rq; i++)
1049 bnx2fc_return_rqe(tgt, 1);
1050
1051 num_rq_zero:
1052
1053 fps = &per_cpu(bnx2fc_percpu, cpu);
1054 spin_lock_bh(&fps->fp_work_lock);
1055 if (fps->iothread) {
1056 work = bnx2fc_alloc_work(tgt, wqe, rq_data_buff,
1057 num_rq, task);
1058 if (work) {
1059 list_add_tail(&work->list, &fps->work_list);
1060 wake_up_process(fps->iothread);
1061 spin_unlock_bh(&fps->fp_work_lock);
1062 return true;
1063 }
1064 }
1065 spin_unlock_bh(&fps->fp_work_lock);
1066 bnx2fc_process_cq_compl(tgt, wqe,
1067 rq_data_buff, num_rq, task);
1068
1069 return true;
1070 }
1071
1072 int bnx2fc_process_new_cqes(struct bnx2fc_rport *tgt)
1073 {
1074 struct fcoe_cqe *cq;
1075 u32 cq_cons;
1076 struct fcoe_cqe *cqe;
1077 u32 num_free_sqes = 0;
1078 u32 num_cqes = 0;
1079 u16 wqe;
1080
1081 /*
1082 * cq_lock is a low contention lock used to protect
1083 * the CQ data structure from being freed up during
1084 * the upload operation
1085 */
1086 spin_lock_bh(&tgt->cq_lock);
1087
1088 if (!tgt->cq) {
1089 printk(KERN_ERR PFX "process_new_cqes: cq is NULL\n");
1090 spin_unlock_bh(&tgt->cq_lock);
1091 return 0;
1092 }
1093 cq = tgt->cq;
1094 cq_cons = tgt->cq_cons_idx;
1095 cqe = &cq[cq_cons];
1096
1097 while (((wqe = cqe->wqe) & FCOE_CQE_TOGGLE_BIT) ==
1098 (tgt->cq_curr_toggle_bit <<
1099 FCOE_CQE_TOGGLE_BIT_SHIFT)) {
1100
1101 /* new entry on the cq */
1102 if (wqe & FCOE_CQE_CQE_TYPE) {
1103 /* Unsolicited event notification */
1104 bnx2fc_process_unsol_compl(tgt, wqe);
1105 } else {
1106 if (bnx2fc_pending_work(tgt, wqe))
1107 num_free_sqes++;
1108 }
1109 cqe++;
1110 tgt->cq_cons_idx++;
1111 num_cqes++;
1112
1113 if (tgt->cq_cons_idx == BNX2FC_CQ_WQES_MAX) {
1114 tgt->cq_cons_idx = 0;
1115 cqe = cq;
1116 tgt->cq_curr_toggle_bit =
1117 1 - tgt->cq_curr_toggle_bit;
1118 }
1119 }
1120 if (num_cqes) {
1121 /* Arm CQ only if doorbell is mapped */
1122 if (tgt->ctx_base)
1123 bnx2fc_arm_cq(tgt);
1124 atomic_add(num_free_sqes, &tgt->free_sqes);
1125 }
1126 spin_unlock_bh(&tgt->cq_lock);
1127 return 0;
1128 }
1129
1130 /**
1131 * bnx2fc_fastpath_notification - process global event queue (KCQ)
1132 *
1133 * @hba: adapter structure pointer
1134 * @new_cqe_kcqe: pointer to newly DMA'd KCQ entry
1135 *
1136 * Fast path event notification handler
1137 */
1138 static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
1139 struct fcoe_kcqe *new_cqe_kcqe)
1140 {
1141 u32 conn_id = new_cqe_kcqe->fcoe_conn_id;
1142 struct bnx2fc_rport *tgt = hba->tgt_ofld_list[conn_id];
1143
1144 if (!tgt) {
1145 printk(KERN_ERR PFX "conn_id 0x%x not valid\n", conn_id);
1146 return;
1147 }
1148
1149 bnx2fc_process_new_cqes(tgt);
1150 }
1151
1152 /**
1153 * bnx2fc_process_ofld_cmpl - process FCoE session offload completion
1154 *
1155 * @hba: adapter structure pointer
1156 * @ofld_kcqe: connection offload kcqe pointer
1157 *
1158 * handle session offload completion, enable the session if offload is
1159 * successful.
1160 */
1161 static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
1162 struct fcoe_kcqe *ofld_kcqe)
1163 {
1164 struct bnx2fc_rport *tgt;
1165 struct bnx2fc_interface *interface;
1166 u32 conn_id;
1167 u32 context_id;
1168
1169 conn_id = ofld_kcqe->fcoe_conn_id;
1170 context_id = ofld_kcqe->fcoe_conn_context_id;
1171 tgt = hba->tgt_ofld_list[conn_id];
1172 if (!tgt) {
1173 printk(KERN_ALERT PFX "ERROR:ofld_cmpl: No pending ofld req\n");
1174 return;
1175 }
1176 BNX2FC_TGT_DBG(tgt, "Entered ofld compl - context_id = 0x%x\n",
1177 ofld_kcqe->fcoe_conn_context_id);
1178 interface = tgt->port->priv;
1179 if (hba != interface->hba) {
1180 printk(KERN_ERR PFX "ERROR:ofld_cmpl: HBA mis-match\n");
1181 goto ofld_cmpl_err;
1182 }
1183 /*
1184 * cnic has allocated a context_id for this session; use this
1185 * while enabling the session.
1186 */
1187 tgt->context_id = context_id;
1188 if (ofld_kcqe->completion_status) {
1189 if (ofld_kcqe->completion_status ==
1190 FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE) {
1191 printk(KERN_ERR PFX "unable to allocate FCoE context "
1192 "resources\n");
1193 set_bit(BNX2FC_FLAG_CTX_ALLOC_FAILURE, &tgt->flags);
1194 }
1195 } else {
1196 /* FW offload request successfully completed */
1197 set_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
1198 }
1199 ofld_cmpl_err:
1200 set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
1201 wake_up_interruptible(&tgt->ofld_wait);
1202 }
1203
1204 /**
1205 * bnx2fc_process_enable_conn_cmpl - process FCoE session enable completion
1206 *
1207 * @hba: adapter structure pointer
1208 * @ofld_kcqe: connection offload kcqe pointer
1209 *
1210 * handle session enable completion, mark the rport as ready
1211 */
1212
1213 static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
1214 struct fcoe_kcqe *ofld_kcqe)
1215 {
1216 struct bnx2fc_rport *tgt;
1217 struct bnx2fc_interface *interface;
1218 u32 conn_id;
1219 u32 context_id;
1220
1221 context_id = ofld_kcqe->fcoe_conn_context_id;
1222 conn_id = ofld_kcqe->fcoe_conn_id;
1223 tgt = hba->tgt_ofld_list[conn_id];
1224 if (!tgt) {
1225 printk(KERN_ERR PFX "ERROR:enbl_cmpl: No pending ofld req\n");
1226 return;
1227 }
1228
1229 BNX2FC_TGT_DBG(tgt, "Enable compl - context_id = 0x%x\n",
1230 ofld_kcqe->fcoe_conn_context_id);
1231
1232 /*
1233 * context_id should be the same for this target during offload
1234 * and enable
1235 */
1236 if (tgt->context_id != context_id) {
1237 printk(KERN_ERR PFX "context id mis-match\n");
1238 return;
1239 }
1240 interface = tgt->port->priv;
1241 if (hba != interface->hba) {
1242 printk(KERN_ERR PFX "bnx2fc-enbl_cmpl: HBA mis-match\n");
1243 goto enbl_cmpl_err;
1244 }
1245 if (!ofld_kcqe->completion_status)
1246 /* enable successful - rport ready for issuing IOs */
1247 set_bit(BNX2FC_FLAG_ENABLED, &tgt->flags);
1248
1249 enbl_cmpl_err:
1250 set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
1251 wake_up_interruptible(&tgt->ofld_wait);
1252 }
1253
1254 static void bnx2fc_process_conn_disable_cmpl(struct bnx2fc_hba *hba,
1255 struct fcoe_kcqe *disable_kcqe)
1256 {
1257
1258 struct bnx2fc_rport *tgt;
1259 u32 conn_id;
1260
1261 conn_id = disable_kcqe->fcoe_conn_id;
1262 tgt = hba->tgt_ofld_list[conn_id];
1263 if (!tgt) {
1264 printk(KERN_ERR PFX "ERROR: disable_cmpl: No disable req\n");
1265 return;
1266 }
1267
1268 BNX2FC_TGT_DBG(tgt, PFX "disable_cmpl: conn_id %d\n", conn_id);
1269
1270 if (disable_kcqe->completion_status) {
1271 printk(KERN_ERR PFX "Disable failed with cmpl status %d\n",
1272 disable_kcqe->completion_status);
1273 set_bit(BNX2FC_FLAG_DISABLE_FAILED, &tgt->flags);
1274 set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
1275 wake_up_interruptible(&tgt->upld_wait);
1276 } else {
1277 /* disable successful */
1278 BNX2FC_TGT_DBG(tgt, "disable successful\n");
1279 clear_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
1280 clear_bit(BNX2FC_FLAG_ENABLED, &tgt->flags);
1281 set_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
1282 set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
1283 wake_up_interruptible(&tgt->upld_wait);
1284 }
1285 }
1286
1287 static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
1288 struct fcoe_kcqe *destroy_kcqe)
1289 {
1290 struct bnx2fc_rport *tgt;
1291 u32 conn_id;
1292
1293 conn_id = destroy_kcqe->fcoe_conn_id;
1294 tgt = hba->tgt_ofld_list[conn_id];
1295 if (!tgt) {
1296 printk(KERN_ERR PFX "destroy_cmpl: No destroy req\n");
1297 return;
1298 }
1299
1300 BNX2FC_TGT_DBG(tgt, "destroy_cmpl: conn_id %d\n", conn_id);
1301
1302 if (destroy_kcqe->completion_status) {
1303 printk(KERN_ERR PFX "Destroy conn failed, cmpl status %d\n",
1304 destroy_kcqe->completion_status);
1305 return;
1306 } else {
1307 /* destroy successful */
1308 BNX2FC_TGT_DBG(tgt, "upload successful\n");
1309 clear_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
1310 set_bit(BNX2FC_FLAG_DESTROYED, &tgt->flags);
1311 set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
1312 wake_up_interruptible(&tgt->upld_wait);
1313 }
1314 }
1315
1316 static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code)
1317 {
1318 switch (err_code) {
1319 case FCOE_KCQE_COMPLETION_STATUS_INVALID_OPCODE:
1320 printk(KERN_ERR PFX "init_failure due to invalid opcode\n");
1321 break;
1322
1323 case FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE:
1324 printk(KERN_ERR PFX "init failed due to ctx alloc failure\n");
1325 break;
1326
1327 case FCOE_KCQE_COMPLETION_STATUS_NIC_ERROR:
1328 printk(KERN_ERR PFX "init_failure due to NIC error\n");
1329 break;
1330 case FCOE_KCQE_COMPLETION_STATUS_ERROR:
1331 printk(KERN_ERR PFX "init failure due to compl status err\n");
1332 break;
1333 case FCOE_KCQE_COMPLETION_STATUS_WRONG_HSI_VERSION:
1334 printk(KERN_ERR PFX "init failure due to HSI mismatch\n");
1335 break;
1336 default:
1337 printk(KERN_ERR PFX "Unknown Error code %d\n", err_code);
1338 }
1339 }
1340
1341 /**
1342 * bnx2fc_indicae_kcqe - process KCQE
1343 *
1344 * @hba: adapter structure pointer
1345 * @kcqe: kcqe pointer
1346 * @num_cqe: Number of completion queue elements
1347 *
1348 * Generic KCQ event handler
1349 */
1350 void bnx2fc_indicate_kcqe(void *context, struct kcqe *kcq[],
1351 u32 num_cqe)
1352 {
1353 struct bnx2fc_hba *hba = (struct bnx2fc_hba *)context;
1354 int i = 0;
1355 struct fcoe_kcqe *kcqe = NULL;
1356
1357 while (i < num_cqe) {
1358 kcqe = (struct fcoe_kcqe *) kcq[i++];
1359
1360 switch (kcqe->op_code) {
1361 case FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION:
1362 bnx2fc_fastpath_notification(hba, kcqe);
1363 break;
1364
1365 case FCOE_KCQE_OPCODE_OFFLOAD_CONN:
1366 bnx2fc_process_ofld_cmpl(hba, kcqe);
1367 break;
1368
1369 case FCOE_KCQE_OPCODE_ENABLE_CONN:
1370 bnx2fc_process_enable_conn_cmpl(hba, kcqe);
1371 break;
1372
1373 case FCOE_KCQE_OPCODE_INIT_FUNC:
1374 if (kcqe->completion_status !=
1375 FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
1376 bnx2fc_init_failure(hba,
1377 kcqe->completion_status);
1378 } else {
1379 set_bit(ADAPTER_STATE_UP, &hba->adapter_state);
1380 bnx2fc_get_link_state(hba);
1381 printk(KERN_INFO PFX "[%.2x]: FCOE_INIT passed\n",
1382 (u8)hba->pcidev->bus->number);
1383 }
1384 break;
1385
1386 case FCOE_KCQE_OPCODE_DESTROY_FUNC:
1387 if (kcqe->completion_status !=
1388 FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
1389
1390 printk(KERN_ERR PFX "DESTROY failed\n");
1391 } else {
1392 printk(KERN_ERR PFX "DESTROY success\n");
1393 }
1394 set_bit(BNX2FC_FLAG_DESTROY_CMPL, &hba->flags);
1395 wake_up_interruptible(&hba->destroy_wait);
1396 break;
1397
1398 case FCOE_KCQE_OPCODE_DISABLE_CONN:
1399 bnx2fc_process_conn_disable_cmpl(hba, kcqe);
1400 break;
1401
1402 case FCOE_KCQE_OPCODE_DESTROY_CONN:
1403 bnx2fc_process_conn_destroy_cmpl(hba, kcqe);
1404 break;
1405
1406 case FCOE_KCQE_OPCODE_STAT_FUNC:
1407 if (kcqe->completion_status !=
1408 FCOE_KCQE_COMPLETION_STATUS_SUCCESS)
1409 printk(KERN_ERR PFX "STAT failed\n");
1410 complete(&hba->stat_req_done);
1411 break;
1412
1413 case FCOE_KCQE_OPCODE_FCOE_ERROR:
1414 /* fall thru */
1415 default:
1416 printk(KERN_ERR PFX "unknown opcode 0x%x\n",
1417 kcqe->op_code);
1418 }
1419 }
1420 }
1421
1422 void bnx2fc_add_2_sq(struct bnx2fc_rport *tgt, u16 xid)
1423 {
1424 struct fcoe_sqe *sqe;
1425
1426 sqe = &tgt->sq[tgt->sq_prod_idx];
1427
1428 /* Fill SQ WQE */
1429 sqe->wqe = xid << FCOE_SQE_TASK_ID_SHIFT;
1430 sqe->wqe |= tgt->sq_curr_toggle_bit << FCOE_SQE_TOGGLE_BIT_SHIFT;
1431
1432 /* Advance SQ Prod Idx */
1433 if (++tgt->sq_prod_idx == BNX2FC_SQ_WQES_MAX) {
1434 tgt->sq_prod_idx = 0;
1435 tgt->sq_curr_toggle_bit = 1 - tgt->sq_curr_toggle_bit;
1436 }
1437 }
1438
1439 void bnx2fc_ring_doorbell(struct bnx2fc_rport *tgt)
1440 {
1441 struct b577xx_doorbell_set_prod *sq_db = &tgt->sq_db;
1442 u32 msg;
1443
1444 wmb();
1445 sq_db->prod = tgt->sq_prod_idx |
1446 (tgt->sq_curr_toggle_bit << 15);
1447 msg = *((u32 *)sq_db);
1448 writel(cpu_to_le32(msg), tgt->ctx_base);
1449
1450 }
1451
1452 int bnx2fc_map_doorbell(struct bnx2fc_rport *tgt)
1453 {
1454 u32 context_id = tgt->context_id;
1455 struct fcoe_port *port = tgt->port;
1456 u32 reg_off;
1457 resource_size_t reg_base;
1458 struct bnx2fc_interface *interface = port->priv;
1459 struct bnx2fc_hba *hba = interface->hba;
1460
1461 reg_base = pci_resource_start(hba->pcidev,
1462 BNX2X_DOORBELL_PCI_BAR);
1463 reg_off = (1 << BNX2X_DB_SHIFT) * (context_id & 0x1FFFF);
1464 tgt->ctx_base = ioremap(reg_base + reg_off, 4);
1465 if (!tgt->ctx_base)
1466 return -ENOMEM;
1467 return 0;
1468 }
1469
1470 char *bnx2fc_get_next_rqe(struct bnx2fc_rport *tgt, u8 num_items)
1471 {
1472 char *buf = (char *)tgt->rq + (tgt->rq_cons_idx * BNX2FC_RQ_BUF_SZ);
1473
1474 if (tgt->rq_cons_idx + num_items > BNX2FC_RQ_WQES_MAX)
1475 return NULL;
1476
1477 tgt->rq_cons_idx += num_items;
1478
1479 if (tgt->rq_cons_idx >= BNX2FC_RQ_WQES_MAX)
1480 tgt->rq_cons_idx -= BNX2FC_RQ_WQES_MAX;
1481
1482 return buf;
1483 }
1484
1485 void bnx2fc_return_rqe(struct bnx2fc_rport *tgt, u8 num_items)
1486 {
1487 /* return the rq buffer */
1488 u32 next_prod_idx = tgt->rq_prod_idx + num_items;
1489 if ((next_prod_idx & 0x7fff) == BNX2FC_RQ_WQES_MAX) {
1490 /* Wrap around RQ */
1491 next_prod_idx += 0x8000 - BNX2FC_RQ_WQES_MAX;
1492 }
1493 tgt->rq_prod_idx = next_prod_idx;
1494 tgt->conn_db->rq_prod = tgt->rq_prod_idx;
1495 }
1496
1497 void bnx2fc_init_seq_cleanup_task(struct bnx2fc_cmd *seq_clnp_req,
1498 struct fcoe_task_ctx_entry *task,
1499 struct bnx2fc_cmd *orig_io_req,
1500 u32 offset)
1501 {
1502 struct scsi_cmnd *sc_cmd = orig_io_req->sc_cmd;
1503 struct bnx2fc_rport *tgt = seq_clnp_req->tgt;
1504 struct fcoe_bd_ctx *bd = orig_io_req->bd_tbl->bd_tbl;
1505 struct fcoe_ext_mul_sges_ctx *sgl;
1506 u8 task_type = FCOE_TASK_TYPE_SEQUENCE_CLEANUP;
1507 u8 orig_task_type;
1508 u16 orig_xid = orig_io_req->xid;
1509 u32 context_id = tgt->context_id;
1510 u64 phys_addr = (u64)orig_io_req->bd_tbl->bd_tbl_dma;
1511 u32 orig_offset = offset;
1512 int bd_count;
1513 int orig_task_idx, index;
1514 int i;
1515
1516 memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
1517
1518 if (sc_cmd->sc_data_direction == DMA_TO_DEVICE)
1519 orig_task_type = FCOE_TASK_TYPE_WRITE;
1520 else
1521 orig_task_type = FCOE_TASK_TYPE_READ;
1522
1523 /* Tx flags */
1524 task->txwr_rxrd.const_ctx.tx_flags =
1525 FCOE_TASK_TX_STATE_SEQUENCE_CLEANUP <<
1526 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
1527 /* init flags */
1528 task->txwr_rxrd.const_ctx.init_flags = task_type <<
1529 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
1530 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
1531 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
1532 task->rxwr_txrd.const_ctx.init_flags = context_id <<
1533 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
1534 task->rxwr_txrd.const_ctx.init_flags = context_id <<
1535 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
1536
1537 task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid;
1538
1539 task->txwr_rxrd.union_ctx.cleanup.ctx.rolled_tx_seq_cnt = 0;
1540 task->txwr_rxrd.union_ctx.cleanup.ctx.rolled_tx_data_offset = offset;
1541
1542 bd_count = orig_io_req->bd_tbl->bd_valid;
1543
1544 /* obtain the appropriate bd entry from relative offset */
1545 for (i = 0; i < bd_count; i++) {
1546 if (offset < bd[i].buf_len)
1547 break;
1548 offset -= bd[i].buf_len;
1549 }
1550 phys_addr += (i * sizeof(struct fcoe_bd_ctx));
1551
1552 if (orig_task_type == FCOE_TASK_TYPE_WRITE) {
1553 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
1554 (u32)phys_addr;
1555 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
1556 (u32)((u64)phys_addr >> 32);
1557 task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size =
1558 bd_count;
1559 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_off =
1560 offset; /* adjusted offset */
1561 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_idx = i;
1562 } else {
1563 orig_task_idx = orig_xid / BNX2FC_TASKS_PER_PAGE;
1564 index = orig_xid % BNX2FC_TASKS_PER_PAGE;
1565
1566 /* Multiple SGEs were used for this IO */
1567 sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
1568 sgl->mul_sgl.cur_sge_addr.lo = (u32)phys_addr;
1569 sgl->mul_sgl.cur_sge_addr.hi = (u32)((u64)phys_addr >> 32);
1570 sgl->mul_sgl.sgl_size = bd_count;
1571 sgl->mul_sgl.cur_sge_off = offset; /*adjusted offset */
1572 sgl->mul_sgl.cur_sge_idx = i;
1573
1574 memset(&task->rxwr_only.rx_seq_ctx, 0,
1575 sizeof(struct fcoe_rx_seq_ctx));
1576 task->rxwr_only.rx_seq_ctx.low_exp_ro = orig_offset;
1577 task->rxwr_only.rx_seq_ctx.high_exp_ro = orig_offset;
1578 }
1579 }
1580 void bnx2fc_init_cleanup_task(struct bnx2fc_cmd *io_req,
1581 struct fcoe_task_ctx_entry *task,
1582 u16 orig_xid)
1583 {
1584 u8 task_type = FCOE_TASK_TYPE_EXCHANGE_CLEANUP;
1585 struct bnx2fc_rport *tgt = io_req->tgt;
1586 u32 context_id = tgt->context_id;
1587
1588 memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
1589
1590 /* Tx Write Rx Read */
1591 /* init flags */
1592 task->txwr_rxrd.const_ctx.init_flags = task_type <<
1593 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
1594 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
1595 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
1596 if (tgt->dev_type == TYPE_TAPE)
1597 task->txwr_rxrd.const_ctx.init_flags |=
1598 FCOE_TASK_DEV_TYPE_TAPE <<
1599 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
1600 else
1601 task->txwr_rxrd.const_ctx.init_flags |=
1602 FCOE_TASK_DEV_TYPE_DISK <<
1603 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
1604 task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid;
1605
1606 /* Tx flags */
1607 task->txwr_rxrd.const_ctx.tx_flags =
1608 FCOE_TASK_TX_STATE_EXCHANGE_CLEANUP <<
1609 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
1610
1611 /* Rx Read Tx Write */
1612 task->rxwr_txrd.const_ctx.init_flags = context_id <<
1613 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
1614 task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
1615 FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
1616 }
1617
1618 void bnx2fc_init_mp_task(struct bnx2fc_cmd *io_req,
1619 struct fcoe_task_ctx_entry *task)
1620 {
1621 struct bnx2fc_mp_req *mp_req = &(io_req->mp_req);
1622 struct bnx2fc_rport *tgt = io_req->tgt;
1623 struct fc_frame_header *fc_hdr;
1624 struct fcoe_ext_mul_sges_ctx *sgl;
1625 u8 task_type = 0;
1626 u64 *hdr;
1627 u64 temp_hdr[3];
1628 u32 context_id;
1629
1630
1631 /* Obtain task_type */
1632 if ((io_req->cmd_type == BNX2FC_TASK_MGMT_CMD) ||
1633 (io_req->cmd_type == BNX2FC_ELS)) {
1634 task_type = FCOE_TASK_TYPE_MIDPATH;
1635 } else if (io_req->cmd_type == BNX2FC_ABTS) {
1636 task_type = FCOE_TASK_TYPE_ABTS;
1637 }
1638
1639 memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
1640
1641 /* Setup the task from io_req for easy reference */
1642 io_req->task = task;
1643
1644 BNX2FC_IO_DBG(io_req, "Init MP task for cmd_type = %d task_type = %d\n",
1645 io_req->cmd_type, task_type);
1646
1647 /* Tx only */
1648 if ((task_type == FCOE_TASK_TYPE_MIDPATH) ||
1649 (task_type == FCOE_TASK_TYPE_UNSOLICITED)) {
1650 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
1651 (u32)mp_req->mp_req_bd_dma;
1652 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
1653 (u32)((u64)mp_req->mp_req_bd_dma >> 32);
1654 task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size = 1;
1655 }
1656
1657 /* Tx Write Rx Read */
1658 /* init flags */
1659 task->txwr_rxrd.const_ctx.init_flags = task_type <<
1660 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
1661 if (tgt->dev_type == TYPE_TAPE)
1662 task->txwr_rxrd.const_ctx.init_flags |=
1663 FCOE_TASK_DEV_TYPE_TAPE <<
1664 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
1665 else
1666 task->txwr_rxrd.const_ctx.init_flags |=
1667 FCOE_TASK_DEV_TYPE_DISK <<
1668 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
1669 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
1670 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
1671
1672 /* tx flags */
1673 task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_INIT <<
1674 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
1675
1676 /* Rx Write Tx Read */
1677 task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
1678
1679 /* rx flags */
1680 task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
1681 FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
1682
1683 context_id = tgt->context_id;
1684 task->rxwr_txrd.const_ctx.init_flags = context_id <<
1685 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
1686
1687 fc_hdr = &(mp_req->req_fc_hdr);
1688 if (task_type == FCOE_TASK_TYPE_MIDPATH) {
1689 fc_hdr->fh_ox_id = cpu_to_be16(io_req->xid);
1690 fc_hdr->fh_rx_id = htons(0xffff);
1691 task->rxwr_txrd.var_ctx.rx_id = 0xffff;
1692 } else if (task_type == FCOE_TASK_TYPE_UNSOLICITED) {
1693 fc_hdr->fh_rx_id = cpu_to_be16(io_req->xid);
1694 }
1695
1696 /* Fill FC Header into middle path buffer */
1697 hdr = (u64 *) &task->txwr_rxrd.union_ctx.tx_frame.fc_hdr;
1698 memcpy(temp_hdr, fc_hdr, sizeof(temp_hdr));
1699 hdr[0] = cpu_to_be64(temp_hdr[0]);
1700 hdr[1] = cpu_to_be64(temp_hdr[1]);
1701 hdr[2] = cpu_to_be64(temp_hdr[2]);
1702
1703 /* Rx Only */
1704 if (task_type == FCOE_TASK_TYPE_MIDPATH) {
1705 sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
1706
1707 sgl->mul_sgl.cur_sge_addr.lo = (u32)mp_req->mp_resp_bd_dma;
1708 sgl->mul_sgl.cur_sge_addr.hi =
1709 (u32)((u64)mp_req->mp_resp_bd_dma >> 32);
1710 sgl->mul_sgl.sgl_size = 1;
1711 }
1712 }
1713
1714 void bnx2fc_init_task(struct bnx2fc_cmd *io_req,
1715 struct fcoe_task_ctx_entry *task)
1716 {
1717 u8 task_type;
1718 struct scsi_cmnd *sc_cmd = io_req->sc_cmd;
1719 struct io_bdt *bd_tbl = io_req->bd_tbl;
1720 struct bnx2fc_rport *tgt = io_req->tgt;
1721 struct fcoe_cached_sge_ctx *cached_sge;
1722 struct fcoe_ext_mul_sges_ctx *sgl;
1723 int dev_type = tgt->dev_type;
1724 u64 *fcp_cmnd;
1725 u64 tmp_fcp_cmnd[4];
1726 u32 context_id;
1727 int cnt, i;
1728 int bd_count;
1729
1730 memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
1731
1732 /* Setup the task from io_req for easy reference */
1733 io_req->task = task;
1734
1735 if (sc_cmd->sc_data_direction == DMA_TO_DEVICE)
1736 task_type = FCOE_TASK_TYPE_WRITE;
1737 else
1738 task_type = FCOE_TASK_TYPE_READ;
1739
1740 /* Tx only */
1741 bd_count = bd_tbl->bd_valid;
1742 cached_sge = &task->rxwr_only.union_ctx.read_info.sgl_ctx.cached_sge;
1743 if (task_type == FCOE_TASK_TYPE_WRITE) {
1744 if ((dev_type == TYPE_DISK) && (bd_count == 1)) {
1745 struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
1746
1747 task->txwr_only.sgl_ctx.cached_sge.cur_buf_addr.lo =
1748 cached_sge->cur_buf_addr.lo =
1749 fcoe_bd_tbl->buf_addr_lo;
1750 task->txwr_only.sgl_ctx.cached_sge.cur_buf_addr.hi =
1751 cached_sge->cur_buf_addr.hi =
1752 fcoe_bd_tbl->buf_addr_hi;
1753 task->txwr_only.sgl_ctx.cached_sge.cur_buf_rem =
1754 cached_sge->cur_buf_rem =
1755 fcoe_bd_tbl->buf_len;
1756
1757 task->txwr_rxrd.const_ctx.init_flags |= 1 <<
1758 FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
1759 } else {
1760 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
1761 (u32)bd_tbl->bd_tbl_dma;
1762 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
1763 (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
1764 task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size =
1765 bd_tbl->bd_valid;
1766 }
1767 }
1768
1769 /*Tx Write Rx Read */
1770 /* Init state to NORMAL */
1771 task->txwr_rxrd.const_ctx.init_flags |= task_type <<
1772 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
1773 if (dev_type == TYPE_TAPE) {
1774 task->txwr_rxrd.const_ctx.init_flags |=
1775 FCOE_TASK_DEV_TYPE_TAPE <<
1776 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
1777 io_req->rec_retry = 0;
1778 io_req->rec_retry = 0;
1779 } else
1780 task->txwr_rxrd.const_ctx.init_flags |=
1781 FCOE_TASK_DEV_TYPE_DISK <<
1782 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
1783 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
1784 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
1785 /* tx flags */
1786 task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_NORMAL <<
1787 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
1788
1789 /* Set initial seq counter */
1790 task->txwr_rxrd.union_ctx.tx_seq.ctx.seq_cnt = 1;
1791
1792 /* Fill FCP_CMND IU */
1793 fcp_cmnd = (u64 *)
1794 task->txwr_rxrd.union_ctx.fcp_cmd.opaque;
1795 bnx2fc_build_fcp_cmnd(io_req, (struct fcp_cmnd *)&tmp_fcp_cmnd);
1796
1797 /* swap fcp_cmnd */
1798 cnt = sizeof(struct fcp_cmnd) / sizeof(u64);
1799
1800 for (i = 0; i < cnt; i++) {
1801 *fcp_cmnd = cpu_to_be64(tmp_fcp_cmnd[i]);
1802 fcp_cmnd++;
1803 }
1804
1805 /* Rx Write Tx Read */
1806 task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
1807
1808 context_id = tgt->context_id;
1809 task->rxwr_txrd.const_ctx.init_flags = context_id <<
1810 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
1811
1812 /* rx flags */
1813 /* Set state to "waiting for the first packet" */
1814 task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
1815 FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
1816
1817 task->rxwr_txrd.var_ctx.rx_id = 0xffff;
1818
1819 /* Rx Only */
1820 if (task_type != FCOE_TASK_TYPE_READ)
1821 return;
1822
1823 sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
1824 bd_count = bd_tbl->bd_valid;
1825
1826 if (dev_type == TYPE_DISK) {
1827 if (bd_count == 1) {
1828
1829 struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
1830
1831 cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
1832 cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
1833 cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
1834 task->txwr_rxrd.const_ctx.init_flags |= 1 <<
1835 FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
1836 } else if (bd_count == 2) {
1837 struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
1838
1839 cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
1840 cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
1841 cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
1842
1843 fcoe_bd_tbl++;
1844 cached_sge->second_buf_addr.lo =
1845 fcoe_bd_tbl->buf_addr_lo;
1846 cached_sge->second_buf_addr.hi =
1847 fcoe_bd_tbl->buf_addr_hi;
1848 cached_sge->second_buf_rem = fcoe_bd_tbl->buf_len;
1849 task->txwr_rxrd.const_ctx.init_flags |= 1 <<
1850 FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
1851 } else {
1852
1853 sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma;
1854 sgl->mul_sgl.cur_sge_addr.hi =
1855 (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
1856 sgl->mul_sgl.sgl_size = bd_count;
1857 }
1858 } else {
1859 sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma;
1860 sgl->mul_sgl.cur_sge_addr.hi =
1861 (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
1862 sgl->mul_sgl.sgl_size = bd_count;
1863 }
1864 }
1865
1866 /**
1867 * bnx2fc_setup_task_ctx - allocate and map task context
1868 *
1869 * @hba: pointer to adapter structure
1870 *
1871 * allocate memory for task context, and associated BD table to be used
1872 * by firmware
1873 *
1874 */
1875 int bnx2fc_setup_task_ctx(struct bnx2fc_hba *hba)
1876 {
1877 int rc = 0;
1878 struct regpair *task_ctx_bdt;
1879 dma_addr_t addr;
1880 int task_ctx_arr_sz;
1881 int i;
1882
1883 /*
1884 * Allocate task context bd table. A page size of bd table
1885 * can map 256 buffers. Each buffer contains 32 task context
1886 * entries. Hence the limit with one page is 8192 task context
1887 * entries.
1888 */
1889 hba->task_ctx_bd_tbl = dma_alloc_coherent(&hba->pcidev->dev,
1890 PAGE_SIZE,
1891 &hba->task_ctx_bd_dma,
1892 GFP_KERNEL);
1893 if (!hba->task_ctx_bd_tbl) {
1894 printk(KERN_ERR PFX "unable to allocate task context BDT\n");
1895 rc = -1;
1896 goto out;
1897 }
1898
1899 /*
1900 * Allocate task_ctx which is an array of pointers pointing to
1901 * a page containing 32 task contexts
1902 */
1903 task_ctx_arr_sz = (hba->max_tasks / BNX2FC_TASKS_PER_PAGE);
1904 hba->task_ctx = kzalloc((task_ctx_arr_sz * sizeof(void *)),
1905 GFP_KERNEL);
1906 if (!hba->task_ctx) {
1907 printk(KERN_ERR PFX "unable to allocate task context array\n");
1908 rc = -1;
1909 goto out1;
1910 }
1911
1912 /*
1913 * Allocate task_ctx_dma which is an array of dma addresses
1914 */
1915 hba->task_ctx_dma = kmalloc((task_ctx_arr_sz *
1916 sizeof(dma_addr_t)), GFP_KERNEL);
1917 if (!hba->task_ctx_dma) {
1918 printk(KERN_ERR PFX "unable to alloc context mapping array\n");
1919 rc = -1;
1920 goto out2;
1921 }
1922
1923 task_ctx_bdt = (struct regpair *)hba->task_ctx_bd_tbl;
1924 for (i = 0; i < task_ctx_arr_sz; i++) {
1925
1926 hba->task_ctx[i] = dma_alloc_coherent(&hba->pcidev->dev,
1927 PAGE_SIZE,
1928 &hba->task_ctx_dma[i],
1929 GFP_KERNEL);
1930 if (!hba->task_ctx[i]) {
1931 printk(KERN_ERR PFX "unable to alloc task context\n");
1932 rc = -1;
1933 goto out3;
1934 }
1935 addr = (u64)hba->task_ctx_dma[i];
1936 task_ctx_bdt->hi = cpu_to_le32((u64)addr >> 32);
1937 task_ctx_bdt->lo = cpu_to_le32((u32)addr);
1938 task_ctx_bdt++;
1939 }
1940 return 0;
1941
1942 out3:
1943 for (i = 0; i < task_ctx_arr_sz; i++) {
1944 if (hba->task_ctx[i]) {
1945
1946 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
1947 hba->task_ctx[i], hba->task_ctx_dma[i]);
1948 hba->task_ctx[i] = NULL;
1949 }
1950 }
1951
1952 kfree(hba->task_ctx_dma);
1953 hba->task_ctx_dma = NULL;
1954 out2:
1955 kfree(hba->task_ctx);
1956 hba->task_ctx = NULL;
1957 out1:
1958 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
1959 hba->task_ctx_bd_tbl, hba->task_ctx_bd_dma);
1960 hba->task_ctx_bd_tbl = NULL;
1961 out:
1962 return rc;
1963 }
1964
1965 void bnx2fc_free_task_ctx(struct bnx2fc_hba *hba)
1966 {
1967 int task_ctx_arr_sz;
1968 int i;
1969
1970 if (hba->task_ctx_bd_tbl) {
1971 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
1972 hba->task_ctx_bd_tbl,
1973 hba->task_ctx_bd_dma);
1974 hba->task_ctx_bd_tbl = NULL;
1975 }
1976
1977 task_ctx_arr_sz = (hba->max_tasks / BNX2FC_TASKS_PER_PAGE);
1978 if (hba->task_ctx) {
1979 for (i = 0; i < task_ctx_arr_sz; i++) {
1980 if (hba->task_ctx[i]) {
1981 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
1982 hba->task_ctx[i],
1983 hba->task_ctx_dma[i]);
1984 hba->task_ctx[i] = NULL;
1985 }
1986 }
1987 kfree(hba->task_ctx);
1988 hba->task_ctx = NULL;
1989 }
1990
1991 kfree(hba->task_ctx_dma);
1992 hba->task_ctx_dma = NULL;
1993 }
1994
1995 static void bnx2fc_free_hash_table(struct bnx2fc_hba *hba)
1996 {
1997 int i;
1998 int segment_count;
1999 u32 *pbl;
2000
2001 if (hba->hash_tbl_segments) {
2002
2003 pbl = hba->hash_tbl_pbl;
2004 if (pbl) {
2005 segment_count = hba->hash_tbl_segment_count;
2006 for (i = 0; i < segment_count; ++i) {
2007 dma_addr_t dma_address;
2008
2009 dma_address = le32_to_cpu(*pbl);
2010 ++pbl;
2011 dma_address += ((u64)le32_to_cpu(*pbl)) << 32;
2012 ++pbl;
2013 dma_free_coherent(&hba->pcidev->dev,
2014 BNX2FC_HASH_TBL_CHUNK_SIZE,
2015 hba->hash_tbl_segments[i],
2016 dma_address);
2017 }
2018 }
2019
2020 kfree(hba->hash_tbl_segments);
2021 hba->hash_tbl_segments = NULL;
2022 }
2023
2024 if (hba->hash_tbl_pbl) {
2025 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
2026 hba->hash_tbl_pbl,
2027 hba->hash_tbl_pbl_dma);
2028 hba->hash_tbl_pbl = NULL;
2029 }
2030 }
2031
2032 static int bnx2fc_allocate_hash_table(struct bnx2fc_hba *hba)
2033 {
2034 int i;
2035 int hash_table_size;
2036 int segment_count;
2037 int segment_array_size;
2038 int dma_segment_array_size;
2039 dma_addr_t *dma_segment_array;
2040 u32 *pbl;
2041
2042 hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
2043 sizeof(struct fcoe_hash_table_entry);
2044
2045 segment_count = hash_table_size + BNX2FC_HASH_TBL_CHUNK_SIZE - 1;
2046 segment_count /= BNX2FC_HASH_TBL_CHUNK_SIZE;
2047 hba->hash_tbl_segment_count = segment_count;
2048
2049 segment_array_size = segment_count * sizeof(*hba->hash_tbl_segments);
2050 hba->hash_tbl_segments = kzalloc(segment_array_size, GFP_KERNEL);
2051 if (!hba->hash_tbl_segments) {
2052 printk(KERN_ERR PFX "hash table pointers alloc failed\n");
2053 return -ENOMEM;
2054 }
2055 dma_segment_array_size = segment_count * sizeof(*dma_segment_array);
2056 dma_segment_array = kzalloc(dma_segment_array_size, GFP_KERNEL);
2057 if (!dma_segment_array) {
2058 printk(KERN_ERR PFX "hash table pointers (dma) alloc failed\n");
2059 goto cleanup_ht;
2060 }
2061
2062 for (i = 0; i < segment_count; ++i) {
2063 hba->hash_tbl_segments[i] = dma_alloc_coherent(&hba->pcidev->dev,
2064 BNX2FC_HASH_TBL_CHUNK_SIZE,
2065 &dma_segment_array[i],
2066 GFP_KERNEL);
2067 if (!hba->hash_tbl_segments[i]) {
2068 printk(KERN_ERR PFX "hash segment alloc failed\n");
2069 goto cleanup_dma;
2070 }
2071 }
2072
2073 hba->hash_tbl_pbl = dma_alloc_coherent(&hba->pcidev->dev, PAGE_SIZE,
2074 &hba->hash_tbl_pbl_dma,
2075 GFP_KERNEL);
2076 if (!hba->hash_tbl_pbl) {
2077 printk(KERN_ERR PFX "hash table pbl alloc failed\n");
2078 goto cleanup_dma;
2079 }
2080
2081 pbl = hba->hash_tbl_pbl;
2082 for (i = 0; i < segment_count; ++i) {
2083 u64 paddr = dma_segment_array[i];
2084 *pbl = cpu_to_le32((u32) paddr);
2085 ++pbl;
2086 *pbl = cpu_to_le32((u32) (paddr >> 32));
2087 ++pbl;
2088 }
2089 pbl = hba->hash_tbl_pbl;
2090 i = 0;
2091 while (*pbl && *(pbl + 1)) {
2092 u32 lo;
2093 u32 hi;
2094 lo = *pbl;
2095 ++pbl;
2096 hi = *pbl;
2097 ++pbl;
2098 ++i;
2099 }
2100 kfree(dma_segment_array);
2101 return 0;
2102
2103 cleanup_dma:
2104 for (i = 0; i < segment_count; ++i) {
2105 if (hba->hash_tbl_segments[i])
2106 dma_free_coherent(&hba->pcidev->dev,
2107 BNX2FC_HASH_TBL_CHUNK_SIZE,
2108 hba->hash_tbl_segments[i],
2109 dma_segment_array[i]);
2110 }
2111
2112 kfree(dma_segment_array);
2113
2114 cleanup_ht:
2115 kfree(hba->hash_tbl_segments);
2116 hba->hash_tbl_segments = NULL;
2117 return -ENOMEM;
2118 }
2119
2120 /**
2121 * bnx2fc_setup_fw_resc - Allocate and map hash table and dummy buffer
2122 *
2123 * @hba: Pointer to adapter structure
2124 *
2125 */
2126 int bnx2fc_setup_fw_resc(struct bnx2fc_hba *hba)
2127 {
2128 u64 addr;
2129 u32 mem_size;
2130 int i;
2131
2132 if (bnx2fc_allocate_hash_table(hba))
2133 return -ENOMEM;
2134
2135 mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
2136 hba->t2_hash_tbl_ptr = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
2137 &hba->t2_hash_tbl_ptr_dma,
2138 GFP_KERNEL);
2139 if (!hba->t2_hash_tbl_ptr) {
2140 printk(KERN_ERR PFX "unable to allocate t2 hash table ptr\n");
2141 bnx2fc_free_fw_resc(hba);
2142 return -ENOMEM;
2143 }
2144
2145 mem_size = BNX2FC_NUM_MAX_SESS *
2146 sizeof(struct fcoe_t2_hash_table_entry);
2147 hba->t2_hash_tbl = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
2148 &hba->t2_hash_tbl_dma,
2149 GFP_KERNEL);
2150 if (!hba->t2_hash_tbl) {
2151 printk(KERN_ERR PFX "unable to allocate t2 hash table\n");
2152 bnx2fc_free_fw_resc(hba);
2153 return -ENOMEM;
2154 }
2155 for (i = 0; i < BNX2FC_NUM_MAX_SESS; i++) {
2156 addr = (unsigned long) hba->t2_hash_tbl_dma +
2157 ((i+1) * sizeof(struct fcoe_t2_hash_table_entry));
2158 hba->t2_hash_tbl[i].next.lo = addr & 0xffffffff;
2159 hba->t2_hash_tbl[i].next.hi = addr >> 32;
2160 }
2161
2162 hba->dummy_buffer = dma_alloc_coherent(&hba->pcidev->dev,
2163 PAGE_SIZE, &hba->dummy_buf_dma,
2164 GFP_KERNEL);
2165 if (!hba->dummy_buffer) {
2166 printk(KERN_ERR PFX "unable to alloc MP Dummy Buffer\n");
2167 bnx2fc_free_fw_resc(hba);
2168 return -ENOMEM;
2169 }
2170
2171 hba->stats_buffer = dma_alloc_coherent(&hba->pcidev->dev, PAGE_SIZE,
2172 &hba->stats_buf_dma,
2173 GFP_KERNEL);
2174 if (!hba->stats_buffer) {
2175 printk(KERN_ERR PFX "unable to alloc Stats Buffer\n");
2176 bnx2fc_free_fw_resc(hba);
2177 return -ENOMEM;
2178 }
2179
2180 return 0;
2181 }
2182
2183 void bnx2fc_free_fw_resc(struct bnx2fc_hba *hba)
2184 {
2185 u32 mem_size;
2186
2187 if (hba->stats_buffer) {
2188 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
2189 hba->stats_buffer, hba->stats_buf_dma);
2190 hba->stats_buffer = NULL;
2191 }
2192
2193 if (hba->dummy_buffer) {
2194 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
2195 hba->dummy_buffer, hba->dummy_buf_dma);
2196 hba->dummy_buffer = NULL;
2197 }
2198
2199 if (hba->t2_hash_tbl_ptr) {
2200 mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
2201 dma_free_coherent(&hba->pcidev->dev, mem_size,
2202 hba->t2_hash_tbl_ptr,
2203 hba->t2_hash_tbl_ptr_dma);
2204 hba->t2_hash_tbl_ptr = NULL;
2205 }
2206
2207 if (hba->t2_hash_tbl) {
2208 mem_size = BNX2FC_NUM_MAX_SESS *
2209 sizeof(struct fcoe_t2_hash_table_entry);
2210 dma_free_coherent(&hba->pcidev->dev, mem_size,
2211 hba->t2_hash_tbl, hba->t2_hash_tbl_dma);
2212 hba->t2_hash_tbl = NULL;
2213 }
2214 bnx2fc_free_hash_table(hba);
2215 }
Linux with added FPC-III support