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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / scsi / pm8001 / pm8001_hwi.c
blobfb9848e1d481c1da09a3434c619e547e332770d7
1 /*
2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm8001_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45
46 /**
47 * read_main_config_table - read the configure table and save it.
48 * @pm8001_ha: our hba card information
49 */
50 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
51 {
52 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
53 pm8001_ha->main_cfg_tbl.pm8001_tbl.signature =
54 pm8001_mr32(address, 0x00);
55 pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev =
56 pm8001_mr32(address, 0x04);
57 pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev =
58 pm8001_mr32(address, 0x08);
59 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io =
60 pm8001_mr32(address, 0x0C);
61 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl =
62 pm8001_mr32(address, 0x10);
63 pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag =
64 pm8001_mr32(address, 0x14);
65 pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset =
66 pm8001_mr32(address, 0x18);
67 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset =
68 pm8001_mr32(address, MAIN_IBQ_OFFSET);
69 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset =
70 pm8001_mr32(address, MAIN_OBQ_OFFSET);
71 pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag =
72 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
73
74 /* read analog Setting offset from the configuration table */
75 pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset =
76 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
77
78 /* read Error Dump Offset and Length */
79 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 =
80 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
81 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 =
82 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
83 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 =
84 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
85 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 =
86 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
87 }
88
89 /**
90 * read_general_status_table - read the general status table and save it.
91 * @pm8001_ha: our hba card information
92 */
93 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
94 {
95 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
96 pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate =
97 pm8001_mr32(address, 0x00);
98 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0 =
99 pm8001_mr32(address, 0x04);
100 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1 =
101 pm8001_mr32(address, 0x08);
102 pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt =
103 pm8001_mr32(address, 0x0C);
104 pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt =
105 pm8001_mr32(address, 0x10);
106 pm8001_ha->gs_tbl.pm8001_tbl.rsvd =
107 pm8001_mr32(address, 0x14);
108 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0] =
109 pm8001_mr32(address, 0x18);
110 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1] =
111 pm8001_mr32(address, 0x1C);
112 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2] =
113 pm8001_mr32(address, 0x20);
114 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3] =
115 pm8001_mr32(address, 0x24);
116 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4] =
117 pm8001_mr32(address, 0x28);
118 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5] =
119 pm8001_mr32(address, 0x2C);
120 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6] =
121 pm8001_mr32(address, 0x30);
122 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7] =
123 pm8001_mr32(address, 0x34);
124 pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val =
125 pm8001_mr32(address, 0x38);
126 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0] =
127 pm8001_mr32(address, 0x3C);
128 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1] =
129 pm8001_mr32(address, 0x40);
130 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0] =
131 pm8001_mr32(address, 0x44);
132 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1] =
133 pm8001_mr32(address, 0x48);
134 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2] =
135 pm8001_mr32(address, 0x4C);
136 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3] =
137 pm8001_mr32(address, 0x50);
138 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4] =
139 pm8001_mr32(address, 0x54);
140 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5] =
141 pm8001_mr32(address, 0x58);
142 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6] =
143 pm8001_mr32(address, 0x5C);
144 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7] =
145 pm8001_mr32(address, 0x60);
146 }
147
148 /**
149 * read_inbnd_queue_table - read the inbound queue table and save it.
150 * @pm8001_ha: our hba card information
151 */
152 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
153 {
154 int i;
155 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
156 for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
157 u32 offset = i * 0x20;
158 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
159 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
160 pm8001_ha->inbnd_q_tbl[i].pi_offset =
161 pm8001_mr32(address, (offset + 0x18));
162 }
163 }
164
165 /**
166 * read_outbnd_queue_table - read the outbound queue table and save it.
167 * @pm8001_ha: our hba card information
168 */
169 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
170 {
171 int i;
172 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
173 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
174 u32 offset = i * 0x24;
175 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
176 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
177 pm8001_ha->outbnd_q_tbl[i].ci_offset =
178 pm8001_mr32(address, (offset + 0x18));
179 }
180 }
181
182 /**
183 * init_default_table_values - init the default table.
184 * @pm8001_ha: our hba card information
185 */
186 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
187 {
188 int i;
189 u32 offsetib, offsetob;
190 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
191 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
192
193 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd = 0;
194 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3 = 0;
195 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7 = 0;
196 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3 = 0;
197 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7 = 0;
198 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 =
199 0;
200 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 =
201 0;
202 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
203 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
204 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0;
205 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0;
206
207 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr =
208 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
209 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr =
210 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
211 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size =
212 PM8001_EVENT_LOG_SIZE;
213 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option = 0x01;
214 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr =
215 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
216 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr =
217 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
218 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size =
219 PM8001_EVENT_LOG_SIZE;
220 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option = 0x01;
221 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt = 0x01;
222 for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
223 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
224 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
225 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
226 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
227 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
228 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
229 pm8001_ha->inbnd_q_tbl[i].base_virt =
230 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
231 pm8001_ha->inbnd_q_tbl[i].total_length =
232 pm8001_ha->memoryMap.region[IB + i].total_len;
233 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
234 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
235 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
236 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
237 pm8001_ha->inbnd_q_tbl[i].ci_virt =
238 pm8001_ha->memoryMap.region[CI + i].virt_ptr;
239 offsetib = i * 0x20;
240 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
241 get_pci_bar_index(pm8001_mr32(addressib,
242 (offsetib + 0x14)));
243 pm8001_ha->inbnd_q_tbl[i].pi_offset =
244 pm8001_mr32(addressib, (offsetib + 0x18));
245 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
246 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
247 }
248 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
249 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
250 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
251 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
252 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
253 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
254 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
255 pm8001_ha->outbnd_q_tbl[i].base_virt =
256 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
257 pm8001_ha->outbnd_q_tbl[i].total_length =
258 pm8001_ha->memoryMap.region[OB + i].total_len;
259 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
260 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
261 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
262 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
263 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay =
264 0 | (10 << 16) | (i << 24);
265 pm8001_ha->outbnd_q_tbl[i].pi_virt =
266 pm8001_ha->memoryMap.region[PI + i].virt_ptr;
267 offsetob = i * 0x24;
268 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
269 get_pci_bar_index(pm8001_mr32(addressob,
270 offsetob + 0x14));
271 pm8001_ha->outbnd_q_tbl[i].ci_offset =
272 pm8001_mr32(addressob, (offsetob + 0x18));
273 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
274 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
275 }
276 }
277
278 /**
279 * update_main_config_table - update the main default table to the HBA.
280 * @pm8001_ha: our hba card information
281 */
282 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
283 {
284 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
285 pm8001_mw32(address, 0x24,
286 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd);
287 pm8001_mw32(address, 0x28,
288 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3);
289 pm8001_mw32(address, 0x2C,
290 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7);
291 pm8001_mw32(address, 0x30,
292 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3);
293 pm8001_mw32(address, 0x34,
294 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7);
295 pm8001_mw32(address, 0x38,
296 pm8001_ha->main_cfg_tbl.pm8001_tbl.
297 outbound_tgt_ITNexus_event_pid0_3);
298 pm8001_mw32(address, 0x3C,
299 pm8001_ha->main_cfg_tbl.pm8001_tbl.
300 outbound_tgt_ITNexus_event_pid4_7);
301 pm8001_mw32(address, 0x40,
302 pm8001_ha->main_cfg_tbl.pm8001_tbl.
303 outbound_tgt_ssp_event_pid0_3);
304 pm8001_mw32(address, 0x44,
305 pm8001_ha->main_cfg_tbl.pm8001_tbl.
306 outbound_tgt_ssp_event_pid4_7);
307 pm8001_mw32(address, 0x48,
308 pm8001_ha->main_cfg_tbl.pm8001_tbl.
309 outbound_tgt_smp_event_pid0_3);
310 pm8001_mw32(address, 0x4C,
311 pm8001_ha->main_cfg_tbl.pm8001_tbl.
312 outbound_tgt_smp_event_pid4_7);
313 pm8001_mw32(address, 0x50,
314 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr);
315 pm8001_mw32(address, 0x54,
316 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr);
317 pm8001_mw32(address, 0x58,
318 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size);
319 pm8001_mw32(address, 0x5C,
320 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option);
321 pm8001_mw32(address, 0x60,
322 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr);
323 pm8001_mw32(address, 0x64,
324 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr);
325 pm8001_mw32(address, 0x68,
326 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size);
327 pm8001_mw32(address, 0x6C,
328 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option);
329 pm8001_mw32(address, 0x70,
330 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt);
331 }
332
333 /**
334 * update_inbnd_queue_table - update the inbound queue table to the HBA.
335 * @pm8001_ha: our hba card information
336 */
337 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
338 int number)
339 {
340 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
341 u16 offset = number * 0x20;
342 pm8001_mw32(address, offset + 0x00,
343 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
344 pm8001_mw32(address, offset + 0x04,
345 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
346 pm8001_mw32(address, offset + 0x08,
347 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
348 pm8001_mw32(address, offset + 0x0C,
349 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
350 pm8001_mw32(address, offset + 0x10,
351 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
352 }
353
354 /**
355 * update_outbnd_queue_table - update the outbound queue table to the HBA.
356 * @pm8001_ha: our hba card information
357 */
358 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
359 int number)
360 {
361 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
362 u16 offset = number * 0x24;
363 pm8001_mw32(address, offset + 0x00,
364 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
365 pm8001_mw32(address, offset + 0x04,
366 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
367 pm8001_mw32(address, offset + 0x08,
368 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
369 pm8001_mw32(address, offset + 0x0C,
370 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
371 pm8001_mw32(address, offset + 0x10,
372 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
373 pm8001_mw32(address, offset + 0x1C,
374 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
375 }
376
377 /**
378 * pm8001_bar4_shift - function is called to shift BAR base address
379 * @pm8001_ha : our hba card infomation
380 * @shiftValue : shifting value in memory bar.
381 */
382 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
383 {
384 u32 regVal;
385 unsigned long start;
386
387 /* program the inbound AXI translation Lower Address */
388 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
389
390 /* confirm the setting is written */
391 start = jiffies + HZ; /* 1 sec */
392 do {
393 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
394 } while ((regVal != shiftValue) && time_before(jiffies, start));
395
396 if (regVal != shiftValue) {
397 PM8001_INIT_DBG(pm8001_ha,
398 pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
399 " = 0x%x\n", regVal));
400 return -1;
401 }
402 return 0;
403 }
404
405 /**
406 * mpi_set_phys_g3_with_ssc
407 * @pm8001_ha: our hba card information
408 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
409 */
410 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
411 u32 SSCbit)
412 {
413 u32 value, offset, i;
414 unsigned long flags;
415
416 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
417 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
418 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
419 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
420 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
421 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
422 #define SNW3_PHY_CAPABILITIES_PARITY 31
423
424 /*
425 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
426 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
427 */
428 spin_lock_irqsave(&pm8001_ha->lock, flags);
429 if (-1 == pm8001_bar4_shift(pm8001_ha,
430 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
431 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
432 return;
433 }
434
435 for (i = 0; i < 4; i++) {
436 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
437 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
438 }
439 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
440 if (-1 == pm8001_bar4_shift(pm8001_ha,
441 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
442 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
443 return;
444 }
445 for (i = 4; i < 8; i++) {
446 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
447 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
448 }
449 /*************************************************************
450 Change the SSC upspreading value to 0x0 so that upspreading is disabled.
451 Device MABC SMOD0 Controls
452 Address: (via MEMBASE-III):
453 Using shifted destination address 0x0_0000: with Offset 0xD8
454
455 31:28 R/W Reserved Do not change
456 27:24 R/W SAS_SMOD_SPRDUP 0000
457 23:20 R/W SAS_SMOD_SPRDDN 0000
458 19:0 R/W Reserved Do not change
459 Upon power-up this register will read as 0x8990c016,
460 and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
461 so that the written value will be 0x8090c016.
462 This will ensure only down-spreading SSC is enabled on the SPC.
463 *************************************************************/
464 value = pm8001_cr32(pm8001_ha, 2, 0xd8);
465 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
466
467 /*set the shifted destination address to 0x0 to avoid error operation */
468 pm8001_bar4_shift(pm8001_ha, 0x0);
469 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
470 return;
471 }
472
473 /**
474 * mpi_set_open_retry_interval_reg
475 * @pm8001_ha: our hba card information
476 * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
477 */
478 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
479 u32 interval)
480 {
481 u32 offset;
482 u32 value;
483 u32 i;
484 unsigned long flags;
485
486 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
487 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
488 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
489 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
490 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
491
492 value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
493 spin_lock_irqsave(&pm8001_ha->lock, flags);
494 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
495 if (-1 == pm8001_bar4_shift(pm8001_ha,
496 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
497 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
498 return;
499 }
500 for (i = 0; i < 4; i++) {
501 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
502 pm8001_cw32(pm8001_ha, 2, offset, value);
503 }
504
505 if (-1 == pm8001_bar4_shift(pm8001_ha,
506 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
507 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
508 return;
509 }
510 for (i = 4; i < 8; i++) {
511 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
512 pm8001_cw32(pm8001_ha, 2, offset, value);
513 }
514 /*set the shifted destination address to 0x0 to avoid error operation */
515 pm8001_bar4_shift(pm8001_ha, 0x0);
516 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
517 return;
518 }
519
520 /**
521 * mpi_init_check - check firmware initialization status.
522 * @pm8001_ha: our hba card information
523 */
524 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
525 {
526 u32 max_wait_count;
527 u32 value;
528 u32 gst_len_mpistate;
529 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
530 table is updated */
531 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
532 /* wait until Inbound DoorBell Clear Register toggled */
533 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
534 do {
535 udelay(1);
536 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
537 value &= SPC_MSGU_CFG_TABLE_UPDATE;
538 } while ((value != 0) && (--max_wait_count));
539
540 if (!max_wait_count)
541 return -1;
542 /* check the MPI-State for initialization */
543 gst_len_mpistate =
544 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
545 GST_GSTLEN_MPIS_OFFSET);
546 if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
547 return -1;
548 /* check MPI Initialization error */
549 gst_len_mpistate = gst_len_mpistate >> 16;
550 if (0x0000 != gst_len_mpistate)
551 return -1;
552 return 0;
553 }
554
555 /**
556 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
557 * @pm8001_ha: our hba card information
558 */
559 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
560 {
561 u32 value, value1;
562 u32 max_wait_count;
563 /* check error state */
564 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
565 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
566 /* check AAP error */
567 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
568 /* error state */
569 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
570 return -1;
571 }
572
573 /* check IOP error */
574 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
575 /* error state */
576 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
577 return -1;
578 }
579
580 /* bit 4-31 of scratch pad1 should be zeros if it is not
581 in error state*/
582 if (value & SCRATCH_PAD1_STATE_MASK) {
583 /* error case */
584 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
585 return -1;
586 }
587
588 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
589 in error state */
590 if (value1 & SCRATCH_PAD2_STATE_MASK) {
591 /* error case */
592 return -1;
593 }
594
595 max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
596
597 /* wait until scratch pad 1 and 2 registers in ready state */
598 do {
599 udelay(1);
600 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
601 & SCRATCH_PAD1_RDY;
602 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
603 & SCRATCH_PAD2_RDY;
604 if ((--max_wait_count) == 0)
605 return -1;
606 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
607 return 0;
608 }
609
610 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
611 {
612 void __iomem *base_addr;
613 u32 value;
614 u32 offset;
615 u32 pcibar;
616 u32 pcilogic;
617
618 value = pm8001_cr32(pm8001_ha, 0, 0x44);
619 offset = value & 0x03FFFFFF;
620 PM8001_INIT_DBG(pm8001_ha,
621 pm8001_printk("Scratchpad 0 Offset: %x\n", offset));
622 pcilogic = (value & 0xFC000000) >> 26;
623 pcibar = get_pci_bar_index(pcilogic);
624 PM8001_INIT_DBG(pm8001_ha,
625 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
626 pm8001_ha->main_cfg_tbl_addr = base_addr =
627 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
628 pm8001_ha->general_stat_tbl_addr =
629 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
630 pm8001_ha->inbnd_q_tbl_addr =
631 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
632 pm8001_ha->outbnd_q_tbl_addr =
633 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
634 }
635
636 /**
637 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
638 * @pm8001_ha: our hba card information
639 */
640 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
641 {
642 u8 i = 0;
643 u16 deviceid;
644 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
645 /* 8081 controllers need BAR shift to access MPI space
646 * as this is shared with BIOS data */
647 if (deviceid == 0x8081 || deviceid == 0x0042) {
648 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
649 PM8001_FAIL_DBG(pm8001_ha,
650 pm8001_printk("Shift Bar4 to 0x%x failed\n",
651 GSM_SM_BASE));
652 return -1;
653 }
654 }
655 /* check the firmware status */
656 if (-1 == check_fw_ready(pm8001_ha)) {
657 PM8001_FAIL_DBG(pm8001_ha,
658 pm8001_printk("Firmware is not ready!\n"));
659 return -EBUSY;
660 }
661
662 /* Initialize pci space address eg: mpi offset */
663 init_pci_device_addresses(pm8001_ha);
664 init_default_table_values(pm8001_ha);
665 read_main_config_table(pm8001_ha);
666 read_general_status_table(pm8001_ha);
667 read_inbnd_queue_table(pm8001_ha);
668 read_outbnd_queue_table(pm8001_ha);
669 /* update main config table ,inbound table and outbound table */
670 update_main_config_table(pm8001_ha);
671 for (i = 0; i < PM8001_MAX_INB_NUM; i++)
672 update_inbnd_queue_table(pm8001_ha, i);
673 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++)
674 update_outbnd_queue_table(pm8001_ha, i);
675 /* 8081 controller donot require these operations */
676 if (deviceid != 0x8081 && deviceid != 0x0042) {
677 mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
678 /* 7->130ms, 34->500ms, 119->1.5s */
679 mpi_set_open_retry_interval_reg(pm8001_ha, 119);
680 }
681 /* notify firmware update finished and check initialization status */
682 if (0 == mpi_init_check(pm8001_ha)) {
683 PM8001_INIT_DBG(pm8001_ha,
684 pm8001_printk("MPI initialize successful!\n"));
685 } else
686 return -EBUSY;
687 /*This register is a 16-bit timer with a resolution of 1us. This is the
688 timer used for interrupt delay/coalescing in the PCIe Application Layer.
689 Zero is not a valid value. A value of 1 in the register will cause the
690 interrupts to be normal. A value greater than 1 will cause coalescing
691 delays.*/
692 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
693 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
694 return 0;
695 }
696
697 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
698 {
699 u32 max_wait_count;
700 u32 value;
701 u32 gst_len_mpistate;
702 u16 deviceid;
703 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
704 if (deviceid == 0x8081 || deviceid == 0x0042) {
705 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
706 PM8001_FAIL_DBG(pm8001_ha,
707 pm8001_printk("Shift Bar4 to 0x%x failed\n",
708 GSM_SM_BASE));
709 return -1;
710 }
711 }
712 init_pci_device_addresses(pm8001_ha);
713 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
714 table is stop */
715 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
716
717 /* wait until Inbound DoorBell Clear Register toggled */
718 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
719 do {
720 udelay(1);
721 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
722 value &= SPC_MSGU_CFG_TABLE_RESET;
723 } while ((value != 0) && (--max_wait_count));
724
725 if (!max_wait_count) {
726 PM8001_FAIL_DBG(pm8001_ha,
727 pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
728 return -1;
729 }
730
731 /* check the MPI-State for termination in progress */
732 /* wait until Inbound DoorBell Clear Register toggled */
733 max_wait_count = 1 * 1000 * 1000; /* 1 sec */
734 do {
735 udelay(1);
736 gst_len_mpistate =
737 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
738 GST_GSTLEN_MPIS_OFFSET);
739 if (GST_MPI_STATE_UNINIT ==
740 (gst_len_mpistate & GST_MPI_STATE_MASK))
741 break;
742 } while (--max_wait_count);
743 if (!max_wait_count) {
744 PM8001_FAIL_DBG(pm8001_ha,
745 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
746 gst_len_mpistate & GST_MPI_STATE_MASK));
747 return -1;
748 }
749 return 0;
750 }
751
752 /**
753 * soft_reset_ready_check - Function to check FW is ready for soft reset.
754 * @pm8001_ha: our hba card information
755 */
756 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
757 {
758 u32 regVal, regVal1, regVal2;
759 if (mpi_uninit_check(pm8001_ha) != 0) {
760 PM8001_FAIL_DBG(pm8001_ha,
761 pm8001_printk("MPI state is not ready\n"));
762 return -1;
763 }
764 /* read the scratch pad 2 register bit 2 */
765 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
766 & SCRATCH_PAD2_FWRDY_RST;
767 if (regVal == SCRATCH_PAD2_FWRDY_RST) {
768 PM8001_INIT_DBG(pm8001_ha,
769 pm8001_printk("Firmware is ready for reset .\n"));
770 } else {
771 unsigned long flags;
772 /* Trigger NMI twice via RB6 */
773 spin_lock_irqsave(&pm8001_ha->lock, flags);
774 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
775 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
776 PM8001_FAIL_DBG(pm8001_ha,
777 pm8001_printk("Shift Bar4 to 0x%x failed\n",
778 RB6_ACCESS_REG));
779 return -1;
780 }
781 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
782 RB6_MAGIC_NUMBER_RST);
783 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
784 /* wait for 100 ms */
785 mdelay(100);
786 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
787 SCRATCH_PAD2_FWRDY_RST;
788 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
789 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
790 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
791 PM8001_FAIL_DBG(pm8001_ha,
792 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
793 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
794 regVal1, regVal2));
795 PM8001_FAIL_DBG(pm8001_ha,
796 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
797 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
798 PM8001_FAIL_DBG(pm8001_ha,
799 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
800 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
801 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
802 return -1;
803 }
804 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
805 }
806 return 0;
807 }
808
809 /**
810 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
811 * the FW register status to the originated status.
812 * @pm8001_ha: our hba card information
813 */
814 static int
815 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
816 {
817 u32 regVal, toggleVal;
818 u32 max_wait_count;
819 u32 regVal1, regVal2, regVal3;
820 u32 signature = 0x252acbcd; /* for host scratch pad0 */
821 unsigned long flags;
822
823 /* step1: Check FW is ready for soft reset */
824 if (soft_reset_ready_check(pm8001_ha) != 0) {
825 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
826 return -1;
827 }
828
829 /* step 2: clear NMI status register on AAP1 and IOP, write the same
830 value to clear */
831 /* map 0x60000 to BAR4(0x20), BAR2(win) */
832 spin_lock_irqsave(&pm8001_ha->lock, flags);
833 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
834 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
835 PM8001_FAIL_DBG(pm8001_ha,
836 pm8001_printk("Shift Bar4 to 0x%x failed\n",
837 MBIC_AAP1_ADDR_BASE));
838 return -1;
839 }
840 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
841 PM8001_INIT_DBG(pm8001_ha,
842 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
843 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
844 /* map 0x70000 to BAR4(0x20), BAR2(win) */
845 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
846 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
847 PM8001_FAIL_DBG(pm8001_ha,
848 pm8001_printk("Shift Bar4 to 0x%x failed\n",
849 MBIC_IOP_ADDR_BASE));
850 return -1;
851 }
852 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
853 PM8001_INIT_DBG(pm8001_ha,
854 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
855 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
856
857 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
858 PM8001_INIT_DBG(pm8001_ha,
859 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
860 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
861
862 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
863 PM8001_INIT_DBG(pm8001_ha,
864 pm8001_printk("PCIE - Event Interrupt = 0x%x\n", regVal));
865 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
866
867 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
868 PM8001_INIT_DBG(pm8001_ha,
869 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
870 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
871
872 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
873 PM8001_INIT_DBG(pm8001_ha,
874 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
875 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
876
877 /* read the scratch pad 1 register bit 2 */
878 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
879 & SCRATCH_PAD1_RST;
880 toggleVal = regVal ^ SCRATCH_PAD1_RST;
881
882 /* set signature in host scratch pad0 register to tell SPC that the
883 host performs the soft reset */
884 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
885
886 /* read required registers for confirmming */
887 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
888 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
889 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
890 PM8001_FAIL_DBG(pm8001_ha,
891 pm8001_printk("Shift Bar4 to 0x%x failed\n",
892 GSM_ADDR_BASE));
893 return -1;
894 }
895 PM8001_INIT_DBG(pm8001_ha,
896 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
897 " Reset = 0x%x\n",
898 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
899
900 /* step 3: host read GSM Configuration and Reset register */
901 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
902 /* Put those bits to low */
903 /* GSM XCBI offset = 0x70 0000
904 0x00 Bit 13 COM_SLV_SW_RSTB 1
905 0x00 Bit 12 QSSP_SW_RSTB 1
906 0x00 Bit 11 RAAE_SW_RSTB 1
907 0x00 Bit 9 RB_1_SW_RSTB 1
908 0x00 Bit 8 SM_SW_RSTB 1
909 */
910 regVal &= ~(0x00003b00);
911 /* host write GSM Configuration and Reset register */
912 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
913 PM8001_INIT_DBG(pm8001_ha,
914 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
915 "Configuration and Reset is set to = 0x%x\n",
916 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
917
918 /* step 4: */
919 /* disable GSM - Read Address Parity Check */
920 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
921 PM8001_INIT_DBG(pm8001_ha,
922 pm8001_printk("GSM 0x700038 - Read Address Parity Check "
923 "Enable = 0x%x\n", regVal1));
924 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
925 PM8001_INIT_DBG(pm8001_ha,
926 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
927 "is set to = 0x%x\n",
928 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
929
930 /* disable GSM - Write Address Parity Check */
931 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
932 PM8001_INIT_DBG(pm8001_ha,
933 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
934 " Enable = 0x%x\n", regVal2));
935 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
936 PM8001_INIT_DBG(pm8001_ha,
937 pm8001_printk("GSM 0x700040 - Write Address Parity Check "
938 "Enable is set to = 0x%x\n",
939 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
940
941 /* disable GSM - Write Data Parity Check */
942 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
943 PM8001_INIT_DBG(pm8001_ha,
944 pm8001_printk("GSM 0x300048 - Write Data Parity Check"
945 " Enable = 0x%x\n", regVal3));
946 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
947 PM8001_INIT_DBG(pm8001_ha,
948 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
949 "is set to = 0x%x\n",
950 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
951
952 /* step 5: delay 10 usec */
953 udelay(10);
954 /* step 5-b: set GPIO-0 output control to tristate anyway */
955 if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
956 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
957 PM8001_INIT_DBG(pm8001_ha,
958 pm8001_printk("Shift Bar4 to 0x%x failed\n",
959 GPIO_ADDR_BASE));
960 return -1;
961 }
962 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
963 PM8001_INIT_DBG(pm8001_ha,
964 pm8001_printk("GPIO Output Control Register:"
965 " = 0x%x\n", regVal));
966 /* set GPIO-0 output control to tri-state */
967 regVal &= 0xFFFFFFFC;
968 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
969
970 /* Step 6: Reset the IOP and AAP1 */
971 /* map 0x00000 to BAR4(0x20), BAR2(win) */
972 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
973 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
974 PM8001_FAIL_DBG(pm8001_ha,
975 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
976 SPC_TOP_LEVEL_ADDR_BASE));
977 return -1;
978 }
979 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
980 PM8001_INIT_DBG(pm8001_ha,
981 pm8001_printk("Top Register before resetting IOP/AAP1"
982 ":= 0x%x\n", regVal));
983 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
984 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
985
986 /* step 7: Reset the BDMA/OSSP */
987 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
988 PM8001_INIT_DBG(pm8001_ha,
989 pm8001_printk("Top Register before resetting BDMA/OSSP"
990 ": = 0x%x\n", regVal));
991 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
992 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
993
994 /* step 8: delay 10 usec */
995 udelay(10);
996
997 /* step 9: bring the BDMA and OSSP out of reset */
998 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
999 PM8001_INIT_DBG(pm8001_ha,
1000 pm8001_printk("Top Register before bringing up BDMA/OSSP"
1001 ":= 0x%x\n", regVal));
1002 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
1003 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1004
1005 /* step 10: delay 10 usec */
1006 udelay(10);
1007
1008 /* step 11: reads and sets the GSM Configuration and Reset Register */
1009 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
1010 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
1011 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1012 PM8001_FAIL_DBG(pm8001_ha,
1013 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
1014 GSM_ADDR_BASE));
1015 return -1;
1016 }
1017 PM8001_INIT_DBG(pm8001_ha,
1018 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
1019 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
1020 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
1021 /* Put those bits to high */
1022 /* GSM XCBI offset = 0x70 0000
1023 0x00 Bit 13 COM_SLV_SW_RSTB 1
1024 0x00 Bit 12 QSSP_SW_RSTB 1
1025 0x00 Bit 11 RAAE_SW_RSTB 1
1026 0x00 Bit 9 RB_1_SW_RSTB 1
1027 0x00 Bit 8 SM_SW_RSTB 1
1028 */
1029 regVal |= (GSM_CONFIG_RESET_VALUE);
1030 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
1031 PM8001_INIT_DBG(pm8001_ha,
1032 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
1033 " Configuration and Reset is set to = 0x%x\n",
1034 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
1035
1036 /* step 12: Restore GSM - Read Address Parity Check */
1037 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
1038 /* just for debugging */
1039 PM8001_INIT_DBG(pm8001_ha,
1040 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
1041 " = 0x%x\n", regVal));
1042 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
1043 PM8001_INIT_DBG(pm8001_ha,
1044 pm8001_printk("GSM 0x700038 - Read Address Parity"
1045 " Check Enable is set to = 0x%x\n",
1046 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
1047 /* Restore GSM - Write Address Parity Check */
1048 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
1049 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
1050 PM8001_INIT_DBG(pm8001_ha,
1051 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
1052 " Enable is set to = 0x%x\n",
1053 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
1054 /* Restore GSM - Write Data Parity Check */
1055 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
1056 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
1057 PM8001_INIT_DBG(pm8001_ha,
1058 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
1059 "is set to = 0x%x\n",
1060 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
1061
1062 /* step 13: bring the IOP and AAP1 out of reset */
1063 /* map 0x00000 to BAR4(0x20), BAR2(win) */
1064 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
1065 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1066 PM8001_FAIL_DBG(pm8001_ha,
1067 pm8001_printk("Shift Bar4 to 0x%x failed\n",
1068 SPC_TOP_LEVEL_ADDR_BASE));
1069 return -1;
1070 }
1071 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1072 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1073 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1074
1075 /* step 14: delay 10 usec - Normal Mode */
1076 udelay(10);
1077 /* check Soft Reset Normal mode or Soft Reset HDA mode */
1078 if (signature == SPC_SOFT_RESET_SIGNATURE) {
1079 /* step 15 (Normal Mode): wait until scratch pad1 register
1080 bit 2 toggled */
1081 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1082 do {
1083 udelay(1);
1084 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1085 SCRATCH_PAD1_RST;
1086 } while ((regVal != toggleVal) && (--max_wait_count));
1087
1088 if (!max_wait_count) {
1089 regVal = pm8001_cr32(pm8001_ha, 0,
1090 MSGU_SCRATCH_PAD_1);
1091 PM8001_FAIL_DBG(pm8001_ha,
1092 pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
1093 "MSGU_SCRATCH_PAD1 = 0x%x\n",
1094 toggleVal, regVal));
1095 PM8001_FAIL_DBG(pm8001_ha,
1096 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1097 pm8001_cr32(pm8001_ha, 0,
1098 MSGU_SCRATCH_PAD_0)));
1099 PM8001_FAIL_DBG(pm8001_ha,
1100 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
1101 pm8001_cr32(pm8001_ha, 0,
1102 MSGU_SCRATCH_PAD_2)));
1103 PM8001_FAIL_DBG(pm8001_ha,
1104 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1105 pm8001_cr32(pm8001_ha, 0,
1106 MSGU_SCRATCH_PAD_3)));
1107 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1108 return -1;
1109 }
1110
1111 /* step 16 (Normal) - Clear ODMR and ODCR */
1112 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1113 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1114
1115 /* step 17 (Normal Mode): wait for the FW and IOP to get
1116 ready - 1 sec timeout */
1117 /* Wait for the SPC Configuration Table to be ready */
1118 if (check_fw_ready(pm8001_ha) == -1) {
1119 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1120 /* return error if MPI Configuration Table not ready */
1121 PM8001_INIT_DBG(pm8001_ha,
1122 pm8001_printk("FW not ready SCRATCH_PAD1"
1123 " = 0x%x\n", regVal));
1124 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1125 /* return error if MPI Configuration Table not ready */
1126 PM8001_INIT_DBG(pm8001_ha,
1127 pm8001_printk("FW not ready SCRATCH_PAD2"
1128 " = 0x%x\n", regVal));
1129 PM8001_INIT_DBG(pm8001_ha,
1130 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1131 pm8001_cr32(pm8001_ha, 0,
1132 MSGU_SCRATCH_PAD_0)));
1133 PM8001_INIT_DBG(pm8001_ha,
1134 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1135 pm8001_cr32(pm8001_ha, 0,
1136 MSGU_SCRATCH_PAD_3)));
1137 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1138 return -1;
1139 }
1140 }
1141 pm8001_bar4_shift(pm8001_ha, 0);
1142 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1143
1144 PM8001_INIT_DBG(pm8001_ha,
1145 pm8001_printk("SPC soft reset Complete\n"));
1146 return 0;
1147 }
1148
1149 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1150 {
1151 u32 i;
1152 u32 regVal;
1153 PM8001_INIT_DBG(pm8001_ha,
1154 pm8001_printk("chip reset start\n"));
1155
1156 /* do SPC chip reset. */
1157 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1158 regVal &= ~(SPC_REG_RESET_DEVICE);
1159 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1160
1161 /* delay 10 usec */
1162 udelay(10);
1163
1164 /* bring chip reset out of reset */
1165 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1166 regVal |= SPC_REG_RESET_DEVICE;
1167 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1168
1169 /* delay 10 usec */
1170 udelay(10);
1171
1172 /* wait for 20 msec until the firmware gets reloaded */
1173 i = 20;
1174 do {
1175 mdelay(1);
1176 } while ((--i) != 0);
1177
1178 PM8001_INIT_DBG(pm8001_ha,
1179 pm8001_printk("chip reset finished\n"));
1180 }
1181
1182 /**
1183 * pm8001_chip_iounmap - which maped when initialized.
1184 * @pm8001_ha: our hba card information
1185 */
1186 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1187 {
1188 s8 bar, logical = 0;
1189 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
1190 /*
1191 ** logical BARs for SPC:
1192 ** bar 0 and 1 - logical BAR0
1193 ** bar 2 and 3 - logical BAR1
1194 ** bar4 - logical BAR2
1195 ** bar5 - logical BAR3
1196 ** Skip the appropriate assignments:
1197 */
1198 if ((bar == 1) || (bar == 3))
1199 continue;
1200 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1201 iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1202 logical++;
1203 }
1204 }
1205 }
1206
1207 #ifndef PM8001_USE_MSIX
1208 /**
1209 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1210 * @pm8001_ha: our hba card information
1211 */
1212 static void
1213 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1214 {
1215 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1216 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1217 }
1218
1219 /**
1220 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1221 * @pm8001_ha: our hba card information
1222 */
1223 static void
1224 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1225 {
1226 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1227 }
1228
1229 #else
1230
1231 /**
1232 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1233 * @pm8001_ha: our hba card information
1234 */
1235 static void
1236 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1237 u32 int_vec_idx)
1238 {
1239 u32 msi_index;
1240 u32 value;
1241 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1242 msi_index += MSIX_TABLE_BASE;
1243 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1244 value = (1 << int_vec_idx);
1245 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value);
1246
1247 }
1248
1249 /**
1250 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1251 * @pm8001_ha: our hba card information
1252 */
1253 static void
1254 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1255 u32 int_vec_idx)
1256 {
1257 u32 msi_index;
1258 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1259 msi_index += MSIX_TABLE_BASE;
1260 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE);
1261 }
1262 #endif
1263
1264 /**
1265 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1266 * @pm8001_ha: our hba card information
1267 */
1268 static void
1269 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1270 {
1271 #ifdef PM8001_USE_MSIX
1272 pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1273 #else
1274 pm8001_chip_intx_interrupt_enable(pm8001_ha);
1275 #endif
1276 }
1277
1278 /**
1279 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1280 * @pm8001_ha: our hba card information
1281 */
1282 static void
1283 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1284 {
1285 #ifdef PM8001_USE_MSIX
1286 pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1287 #else
1288 pm8001_chip_intx_interrupt_disable(pm8001_ha);
1289 #endif
1290 }
1291
1292 /**
1293 * pm8001_mpi_msg_free_get - get the free message buffer for transfer
1294 * inbound queue.
1295 * @circularQ: the inbound queue we want to transfer to HBA.
1296 * @messageSize: the message size of this transfer, normally it is 64 bytes
1297 * @messagePtr: the pointer to message.
1298 */
1299 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
1300 u16 messageSize, void **messagePtr)
1301 {
1302 u32 offset, consumer_index;
1303 struct mpi_msg_hdr *msgHeader;
1304 u8 bcCount = 1; /* only support single buffer */
1305
1306 /* Checks is the requested message size can be allocated in this queue*/
1307 if (messageSize > IOMB_SIZE_SPCV) {
1308 *messagePtr = NULL;
1309 return -1;
1310 }
1311
1312 /* Stores the new consumer index */
1313 consumer_index = pm8001_read_32(circularQ->ci_virt);
1314 circularQ->consumer_index = cpu_to_le32(consumer_index);
1315 if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) ==
1316 le32_to_cpu(circularQ->consumer_index)) {
1317 *messagePtr = NULL;
1318 return -1;
1319 }
1320 /* get memory IOMB buffer address */
1321 offset = circularQ->producer_idx * messageSize;
1322 /* increment to next bcCount element */
1323 circularQ->producer_idx = (circularQ->producer_idx + bcCount)
1324 % PM8001_MPI_QUEUE;
1325 /* Adds that distance to the base of the region virtual address plus
1326 the message header size*/
1327 msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1328 *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1329 return 0;
1330 }
1331
1332 /**
1333 * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to
1334 * FW to tell the fw to get this message from IOMB.
1335 * @pm8001_ha: our hba card information
1336 * @circularQ: the inbound queue we want to transfer to HBA.
1337 * @opCode: the operation code represents commands which LLDD and fw recognized.
1338 * @payload: the command payload of each operation command.
1339 * @nb: size in bytes of the command payload
1340 * @responseQueue: queue to interrupt on w/ command response (if any)
1341 */
1342 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1343 struct inbound_queue_table *circularQ,
1344 u32 opCode, void *payload, size_t nb,
1345 u32 responseQueue)
1346 {
1347 u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1348 void *pMessage;
1349
1350 if (pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size,
1351 &pMessage) < 0) {
1352 PM8001_IO_DBG(pm8001_ha,
1353 pm8001_printk("No free mpi buffer\n"));
1354 return -ENOMEM;
1355 }
1356
1357 if (nb > (pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr)))
1358 nb = pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr);
1359 memcpy(pMessage, payload, nb);
1360 if (nb + sizeof(struct mpi_msg_hdr) < pm8001_ha->iomb_size)
1361 memset(pMessage + nb, 0, pm8001_ha->iomb_size -
1362 (nb + sizeof(struct mpi_msg_hdr)));
1363
1364 /*Build the header*/
1365 Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1366 | ((responseQueue & 0x3F) << 16)
1367 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1368
1369 pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1370 /*Update the PI to the firmware*/
1371 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1372 circularQ->pi_offset, circularQ->producer_idx);
1373 PM8001_DEVIO_DBG(pm8001_ha,
1374 pm8001_printk("INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n",
1375 responseQueue, opCode, circularQ->producer_idx,
1376 circularQ->consumer_index));
1377 return 0;
1378 }
1379
1380 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1381 struct outbound_queue_table *circularQ, u8 bc)
1382 {
1383 u32 producer_index;
1384 struct mpi_msg_hdr *msgHeader;
1385 struct mpi_msg_hdr *pOutBoundMsgHeader;
1386
1387 msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1388 pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1389 circularQ->consumer_idx * pm8001_ha->iomb_size);
1390 if (pOutBoundMsgHeader != msgHeader) {
1391 PM8001_FAIL_DBG(pm8001_ha,
1392 pm8001_printk("consumer_idx = %d msgHeader = %p\n",
1393 circularQ->consumer_idx, msgHeader));
1394
1395 /* Update the producer index from SPC */
1396 producer_index = pm8001_read_32(circularQ->pi_virt);
1397 circularQ->producer_index = cpu_to_le32(producer_index);
1398 PM8001_FAIL_DBG(pm8001_ha,
1399 pm8001_printk("consumer_idx = %d producer_index = %d"
1400 "msgHeader = %p\n", circularQ->consumer_idx,
1401 circularQ->producer_index, msgHeader));
1402 return 0;
1403 }
1404 /* free the circular queue buffer elements associated with the message*/
1405 circularQ->consumer_idx = (circularQ->consumer_idx + bc)
1406 % PM8001_MPI_QUEUE;
1407 /* update the CI of outbound queue */
1408 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1409 circularQ->consumer_idx);
1410 /* Update the producer index from SPC*/
1411 producer_index = pm8001_read_32(circularQ->pi_virt);
1412 circularQ->producer_index = cpu_to_le32(producer_index);
1413 PM8001_IO_DBG(pm8001_ha,
1414 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx,
1415 circularQ->producer_index));
1416 return 0;
1417 }
1418
1419 /**
1420 * pm8001_mpi_msg_consume- get the MPI message from outbound queue
1421 * message table.
1422 * @pm8001_ha: our hba card information
1423 * @circularQ: the outbound queue table.
1424 * @messagePtr1: the message contents of this outbound message.
1425 * @pBC: the message size.
1426 */
1427 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1428 struct outbound_queue_table *circularQ,
1429 void **messagePtr1, u8 *pBC)
1430 {
1431 struct mpi_msg_hdr *msgHeader;
1432 __le32 msgHeader_tmp;
1433 u32 header_tmp;
1434 do {
1435 /* If there are not-yet-delivered messages ... */
1436 if (le32_to_cpu(circularQ->producer_index)
1437 != circularQ->consumer_idx) {
1438 /*Get the pointer to the circular queue buffer element*/
1439 msgHeader = (struct mpi_msg_hdr *)
1440 (circularQ->base_virt +
1441 circularQ->consumer_idx * pm8001_ha->iomb_size);
1442 /* read header */
1443 header_tmp = pm8001_read_32(msgHeader);
1444 msgHeader_tmp = cpu_to_le32(header_tmp);
1445 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
1446 "outbound opcode msgheader:%x ci=%d pi=%d\n",
1447 msgHeader_tmp, circularQ->consumer_idx,
1448 circularQ->producer_index));
1449 if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
1450 if (OPC_OUB_SKIP_ENTRY !=
1451 (le32_to_cpu(msgHeader_tmp) & 0xfff)) {
1452 *messagePtr1 =
1453 ((u8 *)msgHeader) +
1454 sizeof(struct mpi_msg_hdr);
1455 *pBC = (u8)((le32_to_cpu(msgHeader_tmp)
1456 >> 24) & 0x1f);
1457 PM8001_IO_DBG(pm8001_ha,
1458 pm8001_printk(": CI=%d PI=%d "
1459 "msgHeader=%x\n",
1460 circularQ->consumer_idx,
1461 circularQ->producer_index,
1462 msgHeader_tmp));
1463 return MPI_IO_STATUS_SUCCESS;
1464 } else {
1465 circularQ->consumer_idx =
1466 (circularQ->consumer_idx +
1467 ((le32_to_cpu(msgHeader_tmp)
1468 >> 24) & 0x1f))
1469 % PM8001_MPI_QUEUE;
1470 msgHeader_tmp = 0;
1471 pm8001_write_32(msgHeader, 0, 0);
1472 /* update the CI of outbound queue */
1473 pm8001_cw32(pm8001_ha,
1474 circularQ->ci_pci_bar,
1475 circularQ->ci_offset,
1476 circularQ->consumer_idx);
1477 }
1478 } else {
1479 circularQ->consumer_idx =
1480 (circularQ->consumer_idx +
1481 ((le32_to_cpu(msgHeader_tmp) >> 24) &
1482 0x1f)) % PM8001_MPI_QUEUE;
1483 msgHeader_tmp = 0;
1484 pm8001_write_32(msgHeader, 0, 0);
1485 /* update the CI of outbound queue */
1486 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1487 circularQ->ci_offset,
1488 circularQ->consumer_idx);
1489 return MPI_IO_STATUS_FAIL;
1490 }
1491 } else {
1492 u32 producer_index;
1493 void *pi_virt = circularQ->pi_virt;
1494 /* spurious interrupt during setup if
1495 * kexec-ing and driver doing a doorbell access
1496 * with the pre-kexec oq interrupt setup
1497 */
1498 if (!pi_virt)
1499 break;
1500 /* Update the producer index from SPC */
1501 producer_index = pm8001_read_32(pi_virt);
1502 circularQ->producer_index = cpu_to_le32(producer_index);
1503 }
1504 } while (le32_to_cpu(circularQ->producer_index) !=
1505 circularQ->consumer_idx);
1506 /* while we don't have any more not-yet-delivered message */
1507 /* report empty */
1508 return MPI_IO_STATUS_BUSY;
1509 }
1510
1511 void pm8001_work_fn(struct work_struct *work)
1512 {
1513 struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
1514 struct pm8001_device *pm8001_dev;
1515 struct domain_device *dev;
1516
1517 /*
1518 * So far, all users of this stash an associated structure here.
1519 * If we get here, and this pointer is null, then the action
1520 * was cancelled. This nullification happens when the device
1521 * goes away.
1522 */
1523 pm8001_dev = pw->data; /* Most stash device structure */
1524 if ((pm8001_dev == NULL)
1525 || ((pw->handler != IO_XFER_ERROR_BREAK)
1526 && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) {
1527 kfree(pw);
1528 return;
1529 }
1530
1531 switch (pw->handler) {
1532 case IO_XFER_ERROR_BREAK:
1533 { /* This one stashes the sas_task instead */
1534 struct sas_task *t = (struct sas_task *)pm8001_dev;
1535 u32 tag;
1536 struct pm8001_ccb_info *ccb;
1537 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1538 unsigned long flags, flags1;
1539 struct task_status_struct *ts;
1540 int i;
1541
1542 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
1543 break; /* Task still on lu */
1544 spin_lock_irqsave(&pm8001_ha->lock, flags);
1545
1546 spin_lock_irqsave(&t->task_state_lock, flags1);
1547 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1548 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1549 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1550 break; /* Task got completed by another */
1551 }
1552 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1553
1554 /* Search for a possible ccb that matches the task */
1555 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1556 ccb = &pm8001_ha->ccb_info[i];
1557 tag = ccb->ccb_tag;
1558 if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1559 break;
1560 }
1561 if (!ccb) {
1562 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1563 break; /* Task got freed by another */
1564 }
1565 ts = &t->task_status;
1566 ts->resp = SAS_TASK_COMPLETE;
1567 /* Force the midlayer to retry */
1568 ts->stat = SAS_QUEUE_FULL;
1569 pm8001_dev = ccb->device;
1570 if (pm8001_dev)
1571 pm8001_dev->running_req--;
1572 spin_lock_irqsave(&t->task_state_lock, flags1);
1573 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1574 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1575 t->task_state_flags |= SAS_TASK_STATE_DONE;
1576 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1577 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1578 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p"
1579 " done with event 0x%x resp 0x%x stat 0x%x but"
1580 " aborted by upper layer!\n",
1581 t, pw->handler, ts->resp, ts->stat));
1582 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1583 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1584 } else {
1585 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1586 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1587 mb();/* in order to force CPU ordering */
1588 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1589 t->task_done(t);
1590 }
1591 } break;
1592 case IO_XFER_OPEN_RETRY_TIMEOUT:
1593 { /* This one stashes the sas_task instead */
1594 struct sas_task *t = (struct sas_task *)pm8001_dev;
1595 u32 tag;
1596 struct pm8001_ccb_info *ccb;
1597 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1598 unsigned long flags, flags1;
1599 int i, ret = 0;
1600
1601 PM8001_IO_DBG(pm8001_ha,
1602 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1603
1604 ret = pm8001_query_task(t);
1605
1606 PM8001_IO_DBG(pm8001_ha,
1607 switch (ret) {
1608 case TMF_RESP_FUNC_SUCC:
1609 pm8001_printk("...Task on lu\n");
1610 break;
1611
1612 case TMF_RESP_FUNC_COMPLETE:
1613 pm8001_printk("...Task NOT on lu\n");
1614 break;
1615
1616 default:
1617 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
1618 "...query task failed!!!\n"));
1619 break;
1620 });
1621
1622 spin_lock_irqsave(&pm8001_ha->lock, flags);
1623
1624 spin_lock_irqsave(&t->task_state_lock, flags1);
1625
1626 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1627 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1628 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1629 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1630 (void)pm8001_abort_task(t);
1631 break; /* Task got completed by another */
1632 }
1633
1634 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1635
1636 /* Search for a possible ccb that matches the task */
1637 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1638 ccb = &pm8001_ha->ccb_info[i];
1639 tag = ccb->ccb_tag;
1640 if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1641 break;
1642 }
1643 if (!ccb) {
1644 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1645 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1646 (void)pm8001_abort_task(t);
1647 break; /* Task got freed by another */
1648 }
1649
1650 pm8001_dev = ccb->device;
1651 dev = pm8001_dev->sas_device;
1652
1653 switch (ret) {
1654 case TMF_RESP_FUNC_SUCC: /* task on lu */
1655 ccb->open_retry = 1; /* Snub completion */
1656 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1657 ret = pm8001_abort_task(t);
1658 ccb->open_retry = 0;
1659 switch (ret) {
1660 case TMF_RESP_FUNC_SUCC:
1661 case TMF_RESP_FUNC_COMPLETE:
1662 break;
1663 default: /* device misbehavior */
1664 ret = TMF_RESP_FUNC_FAILED;
1665 PM8001_IO_DBG(pm8001_ha,
1666 pm8001_printk("...Reset phy\n"));
1667 pm8001_I_T_nexus_reset(dev);
1668 break;
1669 }
1670 break;
1671
1672 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
1673 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1674 /* Do we need to abort the task locally? */
1675 break;
1676
1677 default: /* device misbehavior */
1678 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1679 ret = TMF_RESP_FUNC_FAILED;
1680 PM8001_IO_DBG(pm8001_ha,
1681 pm8001_printk("...Reset phy\n"));
1682 pm8001_I_T_nexus_reset(dev);
1683 }
1684
1685 if (ret == TMF_RESP_FUNC_FAILED)
1686 t = NULL;
1687 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
1688 PM8001_IO_DBG(pm8001_ha, pm8001_printk("...Complete\n"));
1689 } break;
1690 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1691 dev = pm8001_dev->sas_device;
1692 pm8001_I_T_nexus_event_handler(dev);
1693 break;
1694 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1695 dev = pm8001_dev->sas_device;
1696 pm8001_I_T_nexus_reset(dev);
1697 break;
1698 case IO_DS_IN_ERROR:
1699 dev = pm8001_dev->sas_device;
1700 pm8001_I_T_nexus_reset(dev);
1701 break;
1702 case IO_DS_NON_OPERATIONAL:
1703 dev = pm8001_dev->sas_device;
1704 pm8001_I_T_nexus_reset(dev);
1705 break;
1706 }
1707 kfree(pw);
1708 }
1709
1710 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1711 int handler)
1712 {
1713 struct pm8001_work *pw;
1714 int ret = 0;
1715
1716 pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1717 if (pw) {
1718 pw->pm8001_ha = pm8001_ha;
1719 pw->data = data;
1720 pw->handler = handler;
1721 INIT_WORK(&pw->work, pm8001_work_fn);
1722 queue_work(pm8001_wq, &pw->work);
1723 } else
1724 ret = -ENOMEM;
1725
1726 return ret;
1727 }
1728
1729 static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1730 struct pm8001_device *pm8001_ha_dev)
1731 {
1732 int res;
1733 u32 ccb_tag;
1734 struct pm8001_ccb_info *ccb;
1735 struct sas_task *task = NULL;
1736 struct task_abort_req task_abort;
1737 struct inbound_queue_table *circularQ;
1738 u32 opc = OPC_INB_SATA_ABORT;
1739 int ret;
1740
1741 if (!pm8001_ha_dev) {
1742 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1743 return;
1744 }
1745
1746 task = sas_alloc_slow_task(GFP_ATOMIC);
1747
1748 if (!task) {
1749 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1750 "allocate task\n"));
1751 return;
1752 }
1753
1754 task->task_done = pm8001_task_done;
1755
1756 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1757 if (res)
1758 return;
1759
1760 ccb = &pm8001_ha->ccb_info[ccb_tag];
1761 ccb->device = pm8001_ha_dev;
1762 ccb->ccb_tag = ccb_tag;
1763 ccb->task = task;
1764
1765 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1766
1767 memset(&task_abort, 0, sizeof(task_abort));
1768 task_abort.abort_all = cpu_to_le32(1);
1769 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1770 task_abort.tag = cpu_to_le32(ccb_tag);
1771
1772 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
1773 sizeof(task_abort), 0);
1774 if (ret)
1775 pm8001_tag_free(pm8001_ha, ccb_tag);
1776
1777 }
1778
1779 static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha,
1780 struct pm8001_device *pm8001_ha_dev)
1781 {
1782 struct sata_start_req sata_cmd;
1783 int res;
1784 u32 ccb_tag;
1785 struct pm8001_ccb_info *ccb;
1786 struct sas_task *task = NULL;
1787 struct host_to_dev_fis fis;
1788 struct domain_device *dev;
1789 struct inbound_queue_table *circularQ;
1790 u32 opc = OPC_INB_SATA_HOST_OPSTART;
1791
1792 task = sas_alloc_slow_task(GFP_ATOMIC);
1793
1794 if (!task) {
1795 PM8001_FAIL_DBG(pm8001_ha,
1796 pm8001_printk("cannot allocate task !!!\n"));
1797 return;
1798 }
1799 task->task_done = pm8001_task_done;
1800
1801 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1802 if (res) {
1803 sas_free_task(task);
1804 PM8001_FAIL_DBG(pm8001_ha,
1805 pm8001_printk("cannot allocate tag !!!\n"));
1806 return;
1807 }
1808
1809 /* allocate domain device by ourselves as libsas
1810 * is not going to provide any
1811 */
1812 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1813 if (!dev) {
1814 sas_free_task(task);
1815 pm8001_tag_free(pm8001_ha, ccb_tag);
1816 PM8001_FAIL_DBG(pm8001_ha,
1817 pm8001_printk("Domain device cannot be allocated\n"));
1818 return;
1819 }
1820 task->dev = dev;
1821 task->dev->lldd_dev = pm8001_ha_dev;
1822
1823 ccb = &pm8001_ha->ccb_info[ccb_tag];
1824 ccb->device = pm8001_ha_dev;
1825 ccb->ccb_tag = ccb_tag;
1826 ccb->task = task;
1827 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1828 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1829
1830 memset(&sata_cmd, 0, sizeof(sata_cmd));
1831 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1832
1833 /* construct read log FIS */
1834 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1835 fis.fis_type = 0x27;
1836 fis.flags = 0x80;
1837 fis.command = ATA_CMD_READ_LOG_EXT;
1838 fis.lbal = 0x10;
1839 fis.sector_count = 0x1;
1840
1841 sata_cmd.tag = cpu_to_le32(ccb_tag);
1842 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1843 sata_cmd.ncqtag_atap_dir_m |= ((0x1 << 7) | (0x5 << 9));
1844 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1845
1846 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
1847 sizeof(sata_cmd), 0);
1848 if (res) {
1849 sas_free_task(task);
1850 pm8001_tag_free(pm8001_ha, ccb_tag);
1851 kfree(dev);
1852 }
1853 }
1854
1855 /**
1856 * mpi_ssp_completion- process the event that FW response to the SSP request.
1857 * @pm8001_ha: our hba card information
1858 * @piomb: the message contents of this outbound message.
1859 *
1860 * When FW has completed a ssp request for example a IO request, after it has
1861 * filled the SG data with the data, it will trigger this event represent
1862 * that he has finished the job,please check the coresponding buffer.
1863 * So we will tell the caller who maybe waiting the result to tell upper layer
1864 * that the task has been finished.
1865 */
1866 static void
1867 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1868 {
1869 struct sas_task *t;
1870 struct pm8001_ccb_info *ccb;
1871 unsigned long flags;
1872 u32 status;
1873 u32 param;
1874 u32 tag;
1875 struct ssp_completion_resp *psspPayload;
1876 struct task_status_struct *ts;
1877 struct ssp_response_iu *iu;
1878 struct pm8001_device *pm8001_dev;
1879 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1880 status = le32_to_cpu(psspPayload->status);
1881 tag = le32_to_cpu(psspPayload->tag);
1882 ccb = &pm8001_ha->ccb_info[tag];
1883 if ((status == IO_ABORTED) && ccb->open_retry) {
1884 /* Being completed by another */
1885 ccb->open_retry = 0;
1886 return;
1887 }
1888 pm8001_dev = ccb->device;
1889 param = le32_to_cpu(psspPayload->param);
1890
1891 t = ccb->task;
1892
1893 if (status && status != IO_UNDERFLOW)
1894 PM8001_FAIL_DBG(pm8001_ha,
1895 pm8001_printk("sas IO status 0x%x\n", status));
1896 if (unlikely(!t || !t->lldd_task || !t->dev))
1897 return;
1898 ts = &t->task_status;
1899 /* Print sas address of IO failed device */
1900 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1901 (status != IO_UNDERFLOW))
1902 PM8001_FAIL_DBG(pm8001_ha,
1903 pm8001_printk("SAS Address of IO Failure Drive:"
1904 "%016llx", SAS_ADDR(t->dev->sas_addr)));
1905
1906 if (status)
1907 PM8001_IOERR_DBG(pm8001_ha, pm8001_printk(
1908 "status:0x%x, tag:0x%x, task:0x%p\n",
1909 status, tag, t));
1910
1911 switch (status) {
1912 case IO_SUCCESS:
1913 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
1914 ",param = %d\n", param));
1915 if (param == 0) {
1916 ts->resp = SAS_TASK_COMPLETE;
1917 ts->stat = SAM_STAT_GOOD;
1918 } else {
1919 ts->resp = SAS_TASK_COMPLETE;
1920 ts->stat = SAS_PROTO_RESPONSE;
1921 ts->residual = param;
1922 iu = &psspPayload->ssp_resp_iu;
1923 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1924 }
1925 if (pm8001_dev)
1926 pm8001_dev->running_req--;
1927 break;
1928 case IO_ABORTED:
1929 PM8001_IO_DBG(pm8001_ha,
1930 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1931 ts->resp = SAS_TASK_COMPLETE;
1932 ts->stat = SAS_ABORTED_TASK;
1933 break;
1934 case IO_UNDERFLOW:
1935 /* SSP Completion with error */
1936 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
1937 ",param = %d\n", param));
1938 ts->resp = SAS_TASK_COMPLETE;
1939 ts->stat = SAS_DATA_UNDERRUN;
1940 ts->residual = param;
1941 if (pm8001_dev)
1942 pm8001_dev->running_req--;
1943 break;
1944 case IO_NO_DEVICE:
1945 PM8001_IO_DBG(pm8001_ha,
1946 pm8001_printk("IO_NO_DEVICE\n"));
1947 ts->resp = SAS_TASK_UNDELIVERED;
1948 ts->stat = SAS_PHY_DOWN;
1949 break;
1950 case IO_XFER_ERROR_BREAK:
1951 PM8001_IO_DBG(pm8001_ha,
1952 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1953 ts->resp = SAS_TASK_COMPLETE;
1954 ts->stat = SAS_OPEN_REJECT;
1955 /* Force the midlayer to retry */
1956 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1957 break;
1958 case IO_XFER_ERROR_PHY_NOT_READY:
1959 PM8001_IO_DBG(pm8001_ha,
1960 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1961 ts->resp = SAS_TASK_COMPLETE;
1962 ts->stat = SAS_OPEN_REJECT;
1963 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1964 break;
1965 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1966 PM8001_IO_DBG(pm8001_ha,
1967 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1968 ts->resp = SAS_TASK_COMPLETE;
1969 ts->stat = SAS_OPEN_REJECT;
1970 ts->open_rej_reason = SAS_OREJ_EPROTO;
1971 break;
1972 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1973 PM8001_IO_DBG(pm8001_ha,
1974 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1975 ts->resp = SAS_TASK_COMPLETE;
1976 ts->stat = SAS_OPEN_REJECT;
1977 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1978 break;
1979 case IO_OPEN_CNX_ERROR_BREAK:
1980 PM8001_IO_DBG(pm8001_ha,
1981 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1982 ts->resp = SAS_TASK_COMPLETE;
1983 ts->stat = SAS_OPEN_REJECT;
1984 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1985 break;
1986 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1987 PM8001_IO_DBG(pm8001_ha,
1988 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1989 ts->resp = SAS_TASK_COMPLETE;
1990 ts->stat = SAS_OPEN_REJECT;
1991 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1992 if (!t->uldd_task)
1993 pm8001_handle_event(pm8001_ha,
1994 pm8001_dev,
1995 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1996 break;
1997 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1998 PM8001_IO_DBG(pm8001_ha,
1999 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2000 ts->resp = SAS_TASK_COMPLETE;
2001 ts->stat = SAS_OPEN_REJECT;
2002 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2003 break;
2004 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2005 PM8001_IO_DBG(pm8001_ha,
2006 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2007 "NOT_SUPPORTED\n"));
2008 ts->resp = SAS_TASK_COMPLETE;
2009 ts->stat = SAS_OPEN_REJECT;
2010 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2011 break;
2012 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2013 PM8001_IO_DBG(pm8001_ha,
2014 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2015 ts->resp = SAS_TASK_UNDELIVERED;
2016 ts->stat = SAS_OPEN_REJECT;
2017 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2018 break;
2019 case IO_XFER_ERROR_NAK_RECEIVED:
2020 PM8001_IO_DBG(pm8001_ha,
2021 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2022 ts->resp = SAS_TASK_COMPLETE;
2023 ts->stat = SAS_OPEN_REJECT;
2024 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2025 break;
2026 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2027 PM8001_IO_DBG(pm8001_ha,
2028 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2029 ts->resp = SAS_TASK_COMPLETE;
2030 ts->stat = SAS_NAK_R_ERR;
2031 break;
2032 case IO_XFER_ERROR_DMA:
2033 PM8001_IO_DBG(pm8001_ha,
2034 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2035 ts->resp = SAS_TASK_COMPLETE;
2036 ts->stat = SAS_OPEN_REJECT;
2037 break;
2038 case IO_XFER_OPEN_RETRY_TIMEOUT:
2039 PM8001_IO_DBG(pm8001_ha,
2040 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2041 ts->resp = SAS_TASK_COMPLETE;
2042 ts->stat = SAS_OPEN_REJECT;
2043 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2044 break;
2045 case IO_XFER_ERROR_OFFSET_MISMATCH:
2046 PM8001_IO_DBG(pm8001_ha,
2047 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2048 ts->resp = SAS_TASK_COMPLETE;
2049 ts->stat = SAS_OPEN_REJECT;
2050 break;
2051 case IO_PORT_IN_RESET:
2052 PM8001_IO_DBG(pm8001_ha,
2053 pm8001_printk("IO_PORT_IN_RESET\n"));
2054 ts->resp = SAS_TASK_COMPLETE;
2055 ts->stat = SAS_OPEN_REJECT;
2056 break;
2057 case IO_DS_NON_OPERATIONAL:
2058 PM8001_IO_DBG(pm8001_ha,
2059 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2060 ts->resp = SAS_TASK_COMPLETE;
2061 ts->stat = SAS_OPEN_REJECT;
2062 if (!t->uldd_task)
2063 pm8001_handle_event(pm8001_ha,
2064 pm8001_dev,
2065 IO_DS_NON_OPERATIONAL);
2066 break;
2067 case IO_DS_IN_RECOVERY:
2068 PM8001_IO_DBG(pm8001_ha,
2069 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2070 ts->resp = SAS_TASK_COMPLETE;
2071 ts->stat = SAS_OPEN_REJECT;
2072 break;
2073 case IO_TM_TAG_NOT_FOUND:
2074 PM8001_IO_DBG(pm8001_ha,
2075 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
2076 ts->resp = SAS_TASK_COMPLETE;
2077 ts->stat = SAS_OPEN_REJECT;
2078 break;
2079 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2080 PM8001_IO_DBG(pm8001_ha,
2081 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
2082 ts->resp = SAS_TASK_COMPLETE;
2083 ts->stat = SAS_OPEN_REJECT;
2084 break;
2085 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2086 PM8001_IO_DBG(pm8001_ha,
2087 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2088 ts->resp = SAS_TASK_COMPLETE;
2089 ts->stat = SAS_OPEN_REJECT;
2090 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2091 break;
2092 default:
2093 PM8001_DEVIO_DBG(pm8001_ha,
2094 pm8001_printk("Unknown status 0x%x\n", status));
2095 /* not allowed case. Therefore, return failed status */
2096 ts->resp = SAS_TASK_COMPLETE;
2097 ts->stat = SAS_OPEN_REJECT;
2098 break;
2099 }
2100 PM8001_IO_DBG(pm8001_ha,
2101 pm8001_printk("scsi_status = %x\n ",
2102 psspPayload->ssp_resp_iu.status));
2103 spin_lock_irqsave(&t->task_state_lock, flags);
2104 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2105 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2106 t->task_state_flags |= SAS_TASK_STATE_DONE;
2107 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2108 spin_unlock_irqrestore(&t->task_state_lock, flags);
2109 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2110 " io_status 0x%x resp 0x%x "
2111 "stat 0x%x but aborted by upper layer!\n",
2112 t, status, ts->resp, ts->stat));
2113 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2114 } else {
2115 spin_unlock_irqrestore(&t->task_state_lock, flags);
2116 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2117 mb();/* in order to force CPU ordering */
2118 t->task_done(t);
2119 }
2120 }
2121
2122 /*See the comments for mpi_ssp_completion */
2123 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2124 {
2125 struct sas_task *t;
2126 unsigned long flags;
2127 struct task_status_struct *ts;
2128 struct pm8001_ccb_info *ccb;
2129 struct pm8001_device *pm8001_dev;
2130 struct ssp_event_resp *psspPayload =
2131 (struct ssp_event_resp *)(piomb + 4);
2132 u32 event = le32_to_cpu(psspPayload->event);
2133 u32 tag = le32_to_cpu(psspPayload->tag);
2134 u32 port_id = le32_to_cpu(psspPayload->port_id);
2135 u32 dev_id = le32_to_cpu(psspPayload->device_id);
2136
2137 ccb = &pm8001_ha->ccb_info[tag];
2138 t = ccb->task;
2139 pm8001_dev = ccb->device;
2140 if (event)
2141 PM8001_FAIL_DBG(pm8001_ha,
2142 pm8001_printk("sas IO status 0x%x\n", event));
2143 if (unlikely(!t || !t->lldd_task || !t->dev))
2144 return;
2145 ts = &t->task_status;
2146 PM8001_DEVIO_DBG(pm8001_ha,
2147 pm8001_printk("port_id = %x,device_id = %x\n",
2148 port_id, dev_id));
2149 switch (event) {
2150 case IO_OVERFLOW:
2151 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
2152 ts->resp = SAS_TASK_COMPLETE;
2153 ts->stat = SAS_DATA_OVERRUN;
2154 ts->residual = 0;
2155 if (pm8001_dev)
2156 pm8001_dev->running_req--;
2157 break;
2158 case IO_XFER_ERROR_BREAK:
2159 PM8001_IO_DBG(pm8001_ha,
2160 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2161 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2162 return;
2163 case IO_XFER_ERROR_PHY_NOT_READY:
2164 PM8001_IO_DBG(pm8001_ha,
2165 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2166 ts->resp = SAS_TASK_COMPLETE;
2167 ts->stat = SAS_OPEN_REJECT;
2168 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2169 break;
2170 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2171 PM8001_IO_DBG(pm8001_ha,
2172 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2173 "_SUPPORTED\n"));
2174 ts->resp = SAS_TASK_COMPLETE;
2175 ts->stat = SAS_OPEN_REJECT;
2176 ts->open_rej_reason = SAS_OREJ_EPROTO;
2177 break;
2178 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2179 PM8001_IO_DBG(pm8001_ha,
2180 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2181 ts->resp = SAS_TASK_COMPLETE;
2182 ts->stat = SAS_OPEN_REJECT;
2183 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2184 break;
2185 case IO_OPEN_CNX_ERROR_BREAK:
2186 PM8001_IO_DBG(pm8001_ha,
2187 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2188 ts->resp = SAS_TASK_COMPLETE;
2189 ts->stat = SAS_OPEN_REJECT;
2190 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2191 break;
2192 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2193 PM8001_IO_DBG(pm8001_ha,
2194 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2195 ts->resp = SAS_TASK_COMPLETE;
2196 ts->stat = SAS_OPEN_REJECT;
2197 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2198 if (!t->uldd_task)
2199 pm8001_handle_event(pm8001_ha,
2200 pm8001_dev,
2201 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2202 break;
2203 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2204 PM8001_IO_DBG(pm8001_ha,
2205 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2206 ts->resp = SAS_TASK_COMPLETE;
2207 ts->stat = SAS_OPEN_REJECT;
2208 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2209 break;
2210 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2211 PM8001_IO_DBG(pm8001_ha,
2212 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2213 "NOT_SUPPORTED\n"));
2214 ts->resp = SAS_TASK_COMPLETE;
2215 ts->stat = SAS_OPEN_REJECT;
2216 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2217 break;
2218 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2219 PM8001_IO_DBG(pm8001_ha,
2220 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2221 ts->resp = SAS_TASK_COMPLETE;
2222 ts->stat = SAS_OPEN_REJECT;
2223 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2224 break;
2225 case IO_XFER_ERROR_NAK_RECEIVED:
2226 PM8001_IO_DBG(pm8001_ha,
2227 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2228 ts->resp = SAS_TASK_COMPLETE;
2229 ts->stat = SAS_OPEN_REJECT;
2230 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2231 break;
2232 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2233 PM8001_IO_DBG(pm8001_ha,
2234 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2235 ts->resp = SAS_TASK_COMPLETE;
2236 ts->stat = SAS_NAK_R_ERR;
2237 break;
2238 case IO_XFER_OPEN_RETRY_TIMEOUT:
2239 PM8001_IO_DBG(pm8001_ha,
2240 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2241 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2242 return;
2243 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2244 PM8001_IO_DBG(pm8001_ha,
2245 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2246 ts->resp = SAS_TASK_COMPLETE;
2247 ts->stat = SAS_DATA_OVERRUN;
2248 break;
2249 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2250 PM8001_IO_DBG(pm8001_ha,
2251 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2252 ts->resp = SAS_TASK_COMPLETE;
2253 ts->stat = SAS_DATA_OVERRUN;
2254 break;
2255 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2256 PM8001_IO_DBG(pm8001_ha,
2257 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2258 ts->resp = SAS_TASK_COMPLETE;
2259 ts->stat = SAS_DATA_OVERRUN;
2260 break;
2261 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2262 PM8001_IO_DBG(pm8001_ha,
2263 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
2264 ts->resp = SAS_TASK_COMPLETE;
2265 ts->stat = SAS_DATA_OVERRUN;
2266 break;
2267 case IO_XFER_ERROR_OFFSET_MISMATCH:
2268 PM8001_IO_DBG(pm8001_ha,
2269 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2270 ts->resp = SAS_TASK_COMPLETE;
2271 ts->stat = SAS_DATA_OVERRUN;
2272 break;
2273 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2274 PM8001_IO_DBG(pm8001_ha,
2275 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2276 ts->resp = SAS_TASK_COMPLETE;
2277 ts->stat = SAS_DATA_OVERRUN;
2278 break;
2279 case IO_XFER_CMD_FRAME_ISSUED:
2280 PM8001_IO_DBG(pm8001_ha,
2281 pm8001_printk(" IO_XFER_CMD_FRAME_ISSUED\n"));
2282 return;
2283 default:
2284 PM8001_DEVIO_DBG(pm8001_ha,
2285 pm8001_printk("Unknown status 0x%x\n", event));
2286 /* not allowed case. Therefore, return failed status */
2287 ts->resp = SAS_TASK_COMPLETE;
2288 ts->stat = SAS_DATA_OVERRUN;
2289 break;
2290 }
2291 spin_lock_irqsave(&t->task_state_lock, flags);
2292 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2293 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2294 t->task_state_flags |= SAS_TASK_STATE_DONE;
2295 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2296 spin_unlock_irqrestore(&t->task_state_lock, flags);
2297 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2298 " event 0x%x resp 0x%x "
2299 "stat 0x%x but aborted by upper layer!\n",
2300 t, event, ts->resp, ts->stat));
2301 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2302 } else {
2303 spin_unlock_irqrestore(&t->task_state_lock, flags);
2304 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2305 mb();/* in order to force CPU ordering */
2306 t->task_done(t);
2307 }
2308 }
2309
2310 /*See the comments for mpi_ssp_completion */
2311 static void
2312 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2313 {
2314 struct sas_task *t;
2315 struct pm8001_ccb_info *ccb;
2316 u32 param;
2317 u32 status;
2318 u32 tag;
2319 int i, j;
2320 u8 sata_addr_low[4];
2321 u32 temp_sata_addr_low;
2322 u8 sata_addr_hi[4];
2323 u32 temp_sata_addr_hi;
2324 struct sata_completion_resp *psataPayload;
2325 struct task_status_struct *ts;
2326 struct ata_task_resp *resp ;
2327 u32 *sata_resp;
2328 struct pm8001_device *pm8001_dev;
2329 unsigned long flags;
2330
2331 psataPayload = (struct sata_completion_resp *)(piomb + 4);
2332 status = le32_to_cpu(psataPayload->status);
2333 tag = le32_to_cpu(psataPayload->tag);
2334
2335 if (!tag) {
2336 PM8001_FAIL_DBG(pm8001_ha,
2337 pm8001_printk("tag null\n"));
2338 return;
2339 }
2340 ccb = &pm8001_ha->ccb_info[tag];
2341 param = le32_to_cpu(psataPayload->param);
2342 if (ccb) {
2343 t = ccb->task;
2344 pm8001_dev = ccb->device;
2345 } else {
2346 PM8001_FAIL_DBG(pm8001_ha,
2347 pm8001_printk("ccb null\n"));
2348 return;
2349 }
2350
2351 if (t) {
2352 if (t->dev && (t->dev->lldd_dev))
2353 pm8001_dev = t->dev->lldd_dev;
2354 } else {
2355 PM8001_FAIL_DBG(pm8001_ha,
2356 pm8001_printk("task null\n"));
2357 return;
2358 }
2359
2360 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2361 && unlikely(!t || !t->lldd_task || !t->dev)) {
2362 PM8001_FAIL_DBG(pm8001_ha,
2363 pm8001_printk("task or dev null\n"));
2364 return;
2365 }
2366
2367 ts = &t->task_status;
2368 if (!ts) {
2369 PM8001_FAIL_DBG(pm8001_ha,
2370 pm8001_printk("ts null\n"));
2371 return;
2372 }
2373
2374 if (status)
2375 PM8001_IOERR_DBG(pm8001_ha, pm8001_printk(
2376 "status:0x%x, tag:0x%x, task::0x%p\n",
2377 status, tag, t));
2378
2379 /* Print sas address of IO failed device */
2380 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2381 (status != IO_UNDERFLOW)) {
2382 if (!((t->dev->parent) &&
2383 (dev_is_expander(t->dev->parent->dev_type)))) {
2384 for (i = 0 , j = 4; j <= 7 && i <= 3; i++ , j++)
2385 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2386 for (i = 0 , j = 0; j <= 3 && i <= 3; i++ , j++)
2387 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2388 memcpy(&temp_sata_addr_low, sata_addr_low,
2389 sizeof(sata_addr_low));
2390 memcpy(&temp_sata_addr_hi, sata_addr_hi,
2391 sizeof(sata_addr_hi));
2392 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2393 |((temp_sata_addr_hi << 8) &
2394 0xff0000) |
2395 ((temp_sata_addr_hi >> 8)
2396 & 0xff00) |
2397 ((temp_sata_addr_hi << 24) &
2398 0xff000000));
2399 temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2400 & 0xff) |
2401 ((temp_sata_addr_low << 8)
2402 & 0xff0000) |
2403 ((temp_sata_addr_low >> 8)
2404 & 0xff00) |
2405 ((temp_sata_addr_low << 24)
2406 & 0xff000000)) +
2407 pm8001_dev->attached_phy +
2408 0x10);
2409 PM8001_FAIL_DBG(pm8001_ha,
2410 pm8001_printk("SAS Address of IO Failure Drive:"
2411 "%08x%08x", temp_sata_addr_hi,
2412 temp_sata_addr_low));
2413 } else {
2414 PM8001_FAIL_DBG(pm8001_ha,
2415 pm8001_printk("SAS Address of IO Failure Drive:"
2416 "%016llx", SAS_ADDR(t->dev->sas_addr)));
2417 }
2418 }
2419 switch (status) {
2420 case IO_SUCCESS:
2421 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2422 if (param == 0) {
2423 ts->resp = SAS_TASK_COMPLETE;
2424 ts->stat = SAM_STAT_GOOD;
2425 /* check if response is for SEND READ LOG */
2426 if (pm8001_dev &&
2427 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2428 /* set new bit for abort_all */
2429 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2430 /* clear bit for read log */
2431 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2432 pm8001_send_abort_all(pm8001_ha, pm8001_dev);
2433 /* Free the tag */
2434 pm8001_tag_free(pm8001_ha, tag);
2435 sas_free_task(t);
2436 return;
2437 }
2438 } else {
2439 u8 len;
2440 ts->resp = SAS_TASK_COMPLETE;
2441 ts->stat = SAS_PROTO_RESPONSE;
2442 ts->residual = param;
2443 PM8001_IO_DBG(pm8001_ha,
2444 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2445 param));
2446 sata_resp = &psataPayload->sata_resp[0];
2447 resp = (struct ata_task_resp *)ts->buf;
2448 if (t->ata_task.dma_xfer == 0 &&
2449 t->data_dir == DMA_FROM_DEVICE) {
2450 len = sizeof(struct pio_setup_fis);
2451 PM8001_IO_DBG(pm8001_ha,
2452 pm8001_printk("PIO read len = %d\n", len));
2453 } else if (t->ata_task.use_ncq) {
2454 len = sizeof(struct set_dev_bits_fis);
2455 PM8001_IO_DBG(pm8001_ha,
2456 pm8001_printk("FPDMA len = %d\n", len));
2457 } else {
2458 len = sizeof(struct dev_to_host_fis);
2459 PM8001_IO_DBG(pm8001_ha,
2460 pm8001_printk("other len = %d\n", len));
2461 }
2462 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2463 resp->frame_len = len;
2464 memcpy(&resp->ending_fis[0], sata_resp, len);
2465 ts->buf_valid_size = sizeof(*resp);
2466 } else
2467 PM8001_IO_DBG(pm8001_ha,
2468 pm8001_printk("response to large\n"));
2469 }
2470 if (pm8001_dev)
2471 pm8001_dev->running_req--;
2472 break;
2473 case IO_ABORTED:
2474 PM8001_IO_DBG(pm8001_ha,
2475 pm8001_printk("IO_ABORTED IOMB Tag\n"));
2476 ts->resp = SAS_TASK_COMPLETE;
2477 ts->stat = SAS_ABORTED_TASK;
2478 if (pm8001_dev)
2479 pm8001_dev->running_req--;
2480 break;
2481 /* following cases are to do cases */
2482 case IO_UNDERFLOW:
2483 /* SATA Completion with error */
2484 PM8001_IO_DBG(pm8001_ha,
2485 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2486 ts->resp = SAS_TASK_COMPLETE;
2487 ts->stat = SAS_DATA_UNDERRUN;
2488 ts->residual = param;
2489 if (pm8001_dev)
2490 pm8001_dev->running_req--;
2491 break;
2492 case IO_NO_DEVICE:
2493 PM8001_IO_DBG(pm8001_ha,
2494 pm8001_printk("IO_NO_DEVICE\n"));
2495 ts->resp = SAS_TASK_UNDELIVERED;
2496 ts->stat = SAS_PHY_DOWN;
2497 break;
2498 case IO_XFER_ERROR_BREAK:
2499 PM8001_IO_DBG(pm8001_ha,
2500 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2501 ts->resp = SAS_TASK_COMPLETE;
2502 ts->stat = SAS_INTERRUPTED;
2503 break;
2504 case IO_XFER_ERROR_PHY_NOT_READY:
2505 PM8001_IO_DBG(pm8001_ha,
2506 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2507 ts->resp = SAS_TASK_COMPLETE;
2508 ts->stat = SAS_OPEN_REJECT;
2509 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2510 break;
2511 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2512 PM8001_IO_DBG(pm8001_ha,
2513 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2514 "_SUPPORTED\n"));
2515 ts->resp = SAS_TASK_COMPLETE;
2516 ts->stat = SAS_OPEN_REJECT;
2517 ts->open_rej_reason = SAS_OREJ_EPROTO;
2518 break;
2519 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2520 PM8001_IO_DBG(pm8001_ha,
2521 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2522 ts->resp = SAS_TASK_COMPLETE;
2523 ts->stat = SAS_OPEN_REJECT;
2524 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2525 break;
2526 case IO_OPEN_CNX_ERROR_BREAK:
2527 PM8001_IO_DBG(pm8001_ha,
2528 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2529 ts->resp = SAS_TASK_COMPLETE;
2530 ts->stat = SAS_OPEN_REJECT;
2531 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2532 break;
2533 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2534 PM8001_IO_DBG(pm8001_ha,
2535 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2536 ts->resp = SAS_TASK_COMPLETE;
2537 ts->stat = SAS_DEV_NO_RESPONSE;
2538 if (!t->uldd_task) {
2539 pm8001_handle_event(pm8001_ha,
2540 pm8001_dev,
2541 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2542 ts->resp = SAS_TASK_UNDELIVERED;
2543 ts->stat = SAS_QUEUE_FULL;
2544 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2545 return;
2546 }
2547 break;
2548 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2549 PM8001_IO_DBG(pm8001_ha,
2550 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2551 ts->resp = SAS_TASK_UNDELIVERED;
2552 ts->stat = SAS_OPEN_REJECT;
2553 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2554 if (!t->uldd_task) {
2555 pm8001_handle_event(pm8001_ha,
2556 pm8001_dev,
2557 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2558 ts->resp = SAS_TASK_UNDELIVERED;
2559 ts->stat = SAS_QUEUE_FULL;
2560 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2561 return;
2562 }
2563 break;
2564 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2565 PM8001_IO_DBG(pm8001_ha,
2566 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2567 "NOT_SUPPORTED\n"));
2568 ts->resp = SAS_TASK_COMPLETE;
2569 ts->stat = SAS_OPEN_REJECT;
2570 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2571 break;
2572 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2573 PM8001_IO_DBG(pm8001_ha,
2574 pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
2575 "_BUSY\n"));
2576 ts->resp = SAS_TASK_COMPLETE;
2577 ts->stat = SAS_DEV_NO_RESPONSE;
2578 if (!t->uldd_task) {
2579 pm8001_handle_event(pm8001_ha,
2580 pm8001_dev,
2581 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2582 ts->resp = SAS_TASK_UNDELIVERED;
2583 ts->stat = SAS_QUEUE_FULL;
2584 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2585 return;
2586 }
2587 break;
2588 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2589 PM8001_IO_DBG(pm8001_ha,
2590 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2591 ts->resp = SAS_TASK_COMPLETE;
2592 ts->stat = SAS_OPEN_REJECT;
2593 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2594 break;
2595 case IO_XFER_ERROR_NAK_RECEIVED:
2596 PM8001_IO_DBG(pm8001_ha,
2597 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2598 ts->resp = SAS_TASK_COMPLETE;
2599 ts->stat = SAS_NAK_R_ERR;
2600 break;
2601 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2602 PM8001_IO_DBG(pm8001_ha,
2603 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2604 ts->resp = SAS_TASK_COMPLETE;
2605 ts->stat = SAS_NAK_R_ERR;
2606 break;
2607 case IO_XFER_ERROR_DMA:
2608 PM8001_IO_DBG(pm8001_ha,
2609 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2610 ts->resp = SAS_TASK_COMPLETE;
2611 ts->stat = SAS_ABORTED_TASK;
2612 break;
2613 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2614 PM8001_IO_DBG(pm8001_ha,
2615 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2616 ts->resp = SAS_TASK_UNDELIVERED;
2617 ts->stat = SAS_DEV_NO_RESPONSE;
2618 break;
2619 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2620 PM8001_IO_DBG(pm8001_ha,
2621 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2622 ts->resp = SAS_TASK_COMPLETE;
2623 ts->stat = SAS_DATA_UNDERRUN;
2624 break;
2625 case IO_XFER_OPEN_RETRY_TIMEOUT:
2626 PM8001_IO_DBG(pm8001_ha,
2627 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2628 ts->resp = SAS_TASK_COMPLETE;
2629 ts->stat = SAS_OPEN_TO;
2630 break;
2631 case IO_PORT_IN_RESET:
2632 PM8001_IO_DBG(pm8001_ha,
2633 pm8001_printk("IO_PORT_IN_RESET\n"));
2634 ts->resp = SAS_TASK_COMPLETE;
2635 ts->stat = SAS_DEV_NO_RESPONSE;
2636 break;
2637 case IO_DS_NON_OPERATIONAL:
2638 PM8001_IO_DBG(pm8001_ha,
2639 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2640 ts->resp = SAS_TASK_COMPLETE;
2641 ts->stat = SAS_DEV_NO_RESPONSE;
2642 if (!t->uldd_task) {
2643 pm8001_handle_event(pm8001_ha, pm8001_dev,
2644 IO_DS_NON_OPERATIONAL);
2645 ts->resp = SAS_TASK_UNDELIVERED;
2646 ts->stat = SAS_QUEUE_FULL;
2647 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2648 return;
2649 }
2650 break;
2651 case IO_DS_IN_RECOVERY:
2652 PM8001_IO_DBG(pm8001_ha,
2653 pm8001_printk(" IO_DS_IN_RECOVERY\n"));
2654 ts->resp = SAS_TASK_COMPLETE;
2655 ts->stat = SAS_DEV_NO_RESPONSE;
2656 break;
2657 case IO_DS_IN_ERROR:
2658 PM8001_IO_DBG(pm8001_ha,
2659 pm8001_printk("IO_DS_IN_ERROR\n"));
2660 ts->resp = SAS_TASK_COMPLETE;
2661 ts->stat = SAS_DEV_NO_RESPONSE;
2662 if (!t->uldd_task) {
2663 pm8001_handle_event(pm8001_ha, pm8001_dev,
2664 IO_DS_IN_ERROR);
2665 ts->resp = SAS_TASK_UNDELIVERED;
2666 ts->stat = SAS_QUEUE_FULL;
2667 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2668 return;
2669 }
2670 break;
2671 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2672 PM8001_IO_DBG(pm8001_ha,
2673 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2674 ts->resp = SAS_TASK_COMPLETE;
2675 ts->stat = SAS_OPEN_REJECT;
2676 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2677 break;
2678 default:
2679 PM8001_DEVIO_DBG(pm8001_ha,
2680 pm8001_printk("Unknown status 0x%x\n", status));
2681 /* not allowed case. Therefore, return failed status */
2682 ts->resp = SAS_TASK_COMPLETE;
2683 ts->stat = SAS_DEV_NO_RESPONSE;
2684 break;
2685 }
2686 spin_lock_irqsave(&t->task_state_lock, flags);
2687 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2688 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2689 t->task_state_flags |= SAS_TASK_STATE_DONE;
2690 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2691 spin_unlock_irqrestore(&t->task_state_lock, flags);
2692 PM8001_FAIL_DBG(pm8001_ha,
2693 pm8001_printk("task 0x%p done with io_status 0x%x"
2694 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2695 t, status, ts->resp, ts->stat));
2696 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2697 } else {
2698 spin_unlock_irqrestore(&t->task_state_lock, flags);
2699 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2700 }
2701 }
2702
2703 /*See the comments for mpi_ssp_completion */
2704 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2705 {
2706 struct sas_task *t;
2707 struct task_status_struct *ts;
2708 struct pm8001_ccb_info *ccb;
2709 struct pm8001_device *pm8001_dev;
2710 struct sata_event_resp *psataPayload =
2711 (struct sata_event_resp *)(piomb + 4);
2712 u32 event = le32_to_cpu(psataPayload->event);
2713 u32 tag = le32_to_cpu(psataPayload->tag);
2714 u32 port_id = le32_to_cpu(psataPayload->port_id);
2715 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2716 unsigned long flags;
2717
2718 ccb = &pm8001_ha->ccb_info[tag];
2719
2720 if (ccb) {
2721 t = ccb->task;
2722 pm8001_dev = ccb->device;
2723 } else {
2724 PM8001_FAIL_DBG(pm8001_ha,
2725 pm8001_printk("No CCB !!!. returning\n"));
2726 }
2727 if (event)
2728 PM8001_FAIL_DBG(pm8001_ha,
2729 pm8001_printk("SATA EVENT 0x%x\n", event));
2730
2731 /* Check if this is NCQ error */
2732 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2733 /* find device using device id */
2734 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2735 /* send read log extension */
2736 if (pm8001_dev)
2737 pm8001_send_read_log(pm8001_ha, pm8001_dev);
2738 return;
2739 }
2740
2741 ccb = &pm8001_ha->ccb_info[tag];
2742 t = ccb->task;
2743 pm8001_dev = ccb->device;
2744 if (event)
2745 PM8001_FAIL_DBG(pm8001_ha,
2746 pm8001_printk("sata IO status 0x%x\n", event));
2747 if (unlikely(!t || !t->lldd_task || !t->dev))
2748 return;
2749 ts = &t->task_status;
2750 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
2751 "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n",
2752 port_id, dev_id, tag, event));
2753 switch (event) {
2754 case IO_OVERFLOW:
2755 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2756 ts->resp = SAS_TASK_COMPLETE;
2757 ts->stat = SAS_DATA_OVERRUN;
2758 ts->residual = 0;
2759 if (pm8001_dev)
2760 pm8001_dev->running_req--;
2761 break;
2762 case IO_XFER_ERROR_BREAK:
2763 PM8001_IO_DBG(pm8001_ha,
2764 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2765 ts->resp = SAS_TASK_COMPLETE;
2766 ts->stat = SAS_INTERRUPTED;
2767 break;
2768 case IO_XFER_ERROR_PHY_NOT_READY:
2769 PM8001_IO_DBG(pm8001_ha,
2770 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2771 ts->resp = SAS_TASK_COMPLETE;
2772 ts->stat = SAS_OPEN_REJECT;
2773 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2774 break;
2775 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2776 PM8001_IO_DBG(pm8001_ha,
2777 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2778 "_SUPPORTED\n"));
2779 ts->resp = SAS_TASK_COMPLETE;
2780 ts->stat = SAS_OPEN_REJECT;
2781 ts->open_rej_reason = SAS_OREJ_EPROTO;
2782 break;
2783 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2784 PM8001_IO_DBG(pm8001_ha,
2785 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2786 ts->resp = SAS_TASK_COMPLETE;
2787 ts->stat = SAS_OPEN_REJECT;
2788 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2789 break;
2790 case IO_OPEN_CNX_ERROR_BREAK:
2791 PM8001_IO_DBG(pm8001_ha,
2792 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2793 ts->resp = SAS_TASK_COMPLETE;
2794 ts->stat = SAS_OPEN_REJECT;
2795 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2796 break;
2797 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2798 PM8001_IO_DBG(pm8001_ha,
2799 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2800 ts->resp = SAS_TASK_UNDELIVERED;
2801 ts->stat = SAS_DEV_NO_RESPONSE;
2802 if (!t->uldd_task) {
2803 pm8001_handle_event(pm8001_ha,
2804 pm8001_dev,
2805 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2806 ts->resp = SAS_TASK_COMPLETE;
2807 ts->stat = SAS_QUEUE_FULL;
2808 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2809 return;
2810 }
2811 break;
2812 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2813 PM8001_IO_DBG(pm8001_ha,
2814 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2815 ts->resp = SAS_TASK_UNDELIVERED;
2816 ts->stat = SAS_OPEN_REJECT;
2817 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2818 break;
2819 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2820 PM8001_IO_DBG(pm8001_ha,
2821 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2822 "NOT_SUPPORTED\n"));
2823 ts->resp = SAS_TASK_COMPLETE;
2824 ts->stat = SAS_OPEN_REJECT;
2825 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2826 break;
2827 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2828 PM8001_IO_DBG(pm8001_ha,
2829 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2830 ts->resp = SAS_TASK_COMPLETE;
2831 ts->stat = SAS_OPEN_REJECT;
2832 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2833 break;
2834 case IO_XFER_ERROR_NAK_RECEIVED:
2835 PM8001_IO_DBG(pm8001_ha,
2836 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2837 ts->resp = SAS_TASK_COMPLETE;
2838 ts->stat = SAS_NAK_R_ERR;
2839 break;
2840 case IO_XFER_ERROR_PEER_ABORTED:
2841 PM8001_IO_DBG(pm8001_ha,
2842 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2843 ts->resp = SAS_TASK_COMPLETE;
2844 ts->stat = SAS_NAK_R_ERR;
2845 break;
2846 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2847 PM8001_IO_DBG(pm8001_ha,
2848 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2849 ts->resp = SAS_TASK_COMPLETE;
2850 ts->stat = SAS_DATA_UNDERRUN;
2851 break;
2852 case IO_XFER_OPEN_RETRY_TIMEOUT:
2853 PM8001_IO_DBG(pm8001_ha,
2854 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2855 ts->resp = SAS_TASK_COMPLETE;
2856 ts->stat = SAS_OPEN_TO;
2857 break;
2858 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2859 PM8001_IO_DBG(pm8001_ha,
2860 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2861 ts->resp = SAS_TASK_COMPLETE;
2862 ts->stat = SAS_OPEN_TO;
2863 break;
2864 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2865 PM8001_IO_DBG(pm8001_ha,
2866 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2867 ts->resp = SAS_TASK_COMPLETE;
2868 ts->stat = SAS_OPEN_TO;
2869 break;
2870 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2871 PM8001_IO_DBG(pm8001_ha,
2872 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2873 ts->resp = SAS_TASK_COMPLETE;
2874 ts->stat = SAS_OPEN_TO;
2875 break;
2876 case IO_XFER_ERROR_OFFSET_MISMATCH:
2877 PM8001_IO_DBG(pm8001_ha,
2878 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2879 ts->resp = SAS_TASK_COMPLETE;
2880 ts->stat = SAS_OPEN_TO;
2881 break;
2882 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2883 PM8001_IO_DBG(pm8001_ha,
2884 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2885 ts->resp = SAS_TASK_COMPLETE;
2886 ts->stat = SAS_OPEN_TO;
2887 break;
2888 case IO_XFER_CMD_FRAME_ISSUED:
2889 PM8001_IO_DBG(pm8001_ha,
2890 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2891 break;
2892 case IO_XFER_PIO_SETUP_ERROR:
2893 PM8001_IO_DBG(pm8001_ha,
2894 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2895 ts->resp = SAS_TASK_COMPLETE;
2896 ts->stat = SAS_OPEN_TO;
2897 break;
2898 default:
2899 PM8001_DEVIO_DBG(pm8001_ha,
2900 pm8001_printk("Unknown status 0x%x\n", event));
2901 /* not allowed case. Therefore, return failed status */
2902 ts->resp = SAS_TASK_COMPLETE;
2903 ts->stat = SAS_OPEN_TO;
2904 break;
2905 }
2906 spin_lock_irqsave(&t->task_state_lock, flags);
2907 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2908 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2909 t->task_state_flags |= SAS_TASK_STATE_DONE;
2910 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2911 spin_unlock_irqrestore(&t->task_state_lock, flags);
2912 PM8001_FAIL_DBG(pm8001_ha,
2913 pm8001_printk("task 0x%p done with io_status 0x%x"
2914 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2915 t, event, ts->resp, ts->stat));
2916 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2917 } else {
2918 spin_unlock_irqrestore(&t->task_state_lock, flags);
2919 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2920 }
2921 }
2922
2923 /*See the comments for mpi_ssp_completion */
2924 static void
2925 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2926 {
2927 struct sas_task *t;
2928 struct pm8001_ccb_info *ccb;
2929 unsigned long flags;
2930 u32 status;
2931 u32 tag;
2932 struct smp_completion_resp *psmpPayload;
2933 struct task_status_struct *ts;
2934 struct pm8001_device *pm8001_dev;
2935
2936 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2937 status = le32_to_cpu(psmpPayload->status);
2938 tag = le32_to_cpu(psmpPayload->tag);
2939
2940 ccb = &pm8001_ha->ccb_info[tag];
2941 t = ccb->task;
2942 ts = &t->task_status;
2943 pm8001_dev = ccb->device;
2944 if (status) {
2945 PM8001_FAIL_DBG(pm8001_ha,
2946 pm8001_printk("smp IO status 0x%x\n", status));
2947 PM8001_IOERR_DBG(pm8001_ha,
2948 pm8001_printk("status:0x%x, tag:0x%x, task:0x%p\n",
2949 status, tag, t));
2950 }
2951 if (unlikely(!t || !t->lldd_task || !t->dev))
2952 return;
2953
2954 switch (status) {
2955 case IO_SUCCESS:
2956 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2957 ts->resp = SAS_TASK_COMPLETE;
2958 ts->stat = SAM_STAT_GOOD;
2959 if (pm8001_dev)
2960 pm8001_dev->running_req--;
2961 break;
2962 case IO_ABORTED:
2963 PM8001_IO_DBG(pm8001_ha,
2964 pm8001_printk("IO_ABORTED IOMB\n"));
2965 ts->resp = SAS_TASK_COMPLETE;
2966 ts->stat = SAS_ABORTED_TASK;
2967 if (pm8001_dev)
2968 pm8001_dev->running_req--;
2969 break;
2970 case IO_OVERFLOW:
2971 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2972 ts->resp = SAS_TASK_COMPLETE;
2973 ts->stat = SAS_DATA_OVERRUN;
2974 ts->residual = 0;
2975 if (pm8001_dev)
2976 pm8001_dev->running_req--;
2977 break;
2978 case IO_NO_DEVICE:
2979 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2980 ts->resp = SAS_TASK_COMPLETE;
2981 ts->stat = SAS_PHY_DOWN;
2982 break;
2983 case IO_ERROR_HW_TIMEOUT:
2984 PM8001_IO_DBG(pm8001_ha,
2985 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2986 ts->resp = SAS_TASK_COMPLETE;
2987 ts->stat = SAM_STAT_BUSY;
2988 break;
2989 case IO_XFER_ERROR_BREAK:
2990 PM8001_IO_DBG(pm8001_ha,
2991 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2992 ts->resp = SAS_TASK_COMPLETE;
2993 ts->stat = SAM_STAT_BUSY;
2994 break;
2995 case IO_XFER_ERROR_PHY_NOT_READY:
2996 PM8001_IO_DBG(pm8001_ha,
2997 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2998 ts->resp = SAS_TASK_COMPLETE;
2999 ts->stat = SAM_STAT_BUSY;
3000 break;
3001 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
3002 PM8001_IO_DBG(pm8001_ha,
3003 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
3004 ts->resp = SAS_TASK_COMPLETE;
3005 ts->stat = SAS_OPEN_REJECT;
3006 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3007 break;
3008 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
3009 PM8001_IO_DBG(pm8001_ha,
3010 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
3011 ts->resp = SAS_TASK_COMPLETE;
3012 ts->stat = SAS_OPEN_REJECT;
3013 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3014 break;
3015 case IO_OPEN_CNX_ERROR_BREAK:
3016 PM8001_IO_DBG(pm8001_ha,
3017 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
3018 ts->resp = SAS_TASK_COMPLETE;
3019 ts->stat = SAS_OPEN_REJECT;
3020 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
3021 break;
3022 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
3023 PM8001_IO_DBG(pm8001_ha,
3024 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
3025 ts->resp = SAS_TASK_COMPLETE;
3026 ts->stat = SAS_OPEN_REJECT;
3027 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3028 pm8001_handle_event(pm8001_ha,
3029 pm8001_dev,
3030 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
3031 break;
3032 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
3033 PM8001_IO_DBG(pm8001_ha,
3034 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
3035 ts->resp = SAS_TASK_COMPLETE;
3036 ts->stat = SAS_OPEN_REJECT;
3037 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
3038 break;
3039 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
3040 PM8001_IO_DBG(pm8001_ha,
3041 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
3042 "NOT_SUPPORTED\n"));
3043 ts->resp = SAS_TASK_COMPLETE;
3044 ts->stat = SAS_OPEN_REJECT;
3045 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
3046 break;
3047 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
3048 PM8001_IO_DBG(pm8001_ha,
3049 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
3050 ts->resp = SAS_TASK_COMPLETE;
3051 ts->stat = SAS_OPEN_REJECT;
3052 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
3053 break;
3054 case IO_XFER_ERROR_RX_FRAME:
3055 PM8001_IO_DBG(pm8001_ha,
3056 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
3057 ts->resp = SAS_TASK_COMPLETE;
3058 ts->stat = SAS_DEV_NO_RESPONSE;
3059 break;
3060 case IO_XFER_OPEN_RETRY_TIMEOUT:
3061 PM8001_IO_DBG(pm8001_ha,
3062 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
3063 ts->resp = SAS_TASK_COMPLETE;
3064 ts->stat = SAS_OPEN_REJECT;
3065 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3066 break;
3067 case IO_ERROR_INTERNAL_SMP_RESOURCE:
3068 PM8001_IO_DBG(pm8001_ha,
3069 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
3070 ts->resp = SAS_TASK_COMPLETE;
3071 ts->stat = SAS_QUEUE_FULL;
3072 break;
3073 case IO_PORT_IN_RESET:
3074 PM8001_IO_DBG(pm8001_ha,
3075 pm8001_printk("IO_PORT_IN_RESET\n"));
3076 ts->resp = SAS_TASK_COMPLETE;
3077 ts->stat = SAS_OPEN_REJECT;
3078 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3079 break;
3080 case IO_DS_NON_OPERATIONAL:
3081 PM8001_IO_DBG(pm8001_ha,
3082 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
3083 ts->resp = SAS_TASK_COMPLETE;
3084 ts->stat = SAS_DEV_NO_RESPONSE;
3085 break;
3086 case IO_DS_IN_RECOVERY:
3087 PM8001_IO_DBG(pm8001_ha,
3088 pm8001_printk("IO_DS_IN_RECOVERY\n"));
3089 ts->resp = SAS_TASK_COMPLETE;
3090 ts->stat = SAS_OPEN_REJECT;
3091 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3092 break;
3093 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3094 PM8001_IO_DBG(pm8001_ha,
3095 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
3096 ts->resp = SAS_TASK_COMPLETE;
3097 ts->stat = SAS_OPEN_REJECT;
3098 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3099 break;
3100 default:
3101 PM8001_DEVIO_DBG(pm8001_ha,
3102 pm8001_printk("Unknown status 0x%x\n", status));
3103 ts->resp = SAS_TASK_COMPLETE;
3104 ts->stat = SAS_DEV_NO_RESPONSE;
3105 /* not allowed case. Therefore, return failed status */
3106 break;
3107 }
3108 spin_lock_irqsave(&t->task_state_lock, flags);
3109 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3110 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3111 t->task_state_flags |= SAS_TASK_STATE_DONE;
3112 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3113 spin_unlock_irqrestore(&t->task_state_lock, flags);
3114 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
3115 " io_status 0x%x resp 0x%x "
3116 "stat 0x%x but aborted by upper layer!\n",
3117 t, status, ts->resp, ts->stat));
3118 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3119 } else {
3120 spin_unlock_irqrestore(&t->task_state_lock, flags);
3121 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3122 mb();/* in order to force CPU ordering */
3123 t->task_done(t);
3124 }
3125 }
3126
3127 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
3128 void *piomb)
3129 {
3130 struct set_dev_state_resp *pPayload =
3131 (struct set_dev_state_resp *)(piomb + 4);
3132 u32 tag = le32_to_cpu(pPayload->tag);
3133 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3134 struct pm8001_device *pm8001_dev = ccb->device;
3135 u32 status = le32_to_cpu(pPayload->status);
3136 u32 device_id = le32_to_cpu(pPayload->device_id);
3137 u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS;
3138 u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS;
3139 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state "
3140 "from 0x%x to 0x%x status = 0x%x!\n",
3141 device_id, pds, nds, status));
3142 complete(pm8001_dev->setds_completion);
3143 ccb->task = NULL;
3144 ccb->ccb_tag = 0xFFFFFFFF;
3145 pm8001_tag_free(pm8001_ha, tag);
3146 }
3147
3148 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3149 {
3150 struct get_nvm_data_resp *pPayload =
3151 (struct get_nvm_data_resp *)(piomb + 4);
3152 u32 tag = le32_to_cpu(pPayload->tag);
3153 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3154 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3155 complete(pm8001_ha->nvmd_completion);
3156 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n"));
3157 if ((dlen_status & NVMD_STAT) != 0) {
3158 PM8001_FAIL_DBG(pm8001_ha,
3159 pm8001_printk("Set nvm data error!\n"));
3160 return;
3161 }
3162 ccb->task = NULL;
3163 ccb->ccb_tag = 0xFFFFFFFF;
3164 pm8001_tag_free(pm8001_ha, tag);
3165 }
3166
3167 void
3168 pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3169 {
3170 struct fw_control_ex *fw_control_context;
3171 struct get_nvm_data_resp *pPayload =
3172 (struct get_nvm_data_resp *)(piomb + 4);
3173 u32 tag = le32_to_cpu(pPayload->tag);
3174 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3175 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3176 u32 ir_tds_bn_dps_das_nvm =
3177 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
3178 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
3179 fw_control_context = ccb->fw_control_context;
3180
3181 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n"));
3182 if ((dlen_status & NVMD_STAT) != 0) {
3183 PM8001_FAIL_DBG(pm8001_ha,
3184 pm8001_printk("Get nvm data error!\n"));
3185 complete(pm8001_ha->nvmd_completion);
3186 return;
3187 }
3188
3189 if (ir_tds_bn_dps_das_nvm & IPMode) {
3190 /* indirect mode - IR bit set */
3191 PM8001_MSG_DBG(pm8001_ha,
3192 pm8001_printk("Get NVMD success, IR=1\n"));
3193 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
3194 if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
3195 memcpy(pm8001_ha->sas_addr,
3196 ((u8 *)virt_addr + 4),
3197 SAS_ADDR_SIZE);
3198 PM8001_MSG_DBG(pm8001_ha,
3199 pm8001_printk("Get SAS address"
3200 " from VPD successfully!\n"));
3201 }
3202 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
3203 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
3204 ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
3205 ;
3206 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
3207 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
3208 ;
3209 } else {
3210 /* Should not be happened*/
3211 PM8001_MSG_DBG(pm8001_ha,
3212 pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
3213 ir_tds_bn_dps_das_nvm));
3214 }
3215 } else /* direct mode */{
3216 PM8001_MSG_DBG(pm8001_ha,
3217 pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
3218 (dlen_status & NVMD_LEN) >> 24));
3219 }
3220 /* Though fw_control_context is freed below, usrAddr still needs
3221 * to be updated as this holds the response to the request function
3222 */
3223 memcpy(fw_control_context->usrAddr,
3224 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
3225 fw_control_context->len);
3226 kfree(ccb->fw_control_context);
3227 ccb->task = NULL;
3228 ccb->ccb_tag = 0xFFFFFFFF;
3229 pm8001_tag_free(pm8001_ha, tag);
3230 complete(pm8001_ha->nvmd_completion);
3231 }
3232
3233 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
3234 {
3235 u32 tag;
3236 struct local_phy_ctl_resp *pPayload =
3237 (struct local_phy_ctl_resp *)(piomb + 4);
3238 u32 status = le32_to_cpu(pPayload->status);
3239 u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
3240 u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
3241 tag = le32_to_cpu(pPayload->tag);
3242 if (status != 0) {
3243 PM8001_MSG_DBG(pm8001_ha,
3244 pm8001_printk("%x phy execute %x phy op failed!\n",
3245 phy_id, phy_op));
3246 } else {
3247 PM8001_MSG_DBG(pm8001_ha,
3248 pm8001_printk("%x phy execute %x phy op success!\n",
3249 phy_id, phy_op));
3250 pm8001_ha->phy[phy_id].reset_success = true;
3251 }
3252 if (pm8001_ha->phy[phy_id].enable_completion) {
3253 complete(pm8001_ha->phy[phy_id].enable_completion);
3254 pm8001_ha->phy[phy_id].enable_completion = NULL;
3255 }
3256 pm8001_tag_free(pm8001_ha, tag);
3257 return 0;
3258 }
3259
3260 /**
3261 * pm8001_bytes_dmaed - one of the interface function communication with libsas
3262 * @pm8001_ha: our hba card information
3263 * @i: which phy that received the event.
3264 *
3265 * when HBA driver received the identify done event or initiate FIS received
3266 * event(for SATA), it will invoke this function to notify the sas layer that
3267 * the sas toplogy has formed, please discover the the whole sas domain,
3268 * while receive a broadcast(change) primitive just tell the sas
3269 * layer to discover the changed domain rather than the whole domain.
3270 */
3271 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
3272 {
3273 struct pm8001_phy *phy = &pm8001_ha->phy[i];
3274 struct asd_sas_phy *sas_phy = &phy->sas_phy;
3275 if (!phy->phy_attached)
3276 return;
3277
3278 if (sas_phy->phy) {
3279 struct sas_phy *sphy = sas_phy->phy;
3280 sphy->negotiated_linkrate = sas_phy->linkrate;
3281 sphy->minimum_linkrate = phy->minimum_linkrate;
3282 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3283 sphy->maximum_linkrate = phy->maximum_linkrate;
3284 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
3285 }
3286
3287 if (phy->phy_type & PORT_TYPE_SAS) {
3288 struct sas_identify_frame *id;
3289 id = (struct sas_identify_frame *)phy->frame_rcvd;
3290 id->dev_type = phy->identify.device_type;
3291 id->initiator_bits = SAS_PROTOCOL_ALL;
3292 id->target_bits = phy->identify.target_port_protocols;
3293 } else if (phy->phy_type & PORT_TYPE_SATA) {
3294 /*Nothing*/
3295 }
3296 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i));
3297
3298 sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
3299 pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
3300 }
3301
3302 /* Get the link rate speed */
3303 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
3304 {
3305 struct sas_phy *sas_phy = phy->sas_phy.phy;
3306
3307 switch (link_rate) {
3308 case PHY_SPEED_120:
3309 phy->sas_phy.linkrate = SAS_LINK_RATE_12_0_GBPS;
3310 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_12_0_GBPS;
3311 break;
3312 case PHY_SPEED_60:
3313 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
3314 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
3315 break;
3316 case PHY_SPEED_30:
3317 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
3318 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
3319 break;
3320 case PHY_SPEED_15:
3321 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
3322 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
3323 break;
3324 }
3325 sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
3326 sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
3327 sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3328 sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
3329 sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
3330 }
3331
3332 /**
3333 * asd_get_attached_sas_addr -- extract/generate attached SAS address
3334 * @phy: pointer to asd_phy
3335 * @sas_addr: pointer to buffer where the SAS address is to be written
3336 *
3337 * This function extracts the SAS address from an IDENTIFY frame
3338 * received. If OOB is SATA, then a SAS address is generated from the
3339 * HA tables.
3340 *
3341 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3342 * buffer.
3343 */
3344 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
3345 u8 *sas_addr)
3346 {
3347 if (phy->sas_phy.frame_rcvd[0] == 0x34
3348 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
3349 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
3350 /* FIS device-to-host */
3351 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
3352 addr += phy->sas_phy.id;
3353 *(__be64 *)sas_addr = cpu_to_be64(addr);
3354 } else {
3355 struct sas_identify_frame *idframe =
3356 (void *) phy->sas_phy.frame_rcvd;
3357 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
3358 }
3359 }
3360
3361 /**
3362 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3363 * @pm8001_ha: our hba card information
3364 * @Qnum: the outbound queue message number.
3365 * @SEA: source of event to ack
3366 * @port_id: port id.
3367 * @phyId: phy id.
3368 * @param0: parameter 0.
3369 * @param1: parameter 1.
3370 */
3371 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3372 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3373 {
3374 struct hw_event_ack_req payload;
3375 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3376
3377 struct inbound_queue_table *circularQ;
3378
3379 memset((u8 *)&payload, 0, sizeof(payload));
3380 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3381 payload.tag = cpu_to_le32(1);
3382 payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3383 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
3384 payload.param0 = cpu_to_le32(param0);
3385 payload.param1 = cpu_to_le32(param1);
3386 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
3387 sizeof(payload), 0);
3388 }
3389
3390 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3391 u32 phyId, u32 phy_op);
3392
3393 /**
3394 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3395 * @pm8001_ha: our hba card information
3396 * @piomb: IO message buffer
3397 */
3398 static void
3399 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3400 {
3401 struct hw_event_resp *pPayload =
3402 (struct hw_event_resp *)(piomb + 4);
3403 u32 lr_evt_status_phyid_portid =
3404 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3405 u8 link_rate =
3406 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3407 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3408 u8 phy_id =
3409 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3410 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3411 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3412 struct pm8001_port *port = &pm8001_ha->port[port_id];
3413 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3414 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3415 unsigned long flags;
3416 u8 deviceType = pPayload->sas_identify.dev_type;
3417 port->port_state = portstate;
3418 phy->phy_state = PHY_STATE_LINK_UP_SPC;
3419 PM8001_MSG_DBG(pm8001_ha,
3420 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3421 port_id, phy_id));
3422
3423 switch (deviceType) {
3424 case SAS_PHY_UNUSED:
3425 PM8001_MSG_DBG(pm8001_ha,
3426 pm8001_printk("device type no device.\n"));
3427 break;
3428 case SAS_END_DEVICE:
3429 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
3430 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
3431 PHY_NOTIFY_ENABLE_SPINUP);
3432 port->port_attached = 1;
3433 pm8001_get_lrate_mode(phy, link_rate);
3434 break;
3435 case SAS_EDGE_EXPANDER_DEVICE:
3436 PM8001_MSG_DBG(pm8001_ha,
3437 pm8001_printk("expander device.\n"));
3438 port->port_attached = 1;
3439 pm8001_get_lrate_mode(phy, link_rate);
3440 break;
3441 case SAS_FANOUT_EXPANDER_DEVICE:
3442 PM8001_MSG_DBG(pm8001_ha,
3443 pm8001_printk("fanout expander device.\n"));
3444 port->port_attached = 1;
3445 pm8001_get_lrate_mode(phy, link_rate);
3446 break;
3447 default:
3448 PM8001_DEVIO_DBG(pm8001_ha,
3449 pm8001_printk("unknown device type(%x)\n", deviceType));
3450 break;
3451 }
3452 phy->phy_type |= PORT_TYPE_SAS;
3453 phy->identify.device_type = deviceType;
3454 phy->phy_attached = 1;
3455 if (phy->identify.device_type == SAS_END_DEVICE)
3456 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3457 else if (phy->identify.device_type != SAS_PHY_UNUSED)
3458 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3459 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3460 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3461 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3462 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3463 sizeof(struct sas_identify_frame)-4);
3464 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3465 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3466 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3467 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3468 mdelay(200);/*delay a moment to wait disk to spinup*/
3469 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3470 }
3471
3472 /**
3473 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3474 * @pm8001_ha: our hba card information
3475 * @piomb: IO message buffer
3476 */
3477 static void
3478 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3479 {
3480 struct hw_event_resp *pPayload =
3481 (struct hw_event_resp *)(piomb + 4);
3482 u32 lr_evt_status_phyid_portid =
3483 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3484 u8 link_rate =
3485 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3486 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3487 u8 phy_id =
3488 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3489 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3490 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3491 struct pm8001_port *port = &pm8001_ha->port[port_id];
3492 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3493 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3494 unsigned long flags;
3495 PM8001_DEVIO_DBG(pm8001_ha,
3496 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d,"
3497 " phy id = %d\n", port_id, phy_id));
3498 port->port_state = portstate;
3499 phy->phy_state = PHY_STATE_LINK_UP_SPC;
3500 port->port_attached = 1;
3501 pm8001_get_lrate_mode(phy, link_rate);
3502 phy->phy_type |= PORT_TYPE_SATA;
3503 phy->phy_attached = 1;
3504 phy->sas_phy.oob_mode = SATA_OOB_MODE;
3505 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3506 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3507 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3508 sizeof(struct dev_to_host_fis));
3509 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3510 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3511 phy->identify.device_type = SAS_SATA_DEV;
3512 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3513 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3514 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3515 }
3516
3517 /**
3518 * hw_event_phy_down -we should notify the libsas the phy is down.
3519 * @pm8001_ha: our hba card information
3520 * @piomb: IO message buffer
3521 */
3522 static void
3523 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3524 {
3525 struct hw_event_resp *pPayload =
3526 (struct hw_event_resp *)(piomb + 4);
3527 u32 lr_evt_status_phyid_portid =
3528 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3529 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3530 u8 phy_id =
3531 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3532 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3533 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3534 struct pm8001_port *port = &pm8001_ha->port[port_id];
3535 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3536 port->port_state = portstate;
3537 phy->phy_type = 0;
3538 phy->identify.device_type = 0;
3539 phy->phy_attached = 0;
3540 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3541 switch (portstate) {
3542 case PORT_VALID:
3543 break;
3544 case PORT_INVALID:
3545 PM8001_MSG_DBG(pm8001_ha,
3546 pm8001_printk(" PortInvalid portID %d\n", port_id));
3547 PM8001_MSG_DBG(pm8001_ha,
3548 pm8001_printk(" Last phy Down and port invalid\n"));
3549 port->port_attached = 0;
3550 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3551 port_id, phy_id, 0, 0);
3552 break;
3553 case PORT_IN_RESET:
3554 PM8001_MSG_DBG(pm8001_ha,
3555 pm8001_printk(" Port In Reset portID %d\n", port_id));
3556 break;
3557 case PORT_NOT_ESTABLISHED:
3558 PM8001_MSG_DBG(pm8001_ha,
3559 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
3560 port->port_attached = 0;
3561 break;
3562 case PORT_LOSTCOMM:
3563 PM8001_MSG_DBG(pm8001_ha,
3564 pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
3565 PM8001_MSG_DBG(pm8001_ha,
3566 pm8001_printk(" Last phy Down and port invalid\n"));
3567 port->port_attached = 0;
3568 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3569 port_id, phy_id, 0, 0);
3570 break;
3571 default:
3572 port->port_attached = 0;
3573 PM8001_DEVIO_DBG(pm8001_ha,
3574 pm8001_printk(" phy Down and(default) = %x\n",
3575 portstate));
3576 break;
3577
3578 }
3579 }
3580
3581 /**
3582 * pm8001_mpi_reg_resp -process register device ID response.
3583 * @pm8001_ha: our hba card information
3584 * @piomb: IO message buffer
3585 *
3586 * when sas layer find a device it will notify LLDD, then the driver register
3587 * the domain device to FW, this event is the return device ID which the FW
3588 * has assigned, from now,inter-communication with FW is no longer using the
3589 * SAS address, use device ID which FW assigned.
3590 */
3591 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3592 {
3593 u32 status;
3594 u32 device_id;
3595 u32 htag;
3596 struct pm8001_ccb_info *ccb;
3597 struct pm8001_device *pm8001_dev;
3598 struct dev_reg_resp *registerRespPayload =
3599 (struct dev_reg_resp *)(piomb + 4);
3600
3601 htag = le32_to_cpu(registerRespPayload->tag);
3602 ccb = &pm8001_ha->ccb_info[htag];
3603 pm8001_dev = ccb->device;
3604 status = le32_to_cpu(registerRespPayload->status);
3605 device_id = le32_to_cpu(registerRespPayload->device_id);
3606 PM8001_MSG_DBG(pm8001_ha,
3607 pm8001_printk(" register device is status = %d\n", status));
3608 switch (status) {
3609 case DEVREG_SUCCESS:
3610 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n"));
3611 pm8001_dev->device_id = device_id;
3612 break;
3613 case DEVREG_FAILURE_OUT_OF_RESOURCE:
3614 PM8001_MSG_DBG(pm8001_ha,
3615 pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
3616 break;
3617 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3618 PM8001_MSG_DBG(pm8001_ha,
3619 pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
3620 break;
3621 case DEVREG_FAILURE_INVALID_PHY_ID:
3622 PM8001_MSG_DBG(pm8001_ha,
3623 pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
3624 break;
3625 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3626 PM8001_MSG_DBG(pm8001_ha,
3627 pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
3628 break;
3629 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3630 PM8001_MSG_DBG(pm8001_ha,
3631 pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
3632 break;
3633 case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3634 PM8001_MSG_DBG(pm8001_ha,
3635 pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
3636 break;
3637 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3638 PM8001_MSG_DBG(pm8001_ha,
3639 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
3640 break;
3641 default:
3642 PM8001_MSG_DBG(pm8001_ha,
3643 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_SUPPORTED\n"));
3644 break;
3645 }
3646 complete(pm8001_dev->dcompletion);
3647 ccb->task = NULL;
3648 ccb->ccb_tag = 0xFFFFFFFF;
3649 pm8001_tag_free(pm8001_ha, htag);
3650 return 0;
3651 }
3652
3653 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3654 {
3655 u32 status;
3656 u32 device_id;
3657 struct dev_reg_resp *registerRespPayload =
3658 (struct dev_reg_resp *)(piomb + 4);
3659
3660 status = le32_to_cpu(registerRespPayload->status);
3661 device_id = le32_to_cpu(registerRespPayload->device_id);
3662 if (status != 0)
3663 PM8001_MSG_DBG(pm8001_ha,
3664 pm8001_printk(" deregister device failed ,status = %x"
3665 ", device_id = %x\n", status, device_id));
3666 return 0;
3667 }
3668
3669 /**
3670 * fw_flash_update_resp - Response from FW for flash update command.
3671 * @pm8001_ha: our hba card information
3672 * @piomb: IO message buffer
3673 */
3674 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
3675 void *piomb)
3676 {
3677 u32 status;
3678 struct fw_flash_Update_resp *ppayload =
3679 (struct fw_flash_Update_resp *)(piomb + 4);
3680 u32 tag = le32_to_cpu(ppayload->tag);
3681 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3682 status = le32_to_cpu(ppayload->status);
3683 switch (status) {
3684 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3685 PM8001_MSG_DBG(pm8001_ha,
3686 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
3687 break;
3688 case FLASH_UPDATE_IN_PROGRESS:
3689 PM8001_MSG_DBG(pm8001_ha,
3690 pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
3691 break;
3692 case FLASH_UPDATE_HDR_ERR:
3693 PM8001_MSG_DBG(pm8001_ha,
3694 pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
3695 break;
3696 case FLASH_UPDATE_OFFSET_ERR:
3697 PM8001_MSG_DBG(pm8001_ha,
3698 pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
3699 break;
3700 case FLASH_UPDATE_CRC_ERR:
3701 PM8001_MSG_DBG(pm8001_ha,
3702 pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
3703 break;
3704 case FLASH_UPDATE_LENGTH_ERR:
3705 PM8001_MSG_DBG(pm8001_ha,
3706 pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
3707 break;
3708 case FLASH_UPDATE_HW_ERR:
3709 PM8001_MSG_DBG(pm8001_ha,
3710 pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
3711 break;
3712 case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3713 PM8001_MSG_DBG(pm8001_ha,
3714 pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
3715 break;
3716 case FLASH_UPDATE_DISABLED:
3717 PM8001_MSG_DBG(pm8001_ha,
3718 pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
3719 break;
3720 default:
3721 PM8001_DEVIO_DBG(pm8001_ha,
3722 pm8001_printk("No matched status = %d\n", status));
3723 break;
3724 }
3725 kfree(ccb->fw_control_context);
3726 ccb->task = NULL;
3727 ccb->ccb_tag = 0xFFFFFFFF;
3728 pm8001_tag_free(pm8001_ha, tag);
3729 complete(pm8001_ha->nvmd_completion);
3730 return 0;
3731 }
3732
3733 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
3734 {
3735 u32 status;
3736 int i;
3737 struct general_event_resp *pPayload =
3738 (struct general_event_resp *)(piomb + 4);
3739 status = le32_to_cpu(pPayload->status);
3740 PM8001_MSG_DBG(pm8001_ha,
3741 pm8001_printk(" status = 0x%x\n", status));
3742 for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3743 PM8001_MSG_DBG(pm8001_ha,
3744 pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i,
3745 pPayload->inb_IOMB_payload[i]));
3746 return 0;
3747 }
3748
3749 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3750 {
3751 struct sas_task *t;
3752 struct pm8001_ccb_info *ccb;
3753 unsigned long flags;
3754 u32 status ;
3755 u32 tag, scp;
3756 struct task_status_struct *ts;
3757 struct pm8001_device *pm8001_dev;
3758
3759 struct task_abort_resp *pPayload =
3760 (struct task_abort_resp *)(piomb + 4);
3761
3762 status = le32_to_cpu(pPayload->status);
3763 tag = le32_to_cpu(pPayload->tag);
3764 if (!tag) {
3765 PM8001_FAIL_DBG(pm8001_ha,
3766 pm8001_printk(" TAG NULL. RETURNING !!!"));
3767 return -1;
3768 }
3769
3770 scp = le32_to_cpu(pPayload->scp);
3771 ccb = &pm8001_ha->ccb_info[tag];
3772 t = ccb->task;
3773 pm8001_dev = ccb->device; /* retrieve device */
3774
3775 if (!t) {
3776 PM8001_FAIL_DBG(pm8001_ha,
3777 pm8001_printk(" TASK NULL. RETURNING !!!"));
3778 return -1;
3779 }
3780 ts = &t->task_status;
3781 if (status != 0)
3782 PM8001_FAIL_DBG(pm8001_ha,
3783 pm8001_printk("task abort failed status 0x%x ,"
3784 "tag = 0x%x, scp= 0x%x\n", status, tag, scp));
3785 switch (status) {
3786 case IO_SUCCESS:
3787 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
3788 ts->resp = SAS_TASK_COMPLETE;
3789 ts->stat = SAM_STAT_GOOD;
3790 break;
3791 case IO_NOT_VALID:
3792 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n"));
3793 ts->resp = TMF_RESP_FUNC_FAILED;
3794 break;
3795 }
3796 spin_lock_irqsave(&t->task_state_lock, flags);
3797 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3798 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3799 t->task_state_flags |= SAS_TASK_STATE_DONE;
3800 spin_unlock_irqrestore(&t->task_state_lock, flags);
3801 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3802 mb();
3803
3804 if (pm8001_dev->id & NCQ_ABORT_ALL_FLAG) {
3805 pm8001_tag_free(pm8001_ha, tag);
3806 sas_free_task(t);
3807 /* clear the flag */
3808 pm8001_dev->id &= 0xBFFFFFFF;
3809 } else
3810 t->task_done(t);
3811
3812 return 0;
3813 }
3814
3815 /**
3816 * mpi_hw_event -The hw event has come.
3817 * @pm8001_ha: our hba card information
3818 * @piomb: IO message buffer
3819 */
3820 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
3821 {
3822 unsigned long flags;
3823 struct hw_event_resp *pPayload =
3824 (struct hw_event_resp *)(piomb + 4);
3825 u32 lr_evt_status_phyid_portid =
3826 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3827 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3828 u8 phy_id =
3829 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3830 u16 eventType =
3831 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3832 u8 status =
3833 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3834 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3835 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3836 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3837 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
3838 "SPC HW event for portid:%d, phyid:%d, event:%x, status:%x\n",
3839 port_id, phy_id, eventType, status));
3840 switch (eventType) {
3841 case HW_EVENT_PHY_START_STATUS:
3842 PM8001_MSG_DBG(pm8001_ha,
3843 pm8001_printk("HW_EVENT_PHY_START_STATUS"
3844 " status = %x\n", status));
3845 if (status == 0) {
3846 phy->phy_state = 1;
3847 if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3848 phy->enable_completion != NULL)
3849 complete(phy->enable_completion);
3850 }
3851 break;
3852 case HW_EVENT_SAS_PHY_UP:
3853 PM8001_MSG_DBG(pm8001_ha,
3854 pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3855 hw_event_sas_phy_up(pm8001_ha, piomb);
3856 break;
3857 case HW_EVENT_SATA_PHY_UP:
3858 PM8001_MSG_DBG(pm8001_ha,
3859 pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3860 hw_event_sata_phy_up(pm8001_ha, piomb);
3861 break;
3862 case HW_EVENT_PHY_STOP_STATUS:
3863 PM8001_MSG_DBG(pm8001_ha,
3864 pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
3865 "status = %x\n", status));
3866 if (status == 0)
3867 phy->phy_state = 0;
3868 break;
3869 case HW_EVENT_SATA_SPINUP_HOLD:
3870 PM8001_MSG_DBG(pm8001_ha,
3871 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3872 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3873 break;
3874 case HW_EVENT_PHY_DOWN:
3875 PM8001_MSG_DBG(pm8001_ha,
3876 pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3877 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3878 phy->phy_attached = 0;
3879 phy->phy_state = 0;
3880 hw_event_phy_down(pm8001_ha, piomb);
3881 break;
3882 case HW_EVENT_PORT_INVALID:
3883 PM8001_MSG_DBG(pm8001_ha,
3884 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3885 sas_phy_disconnected(sas_phy);
3886 phy->phy_attached = 0;
3887 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3888 break;
3889 /* the broadcast change primitive received, tell the LIBSAS this event
3890 to revalidate the sas domain*/
3891 case HW_EVENT_BROADCAST_CHANGE:
3892 PM8001_MSG_DBG(pm8001_ha,
3893 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3894 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3895 port_id, phy_id, 1, 0);
3896 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3897 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3898 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3899 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3900 break;
3901 case HW_EVENT_PHY_ERROR:
3902 PM8001_MSG_DBG(pm8001_ha,
3903 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3904 sas_phy_disconnected(&phy->sas_phy);
3905 phy->phy_attached = 0;
3906 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3907 break;
3908 case HW_EVENT_BROADCAST_EXP:
3909 PM8001_MSG_DBG(pm8001_ha,
3910 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3911 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3912 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3913 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3914 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3915 break;
3916 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3917 PM8001_MSG_DBG(pm8001_ha,
3918 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3919 pm8001_hw_event_ack_req(pm8001_ha, 0,
3920 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3921 sas_phy_disconnected(sas_phy);
3922 phy->phy_attached = 0;
3923 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3924 break;
3925 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3926 PM8001_MSG_DBG(pm8001_ha,
3927 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3928 pm8001_hw_event_ack_req(pm8001_ha, 0,
3929 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3930 port_id, phy_id, 0, 0);
3931 sas_phy_disconnected(sas_phy);
3932 phy->phy_attached = 0;
3933 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3934 break;
3935 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3936 PM8001_MSG_DBG(pm8001_ha,
3937 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3938 pm8001_hw_event_ack_req(pm8001_ha, 0,
3939 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3940 port_id, phy_id, 0, 0);
3941 sas_phy_disconnected(sas_phy);
3942 phy->phy_attached = 0;
3943 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3944 break;
3945 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3946 PM8001_MSG_DBG(pm8001_ha,
3947 pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3948 pm8001_hw_event_ack_req(pm8001_ha, 0,
3949 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3950 port_id, phy_id, 0, 0);
3951 sas_phy_disconnected(sas_phy);
3952 phy->phy_attached = 0;
3953 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3954 break;
3955 case HW_EVENT_MALFUNCTION:
3956 PM8001_MSG_DBG(pm8001_ha,
3957 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3958 break;
3959 case HW_EVENT_BROADCAST_SES:
3960 PM8001_MSG_DBG(pm8001_ha,
3961 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3962 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3963 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3964 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3965 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3966 break;
3967 case HW_EVENT_INBOUND_CRC_ERROR:
3968 PM8001_MSG_DBG(pm8001_ha,
3969 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3970 pm8001_hw_event_ack_req(pm8001_ha, 0,
3971 HW_EVENT_INBOUND_CRC_ERROR,
3972 port_id, phy_id, 0, 0);
3973 break;
3974 case HW_EVENT_HARD_RESET_RECEIVED:
3975 PM8001_MSG_DBG(pm8001_ha,
3976 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3977 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3978 break;
3979 case HW_EVENT_ID_FRAME_TIMEOUT:
3980 PM8001_MSG_DBG(pm8001_ha,
3981 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3982 sas_phy_disconnected(sas_phy);
3983 phy->phy_attached = 0;
3984 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3985 break;
3986 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3987 PM8001_MSG_DBG(pm8001_ha,
3988 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3989 pm8001_hw_event_ack_req(pm8001_ha, 0,
3990 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3991 port_id, phy_id, 0, 0);
3992 sas_phy_disconnected(sas_phy);
3993 phy->phy_attached = 0;
3994 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3995 break;
3996 case HW_EVENT_PORT_RESET_TIMER_TMO:
3997 PM8001_MSG_DBG(pm8001_ha,
3998 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3999 sas_phy_disconnected(sas_phy);
4000 phy->phy_attached = 0;
4001 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
4002 break;
4003 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
4004 PM8001_MSG_DBG(pm8001_ha,
4005 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
4006 sas_phy_disconnected(sas_phy);
4007 phy->phy_attached = 0;
4008 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
4009 break;
4010 case HW_EVENT_PORT_RECOVER:
4011 PM8001_MSG_DBG(pm8001_ha,
4012 pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
4013 break;
4014 case HW_EVENT_PORT_RESET_COMPLETE:
4015 PM8001_MSG_DBG(pm8001_ha,
4016 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
4017 break;
4018 case EVENT_BROADCAST_ASYNCH_EVENT:
4019 PM8001_MSG_DBG(pm8001_ha,
4020 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
4021 break;
4022 default:
4023 PM8001_DEVIO_DBG(pm8001_ha,
4024 pm8001_printk("Unknown event type = %x\n", eventType));
4025 break;
4026 }
4027 return 0;
4028 }
4029
4030 /**
4031 * process_one_iomb - process one outbound Queue memory block
4032 * @pm8001_ha: our hba card information
4033 * @piomb: IO message buffer
4034 */
4035 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
4036 {
4037 __le32 pHeader = *(__le32 *)piomb;
4038 u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
4039
4040 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:"));
4041
4042 switch (opc) {
4043 case OPC_OUB_ECHO:
4044 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
4045 break;
4046 case OPC_OUB_HW_EVENT:
4047 PM8001_MSG_DBG(pm8001_ha,
4048 pm8001_printk("OPC_OUB_HW_EVENT\n"));
4049 mpi_hw_event(pm8001_ha, piomb);
4050 break;
4051 case OPC_OUB_SSP_COMP:
4052 PM8001_MSG_DBG(pm8001_ha,
4053 pm8001_printk("OPC_OUB_SSP_COMP\n"));
4054 mpi_ssp_completion(pm8001_ha, piomb);
4055 break;
4056 case OPC_OUB_SMP_COMP:
4057 PM8001_MSG_DBG(pm8001_ha,
4058 pm8001_printk("OPC_OUB_SMP_COMP\n"));
4059 mpi_smp_completion(pm8001_ha, piomb);
4060 break;
4061 case OPC_OUB_LOCAL_PHY_CNTRL:
4062 PM8001_MSG_DBG(pm8001_ha,
4063 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
4064 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
4065 break;
4066 case OPC_OUB_DEV_REGIST:
4067 PM8001_MSG_DBG(pm8001_ha,
4068 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
4069 pm8001_mpi_reg_resp(pm8001_ha, piomb);
4070 break;
4071 case OPC_OUB_DEREG_DEV:
4072 PM8001_MSG_DBG(pm8001_ha,
4073 pm8001_printk("unregister the device\n"));
4074 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
4075 break;
4076 case OPC_OUB_GET_DEV_HANDLE:
4077 PM8001_MSG_DBG(pm8001_ha,
4078 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
4079 break;
4080 case OPC_OUB_SATA_COMP:
4081 PM8001_MSG_DBG(pm8001_ha,
4082 pm8001_printk("OPC_OUB_SATA_COMP\n"));
4083 mpi_sata_completion(pm8001_ha, piomb);
4084 break;
4085 case OPC_OUB_SATA_EVENT:
4086 PM8001_MSG_DBG(pm8001_ha,
4087 pm8001_printk("OPC_OUB_SATA_EVENT\n"));
4088 mpi_sata_event(pm8001_ha, piomb);
4089 break;
4090 case OPC_OUB_SSP_EVENT:
4091 PM8001_MSG_DBG(pm8001_ha,
4092 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
4093 mpi_ssp_event(pm8001_ha, piomb);
4094 break;
4095 case OPC_OUB_DEV_HANDLE_ARRIV:
4096 PM8001_MSG_DBG(pm8001_ha,
4097 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
4098 /*This is for target*/
4099 break;
4100 case OPC_OUB_SSP_RECV_EVENT:
4101 PM8001_MSG_DBG(pm8001_ha,
4102 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
4103 /*This is for target*/
4104 break;
4105 case OPC_OUB_DEV_INFO:
4106 PM8001_MSG_DBG(pm8001_ha,
4107 pm8001_printk("OPC_OUB_DEV_INFO\n"));
4108 break;
4109 case OPC_OUB_FW_FLASH_UPDATE:
4110 PM8001_MSG_DBG(pm8001_ha,
4111 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
4112 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
4113 break;
4114 case OPC_OUB_GPIO_RESPONSE:
4115 PM8001_MSG_DBG(pm8001_ha,
4116 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
4117 break;
4118 case OPC_OUB_GPIO_EVENT:
4119 PM8001_MSG_DBG(pm8001_ha,
4120 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
4121 break;
4122 case OPC_OUB_GENERAL_EVENT:
4123 PM8001_MSG_DBG(pm8001_ha,
4124 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
4125 pm8001_mpi_general_event(pm8001_ha, piomb);
4126 break;
4127 case OPC_OUB_SSP_ABORT_RSP:
4128 PM8001_MSG_DBG(pm8001_ha,
4129 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
4130 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4131 break;
4132 case OPC_OUB_SATA_ABORT_RSP:
4133 PM8001_MSG_DBG(pm8001_ha,
4134 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
4135 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4136 break;
4137 case OPC_OUB_SAS_DIAG_MODE_START_END:
4138 PM8001_MSG_DBG(pm8001_ha,
4139 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
4140 break;
4141 case OPC_OUB_SAS_DIAG_EXECUTE:
4142 PM8001_MSG_DBG(pm8001_ha,
4143 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
4144 break;
4145 case OPC_OUB_GET_TIME_STAMP:
4146 PM8001_MSG_DBG(pm8001_ha,
4147 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
4148 break;
4149 case OPC_OUB_SAS_HW_EVENT_ACK:
4150 PM8001_MSG_DBG(pm8001_ha,
4151 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
4152 break;
4153 case OPC_OUB_PORT_CONTROL:
4154 PM8001_MSG_DBG(pm8001_ha,
4155 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
4156 break;
4157 case OPC_OUB_SMP_ABORT_RSP:
4158 PM8001_MSG_DBG(pm8001_ha,
4159 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
4160 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4161 break;
4162 case OPC_OUB_GET_NVMD_DATA:
4163 PM8001_MSG_DBG(pm8001_ha,
4164 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
4165 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
4166 break;
4167 case OPC_OUB_SET_NVMD_DATA:
4168 PM8001_MSG_DBG(pm8001_ha,
4169 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
4170 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
4171 break;
4172 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
4173 PM8001_MSG_DBG(pm8001_ha,
4174 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
4175 break;
4176 case OPC_OUB_SET_DEVICE_STATE:
4177 PM8001_MSG_DBG(pm8001_ha,
4178 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
4179 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
4180 break;
4181 case OPC_OUB_GET_DEVICE_STATE:
4182 PM8001_MSG_DBG(pm8001_ha,
4183 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
4184 break;
4185 case OPC_OUB_SET_DEV_INFO:
4186 PM8001_MSG_DBG(pm8001_ha,
4187 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
4188 break;
4189 case OPC_OUB_SAS_RE_INITIALIZE:
4190 PM8001_MSG_DBG(pm8001_ha,
4191 pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
4192 break;
4193 default:
4194 PM8001_DEVIO_DBG(pm8001_ha,
4195 pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
4196 opc));
4197 break;
4198 }
4199 }
4200
4201 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4202 {
4203 struct outbound_queue_table *circularQ;
4204 void *pMsg1 = NULL;
4205 u8 uninitialized_var(bc);
4206 u32 ret = MPI_IO_STATUS_FAIL;
4207 unsigned long flags;
4208
4209 spin_lock_irqsave(&pm8001_ha->lock, flags);
4210 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4211 do {
4212 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4213 if (MPI_IO_STATUS_SUCCESS == ret) {
4214 /* process the outbound message */
4215 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
4216 /* free the message from the outbound circular buffer */
4217 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4218 circularQ, bc);
4219 }
4220 if (MPI_IO_STATUS_BUSY == ret) {
4221 /* Update the producer index from SPC */
4222 circularQ->producer_index =
4223 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4224 if (le32_to_cpu(circularQ->producer_index) ==
4225 circularQ->consumer_idx)
4226 /* OQ is empty */
4227 break;
4228 }
4229 } while (1);
4230 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4231 return ret;
4232 }
4233
4234 /* DMA_... to our direction translation. */
4235 static const u8 data_dir_flags[] = {
4236 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
4237 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */
4238 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */
4239 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */
4240 };
4241 void
4242 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
4243 {
4244 int i;
4245 struct scatterlist *sg;
4246 struct pm8001_prd *buf_prd = prd;
4247
4248 for_each_sg(scatter, sg, nr, i) {
4249 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
4250 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
4251 buf_prd->im_len.e = 0;
4252 buf_prd++;
4253 }
4254 }
4255
4256 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd)
4257 {
4258 psmp_cmd->tag = hTag;
4259 psmp_cmd->device_id = cpu_to_le32(deviceID);
4260 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4261 }
4262
4263 /**
4264 * pm8001_chip_smp_req - send a SMP task to FW
4265 * @pm8001_ha: our hba card information.
4266 * @ccb: the ccb information this request used.
4267 */
4268 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4269 struct pm8001_ccb_info *ccb)
4270 {
4271 int elem, rc;
4272 struct sas_task *task = ccb->task;
4273 struct domain_device *dev = task->dev;
4274 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4275 struct scatterlist *sg_req, *sg_resp;
4276 u32 req_len, resp_len;
4277 struct smp_req smp_cmd;
4278 u32 opc;
4279 struct inbound_queue_table *circularQ;
4280
4281 memset(&smp_cmd, 0, sizeof(smp_cmd));
4282 /*
4283 * DMA-map SMP request, response buffers
4284 */
4285 sg_req = &task->smp_task.smp_req;
4286 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4287 if (!elem)
4288 return -ENOMEM;
4289 req_len = sg_dma_len(sg_req);
4290
4291 sg_resp = &task->smp_task.smp_resp;
4292 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4293 if (!elem) {
4294 rc = -ENOMEM;
4295 goto err_out;
4296 }
4297 resp_len = sg_dma_len(sg_resp);
4298 /* must be in dwords */
4299 if ((req_len & 0x3) || (resp_len & 0x3)) {
4300 rc = -EINVAL;
4301 goto err_out_2;
4302 }
4303
4304 opc = OPC_INB_SMP_REQUEST;
4305 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4306 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4307 smp_cmd.long_smp_req.long_req_addr =
4308 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4309 smp_cmd.long_smp_req.long_req_size =
4310 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4311 smp_cmd.long_smp_req.long_resp_addr =
4312 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
4313 smp_cmd.long_smp_req.long_resp_size =
4314 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4315 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
4316 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4317 &smp_cmd, sizeof(smp_cmd), 0);
4318 if (rc)
4319 goto err_out_2;
4320
4321 return 0;
4322
4323 err_out_2:
4324 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4325 DMA_FROM_DEVICE);
4326 err_out:
4327 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4328 DMA_TO_DEVICE);
4329 return rc;
4330 }
4331
4332 /**
4333 * pm8001_chip_ssp_io_req - send a SSP task to FW
4334 * @pm8001_ha: our hba card information.
4335 * @ccb: the ccb information this request used.
4336 */
4337 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4338 struct pm8001_ccb_info *ccb)
4339 {
4340 struct sas_task *task = ccb->task;
4341 struct domain_device *dev = task->dev;
4342 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4343 struct ssp_ini_io_start_req ssp_cmd;
4344 u32 tag = ccb->ccb_tag;
4345 int ret;
4346 u64 phys_addr;
4347 struct inbound_queue_table *circularQ;
4348 u32 opc = OPC_INB_SSPINIIOSTART;
4349 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4350 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4351 ssp_cmd.dir_m_tlr =
4352 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
4353 SAS 1.1 compatible TLR*/
4354 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4355 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4356 ssp_cmd.tag = cpu_to_le32(tag);
4357 if (task->ssp_task.enable_first_burst)
4358 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4359 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4360 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4361 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4362 task->ssp_task.cmd->cmd_len);
4363 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4364
4365 /* fill in PRD (scatter/gather) table, if any */
4366 if (task->num_scatter > 1) {
4367 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4368 phys_addr = ccb->ccb_dma_handle +
4369 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4370 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr));
4371 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr));
4372 ssp_cmd.esgl = cpu_to_le32(1<<31);
4373 } else if (task->num_scatter == 1) {
4374 u64 dma_addr = sg_dma_address(task->scatter);
4375 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4376 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr));
4377 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4378 ssp_cmd.esgl = 0;
4379 } else if (task->num_scatter == 0) {
4380 ssp_cmd.addr_low = 0;
4381 ssp_cmd.addr_high = 0;
4382 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4383 ssp_cmd.esgl = 0;
4384 }
4385 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd,
4386 sizeof(ssp_cmd), 0);
4387 return ret;
4388 }
4389
4390 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4391 struct pm8001_ccb_info *ccb)
4392 {
4393 struct sas_task *task = ccb->task;
4394 struct domain_device *dev = task->dev;
4395 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4396 u32 tag = ccb->ccb_tag;
4397 int ret;
4398 struct sata_start_req sata_cmd;
4399 u32 hdr_tag, ncg_tag = 0;
4400 u64 phys_addr;
4401 u32 ATAP = 0x0;
4402 u32 dir;
4403 struct inbound_queue_table *circularQ;
4404 unsigned long flags;
4405 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4406 memset(&sata_cmd, 0, sizeof(sata_cmd));
4407 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4408 if (task->data_dir == DMA_NONE) {
4409 ATAP = 0x04; /* no data*/
4410 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4411 } else if (likely(!task->ata_task.device_control_reg_update)) {
4412 if (task->ata_task.dma_xfer) {
4413 ATAP = 0x06; /* DMA */
4414 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4415 } else {
4416 ATAP = 0x05; /* PIO*/
4417 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4418 }
4419 if (task->ata_task.use_ncq &&
4420 dev->sata_dev.class != ATA_DEV_ATAPI) {
4421 ATAP = 0x07; /* FPDMA */
4422 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4423 }
4424 }
4425 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4426 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4427 ncg_tag = hdr_tag;
4428 }
4429 dir = data_dir_flags[task->data_dir] << 8;
4430 sata_cmd.tag = cpu_to_le32(tag);
4431 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4432 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4433 sata_cmd.ncqtag_atap_dir_m =
4434 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
4435 sata_cmd.sata_fis = task->ata_task.fis;
4436 if (likely(!task->ata_task.device_control_reg_update))
4437 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4438 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4439 /* fill in PRD (scatter/gather) table, if any */
4440 if (task->num_scatter > 1) {
4441 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4442 phys_addr = ccb->ccb_dma_handle +
4443 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4444 sata_cmd.addr_low = lower_32_bits(phys_addr);
4445 sata_cmd.addr_high = upper_32_bits(phys_addr);
4446 sata_cmd.esgl = cpu_to_le32(1 << 31);
4447 } else if (task->num_scatter == 1) {
4448 u64 dma_addr = sg_dma_address(task->scatter);
4449 sata_cmd.addr_low = lower_32_bits(dma_addr);
4450 sata_cmd.addr_high = upper_32_bits(dma_addr);
4451 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4452 sata_cmd.esgl = 0;
4453 } else if (task->num_scatter == 0) {
4454 sata_cmd.addr_low = 0;
4455 sata_cmd.addr_high = 0;
4456 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4457 sata_cmd.esgl = 0;
4458 }
4459
4460 /* Check for read log for failed drive and return */
4461 if (sata_cmd.sata_fis.command == 0x2f) {
4462 if (((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4463 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4464 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4465 struct task_status_struct *ts;
4466
4467 pm8001_ha_dev->id &= 0xDFFFFFFF;
4468 ts = &task->task_status;
4469
4470 spin_lock_irqsave(&task->task_state_lock, flags);
4471 ts->resp = SAS_TASK_COMPLETE;
4472 ts->stat = SAM_STAT_GOOD;
4473 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4474 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4475 task->task_state_flags |= SAS_TASK_STATE_DONE;
4476 if (unlikely((task->task_state_flags &
4477 SAS_TASK_STATE_ABORTED))) {
4478 spin_unlock_irqrestore(&task->task_state_lock,
4479 flags);
4480 PM8001_FAIL_DBG(pm8001_ha,
4481 pm8001_printk("task 0x%p resp 0x%x "
4482 " stat 0x%x but aborted by upper layer "
4483 "\n", task, ts->resp, ts->stat));
4484 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4485 } else {
4486 spin_unlock_irqrestore(&task->task_state_lock,
4487 flags);
4488 pm8001_ccb_task_free_done(pm8001_ha, task,
4489 ccb, tag);
4490 return 0;
4491 }
4492 }
4493 }
4494
4495 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
4496 sizeof(sata_cmd), 0);
4497 return ret;
4498 }
4499
4500 /**
4501 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
4502 * @pm8001_ha: our hba card information.
4503 * @num: the inbound queue number
4504 * @phy_id: the phy id which we wanted to start up.
4505 */
4506 static int
4507 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4508 {
4509 struct phy_start_req payload;
4510 struct inbound_queue_table *circularQ;
4511 int ret;
4512 u32 tag = 0x01;
4513 u32 opcode = OPC_INB_PHYSTART;
4514 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4515 memset(&payload, 0, sizeof(payload));
4516 payload.tag = cpu_to_le32(tag);
4517 /*
4518 ** [0:7] PHY Identifier
4519 ** [8:11] link rate 1.5G, 3G, 6G
4520 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
4521 ** [14] 0b disable spin up hold; 1b enable spin up hold
4522 */
4523 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4524 LINKMODE_AUTO | LINKRATE_15 |
4525 LINKRATE_30 | LINKRATE_60 | phy_id);
4526 payload.sas_identify.dev_type = SAS_END_DEVICE;
4527 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4528 memcpy(payload.sas_identify.sas_addr,
4529 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4530 payload.sas_identify.phy_id = phy_id;
4531 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4532 sizeof(payload), 0);
4533 return ret;
4534 }
4535
4536 /**
4537 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4538 * @pm8001_ha: our hba card information.
4539 * @num: the inbound queue number
4540 * @phy_id: the phy id which we wanted to start up.
4541 */
4542 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4543 u8 phy_id)
4544 {
4545 struct phy_stop_req payload;
4546 struct inbound_queue_table *circularQ;
4547 int ret;
4548 u32 tag = 0x01;
4549 u32 opcode = OPC_INB_PHYSTOP;
4550 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4551 memset(&payload, 0, sizeof(payload));
4552 payload.tag = cpu_to_le32(tag);
4553 payload.phy_id = cpu_to_le32(phy_id);
4554 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4555 sizeof(payload), 0);
4556 return ret;
4557 }
4558
4559 /**
4560 * see comments on pm8001_mpi_reg_resp.
4561 */
4562 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4563 struct pm8001_device *pm8001_dev, u32 flag)
4564 {
4565 struct reg_dev_req payload;
4566 u32 opc;
4567 u32 stp_sspsmp_sata = 0x4;
4568 struct inbound_queue_table *circularQ;
4569 u32 linkrate, phy_id;
4570 int rc, tag = 0xdeadbeef;
4571 struct pm8001_ccb_info *ccb;
4572 u8 retryFlag = 0x1;
4573 u16 firstBurstSize = 0;
4574 u16 ITNT = 2000;
4575 struct domain_device *dev = pm8001_dev->sas_device;
4576 struct domain_device *parent_dev = dev->parent;
4577 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4578
4579 memset(&payload, 0, sizeof(payload));
4580 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4581 if (rc)
4582 return rc;
4583 ccb = &pm8001_ha->ccb_info[tag];
4584 ccb->device = pm8001_dev;
4585 ccb->ccb_tag = tag;
4586 payload.tag = cpu_to_le32(tag);
4587 if (flag == 1)
4588 stp_sspsmp_sata = 0x02; /*direct attached sata */
4589 else {
4590 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4591 stp_sspsmp_sata = 0x00; /* stp*/
4592 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4593 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4594 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4595 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4596 }
4597 if (parent_dev && dev_is_expander(parent_dev->dev_type))
4598 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4599 else
4600 phy_id = pm8001_dev->attached_phy;
4601 opc = OPC_INB_REG_DEV;
4602 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4603 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4604 payload.phyid_portid =
4605 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
4606 ((phy_id & 0x0F) << 4));
4607 payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4608 ((linkrate & 0x0F) * 0x1000000) |
4609 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4610 payload.firstburstsize_ITNexustimeout =
4611 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4612 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4613 SAS_ADDR_SIZE);
4614 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4615 sizeof(payload), 0);
4616 return rc;
4617 }
4618
4619 /**
4620 * see comments on pm8001_mpi_reg_resp.
4621 */
4622 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4623 u32 device_id)
4624 {
4625 struct dereg_dev_req payload;
4626 u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4627 int ret;
4628 struct inbound_queue_table *circularQ;
4629
4630 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4631 memset(&payload, 0, sizeof(payload));
4632 payload.tag = cpu_to_le32(1);
4633 payload.device_id = cpu_to_le32(device_id);
4634 PM8001_MSG_DBG(pm8001_ha,
4635 pm8001_printk("unregister device device_id = %d\n", device_id));
4636 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4637 sizeof(payload), 0);
4638 return ret;
4639 }
4640
4641 /**
4642 * pm8001_chip_phy_ctl_req - support the local phy operation
4643 * @pm8001_ha: our hba card information.
4644 * @num: the inbound queue number
4645 * @phy_id: the phy id which we wanted to operate
4646 * @phy_op:
4647 */
4648 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4649 u32 phyId, u32 phy_op)
4650 {
4651 struct local_phy_ctl_req payload;
4652 struct inbound_queue_table *circularQ;
4653 int ret;
4654 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4655 memset(&payload, 0, sizeof(payload));
4656 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4657 payload.tag = cpu_to_le32(1);
4658 payload.phyop_phyid =
4659 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4660 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4661 sizeof(payload), 0);
4662 return ret;
4663 }
4664
4665 static u32 pm8001_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4666 {
4667 #ifdef PM8001_USE_MSIX
4668 return 1;
4669 #else
4670 u32 value;
4671
4672 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4673 if (value)
4674 return 1;
4675 return 0;
4676 #endif
4677 }
4678
4679 /**
4680 * pm8001_chip_isr - PM8001 isr handler.
4681 * @pm8001_ha: our hba card information.
4682 * @irq: irq number.
4683 * @stat: stat.
4684 */
4685 static irqreturn_t
4686 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4687 {
4688 pm8001_chip_interrupt_disable(pm8001_ha, vec);
4689 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
4690 "irq vec %d, ODMR:0x%x\n",
4691 vec, pm8001_cr32(pm8001_ha, 0, 0x30)));
4692 process_oq(pm8001_ha, vec);
4693 pm8001_chip_interrupt_enable(pm8001_ha, vec);
4694 return IRQ_HANDLED;
4695 }
4696
4697 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4698 u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4699 {
4700 struct task_abort_req task_abort;
4701 struct inbound_queue_table *circularQ;
4702 int ret;
4703 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4704 memset(&task_abort, 0, sizeof(task_abort));
4705 if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4706 task_abort.abort_all = 0;
4707 task_abort.device_id = cpu_to_le32(dev_id);
4708 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4709 task_abort.tag = cpu_to_le32(cmd_tag);
4710 } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4711 task_abort.abort_all = cpu_to_le32(1);
4712 task_abort.device_id = cpu_to_le32(dev_id);
4713 task_abort.tag = cpu_to_le32(cmd_tag);
4714 }
4715 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
4716 sizeof(task_abort), 0);
4717 return ret;
4718 }
4719
4720 /**
4721 * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4722 * @task: the task we wanted to aborted.
4723 * @flag: the abort flag.
4724 */
4725 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4726 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4727 {
4728 u32 opc, device_id;
4729 int rc = TMF_RESP_FUNC_FAILED;
4730 PM8001_EH_DBG(pm8001_ha,
4731 pm8001_printk("cmd_tag = %x, abort task tag = 0x%x",
4732 cmd_tag, task_tag));
4733 if (pm8001_dev->dev_type == SAS_END_DEVICE)
4734 opc = OPC_INB_SSP_ABORT;
4735 else if (pm8001_dev->dev_type == SAS_SATA_DEV)
4736 opc = OPC_INB_SATA_ABORT;
4737 else
4738 opc = OPC_INB_SMP_ABORT;/* SMP */
4739 device_id = pm8001_dev->device_id;
4740 rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4741 task_tag, cmd_tag);
4742 if (rc != TMF_RESP_FUNC_COMPLETE)
4743 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc));
4744 return rc;
4745 }
4746
4747 /**
4748 * pm8001_chip_ssp_tm_req - built the task management command.
4749 * @pm8001_ha: our hba card information.
4750 * @ccb: the ccb information.
4751 * @tmf: task management function.
4752 */
4753 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4754 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4755 {
4756 struct sas_task *task = ccb->task;
4757 struct domain_device *dev = task->dev;
4758 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4759 u32 opc = OPC_INB_SSPINITMSTART;
4760 struct inbound_queue_table *circularQ;
4761 struct ssp_ini_tm_start_req sspTMCmd;
4762 int ret;
4763
4764 memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4765 sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4766 sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4767 sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4768 memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4769 sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4770 if (pm8001_ha->chip_id != chip_8001)
4771 sspTMCmd.ds_ads_m = 0x08;
4772 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4773 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd,
4774 sizeof(sspTMCmd), 0);
4775 return ret;
4776 }
4777
4778 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4779 void *payload)
4780 {
4781 u32 opc = OPC_INB_GET_NVMD_DATA;
4782 u32 nvmd_type;
4783 int rc;
4784 u32 tag;
4785 struct pm8001_ccb_info *ccb;
4786 struct inbound_queue_table *circularQ;
4787 struct get_nvm_data_req nvmd_req;
4788 struct fw_control_ex *fw_control_context;
4789 struct pm8001_ioctl_payload *ioctl_payload = payload;
4790
4791 nvmd_type = ioctl_payload->minor_function;
4792 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4793 if (!fw_control_context)
4794 return -ENOMEM;
4795 fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific;
4796 fw_control_context->len = ioctl_payload->rd_length;
4797 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4798 memset(&nvmd_req, 0, sizeof(nvmd_req));
4799 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4800 if (rc) {
4801 kfree(fw_control_context);
4802 return rc;
4803 }
4804 ccb = &pm8001_ha->ccb_info[tag];
4805 ccb->ccb_tag = tag;
4806 ccb->fw_control_context = fw_control_context;
4807 nvmd_req.tag = cpu_to_le32(tag);
4808
4809 switch (nvmd_type) {
4810 case TWI_DEVICE: {
4811 u32 twi_addr, twi_page_size;
4812 twi_addr = 0xa8;
4813 twi_page_size = 2;
4814
4815 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4816 twi_page_size << 8 | TWI_DEVICE);
4817 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4818 nvmd_req.resp_addr_hi =
4819 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4820 nvmd_req.resp_addr_lo =
4821 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4822 break;
4823 }
4824 case C_SEEPROM: {
4825 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4826 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4827 nvmd_req.resp_addr_hi =
4828 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4829 nvmd_req.resp_addr_lo =
4830 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4831 break;
4832 }
4833 case VPD_FLASH: {
4834 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4835 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4836 nvmd_req.resp_addr_hi =
4837 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4838 nvmd_req.resp_addr_lo =
4839 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4840 break;
4841 }
4842 case EXPAN_ROM: {
4843 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4844 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4845 nvmd_req.resp_addr_hi =
4846 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4847 nvmd_req.resp_addr_lo =
4848 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4849 break;
4850 }
4851 case IOP_RDUMP: {
4852 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP);
4853 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4854 nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset);
4855 nvmd_req.resp_addr_hi =
4856 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4857 nvmd_req.resp_addr_lo =
4858 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4859 break;
4860 }
4861 default:
4862 break;
4863 }
4864 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req,
4865 sizeof(nvmd_req), 0);
4866 if (rc) {
4867 kfree(fw_control_context);
4868 pm8001_tag_free(pm8001_ha, tag);
4869 }
4870 return rc;
4871 }
4872
4873 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4874 void *payload)
4875 {
4876 u32 opc = OPC_INB_SET_NVMD_DATA;
4877 u32 nvmd_type;
4878 int rc;
4879 u32 tag;
4880 struct pm8001_ccb_info *ccb;
4881 struct inbound_queue_table *circularQ;
4882 struct set_nvm_data_req nvmd_req;
4883 struct fw_control_ex *fw_control_context;
4884 struct pm8001_ioctl_payload *ioctl_payload = payload;
4885
4886 nvmd_type = ioctl_payload->minor_function;
4887 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4888 if (!fw_control_context)
4889 return -ENOMEM;
4890 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4891 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4892 &ioctl_payload->func_specific,
4893 ioctl_payload->wr_length);
4894 memset(&nvmd_req, 0, sizeof(nvmd_req));
4895 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4896 if (rc) {
4897 kfree(fw_control_context);
4898 return -EBUSY;
4899 }
4900 ccb = &pm8001_ha->ccb_info[tag];
4901 ccb->fw_control_context = fw_control_context;
4902 ccb->ccb_tag = tag;
4903 nvmd_req.tag = cpu_to_le32(tag);
4904 switch (nvmd_type) {
4905 case TWI_DEVICE: {
4906 u32 twi_addr, twi_page_size;
4907 twi_addr = 0xa8;
4908 twi_page_size = 2;
4909 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4910 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4911 twi_page_size << 8 | TWI_DEVICE);
4912 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4913 nvmd_req.resp_addr_hi =
4914 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4915 nvmd_req.resp_addr_lo =
4916 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4917 break;
4918 }
4919 case C_SEEPROM:
4920 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4921 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4922 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4923 nvmd_req.resp_addr_hi =
4924 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4925 nvmd_req.resp_addr_lo =
4926 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4927 break;
4928 case VPD_FLASH:
4929 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4930 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4931 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4932 nvmd_req.resp_addr_hi =
4933 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4934 nvmd_req.resp_addr_lo =
4935 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4936 break;
4937 case EXPAN_ROM:
4938 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4939 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4940 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4941 nvmd_req.resp_addr_hi =
4942 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4943 nvmd_req.resp_addr_lo =
4944 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4945 break;
4946 default:
4947 break;
4948 }
4949 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req,
4950 sizeof(nvmd_req), 0);
4951 if (rc) {
4952 kfree(fw_control_context);
4953 pm8001_tag_free(pm8001_ha, tag);
4954 }
4955 return rc;
4956 }
4957
4958 /**
4959 * pm8001_chip_fw_flash_update_build - support the firmware update operation
4960 * @pm8001_ha: our hba card information.
4961 * @fw_flash_updata_info: firmware flash update param
4962 */
4963 int
4964 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4965 void *fw_flash_updata_info, u32 tag)
4966 {
4967 struct fw_flash_Update_req payload;
4968 struct fw_flash_updata_info *info;
4969 struct inbound_queue_table *circularQ;
4970 int ret;
4971 u32 opc = OPC_INB_FW_FLASH_UPDATE;
4972
4973 memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4974 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4975 info = fw_flash_updata_info;
4976 payload.tag = cpu_to_le32(tag);
4977 payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4978 payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4979 payload.total_image_len = cpu_to_le32(info->total_image_len);
4980 payload.len = info->sgl.im_len.len ;
4981 payload.sgl_addr_lo =
4982 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr)));
4983 payload.sgl_addr_hi =
4984 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr)));
4985 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4986 sizeof(payload), 0);
4987 return ret;
4988 }
4989
4990 int
4991 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4992 void *payload)
4993 {
4994 struct fw_flash_updata_info flash_update_info;
4995 struct fw_control_info *fw_control;
4996 struct fw_control_ex *fw_control_context;
4997 int rc;
4998 u32 tag;
4999 struct pm8001_ccb_info *ccb;
5000 void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr;
5001 dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr;
5002 struct pm8001_ioctl_payload *ioctl_payload = payload;
5003
5004 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
5005 if (!fw_control_context)
5006 return -ENOMEM;
5007 fw_control = (struct fw_control_info *)&ioctl_payload->func_specific;
5008 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
5009 "dma fw_control context input length :%x\n", fw_control->len));
5010 memcpy(buffer, fw_control->buffer, fw_control->len);
5011 flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
5012 flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
5013 flash_update_info.sgl.im_len.e = 0;
5014 flash_update_info.cur_image_offset = fw_control->offset;
5015 flash_update_info.cur_image_len = fw_control->len;
5016 flash_update_info.total_image_len = fw_control->size;
5017 fw_control_context->fw_control = fw_control;
5018 fw_control_context->virtAddr = buffer;
5019 fw_control_context->phys_addr = phys_addr;
5020 fw_control_context->len = fw_control->len;
5021 rc = pm8001_tag_alloc(pm8001_ha, &tag);
5022 if (rc) {
5023 kfree(fw_control_context);
5024 return -EBUSY;
5025 }
5026 ccb = &pm8001_ha->ccb_info[tag];
5027 ccb->fw_control_context = fw_control_context;
5028 ccb->ccb_tag = tag;
5029 rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
5030 tag);
5031 return rc;
5032 }
5033
5034 ssize_t
5035 pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf)
5036 {
5037 u32 value, rem, offset = 0, bar = 0;
5038 u32 index, work_offset, dw_length;
5039 u32 shift_value, gsm_base, gsm_dump_offset;
5040 char *direct_data;
5041 struct Scsi_Host *shost = class_to_shost(cdev);
5042 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
5043 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
5044
5045 direct_data = buf;
5046 gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset;
5047
5048 /* check max is 1 Mbytes */
5049 if ((length > 0x100000) || (gsm_dump_offset & 3) ||
5050 ((gsm_dump_offset + length) > 0x1000000))
5051 return -EINVAL;
5052
5053 if (pm8001_ha->chip_id == chip_8001)
5054 bar = 2;
5055 else
5056 bar = 1;
5057
5058 work_offset = gsm_dump_offset & 0xFFFF0000;
5059 offset = gsm_dump_offset & 0x0000FFFF;
5060 gsm_dump_offset = work_offset;
5061 /* adjust length to dword boundary */
5062 rem = length & 3;
5063 dw_length = length >> 2;
5064
5065 for (index = 0; index < dw_length; index++) {
5066 if ((work_offset + offset) & 0xFFFF0000) {
5067 if (pm8001_ha->chip_id == chip_8001)
5068 shift_value = ((gsm_dump_offset + offset) &
5069 SHIFT_REG_64K_MASK);
5070 else
5071 shift_value = (((gsm_dump_offset + offset) &
5072 SHIFT_REG_64K_MASK) >>
5073 SHIFT_REG_BIT_SHIFT);
5074
5075 if (pm8001_ha->chip_id == chip_8001) {
5076 gsm_base = GSM_BASE;
5077 if (-1 == pm8001_bar4_shift(pm8001_ha,
5078 (gsm_base + shift_value)))
5079 return -EIO;
5080 } else {
5081 gsm_base = 0;
5082 if (-1 == pm80xx_bar4_shift(pm8001_ha,
5083 (gsm_base + shift_value)))
5084 return -EIO;
5085 }
5086 gsm_dump_offset = (gsm_dump_offset + offset) &
5087 0xFFFF0000;
5088 work_offset = 0;
5089 offset = offset & 0x0000FFFF;
5090 }
5091 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
5092 0x0000FFFF);
5093 direct_data += sprintf(direct_data, "%08x ", value);
5094 offset += 4;
5095 }
5096 if (rem != 0) {
5097 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
5098 0x0000FFFF);
5099 /* xfr for non_dw */
5100 direct_data += sprintf(direct_data, "%08x ", value);
5101 }
5102 /* Shift back to BAR4 original address */
5103 if (-1 == pm8001_bar4_shift(pm8001_ha, 0))
5104 return -EIO;
5105 pm8001_ha->fatal_forensic_shift_offset += 1024;
5106
5107 if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000)
5108 pm8001_ha->fatal_forensic_shift_offset = 0;
5109 return direct_data - buf;
5110 }
5111
5112 int
5113 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
5114 struct pm8001_device *pm8001_dev, u32 state)
5115 {
5116 struct set_dev_state_req payload;
5117 struct inbound_queue_table *circularQ;
5118 struct pm8001_ccb_info *ccb;
5119 int rc;
5120 u32 tag;
5121 u32 opc = OPC_INB_SET_DEVICE_STATE;
5122 memset(&payload, 0, sizeof(payload));
5123 rc = pm8001_tag_alloc(pm8001_ha, &tag);
5124 if (rc)
5125 return -1;
5126 ccb = &pm8001_ha->ccb_info[tag];
5127 ccb->ccb_tag = tag;
5128 ccb->device = pm8001_dev;
5129 circularQ = &pm8001_ha->inbnd_q_tbl[0];
5130 payload.tag = cpu_to_le32(tag);
5131 payload.device_id = cpu_to_le32(pm8001_dev->device_id);
5132 payload.nds = cpu_to_le32(state);
5133 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
5134 sizeof(payload), 0);
5135 return rc;
5136
5137 }
5138
5139 static int
5140 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
5141 {
5142 struct sas_re_initialization_req payload;
5143 struct inbound_queue_table *circularQ;
5144 struct pm8001_ccb_info *ccb;
5145 int rc;
5146 u32 tag;
5147 u32 opc = OPC_INB_SAS_RE_INITIALIZE;
5148 memset(&payload, 0, sizeof(payload));
5149 rc = pm8001_tag_alloc(pm8001_ha, &tag);
5150 if (rc)
5151 return -ENOMEM;
5152 ccb = &pm8001_ha->ccb_info[tag];
5153 ccb->ccb_tag = tag;
5154 circularQ = &pm8001_ha->inbnd_q_tbl[0];
5155 payload.tag = cpu_to_le32(tag);
5156 payload.SSAHOLT = cpu_to_le32(0xd << 25);
5157 payload.sata_hol_tmo = cpu_to_le32(80);
5158 payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
5159 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
5160 sizeof(payload), 0);
5161 if (rc)
5162 pm8001_tag_free(pm8001_ha, tag);
5163 return rc;
5164
5165 }
5166
5167 const struct pm8001_dispatch pm8001_8001_dispatch = {
5168 .name = "pmc8001",
5169 .chip_init = pm8001_chip_init,
5170 .chip_soft_rst = pm8001_chip_soft_rst,
5171 .chip_rst = pm8001_hw_chip_rst,
5172 .chip_iounmap = pm8001_chip_iounmap,
5173 .isr = pm8001_chip_isr,
5174 .is_our_interrupt = pm8001_chip_is_our_interrupt,
5175 .isr_process_oq = process_oq,
5176 .interrupt_enable = pm8001_chip_interrupt_enable,
5177 .interrupt_disable = pm8001_chip_interrupt_disable,
5178 .make_prd = pm8001_chip_make_sg,
5179 .smp_req = pm8001_chip_smp_req,
5180 .ssp_io_req = pm8001_chip_ssp_io_req,
5181 .sata_req = pm8001_chip_sata_req,
5182 .phy_start_req = pm8001_chip_phy_start_req,
5183 .phy_stop_req = pm8001_chip_phy_stop_req,
5184 .reg_dev_req = pm8001_chip_reg_dev_req,
5185 .dereg_dev_req = pm8001_chip_dereg_dev_req,
5186 .phy_ctl_req = pm8001_chip_phy_ctl_req,
5187 .task_abort = pm8001_chip_abort_task,
5188 .ssp_tm_req = pm8001_chip_ssp_tm_req,
5189 .get_nvmd_req = pm8001_chip_get_nvmd_req,
5190 .set_nvmd_req = pm8001_chip_set_nvmd_req,
5191 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
5192 .set_dev_state_req = pm8001_chip_set_dev_state_req,
5193 .sas_re_init_req = pm8001_chip_sas_re_initialization,
5194 };
Linux with added FPC-III support