gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / scsi / pm8001 / pm80xx_hwi.c
blob4d205ebaee87dc0bb05b429c33cf92e6ea9c3c5c
1 /*
2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
5 * All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm80xx_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
46 #define SMP_DIRECT 1
47 #define SMP_INDIRECT 2
50 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
52 u32 reg_val;
53 unsigned long start;
54 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
55 /* confirm the setting is written */
56 start = jiffies + HZ; /* 1 sec */
57 do {
58 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
59 } while ((reg_val != shift_value) && time_before(jiffies, start));
60 if (reg_val != shift_value) {
61 PM8001_FAIL_DBG(pm8001_ha,
62 pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
63 " = 0x%x\n", reg_val));
64 return -1;
66 return 0;
69 void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset,
70 const void *destination,
71 u32 dw_count, u32 bus_base_number)
73 u32 index, value, offset;
74 u32 *destination1;
75 destination1 = (u32 *)destination;
77 for (index = 0; index < dw_count; index += 4, destination1++) {
78 offset = (soffset + index);
79 if (offset < (64 * 1024)) {
80 value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
81 *destination1 = cpu_to_le32(value);
84 return;
87 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
88 struct device_attribute *attr, char *buf)
90 struct Scsi_Host *shost = class_to_shost(cdev);
91 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
92 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
93 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
94 u32 accum_len , reg_val, index, *temp;
95 u32 status = 1;
96 unsigned long start;
97 u8 *direct_data;
98 char *fatal_error_data = buf;
99 u32 length_to_read;
100 u32 offset;
102 pm8001_ha->forensic_info.data_buf.direct_data = buf;
103 if (pm8001_ha->chip_id == chip_8001) {
104 pm8001_ha->forensic_info.data_buf.direct_data +=
105 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
106 "Not supported for SPC controller");
107 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
108 (char *)buf;
110 /* initialize variables for very first call from host application */
111 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
112 PM8001_IO_DBG(pm8001_ha,
113 pm8001_printk("forensic_info TYPE_NON_FATAL..............\n"));
114 direct_data = (u8 *)fatal_error_data;
115 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
116 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
117 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
118 pm8001_ha->forensic_info.data_buf.read_len = 0;
119 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
121 /* Write signature to fatal dump table */
122 pm8001_mw32(fatal_table_address,
123 MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd);
125 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
126 PM8001_IO_DBG(pm8001_ha,
127 pm8001_printk("ossaHwCB: status1 %d\n", status));
128 PM8001_IO_DBG(pm8001_ha,
129 pm8001_printk("ossaHwCB: read_len 0x%x\n",
130 pm8001_ha->forensic_info.data_buf.read_len));
131 PM8001_IO_DBG(pm8001_ha,
132 pm8001_printk("ossaHwCB: direct_len 0x%x\n",
133 pm8001_ha->forensic_info.data_buf.direct_len));
134 PM8001_IO_DBG(pm8001_ha,
135 pm8001_printk("ossaHwCB: direct_offset 0x%x\n",
136 pm8001_ha->forensic_info.data_buf.direct_offset));
138 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
139 /* start to get data */
140 /* Program the MEMBASE II Shifting Register with 0x00.*/
141 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
142 pm8001_ha->fatal_forensic_shift_offset);
143 pm8001_ha->forensic_last_offset = 0;
144 pm8001_ha->forensic_fatal_step = 0;
145 pm8001_ha->fatal_bar_loc = 0;
148 /* Read until accum_len is retrived */
149 accum_len = pm8001_mr32(fatal_table_address,
150 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
151 /* Determine length of data between previously stored transfer length
152 * and current accumulated transfer length
154 length_to_read =
155 accum_len - pm8001_ha->forensic_preserved_accumulated_transfer;
156 PM8001_IO_DBG(pm8001_ha,
157 pm8001_printk("get_fatal_spcv: accum_len 0x%x\n", accum_len));
158 PM8001_IO_DBG(pm8001_ha,
159 pm8001_printk("get_fatal_spcv: length_to_read 0x%x\n",
160 length_to_read));
161 PM8001_IO_DBG(pm8001_ha,
162 pm8001_printk("get_fatal_spcv: last_offset 0x%x\n",
163 pm8001_ha->forensic_last_offset));
164 PM8001_IO_DBG(pm8001_ha,
165 pm8001_printk("get_fatal_spcv: read_len 0x%x\n",
166 pm8001_ha->forensic_info.data_buf.read_len));
167 PM8001_IO_DBG(pm8001_ha,
168 pm8001_printk("get_fatal_spcv:: direct_len 0x%x\n",
169 pm8001_ha->forensic_info.data_buf.direct_len));
170 PM8001_IO_DBG(pm8001_ha,
171 pm8001_printk("get_fatal_spcv:: direct_offset 0x%x\n",
172 pm8001_ha->forensic_info.data_buf.direct_offset));
174 /* If accumulated length failed to read correctly fail the attempt.*/
175 if (accum_len == 0xFFFFFFFF) {
176 PM8001_IO_DBG(pm8001_ha,
177 pm8001_printk("Possible PCI issue 0x%x not expected\n",
178 accum_len));
179 return status;
181 /* If accumulated length is zero fail the attempt */
182 if (accum_len == 0) {
183 pm8001_ha->forensic_info.data_buf.direct_data +=
184 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
185 "%08x ", 0xFFFFFFFF);
186 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
187 (char *)buf;
189 /* Accumulated length is good so start capturing the first data */
190 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
191 if (pm8001_ha->forensic_fatal_step == 0) {
192 moreData:
193 /* If data to read is less than SYSFS_OFFSET then reduce the
194 * length of dataLen
196 if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET
197 > length_to_read) {
198 pm8001_ha->forensic_info.data_buf.direct_len =
199 length_to_read -
200 pm8001_ha->forensic_last_offset;
201 } else {
202 pm8001_ha->forensic_info.data_buf.direct_len =
203 SYSFS_OFFSET;
205 if (pm8001_ha->forensic_info.data_buf.direct_data) {
206 /* Data is in bar, copy to host memory */
207 pm80xx_pci_mem_copy(pm8001_ha,
208 pm8001_ha->fatal_bar_loc,
209 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
210 pm8001_ha->forensic_info.data_buf.direct_len, 1);
212 pm8001_ha->fatal_bar_loc +=
213 pm8001_ha->forensic_info.data_buf.direct_len;
214 pm8001_ha->forensic_info.data_buf.direct_offset +=
215 pm8001_ha->forensic_info.data_buf.direct_len;
216 pm8001_ha->forensic_last_offset +=
217 pm8001_ha->forensic_info.data_buf.direct_len;
218 pm8001_ha->forensic_info.data_buf.read_len =
219 pm8001_ha->forensic_info.data_buf.direct_len;
221 if (pm8001_ha->forensic_last_offset >= length_to_read) {
222 pm8001_ha->forensic_info.data_buf.direct_data +=
223 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
224 "%08x ", 3);
225 for (index = 0; index <
226 (pm8001_ha->forensic_info.data_buf.direct_len
227 / 4); index++) {
228 pm8001_ha->forensic_info.data_buf.direct_data +=
229 sprintf(
230 pm8001_ha->forensic_info.data_buf.direct_data,
231 "%08x ", *(temp + index));
234 pm8001_ha->fatal_bar_loc = 0;
235 pm8001_ha->forensic_fatal_step = 1;
236 pm8001_ha->fatal_forensic_shift_offset = 0;
237 pm8001_ha->forensic_last_offset = 0;
238 status = 0;
239 offset = (int)
240 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
241 - (char *)buf);
242 PM8001_IO_DBG(pm8001_ha,
243 pm8001_printk("get_fatal_spcv:return1 0x%x\n", offset));
244 return (char *)pm8001_ha->
245 forensic_info.data_buf.direct_data -
246 (char *)buf;
248 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
249 pm8001_ha->forensic_info.data_buf.direct_data +=
250 sprintf(pm8001_ha->
251 forensic_info.data_buf.direct_data,
252 "%08x ", 2);
253 for (index = 0; index <
254 (pm8001_ha->forensic_info.data_buf.direct_len
255 / 4); index++) {
256 pm8001_ha->forensic_info.data_buf.direct_data
257 += sprintf(pm8001_ha->
258 forensic_info.data_buf.direct_data,
259 "%08x ", *(temp + index));
261 status = 0;
262 offset = (int)
263 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
264 - (char *)buf);
265 PM8001_IO_DBG(pm8001_ha,
266 pm8001_printk("get_fatal_spcv:return2 0x%x\n", offset));
267 return (char *)pm8001_ha->
268 forensic_info.data_buf.direct_data -
269 (char *)buf;
272 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
273 pm8001_ha->forensic_info.data_buf.direct_data +=
274 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
275 "%08x ", 2);
276 for (index = 0; index <
277 (pm8001_ha->forensic_info.data_buf.direct_len
278 / 4) ; index++) {
279 pm8001_ha->forensic_info.data_buf.direct_data +=
280 sprintf(pm8001_ha->
281 forensic_info.data_buf.direct_data,
282 "%08x ", *(temp + index));
284 pm8001_ha->fatal_forensic_shift_offset += 0x100;
285 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
286 pm8001_ha->fatal_forensic_shift_offset);
287 pm8001_ha->fatal_bar_loc = 0;
288 status = 0;
289 offset = (int)
290 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
291 - (char *)buf);
292 PM8001_IO_DBG(pm8001_ha,
293 pm8001_printk("get_fatal_spcv: return3 0x%x\n", offset));
294 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
295 (char *)buf;
297 if (pm8001_ha->forensic_fatal_step == 1) {
298 /* store previous accumulated length before triggering next
299 * accumulated length update
301 pm8001_ha->forensic_preserved_accumulated_transfer =
302 pm8001_mr32(fatal_table_address,
303 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
305 /* continue capturing the fatal log until Dump status is 0x3 */
306 if (pm8001_mr32(fatal_table_address,
307 MPI_FATAL_EDUMP_TABLE_STATUS) <
308 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
310 /* reset fddstat bit by writing to zero*/
311 pm8001_mw32(fatal_table_address,
312 MPI_FATAL_EDUMP_TABLE_STATUS, 0x0);
314 /* set dump control value to '1' so that new data will
315 * be transferred to shared memory
317 pm8001_mw32(fatal_table_address,
318 MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
319 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
321 /*Poll FDDHSHK until clear */
322 start = jiffies + (2 * HZ); /* 2 sec */
324 do {
325 reg_val = pm8001_mr32(fatal_table_address,
326 MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
327 } while ((reg_val) && time_before(jiffies, start));
329 if (reg_val != 0) {
330 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
331 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n",
332 reg_val));
333 /* Fail the dump if a timeout occurs */
334 pm8001_ha->forensic_info.data_buf.direct_data +=
335 sprintf(
336 pm8001_ha->forensic_info.data_buf.direct_data,
337 "%08x ", 0xFFFFFFFF);
338 return((char *)
339 pm8001_ha->forensic_info.data_buf.direct_data
340 - (char *)buf);
342 /* Poll status register until set to 2 or
343 * 3 for up to 2 seconds
345 start = jiffies + (2 * HZ); /* 2 sec */
347 do {
348 reg_val = pm8001_mr32(fatal_table_address,
349 MPI_FATAL_EDUMP_TABLE_STATUS);
350 } while (((reg_val != 2) && (reg_val != 3)) &&
351 time_before(jiffies, start));
353 if (reg_val < 2) {
354 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
355 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n",
356 reg_val));
357 /* Fail the dump if a timeout occurs */
358 pm8001_ha->forensic_info.data_buf.direct_data +=
359 sprintf(
360 pm8001_ha->forensic_info.data_buf.direct_data,
361 "%08x ", 0xFFFFFFFF);
362 pm8001_cw32(pm8001_ha, 0,
363 MEMBASE_II_SHIFT_REGISTER,
364 pm8001_ha->fatal_forensic_shift_offset);
366 /* Read the next block of the debug data.*/
367 length_to_read = pm8001_mr32(fatal_table_address,
368 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) -
369 pm8001_ha->forensic_preserved_accumulated_transfer;
370 if (length_to_read != 0x0) {
371 pm8001_ha->forensic_fatal_step = 0;
372 goto moreData;
373 } else {
374 pm8001_ha->forensic_info.data_buf.direct_data +=
375 sprintf(
376 pm8001_ha->forensic_info.data_buf.direct_data,
377 "%08x ", 4);
378 pm8001_ha->forensic_info.data_buf.read_len
379 = 0xFFFFFFFF;
380 pm8001_ha->forensic_info.data_buf.direct_len
381 = 0;
382 pm8001_ha->forensic_info.data_buf.direct_offset
383 = 0;
384 pm8001_ha->forensic_info.data_buf.read_len = 0;
388 offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data
389 - (char *)buf);
390 PM8001_IO_DBG(pm8001_ha,
391 pm8001_printk("get_fatal_spcv: return4 0x%x\n", offset));
392 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
393 (char *)buf;
396 /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma
397 * location by the firmware.
399 ssize_t pm80xx_get_non_fatal_dump(struct device *cdev,
400 struct device_attribute *attr, char *buf)
402 struct Scsi_Host *shost = class_to_shost(cdev);
403 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
404 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
405 void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr;
406 u32 accum_len = 0;
407 u32 total_len = 0;
408 u32 reg_val = 0;
409 u32 *temp = NULL;
410 u32 index = 0;
411 u32 output_length;
412 unsigned long start = 0;
413 char *buf_copy = buf;
415 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
416 if (++pm8001_ha->non_fatal_count == 1) {
417 if (pm8001_ha->chip_id == chip_8001) {
418 snprintf(pm8001_ha->forensic_info.data_buf.direct_data,
419 PAGE_SIZE, "Not supported for SPC controller");
420 return 0;
422 PM8001_IO_DBG(pm8001_ha,
423 pm8001_printk("forensic_info TYPE_NON_FATAL...\n"));
425 * Step 1: Write the host buffer parameters in the MPI Fatal and
426 * Non-Fatal Error Dump Capture Table.This is the buffer
427 * where debug data will be DMAed to.
429 pm8001_mw32(nonfatal_table_address,
430 MPI_FATAL_EDUMP_TABLE_LO_OFFSET,
431 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo);
433 pm8001_mw32(nonfatal_table_address,
434 MPI_FATAL_EDUMP_TABLE_HI_OFFSET,
435 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi);
437 pm8001_mw32(nonfatal_table_address,
438 MPI_FATAL_EDUMP_TABLE_LENGTH, SYSFS_OFFSET);
440 /* Optionally, set the DUMPCTRL bit to 1 if the host
441 * keeps sending active I/Os while capturing the non-fatal
442 * debug data. Otherwise, leave this bit set to zero
444 pm8001_mw32(nonfatal_table_address,
445 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY);
448 * Step 2: Clear Accumulative Length of Debug Data Transferred
449 * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump
450 * Capture Table to zero.
452 pm8001_mw32(nonfatal_table_address,
453 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0);
455 /* initiallize previous accumulated length to 0 */
456 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
457 pm8001_ha->non_fatal_read_length = 0;
460 total_len = pm8001_mr32(nonfatal_table_address,
461 MPI_FATAL_EDUMP_TABLE_TOTAL_LEN);
463 * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT]
464 * field and then request that the SPCv controller transfer the debug
465 * data by setting bit 7 of the Inbound Doorbell Set Register.
467 pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0);
468 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET,
469 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP);
472 * Step 4.1: Read back the Inbound Doorbell Set Register (by polling for
473 * 2 seconds) until register bit 7 is cleared.
474 * This step only indicates the request is accepted by the controller.
476 start = jiffies + (2 * HZ); /* 2 sec */
477 do {
478 reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) &
479 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP;
480 } while ((reg_val != 0) && time_before(jiffies, start));
482 /* Step 4.2: To check the completion of the transfer, poll the Fatal/Non
483 * Fatal Debug Data Transfer Status [FDDTSTAT] field for 2 seconds in
484 * the MPI Fatal and Non-Fatal Error Dump Capture Table.
486 start = jiffies + (2 * HZ); /* 2 sec */
487 do {
488 reg_val = pm8001_mr32(nonfatal_table_address,
489 MPI_FATAL_EDUMP_TABLE_STATUS);
490 } while ((!reg_val) && time_before(jiffies, start));
492 if ((reg_val == 0x00) ||
493 (reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) ||
494 (reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) {
495 pm8001_ha->non_fatal_read_length = 0;
496 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF);
497 pm8001_ha->non_fatal_count = 0;
498 return (buf_copy - buf);
499 } else if (reg_val ==
500 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA) {
501 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 2);
502 } else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) ||
503 (pm8001_ha->non_fatal_read_length >= total_len)) {
504 pm8001_ha->non_fatal_read_length = 0;
505 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 4);
506 pm8001_ha->non_fatal_count = 0;
508 accum_len = pm8001_mr32(nonfatal_table_address,
509 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
510 output_length = accum_len -
511 pm8001_ha->forensic_preserved_accumulated_transfer;
513 for (index = 0; index < output_length/4; index++)
514 buf_copy += snprintf(buf_copy, PAGE_SIZE,
515 "%08x ", *(temp+index));
517 pm8001_ha->non_fatal_read_length += output_length;
519 /* store current accumulated length to use in next iteration as
520 * the previous accumulated length
522 pm8001_ha->forensic_preserved_accumulated_transfer = accum_len;
523 return (buf_copy - buf);
527 * read_main_config_table - read the configure table and save it.
528 * @pm8001_ha: our hba card information
530 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
532 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
534 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature =
535 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
536 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
537 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
538 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
539 pm8001_mr32(address, MAIN_FW_REVISION);
540 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io =
541 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
542 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl =
543 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
544 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
545 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
546 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset =
547 pm8001_mr32(address, MAIN_GST_OFFSET);
548 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
549 pm8001_mr32(address, MAIN_IBQ_OFFSET);
550 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
551 pm8001_mr32(address, MAIN_OBQ_OFFSET);
553 /* read Error Dump Offset and Length */
554 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
555 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
556 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
557 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
558 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
559 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
560 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
561 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
563 /* read GPIO LED settings from the configuration table */
564 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
565 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
567 /* read analog Setting offset from the configuration table */
568 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
569 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
571 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
572 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
573 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
574 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
575 /* read port recover and reset timeout */
576 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
577 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
578 /* read ILA and inactive firmware version */
579 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version =
580 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE);
581 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version =
582 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION);
584 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
585 "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n",
586 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature,
587 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev,
588 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev));
590 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
591 "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n",
592 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset,
593 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset,
594 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset,
595 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset,
596 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset));
598 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
599 "Main cfg table; ila rev:%x Inactive fw rev:%x\n",
600 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version,
601 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version));
605 * read_general_status_table - read the general status table and save it.
606 * @pm8001_ha: our hba card information
608 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
610 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
611 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate =
612 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
613 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 =
614 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
615 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 =
616 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
617 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt =
618 pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
619 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt =
620 pm8001_mr32(address, GST_IOPTCNT_OFFSET);
621 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
622 pm8001_mr32(address, GST_GPIO_INPUT_VAL);
623 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
624 pm8001_mr32(address, GST_RERRINFO_OFFSET0);
625 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
626 pm8001_mr32(address, GST_RERRINFO_OFFSET1);
627 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
628 pm8001_mr32(address, GST_RERRINFO_OFFSET2);
629 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
630 pm8001_mr32(address, GST_RERRINFO_OFFSET3);
631 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
632 pm8001_mr32(address, GST_RERRINFO_OFFSET4);
633 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
634 pm8001_mr32(address, GST_RERRINFO_OFFSET5);
635 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
636 pm8001_mr32(address, GST_RERRINFO_OFFSET6);
637 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
638 pm8001_mr32(address, GST_RERRINFO_OFFSET7);
641 * read_phy_attr_table - read the phy attribute table and save it.
642 * @pm8001_ha: our hba card information
644 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
646 void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
647 pm8001_ha->phy_attr_table.phystart1_16[0] =
648 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
649 pm8001_ha->phy_attr_table.phystart1_16[1] =
650 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
651 pm8001_ha->phy_attr_table.phystart1_16[2] =
652 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
653 pm8001_ha->phy_attr_table.phystart1_16[3] =
654 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
655 pm8001_ha->phy_attr_table.phystart1_16[4] =
656 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
657 pm8001_ha->phy_attr_table.phystart1_16[5] =
658 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
659 pm8001_ha->phy_attr_table.phystart1_16[6] =
660 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
661 pm8001_ha->phy_attr_table.phystart1_16[7] =
662 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
663 pm8001_ha->phy_attr_table.phystart1_16[8] =
664 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
665 pm8001_ha->phy_attr_table.phystart1_16[9] =
666 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
667 pm8001_ha->phy_attr_table.phystart1_16[10] =
668 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
669 pm8001_ha->phy_attr_table.phystart1_16[11] =
670 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
671 pm8001_ha->phy_attr_table.phystart1_16[12] =
672 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
673 pm8001_ha->phy_attr_table.phystart1_16[13] =
674 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
675 pm8001_ha->phy_attr_table.phystart1_16[14] =
676 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
677 pm8001_ha->phy_attr_table.phystart1_16[15] =
678 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
680 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
681 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
682 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
683 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
684 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
685 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
686 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
687 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
688 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
689 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
690 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
691 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
692 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
693 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
694 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
695 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
696 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
697 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
698 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
699 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
700 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
701 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
702 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
703 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
704 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
705 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
706 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
707 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
708 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
709 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
710 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
711 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
716 * read_inbnd_queue_table - read the inbound queue table and save it.
717 * @pm8001_ha: our hba card information
719 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
721 int i;
722 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
723 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
724 u32 offset = i * 0x20;
725 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
726 get_pci_bar_index(pm8001_mr32(address,
727 (offset + IB_PIPCI_BAR)));
728 pm8001_ha->inbnd_q_tbl[i].pi_offset =
729 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
734 * read_outbnd_queue_table - read the outbound queue table and save it.
735 * @pm8001_ha: our hba card information
737 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
739 int i;
740 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
741 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
742 u32 offset = i * 0x24;
743 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
744 get_pci_bar_index(pm8001_mr32(address,
745 (offset + OB_CIPCI_BAR)));
746 pm8001_ha->outbnd_q_tbl[i].ci_offset =
747 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
752 * init_default_table_values - init the default table.
753 * @pm8001_ha: our hba card information
755 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
757 int i;
758 u32 offsetib, offsetob;
759 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
760 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
762 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr =
763 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
764 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr =
765 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
766 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size =
767 PM8001_EVENT_LOG_SIZE;
768 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01;
769 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
770 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
771 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
772 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
773 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size =
774 PM8001_EVENT_LOG_SIZE;
775 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01;
776 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01;
778 /* Disable end to end CRC checking */
779 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
781 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
782 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
783 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
784 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
785 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
786 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
787 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
788 pm8001_ha->inbnd_q_tbl[i].base_virt =
789 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
790 pm8001_ha->inbnd_q_tbl[i].total_length =
791 pm8001_ha->memoryMap.region[IB + i].total_len;
792 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
793 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
794 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
795 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
796 pm8001_ha->inbnd_q_tbl[i].ci_virt =
797 pm8001_ha->memoryMap.region[CI + i].virt_ptr;
798 offsetib = i * 0x20;
799 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
800 get_pci_bar_index(pm8001_mr32(addressib,
801 (offsetib + 0x14)));
802 pm8001_ha->inbnd_q_tbl[i].pi_offset =
803 pm8001_mr32(addressib, (offsetib + 0x18));
804 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
805 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
807 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
808 "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i,
809 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar,
810 pm8001_ha->inbnd_q_tbl[i].pi_offset));
812 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
813 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
814 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
815 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
816 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
817 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
818 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
819 pm8001_ha->outbnd_q_tbl[i].base_virt =
820 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
821 pm8001_ha->outbnd_q_tbl[i].total_length =
822 pm8001_ha->memoryMap.region[OB + i].total_len;
823 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
824 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
825 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
826 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
827 /* interrupt vector based on oq */
828 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
829 pm8001_ha->outbnd_q_tbl[i].pi_virt =
830 pm8001_ha->memoryMap.region[PI + i].virt_ptr;
831 offsetob = i * 0x24;
832 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
833 get_pci_bar_index(pm8001_mr32(addressob,
834 offsetob + 0x14));
835 pm8001_ha->outbnd_q_tbl[i].ci_offset =
836 pm8001_mr32(addressob, (offsetob + 0x18));
837 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
838 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
840 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
841 "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i,
842 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar,
843 pm8001_ha->outbnd_q_tbl[i].ci_offset));
848 * update_main_config_table - update the main default table to the HBA.
849 * @pm8001_ha: our hba card information
851 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
853 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
854 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
855 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
856 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
857 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
858 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
859 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
860 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
861 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
862 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
863 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
864 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
865 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
866 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
867 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
868 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
869 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
870 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
871 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
872 /* Update Fatal error interrupt vector */
873 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
874 ((pm8001_ha->number_of_intr - 1) << 8);
875 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
876 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
877 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
878 "Updated Fatal error interrupt vector 0x%x\n",
879 pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT)));
881 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
882 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
884 /* SPCv specific */
885 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
886 /* Set GPIOLED to 0x2 for LED indicator */
887 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
888 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
889 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
890 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
891 "Programming DW 0x21 in main cfg table with 0x%x\n",
892 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET)));
894 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
895 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
896 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
897 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
899 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
900 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
901 PORT_RECOVERY_TIMEOUT;
902 if (pm8001_ha->chip_id == chip_8006) {
903 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &=
904 0x0000ffff;
905 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
906 CHIP_8006_PORT_RECOVERY_TIMEOUT;
908 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
909 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
913 * update_inbnd_queue_table - update the inbound queue table to the HBA.
914 * @pm8001_ha: our hba card information
916 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
917 int number)
919 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
920 u16 offset = number * 0x20;
921 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
922 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
923 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
924 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
925 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
926 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
927 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
928 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
929 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
930 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
932 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
933 "IQ %d: Element pri size 0x%x\n",
934 number,
935 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt));
937 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
938 "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n",
939 pm8001_ha->inbnd_q_tbl[number].upper_base_addr,
940 pm8001_ha->inbnd_q_tbl[number].lower_base_addr));
942 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
943 "CI upper base addr 0x%x CI lower base addr 0x%x\n",
944 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr,
945 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr));
949 * update_outbnd_queue_table - update the outbound queue table to the HBA.
950 * @pm8001_ha: our hba card information
952 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
953 int number)
955 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
956 u16 offset = number * 0x24;
957 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
958 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
959 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
960 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
961 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
962 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
963 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
964 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
965 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
966 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
967 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
968 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
970 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
971 "OQ %d: Element pri size 0x%x\n",
972 number,
973 pm8001_ha->outbnd_q_tbl[number].element_size_cnt));
975 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
976 "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n",
977 pm8001_ha->outbnd_q_tbl[number].upper_base_addr,
978 pm8001_ha->outbnd_q_tbl[number].lower_base_addr));
980 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
981 "PI upper base addr 0x%x PI lower base addr 0x%x\n",
982 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr,
983 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr));
987 * mpi_init_check - check firmware initialization status.
988 * @pm8001_ha: our hba card information
990 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
992 u32 max_wait_count;
993 u32 value;
994 u32 gst_len_mpistate;
996 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
997 table is updated */
998 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
999 /* wait until Inbound DoorBell Clear Register toggled */
1000 if (IS_SPCV_12G(pm8001_ha->pdev)) {
1001 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
1002 } else {
1003 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
1005 do {
1006 udelay(1);
1007 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1008 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
1009 } while ((value != 0) && (--max_wait_count));
1011 if (!max_wait_count)
1012 return -1;
1013 /* check the MPI-State for initialization upto 100ms*/
1014 max_wait_count = 100 * 1000;/* 100 msec */
1015 do {
1016 udelay(1);
1017 gst_len_mpistate =
1018 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1019 GST_GSTLEN_MPIS_OFFSET);
1020 } while ((GST_MPI_STATE_INIT !=
1021 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
1022 if (!max_wait_count)
1023 return -1;
1025 /* check MPI Initialization error */
1026 gst_len_mpistate = gst_len_mpistate >> 16;
1027 if (0x0000 != gst_len_mpistate)
1028 return -1;
1030 return 0;
1034 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
1035 * @pm8001_ha: our hba card information
1037 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
1039 u32 value;
1040 u32 max_wait_count;
1041 u32 max_wait_time;
1042 int ret = 0;
1044 /* reset / PCIe ready */
1045 max_wait_time = max_wait_count = 100 * 1000; /* 100 milli sec */
1046 do {
1047 udelay(1);
1048 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1049 } while ((value == 0xFFFFFFFF) && (--max_wait_count));
1051 /* check ila status */
1052 max_wait_time = max_wait_count = 1000 * 1000; /* 1000 milli sec */
1053 do {
1054 udelay(1);
1055 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1056 } while (((value & SCRATCH_PAD_ILA_READY) !=
1057 SCRATCH_PAD_ILA_READY) && (--max_wait_count));
1058 if (!max_wait_count)
1059 ret = -1;
1060 else {
1061 PM8001_MSG_DBG(pm8001_ha,
1062 pm8001_printk(" ila ready status in %d millisec\n",
1063 (max_wait_time - max_wait_count)));
1066 /* check RAAE status */
1067 max_wait_time = max_wait_count = 1800 * 1000; /* 1800 milli sec */
1068 do {
1069 udelay(1);
1070 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1071 } while (((value & SCRATCH_PAD_RAAE_READY) !=
1072 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
1073 if (!max_wait_count)
1074 ret = -1;
1075 else {
1076 PM8001_MSG_DBG(pm8001_ha,
1077 pm8001_printk(" raae ready status in %d millisec\n",
1078 (max_wait_time - max_wait_count)));
1081 /* check iop0 status */
1082 max_wait_time = max_wait_count = 600 * 1000; /* 600 milli sec */
1083 do {
1084 udelay(1);
1085 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1086 } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
1087 (--max_wait_count));
1088 if (!max_wait_count)
1089 ret = -1;
1090 else {
1091 PM8001_MSG_DBG(pm8001_ha,
1092 pm8001_printk(" iop0 ready status in %d millisec\n",
1093 (max_wait_time - max_wait_count)));
1096 /* check iop1 status only for 16 port controllers */
1097 if ((pm8001_ha->chip_id != chip_8008) &&
1098 (pm8001_ha->chip_id != chip_8009)) {
1099 /* 200 milli sec */
1100 max_wait_time = max_wait_count = 200 * 1000;
1101 do {
1102 udelay(1);
1103 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1104 } while (((value & SCRATCH_PAD_IOP1_READY) !=
1105 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
1106 if (!max_wait_count)
1107 ret = -1;
1108 else {
1109 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1110 "iop1 ready status in %d millisec\n",
1111 (max_wait_time - max_wait_count)));
1115 return ret;
1118 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
1120 void __iomem *base_addr;
1121 u32 value;
1122 u32 offset;
1123 u32 pcibar;
1124 u32 pcilogic;
1126 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1127 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
1129 PM8001_DEV_DBG(pm8001_ha,
1130 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
1131 offset, value));
1132 pcilogic = (value & 0xFC000000) >> 26;
1133 pcibar = get_pci_bar_index(pcilogic);
1134 PM8001_INIT_DBG(pm8001_ha,
1135 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
1136 pm8001_ha->main_cfg_tbl_addr = base_addr =
1137 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
1138 pm8001_ha->general_stat_tbl_addr =
1139 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
1140 0xFFFFFF);
1141 pm8001_ha->inbnd_q_tbl_addr =
1142 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
1143 0xFFFFFF);
1144 pm8001_ha->outbnd_q_tbl_addr =
1145 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
1146 0xFFFFFF);
1147 pm8001_ha->ivt_tbl_addr =
1148 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
1149 0xFFFFFF);
1150 pm8001_ha->pspa_q_tbl_addr =
1151 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
1152 0xFFFFFF);
1153 pm8001_ha->fatal_tbl_addr =
1154 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
1155 0xFFFFFF);
1157 PM8001_INIT_DBG(pm8001_ha,
1158 pm8001_printk("GST OFFSET 0x%x\n",
1159 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
1160 PM8001_INIT_DBG(pm8001_ha,
1161 pm8001_printk("INBND OFFSET 0x%x\n",
1162 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
1163 PM8001_INIT_DBG(pm8001_ha,
1164 pm8001_printk("OBND OFFSET 0x%x\n",
1165 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
1166 PM8001_INIT_DBG(pm8001_ha,
1167 pm8001_printk("IVT OFFSET 0x%x\n",
1168 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
1169 PM8001_INIT_DBG(pm8001_ha,
1170 pm8001_printk("PSPA OFFSET 0x%x\n",
1171 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
1172 PM8001_INIT_DBG(pm8001_ha,
1173 pm8001_printk("addr - main cfg %p general status %p\n",
1174 pm8001_ha->main_cfg_tbl_addr,
1175 pm8001_ha->general_stat_tbl_addr));
1176 PM8001_INIT_DBG(pm8001_ha,
1177 pm8001_printk("addr - inbnd %p obnd %p\n",
1178 pm8001_ha->inbnd_q_tbl_addr,
1179 pm8001_ha->outbnd_q_tbl_addr));
1180 PM8001_INIT_DBG(pm8001_ha,
1181 pm8001_printk("addr - pspa %p ivt %p\n",
1182 pm8001_ha->pspa_q_tbl_addr,
1183 pm8001_ha->ivt_tbl_addr));
1187 * pm80xx_set_thermal_config - support the thermal configuration
1188 * @pm8001_ha: our hba card information.
1191 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
1193 struct set_ctrl_cfg_req payload;
1194 struct inbound_queue_table *circularQ;
1195 int rc;
1196 u32 tag;
1197 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1198 u32 page_code;
1200 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1201 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1202 if (rc)
1203 return -1;
1205 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1206 payload.tag = cpu_to_le32(tag);
1208 if (IS_SPCV_12G(pm8001_ha->pdev))
1209 page_code = THERMAL_PAGE_CODE_7H;
1210 else
1211 page_code = THERMAL_PAGE_CODE_8H;
1213 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
1214 (THERMAL_ENABLE << 8) | page_code;
1215 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);
1217 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
1218 "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n",
1219 payload.cfg_pg[0], payload.cfg_pg[1]));
1221 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1222 sizeof(payload), 0);
1223 if (rc)
1224 pm8001_tag_free(pm8001_ha, tag);
1225 return rc;
1230 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
1231 * Timer configuration page
1232 * @pm8001_ha: our hba card information.
1234 static int
1235 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
1237 struct set_ctrl_cfg_req payload;
1238 struct inbound_queue_table *circularQ;
1239 SASProtocolTimerConfig_t SASConfigPage;
1240 int rc;
1241 u32 tag;
1242 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1244 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1245 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
1247 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1249 if (rc)
1250 return -1;
1252 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1253 payload.tag = cpu_to_le32(tag);
1255 SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE;
1256 SASConfigPage.MST_MSI = 3 << 15;
1257 SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO;
1258 SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) |
1259 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
1260 SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME;
1262 if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
1263 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;
1266 SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) |
1267 SAS_OPNRJT_RTRY_INTVL;
1268 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16)
1269 | SAS_COPNRJT_RTRY_TMO;
1270 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16)
1271 | SAS_COPNRJT_RTRY_THR;
1272 SASConfigPage.MAX_AIP = SAS_MAX_AIP;
1274 PM8001_INIT_DBG(pm8001_ha,
1275 pm8001_printk("SASConfigPage.pageCode "
1276 "0x%08x\n", SASConfigPage.pageCode));
1277 PM8001_INIT_DBG(pm8001_ha,
1278 pm8001_printk("SASConfigPage.MST_MSI "
1279 " 0x%08x\n", SASConfigPage.MST_MSI));
1280 PM8001_INIT_DBG(pm8001_ha,
1281 pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO "
1282 " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO));
1283 PM8001_INIT_DBG(pm8001_ha,
1284 pm8001_printk("SASConfigPage.STP_FRM_TMO "
1285 " 0x%08x\n", SASConfigPage.STP_FRM_TMO));
1286 PM8001_INIT_DBG(pm8001_ha,
1287 pm8001_printk("SASConfigPage.STP_IDLE_TMO "
1288 " 0x%08x\n", SASConfigPage.STP_IDLE_TMO));
1289 PM8001_INIT_DBG(pm8001_ha,
1290 pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL "
1291 " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL));
1292 PM8001_INIT_DBG(pm8001_ha,
1293 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO "
1294 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
1295 PM8001_INIT_DBG(pm8001_ha,
1296 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR "
1297 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
1298 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP "
1299 " 0x%08x\n", SASConfigPage.MAX_AIP));
1301 memcpy(&payload.cfg_pg, &SASConfigPage,
1302 sizeof(SASProtocolTimerConfig_t));
1304 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1305 sizeof(payload), 0);
1306 if (rc)
1307 pm8001_tag_free(pm8001_ha, tag);
1309 return rc;
1313 * pm80xx_get_encrypt_info - Check for encryption
1314 * @pm8001_ha: our hba card information.
1316 static int
1317 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
1319 u32 scratch3_value;
1320 int ret = -1;
1322 /* Read encryption status from SCRATCH PAD 3 */
1323 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1325 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1326 SCRATCH_PAD3_ENC_READY) {
1327 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1328 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1329 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1330 SCRATCH_PAD3_SMF_ENABLED)
1331 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1332 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1333 SCRATCH_PAD3_SMA_ENABLED)
1334 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1335 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1336 SCRATCH_PAD3_SMB_ENABLED)
1337 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1338 pm8001_ha->encrypt_info.status = 0;
1339 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1340 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
1341 "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
1342 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1343 pm8001_ha->encrypt_info.sec_mode,
1344 pm8001_ha->encrypt_info.status));
1345 ret = 0;
1346 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
1347 SCRATCH_PAD3_ENC_DISABLED) {
1348 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1349 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
1350 scratch3_value));
1351 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
1352 pm8001_ha->encrypt_info.cipher_mode = 0;
1353 pm8001_ha->encrypt_info.sec_mode = 0;
1354 ret = 0;
1355 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1356 SCRATCH_PAD3_ENC_DIS_ERR) {
1357 pm8001_ha->encrypt_info.status =
1358 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1359 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1360 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1361 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1362 SCRATCH_PAD3_SMF_ENABLED)
1363 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1364 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1365 SCRATCH_PAD3_SMA_ENABLED)
1366 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1367 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1368 SCRATCH_PAD3_SMB_ENABLED)
1369 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1370 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1371 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
1372 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1373 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1374 pm8001_ha->encrypt_info.sec_mode,
1375 pm8001_ha->encrypt_info.status));
1376 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1377 SCRATCH_PAD3_ENC_ENA_ERR) {
1379 pm8001_ha->encrypt_info.status =
1380 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1381 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1382 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1383 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1384 SCRATCH_PAD3_SMF_ENABLED)
1385 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1386 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1387 SCRATCH_PAD3_SMA_ENABLED)
1388 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1389 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1390 SCRATCH_PAD3_SMB_ENABLED)
1391 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1393 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1394 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
1395 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1396 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1397 pm8001_ha->encrypt_info.sec_mode,
1398 pm8001_ha->encrypt_info.status));
1400 return ret;
1404 * pm80xx_encrypt_update - update flash with encryption informtion
1405 * @pm8001_ha: our hba card information.
1407 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1409 struct kek_mgmt_req payload;
1410 struct inbound_queue_table *circularQ;
1411 int rc;
1412 u32 tag;
1413 u32 opc = OPC_INB_KEK_MANAGEMENT;
1415 memset(&payload, 0, sizeof(struct kek_mgmt_req));
1416 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1417 if (rc)
1418 return -1;
1420 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1421 payload.tag = cpu_to_le32(tag);
1422 /* Currently only one key is used. New KEK index is 1.
1423 * Current KEK index is 1. Store KEK to NVRAM is 1.
1425 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
1426 KEK_MGMT_SUBOP_KEYCARDUPDATE);
1428 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
1429 "Saving Encryption info to flash. payload 0x%x\n",
1430 payload.new_curidx_ksop));
1432 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1433 sizeof(payload), 0);
1434 if (rc)
1435 pm8001_tag_free(pm8001_ha, tag);
1437 return rc;
1441 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
1442 * @pm8001_ha: our hba card information
1444 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1446 int ret;
1447 u8 i = 0;
1449 /* check the firmware status */
1450 if (-1 == check_fw_ready(pm8001_ha)) {
1451 PM8001_FAIL_DBG(pm8001_ha,
1452 pm8001_printk("Firmware is not ready!\n"));
1453 return -EBUSY;
1456 /* Initialize the controller fatal error flag */
1457 pm8001_ha->controller_fatal_error = false;
1459 /* Initialize pci space address eg: mpi offset */
1460 init_pci_device_addresses(pm8001_ha);
1461 init_default_table_values(pm8001_ha);
1462 read_main_config_table(pm8001_ha);
1463 read_general_status_table(pm8001_ha);
1464 read_inbnd_queue_table(pm8001_ha);
1465 read_outbnd_queue_table(pm8001_ha);
1466 read_phy_attr_table(pm8001_ha);
1468 /* update main config table ,inbound table and outbound table */
1469 update_main_config_table(pm8001_ha);
1470 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++)
1471 update_inbnd_queue_table(pm8001_ha, i);
1472 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++)
1473 update_outbnd_queue_table(pm8001_ha, i);
1475 /* notify firmware update finished and check initialization status */
1476 if (0 == mpi_init_check(pm8001_ha)) {
1477 PM8001_INIT_DBG(pm8001_ha,
1478 pm8001_printk("MPI initialize successful!\n"));
1479 } else
1480 return -EBUSY;
1482 /* send SAS protocol timer configuration page to FW */
1483 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1485 /* Check for encryption */
1486 if (pm8001_ha->chip->encrypt) {
1487 PM8001_INIT_DBG(pm8001_ha,
1488 pm8001_printk("Checking for encryption\n"));
1489 ret = pm80xx_get_encrypt_info(pm8001_ha);
1490 if (ret == -1) {
1491 PM8001_INIT_DBG(pm8001_ha,
1492 pm8001_printk("Encryption error !!\n"));
1493 if (pm8001_ha->encrypt_info.status == 0x81) {
1494 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1495 "Encryption enabled with error."
1496 "Saving encryption key to flash\n"));
1497 pm80xx_encrypt_update(pm8001_ha);
1501 return 0;
1504 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1506 u32 max_wait_count;
1507 u32 value;
1508 u32 gst_len_mpistate;
1509 init_pci_device_addresses(pm8001_ha);
1510 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1511 table is stop */
1512 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1514 /* wait until Inbound DoorBell Clear Register toggled */
1515 if (IS_SPCV_12G(pm8001_ha->pdev)) {
1516 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
1517 } else {
1518 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1520 do {
1521 udelay(1);
1522 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1523 value &= SPCv_MSGU_CFG_TABLE_RESET;
1524 } while ((value != 0) && (--max_wait_count));
1526 if (!max_wait_count) {
1527 PM8001_FAIL_DBG(pm8001_ha,
1528 pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
1529 return -1;
1532 /* check the MPI-State for termination in progress */
1533 /* wait until Inbound DoorBell Clear Register toggled */
1534 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */
1535 do {
1536 udelay(1);
1537 gst_len_mpistate =
1538 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1539 GST_GSTLEN_MPIS_OFFSET);
1540 if (GST_MPI_STATE_UNINIT ==
1541 (gst_len_mpistate & GST_MPI_STATE_MASK))
1542 break;
1543 } while (--max_wait_count);
1544 if (!max_wait_count) {
1545 PM8001_FAIL_DBG(pm8001_ha,
1546 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
1547 gst_len_mpistate & GST_MPI_STATE_MASK));
1548 return -1;
1551 return 0;
1555 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
1556 * the FW register status to the originated status.
1557 * @pm8001_ha: our hba card information
1560 static int
1561 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1563 u32 regval;
1564 u32 bootloader_state;
1565 u32 ibutton0, ibutton1;
1567 /* Process MPI table uninitialization only if FW is ready */
1568 if (!pm8001_ha->controller_fatal_error) {
1569 /* Check if MPI is in ready state to reset */
1570 if (mpi_uninit_check(pm8001_ha) != 0) {
1571 u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1572 u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1573 u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1574 u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1575 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1576 "MPI state is not ready scratch: %x:%x:%x:%x\n",
1577 r0, r1, r2, r3));
1578 /* if things aren't ready but the bootloader is ok then
1579 * try the reset anyway.
1581 if (r1 & SCRATCH_PAD1_BOOTSTATE_MASK)
1582 return -1;
1585 /* checked for reset register normal state; 0x0 */
1586 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1587 PM8001_INIT_DBG(pm8001_ha,
1588 pm8001_printk("reset register before write : 0x%x\n", regval));
1590 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1591 msleep(500);
1593 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1594 PM8001_INIT_DBG(pm8001_ha,
1595 pm8001_printk("reset register after write 0x%x\n", regval));
1597 if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1598 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1599 PM8001_MSG_DBG(pm8001_ha,
1600 pm8001_printk(" soft reset successful [regval: 0x%x]\n",
1601 regval));
1602 } else {
1603 PM8001_MSG_DBG(pm8001_ha,
1604 pm8001_printk(" soft reset failed [regval: 0x%x]\n",
1605 regval));
1607 /* check bootloader is successfully executed or in HDA mode */
1608 bootloader_state =
1609 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1610 SCRATCH_PAD1_BOOTSTATE_MASK;
1612 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1613 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1614 "Bootloader state - HDA mode SEEPROM\n"));
1615 } else if (bootloader_state ==
1616 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1617 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1618 "Bootloader state - HDA mode Bootstrap Pin\n"));
1619 } else if (bootloader_state ==
1620 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1621 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1622 "Bootloader state - HDA mode soft reset\n"));
1623 } else if (bootloader_state ==
1624 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1625 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1626 "Bootloader state-HDA mode critical error\n"));
1628 return -EBUSY;
1631 /* check the firmware status after reset */
1632 if (-1 == check_fw_ready(pm8001_ha)) {
1633 PM8001_FAIL_DBG(pm8001_ha,
1634 pm8001_printk("Firmware is not ready!\n"));
1635 /* check iButton feature support for motherboard controller */
1636 if (pm8001_ha->pdev->subsystem_vendor !=
1637 PCI_VENDOR_ID_ADAPTEC2 &&
1638 pm8001_ha->pdev->subsystem_vendor !=
1639 PCI_VENDOR_ID_ATTO &&
1640 pm8001_ha->pdev->subsystem_vendor != 0) {
1641 ibutton0 = pm8001_cr32(pm8001_ha, 0,
1642 MSGU_HOST_SCRATCH_PAD_6);
1643 ibutton1 = pm8001_cr32(pm8001_ha, 0,
1644 MSGU_HOST_SCRATCH_PAD_7);
1645 if (!ibutton0 && !ibutton1) {
1646 PM8001_FAIL_DBG(pm8001_ha,
1647 pm8001_printk("iButton Feature is"
1648 " not Available!!!\n"));
1649 return -EBUSY;
1651 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1652 PM8001_FAIL_DBG(pm8001_ha,
1653 pm8001_printk("CRC Check for iButton"
1654 " Feature Failed!!!\n"));
1655 return -EBUSY;
1659 PM8001_INIT_DBG(pm8001_ha,
1660 pm8001_printk("SPCv soft reset Complete\n"));
1661 return 0;
1664 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1666 u32 i;
1668 PM8001_INIT_DBG(pm8001_ha,
1669 pm8001_printk("chip reset start\n"));
1671 /* do SPCv chip reset. */
1672 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1673 PM8001_INIT_DBG(pm8001_ha,
1674 pm8001_printk("SPC soft reset Complete\n"));
1676 /* Check this ..whether delay is required or no */
1677 /* delay 10 usec */
1678 udelay(10);
1680 /* wait for 20 msec until the firmware gets reloaded */
1681 i = 20;
1682 do {
1683 mdelay(1);
1684 } while ((--i) != 0);
1686 PM8001_INIT_DBG(pm8001_ha,
1687 pm8001_printk("chip reset finished\n"));
1691 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1692 * @pm8001_ha: our hba card information
1694 static void
1695 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1697 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1698 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1702 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1703 * @pm8001_ha: our hba card information
1705 static void
1706 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1708 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1712 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1713 * @pm8001_ha: our hba card information
1715 static void
1716 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1718 #ifdef PM8001_USE_MSIX
1719 u32 mask;
1720 mask = (u32)(1 << vec);
1722 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1723 return;
1724 #endif
1725 pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1730 * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1731 * @pm8001_ha: our hba card information
1733 static void
1734 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1736 #ifdef PM8001_USE_MSIX
1737 u32 mask;
1738 if (vec == 0xFF)
1739 mask = 0xFFFFFFFF;
1740 else
1741 mask = (u32)(1 << vec);
1742 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1743 return;
1744 #endif
1745 pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1748 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1749 struct pm8001_device *pm8001_ha_dev)
1751 int res;
1752 u32 ccb_tag;
1753 struct pm8001_ccb_info *ccb;
1754 struct sas_task *task = NULL;
1755 struct task_abort_req task_abort;
1756 struct inbound_queue_table *circularQ;
1757 u32 opc = OPC_INB_SATA_ABORT;
1758 int ret;
1760 if (!pm8001_ha_dev) {
1761 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1762 return;
1765 task = sas_alloc_slow_task(GFP_ATOMIC);
1767 if (!task) {
1768 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1769 "allocate task\n"));
1770 return;
1773 task->task_done = pm8001_task_done;
1775 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1776 if (res) {
1777 sas_free_task(task);
1778 return;
1781 ccb = &pm8001_ha->ccb_info[ccb_tag];
1782 ccb->device = pm8001_ha_dev;
1783 ccb->ccb_tag = ccb_tag;
1784 ccb->task = task;
1786 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1788 memset(&task_abort, 0, sizeof(task_abort));
1789 task_abort.abort_all = cpu_to_le32(1);
1790 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1791 task_abort.tag = cpu_to_le32(ccb_tag);
1793 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
1794 sizeof(task_abort), 0);
1795 PM8001_FAIL_DBG(pm8001_ha,
1796 pm8001_printk("Executing abort task end\n"));
1797 if (ret) {
1798 sas_free_task(task);
1799 pm8001_tag_free(pm8001_ha, ccb_tag);
1803 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1804 struct pm8001_device *pm8001_ha_dev)
1806 struct sata_start_req sata_cmd;
1807 int res;
1808 u32 ccb_tag;
1809 struct pm8001_ccb_info *ccb;
1810 struct sas_task *task = NULL;
1811 struct host_to_dev_fis fis;
1812 struct domain_device *dev;
1813 struct inbound_queue_table *circularQ;
1814 u32 opc = OPC_INB_SATA_HOST_OPSTART;
1816 task = sas_alloc_slow_task(GFP_ATOMIC);
1818 if (!task) {
1819 PM8001_FAIL_DBG(pm8001_ha,
1820 pm8001_printk("cannot allocate task !!!\n"));
1821 return;
1823 task->task_done = pm8001_task_done;
1825 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1826 if (res) {
1827 sas_free_task(task);
1828 PM8001_FAIL_DBG(pm8001_ha,
1829 pm8001_printk("cannot allocate tag !!!\n"));
1830 return;
1833 /* allocate domain device by ourselves as libsas
1834 * is not going to provide any
1836 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1837 if (!dev) {
1838 sas_free_task(task);
1839 pm8001_tag_free(pm8001_ha, ccb_tag);
1840 PM8001_FAIL_DBG(pm8001_ha,
1841 pm8001_printk("Domain device cannot be allocated\n"));
1842 return;
1845 task->dev = dev;
1846 task->dev->lldd_dev = pm8001_ha_dev;
1848 ccb = &pm8001_ha->ccb_info[ccb_tag];
1849 ccb->device = pm8001_ha_dev;
1850 ccb->ccb_tag = ccb_tag;
1851 ccb->task = task;
1852 ccb->n_elem = 0;
1853 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1854 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1856 memset(&sata_cmd, 0, sizeof(sata_cmd));
1857 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1859 /* construct read log FIS */
1860 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1861 fis.fis_type = 0x27;
1862 fis.flags = 0x80;
1863 fis.command = ATA_CMD_READ_LOG_EXT;
1864 fis.lbal = 0x10;
1865 fis.sector_count = 0x1;
1867 sata_cmd.tag = cpu_to_le32(ccb_tag);
1868 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1869 sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9));
1870 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1872 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
1873 sizeof(sata_cmd), 0);
1874 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Executing read log end\n"));
1875 if (res) {
1876 sas_free_task(task);
1877 pm8001_tag_free(pm8001_ha, ccb_tag);
1878 kfree(dev);
1883 * mpi_ssp_completion- process the event that FW response to the SSP request.
1884 * @pm8001_ha: our hba card information
1885 * @piomb: the message contents of this outbound message.
1887 * When FW has completed a ssp request for example a IO request, after it has
1888 * filled the SG data with the data, it will trigger this event represent
1889 * that he has finished the job,please check the coresponding buffer.
1890 * So we will tell the caller who maybe waiting the result to tell upper layer
1891 * that the task has been finished.
1893 static void
1894 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1896 struct sas_task *t;
1897 struct pm8001_ccb_info *ccb;
1898 unsigned long flags;
1899 u32 status;
1900 u32 param;
1901 u32 tag;
1902 struct ssp_completion_resp *psspPayload;
1903 struct task_status_struct *ts;
1904 struct ssp_response_iu *iu;
1905 struct pm8001_device *pm8001_dev;
1906 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1907 status = le32_to_cpu(psspPayload->status);
1908 tag = le32_to_cpu(psspPayload->tag);
1909 ccb = &pm8001_ha->ccb_info[tag];
1910 if ((status == IO_ABORTED) && ccb->open_retry) {
1911 /* Being completed by another */
1912 ccb->open_retry = 0;
1913 return;
1915 pm8001_dev = ccb->device;
1916 param = le32_to_cpu(psspPayload->param);
1917 t = ccb->task;
1919 if (status && status != IO_UNDERFLOW)
1920 PM8001_FAIL_DBG(pm8001_ha,
1921 pm8001_printk("sas IO status 0x%x\n", status));
1922 if (unlikely(!t || !t->lldd_task || !t->dev))
1923 return;
1924 ts = &t->task_status;
1926 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
1927 "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t));
1929 /* Print sas address of IO failed device */
1930 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1931 (status != IO_UNDERFLOW))
1932 PM8001_FAIL_DBG(pm8001_ha,
1933 pm8001_printk("SAS Address of IO Failure Drive"
1934 ":%016llx", SAS_ADDR(t->dev->sas_addr)));
1936 switch (status) {
1937 case IO_SUCCESS:
1938 PM8001_IO_DBG(pm8001_ha,
1939 pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
1940 param));
1941 if (param == 0) {
1942 ts->resp = SAS_TASK_COMPLETE;
1943 ts->stat = SAM_STAT_GOOD;
1944 } else {
1945 ts->resp = SAS_TASK_COMPLETE;
1946 ts->stat = SAS_PROTO_RESPONSE;
1947 ts->residual = param;
1948 iu = &psspPayload->ssp_resp_iu;
1949 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1951 if (pm8001_dev)
1952 pm8001_dev->running_req--;
1953 break;
1954 case IO_ABORTED:
1955 PM8001_IO_DBG(pm8001_ha,
1956 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1957 ts->resp = SAS_TASK_COMPLETE;
1958 ts->stat = SAS_ABORTED_TASK;
1959 break;
1960 case IO_UNDERFLOW:
1961 /* SSP Completion with error */
1962 PM8001_IO_DBG(pm8001_ha,
1963 pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
1964 param));
1965 ts->resp = SAS_TASK_COMPLETE;
1966 ts->stat = SAS_DATA_UNDERRUN;
1967 ts->residual = param;
1968 if (pm8001_dev)
1969 pm8001_dev->running_req--;
1970 break;
1971 case IO_NO_DEVICE:
1972 PM8001_IO_DBG(pm8001_ha,
1973 pm8001_printk("IO_NO_DEVICE\n"));
1974 ts->resp = SAS_TASK_UNDELIVERED;
1975 ts->stat = SAS_PHY_DOWN;
1976 break;
1977 case IO_XFER_ERROR_BREAK:
1978 PM8001_IO_DBG(pm8001_ha,
1979 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1980 ts->resp = SAS_TASK_COMPLETE;
1981 ts->stat = SAS_OPEN_REJECT;
1982 /* Force the midlayer to retry */
1983 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1984 break;
1985 case IO_XFER_ERROR_PHY_NOT_READY:
1986 PM8001_IO_DBG(pm8001_ha,
1987 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1988 ts->resp = SAS_TASK_COMPLETE;
1989 ts->stat = SAS_OPEN_REJECT;
1990 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1991 break;
1992 case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
1993 PM8001_IO_DBG(pm8001_ha,
1994 pm8001_printk("IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n"));
1995 ts->resp = SAS_TASK_COMPLETE;
1996 ts->stat = SAS_OPEN_REJECT;
1997 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1998 break;
1999 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2000 PM8001_IO_DBG(pm8001_ha,
2001 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2002 ts->resp = SAS_TASK_COMPLETE;
2003 ts->stat = SAS_OPEN_REJECT;
2004 ts->open_rej_reason = SAS_OREJ_EPROTO;
2005 break;
2006 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2007 PM8001_IO_DBG(pm8001_ha,
2008 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2009 ts->resp = SAS_TASK_COMPLETE;
2010 ts->stat = SAS_OPEN_REJECT;
2011 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2012 break;
2013 case IO_OPEN_CNX_ERROR_BREAK:
2014 PM8001_IO_DBG(pm8001_ha,
2015 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2016 ts->resp = SAS_TASK_COMPLETE;
2017 ts->stat = SAS_OPEN_REJECT;
2018 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2019 break;
2020 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2021 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2022 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2023 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2024 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2025 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2026 PM8001_IO_DBG(pm8001_ha,
2027 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2028 ts->resp = SAS_TASK_COMPLETE;
2029 ts->stat = SAS_OPEN_REJECT;
2030 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2031 if (!t->uldd_task)
2032 pm8001_handle_event(pm8001_ha,
2033 pm8001_dev,
2034 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2035 break;
2036 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2037 PM8001_IO_DBG(pm8001_ha,
2038 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2039 ts->resp = SAS_TASK_COMPLETE;
2040 ts->stat = SAS_OPEN_REJECT;
2041 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2042 break;
2043 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2044 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2045 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2046 ts->resp = SAS_TASK_COMPLETE;
2047 ts->stat = SAS_OPEN_REJECT;
2048 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2049 break;
2050 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2051 PM8001_IO_DBG(pm8001_ha,
2052 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2053 ts->resp = SAS_TASK_UNDELIVERED;
2054 ts->stat = SAS_OPEN_REJECT;
2055 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2056 break;
2057 case IO_XFER_ERROR_NAK_RECEIVED:
2058 PM8001_IO_DBG(pm8001_ha,
2059 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2060 ts->resp = SAS_TASK_COMPLETE;
2061 ts->stat = SAS_OPEN_REJECT;
2062 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2063 break;
2064 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2065 PM8001_IO_DBG(pm8001_ha,
2066 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2067 ts->resp = SAS_TASK_COMPLETE;
2068 ts->stat = SAS_NAK_R_ERR;
2069 break;
2070 case IO_XFER_ERROR_DMA:
2071 PM8001_IO_DBG(pm8001_ha,
2072 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2073 ts->resp = SAS_TASK_COMPLETE;
2074 ts->stat = SAS_OPEN_REJECT;
2075 break;
2076 case IO_XFER_OPEN_RETRY_TIMEOUT:
2077 PM8001_IO_DBG(pm8001_ha,
2078 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2079 ts->resp = SAS_TASK_COMPLETE;
2080 ts->stat = SAS_OPEN_REJECT;
2081 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2082 break;
2083 case IO_XFER_ERROR_OFFSET_MISMATCH:
2084 PM8001_IO_DBG(pm8001_ha,
2085 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2086 ts->resp = SAS_TASK_COMPLETE;
2087 ts->stat = SAS_OPEN_REJECT;
2088 break;
2089 case IO_PORT_IN_RESET:
2090 PM8001_IO_DBG(pm8001_ha,
2091 pm8001_printk("IO_PORT_IN_RESET\n"));
2092 ts->resp = SAS_TASK_COMPLETE;
2093 ts->stat = SAS_OPEN_REJECT;
2094 break;
2095 case IO_DS_NON_OPERATIONAL:
2096 PM8001_IO_DBG(pm8001_ha,
2097 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2098 ts->resp = SAS_TASK_COMPLETE;
2099 ts->stat = SAS_OPEN_REJECT;
2100 if (!t->uldd_task)
2101 pm8001_handle_event(pm8001_ha,
2102 pm8001_dev,
2103 IO_DS_NON_OPERATIONAL);
2104 break;
2105 case IO_DS_IN_RECOVERY:
2106 PM8001_IO_DBG(pm8001_ha,
2107 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2108 ts->resp = SAS_TASK_COMPLETE;
2109 ts->stat = SAS_OPEN_REJECT;
2110 break;
2111 case IO_TM_TAG_NOT_FOUND:
2112 PM8001_IO_DBG(pm8001_ha,
2113 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
2114 ts->resp = SAS_TASK_COMPLETE;
2115 ts->stat = SAS_OPEN_REJECT;
2116 break;
2117 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2118 PM8001_IO_DBG(pm8001_ha,
2119 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
2120 ts->resp = SAS_TASK_COMPLETE;
2121 ts->stat = SAS_OPEN_REJECT;
2122 break;
2123 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2124 PM8001_IO_DBG(pm8001_ha,
2125 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2126 ts->resp = SAS_TASK_COMPLETE;
2127 ts->stat = SAS_OPEN_REJECT;
2128 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2129 break;
2130 default:
2131 PM8001_DEVIO_DBG(pm8001_ha,
2132 pm8001_printk("Unknown status 0x%x\n", status));
2133 /* not allowed case. Therefore, return failed status */
2134 ts->resp = SAS_TASK_COMPLETE;
2135 ts->stat = SAS_OPEN_REJECT;
2136 break;
2138 PM8001_IO_DBG(pm8001_ha,
2139 pm8001_printk("scsi_status = 0x%x\n ",
2140 psspPayload->ssp_resp_iu.status));
2141 spin_lock_irqsave(&t->task_state_lock, flags);
2142 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2143 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2144 t->task_state_flags |= SAS_TASK_STATE_DONE;
2145 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2146 spin_unlock_irqrestore(&t->task_state_lock, flags);
2147 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2148 "task 0x%p done with io_status 0x%x resp 0x%x "
2149 "stat 0x%x but aborted by upper layer!\n",
2150 t, status, ts->resp, ts->stat));
2151 if (t->slow_task)
2152 complete(&t->slow_task->completion);
2153 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2154 } else {
2155 spin_unlock_irqrestore(&t->task_state_lock, flags);
2156 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2157 mb();/* in order to force CPU ordering */
2158 t->task_done(t);
2162 /*See the comments for mpi_ssp_completion */
2163 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2165 struct sas_task *t;
2166 unsigned long flags;
2167 struct task_status_struct *ts;
2168 struct pm8001_ccb_info *ccb;
2169 struct pm8001_device *pm8001_dev;
2170 struct ssp_event_resp *psspPayload =
2171 (struct ssp_event_resp *)(piomb + 4);
2172 u32 event = le32_to_cpu(psspPayload->event);
2173 u32 tag = le32_to_cpu(psspPayload->tag);
2174 u32 port_id = le32_to_cpu(psspPayload->port_id);
2176 ccb = &pm8001_ha->ccb_info[tag];
2177 t = ccb->task;
2178 pm8001_dev = ccb->device;
2179 if (event)
2180 PM8001_FAIL_DBG(pm8001_ha,
2181 pm8001_printk("sas IO status 0x%x\n", event));
2182 if (unlikely(!t || !t->lldd_task || !t->dev))
2183 return;
2184 ts = &t->task_status;
2185 PM8001_IOERR_DBG(pm8001_ha,
2186 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2187 port_id, tag, event));
2188 switch (event) {
2189 case IO_OVERFLOW:
2190 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
2191 ts->resp = SAS_TASK_COMPLETE;
2192 ts->stat = SAS_DATA_OVERRUN;
2193 ts->residual = 0;
2194 if (pm8001_dev)
2195 pm8001_dev->running_req--;
2196 break;
2197 case IO_XFER_ERROR_BREAK:
2198 PM8001_IO_DBG(pm8001_ha,
2199 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2200 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2201 return;
2202 case IO_XFER_ERROR_PHY_NOT_READY:
2203 PM8001_IO_DBG(pm8001_ha,
2204 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2205 ts->resp = SAS_TASK_COMPLETE;
2206 ts->stat = SAS_OPEN_REJECT;
2207 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2208 break;
2209 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2210 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2211 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2212 ts->resp = SAS_TASK_COMPLETE;
2213 ts->stat = SAS_OPEN_REJECT;
2214 ts->open_rej_reason = SAS_OREJ_EPROTO;
2215 break;
2216 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2217 PM8001_IO_DBG(pm8001_ha,
2218 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2219 ts->resp = SAS_TASK_COMPLETE;
2220 ts->stat = SAS_OPEN_REJECT;
2221 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2222 break;
2223 case IO_OPEN_CNX_ERROR_BREAK:
2224 PM8001_IO_DBG(pm8001_ha,
2225 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2226 ts->resp = SAS_TASK_COMPLETE;
2227 ts->stat = SAS_OPEN_REJECT;
2228 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2229 break;
2230 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2231 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2232 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2233 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2234 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2235 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2236 PM8001_IO_DBG(pm8001_ha,
2237 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2238 ts->resp = SAS_TASK_COMPLETE;
2239 ts->stat = SAS_OPEN_REJECT;
2240 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2241 if (!t->uldd_task)
2242 pm8001_handle_event(pm8001_ha,
2243 pm8001_dev,
2244 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2245 break;
2246 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2247 PM8001_IO_DBG(pm8001_ha,
2248 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2249 ts->resp = SAS_TASK_COMPLETE;
2250 ts->stat = SAS_OPEN_REJECT;
2251 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2252 break;
2253 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2254 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2255 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2256 ts->resp = SAS_TASK_COMPLETE;
2257 ts->stat = SAS_OPEN_REJECT;
2258 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2259 break;
2260 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2261 PM8001_IO_DBG(pm8001_ha,
2262 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2263 ts->resp = SAS_TASK_COMPLETE;
2264 ts->stat = SAS_OPEN_REJECT;
2265 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2266 break;
2267 case IO_XFER_ERROR_NAK_RECEIVED:
2268 PM8001_IO_DBG(pm8001_ha,
2269 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2270 ts->resp = SAS_TASK_COMPLETE;
2271 ts->stat = SAS_OPEN_REJECT;
2272 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2273 break;
2274 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2275 PM8001_IO_DBG(pm8001_ha,
2276 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2277 ts->resp = SAS_TASK_COMPLETE;
2278 ts->stat = SAS_NAK_R_ERR;
2279 break;
2280 case IO_XFER_OPEN_RETRY_TIMEOUT:
2281 PM8001_IO_DBG(pm8001_ha,
2282 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2283 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2284 return;
2285 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2286 PM8001_IO_DBG(pm8001_ha,
2287 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2288 ts->resp = SAS_TASK_COMPLETE;
2289 ts->stat = SAS_DATA_OVERRUN;
2290 break;
2291 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2292 PM8001_IO_DBG(pm8001_ha,
2293 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2294 ts->resp = SAS_TASK_COMPLETE;
2295 ts->stat = SAS_DATA_OVERRUN;
2296 break;
2297 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2298 PM8001_IO_DBG(pm8001_ha,
2299 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2300 ts->resp = SAS_TASK_COMPLETE;
2301 ts->stat = SAS_DATA_OVERRUN;
2302 break;
2303 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2304 PM8001_IO_DBG(pm8001_ha,
2305 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
2306 ts->resp = SAS_TASK_COMPLETE;
2307 ts->stat = SAS_DATA_OVERRUN;
2308 break;
2309 case IO_XFER_ERROR_OFFSET_MISMATCH:
2310 PM8001_IO_DBG(pm8001_ha,
2311 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2312 ts->resp = SAS_TASK_COMPLETE;
2313 ts->stat = SAS_DATA_OVERRUN;
2314 break;
2315 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2316 PM8001_IO_DBG(pm8001_ha,
2317 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2318 ts->resp = SAS_TASK_COMPLETE;
2319 ts->stat = SAS_DATA_OVERRUN;
2320 break;
2321 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2322 PM8001_IOERR_DBG(pm8001_ha,
2323 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2324 /* TBC: used default set values */
2325 ts->resp = SAS_TASK_COMPLETE;
2326 ts->stat = SAS_DATA_OVERRUN;
2327 break;
2328 case IO_XFER_CMD_FRAME_ISSUED:
2329 PM8001_IO_DBG(pm8001_ha,
2330 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2331 return;
2332 default:
2333 PM8001_DEVIO_DBG(pm8001_ha,
2334 pm8001_printk("Unknown status 0x%x\n", event));
2335 /* not allowed case. Therefore, return failed status */
2336 ts->resp = SAS_TASK_COMPLETE;
2337 ts->stat = SAS_DATA_OVERRUN;
2338 break;
2340 spin_lock_irqsave(&t->task_state_lock, flags);
2341 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2342 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2343 t->task_state_flags |= SAS_TASK_STATE_DONE;
2344 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2345 spin_unlock_irqrestore(&t->task_state_lock, flags);
2346 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2347 "task 0x%p done with event 0x%x resp 0x%x "
2348 "stat 0x%x but aborted by upper layer!\n",
2349 t, event, ts->resp, ts->stat));
2350 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2351 } else {
2352 spin_unlock_irqrestore(&t->task_state_lock, flags);
2353 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2354 mb();/* in order to force CPU ordering */
2355 t->task_done(t);
2359 /*See the comments for mpi_ssp_completion */
2360 static void
2361 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2363 struct sas_task *t;
2364 struct pm8001_ccb_info *ccb;
2365 u32 param;
2366 u32 status;
2367 u32 tag;
2368 int i, j;
2369 u8 sata_addr_low[4];
2370 u32 temp_sata_addr_low, temp_sata_addr_hi;
2371 u8 sata_addr_hi[4];
2372 struct sata_completion_resp *psataPayload;
2373 struct task_status_struct *ts;
2374 struct ata_task_resp *resp ;
2375 u32 *sata_resp;
2376 struct pm8001_device *pm8001_dev;
2377 unsigned long flags;
2379 psataPayload = (struct sata_completion_resp *)(piomb + 4);
2380 status = le32_to_cpu(psataPayload->status);
2381 tag = le32_to_cpu(psataPayload->tag);
2383 if (!tag) {
2384 PM8001_FAIL_DBG(pm8001_ha,
2385 pm8001_printk("tag null\n"));
2386 return;
2388 ccb = &pm8001_ha->ccb_info[tag];
2389 param = le32_to_cpu(psataPayload->param);
2390 if (ccb) {
2391 t = ccb->task;
2392 pm8001_dev = ccb->device;
2393 } else {
2394 PM8001_FAIL_DBG(pm8001_ha,
2395 pm8001_printk("ccb null\n"));
2396 return;
2399 if (t) {
2400 if (t->dev && (t->dev->lldd_dev))
2401 pm8001_dev = t->dev->lldd_dev;
2402 } else {
2403 PM8001_FAIL_DBG(pm8001_ha,
2404 pm8001_printk("task null\n"));
2405 return;
2408 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2409 && unlikely(!t || !t->lldd_task || !t->dev)) {
2410 PM8001_FAIL_DBG(pm8001_ha,
2411 pm8001_printk("task or dev null\n"));
2412 return;
2415 ts = &t->task_status;
2416 if (!ts) {
2417 PM8001_FAIL_DBG(pm8001_ha,
2418 pm8001_printk("ts null\n"));
2419 return;
2422 if (unlikely(status))
2423 PM8001_IOERR_DBG(pm8001_ha, pm8001_printk(
2424 "status:0x%x, tag:0x%x, task::0x%p\n",
2425 status, tag, t));
2427 /* Print sas address of IO failed device */
2428 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2429 (status != IO_UNDERFLOW)) {
2430 if (!((t->dev->parent) &&
2431 (dev_is_expander(t->dev->parent->dev_type)))) {
2432 for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++)
2433 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2434 for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++)
2435 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2436 memcpy(&temp_sata_addr_low, sata_addr_low,
2437 sizeof(sata_addr_low));
2438 memcpy(&temp_sata_addr_hi, sata_addr_hi,
2439 sizeof(sata_addr_hi));
2440 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2441 |((temp_sata_addr_hi << 8) &
2442 0xff0000) |
2443 ((temp_sata_addr_hi >> 8)
2444 & 0xff00) |
2445 ((temp_sata_addr_hi << 24) &
2446 0xff000000));
2447 temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2448 & 0xff) |
2449 ((temp_sata_addr_low << 8)
2450 & 0xff0000) |
2451 ((temp_sata_addr_low >> 8)
2452 & 0xff00) |
2453 ((temp_sata_addr_low << 24)
2454 & 0xff000000)) +
2455 pm8001_dev->attached_phy +
2456 0x10);
2457 PM8001_FAIL_DBG(pm8001_ha,
2458 pm8001_printk("SAS Address of IO Failure Drive:"
2459 "%08x%08x", temp_sata_addr_hi,
2460 temp_sata_addr_low));
2462 } else {
2463 PM8001_FAIL_DBG(pm8001_ha,
2464 pm8001_printk("SAS Address of IO Failure Drive:"
2465 "%016llx", SAS_ADDR(t->dev->sas_addr)));
2468 switch (status) {
2469 case IO_SUCCESS:
2470 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2471 if (param == 0) {
2472 ts->resp = SAS_TASK_COMPLETE;
2473 ts->stat = SAM_STAT_GOOD;
2474 /* check if response is for SEND READ LOG */
2475 if (pm8001_dev &&
2476 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2477 /* set new bit for abort_all */
2478 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2479 /* clear bit for read log */
2480 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2481 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2482 /* Free the tag */
2483 pm8001_tag_free(pm8001_ha, tag);
2484 sas_free_task(t);
2485 return;
2487 } else {
2488 u8 len;
2489 ts->resp = SAS_TASK_COMPLETE;
2490 ts->stat = SAS_PROTO_RESPONSE;
2491 ts->residual = param;
2492 PM8001_IO_DBG(pm8001_ha,
2493 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2494 param));
2495 sata_resp = &psataPayload->sata_resp[0];
2496 resp = (struct ata_task_resp *)ts->buf;
2497 if (t->ata_task.dma_xfer == 0 &&
2498 t->data_dir == DMA_FROM_DEVICE) {
2499 len = sizeof(struct pio_setup_fis);
2500 PM8001_IO_DBG(pm8001_ha,
2501 pm8001_printk("PIO read len = %d\n", len));
2502 } else if (t->ata_task.use_ncq) {
2503 len = sizeof(struct set_dev_bits_fis);
2504 PM8001_IO_DBG(pm8001_ha,
2505 pm8001_printk("FPDMA len = %d\n", len));
2506 } else {
2507 len = sizeof(struct dev_to_host_fis);
2508 PM8001_IO_DBG(pm8001_ha,
2509 pm8001_printk("other len = %d\n", len));
2511 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2512 resp->frame_len = len;
2513 memcpy(&resp->ending_fis[0], sata_resp, len);
2514 ts->buf_valid_size = sizeof(*resp);
2515 } else
2516 PM8001_IO_DBG(pm8001_ha,
2517 pm8001_printk("response too large\n"));
2519 if (pm8001_dev)
2520 pm8001_dev->running_req--;
2521 break;
2522 case IO_ABORTED:
2523 PM8001_IO_DBG(pm8001_ha,
2524 pm8001_printk("IO_ABORTED IOMB Tag\n"));
2525 ts->resp = SAS_TASK_COMPLETE;
2526 ts->stat = SAS_ABORTED_TASK;
2527 if (pm8001_dev)
2528 pm8001_dev->running_req--;
2529 break;
2530 /* following cases are to do cases */
2531 case IO_UNDERFLOW:
2532 /* SATA Completion with error */
2533 PM8001_IO_DBG(pm8001_ha,
2534 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2535 ts->resp = SAS_TASK_COMPLETE;
2536 ts->stat = SAS_DATA_UNDERRUN;
2537 ts->residual = param;
2538 if (pm8001_dev)
2539 pm8001_dev->running_req--;
2540 break;
2541 case IO_NO_DEVICE:
2542 PM8001_IO_DBG(pm8001_ha,
2543 pm8001_printk("IO_NO_DEVICE\n"));
2544 ts->resp = SAS_TASK_UNDELIVERED;
2545 ts->stat = SAS_PHY_DOWN;
2546 break;
2547 case IO_XFER_ERROR_BREAK:
2548 PM8001_IO_DBG(pm8001_ha,
2549 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2550 ts->resp = SAS_TASK_COMPLETE;
2551 ts->stat = SAS_INTERRUPTED;
2552 break;
2553 case IO_XFER_ERROR_PHY_NOT_READY:
2554 PM8001_IO_DBG(pm8001_ha,
2555 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2556 ts->resp = SAS_TASK_COMPLETE;
2557 ts->stat = SAS_OPEN_REJECT;
2558 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2559 break;
2560 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2561 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2562 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2563 ts->resp = SAS_TASK_COMPLETE;
2564 ts->stat = SAS_OPEN_REJECT;
2565 ts->open_rej_reason = SAS_OREJ_EPROTO;
2566 break;
2567 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2568 PM8001_IO_DBG(pm8001_ha,
2569 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2570 ts->resp = SAS_TASK_COMPLETE;
2571 ts->stat = SAS_OPEN_REJECT;
2572 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2573 break;
2574 case IO_OPEN_CNX_ERROR_BREAK:
2575 PM8001_IO_DBG(pm8001_ha,
2576 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2577 ts->resp = SAS_TASK_COMPLETE;
2578 ts->stat = SAS_OPEN_REJECT;
2579 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2580 break;
2581 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2582 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2583 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2584 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2585 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2586 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2587 PM8001_IO_DBG(pm8001_ha,
2588 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2589 ts->resp = SAS_TASK_COMPLETE;
2590 ts->stat = SAS_DEV_NO_RESPONSE;
2591 if (!t->uldd_task) {
2592 pm8001_handle_event(pm8001_ha,
2593 pm8001_dev,
2594 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2595 ts->resp = SAS_TASK_UNDELIVERED;
2596 ts->stat = SAS_QUEUE_FULL;
2597 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2598 return;
2600 break;
2601 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2602 PM8001_IO_DBG(pm8001_ha,
2603 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2604 ts->resp = SAS_TASK_UNDELIVERED;
2605 ts->stat = SAS_OPEN_REJECT;
2606 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2607 if (!t->uldd_task) {
2608 pm8001_handle_event(pm8001_ha,
2609 pm8001_dev,
2610 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2611 ts->resp = SAS_TASK_UNDELIVERED;
2612 ts->stat = SAS_QUEUE_FULL;
2613 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2614 return;
2616 break;
2617 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2618 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2619 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2620 ts->resp = SAS_TASK_COMPLETE;
2621 ts->stat = SAS_OPEN_REJECT;
2622 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2623 break;
2624 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2625 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2626 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
2627 ts->resp = SAS_TASK_COMPLETE;
2628 ts->stat = SAS_DEV_NO_RESPONSE;
2629 if (!t->uldd_task) {
2630 pm8001_handle_event(pm8001_ha,
2631 pm8001_dev,
2632 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2633 ts->resp = SAS_TASK_UNDELIVERED;
2634 ts->stat = SAS_QUEUE_FULL;
2635 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2636 return;
2638 break;
2639 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2640 PM8001_IO_DBG(pm8001_ha,
2641 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2642 ts->resp = SAS_TASK_COMPLETE;
2643 ts->stat = SAS_OPEN_REJECT;
2644 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2645 break;
2646 case IO_XFER_ERROR_NAK_RECEIVED:
2647 PM8001_IO_DBG(pm8001_ha,
2648 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2649 ts->resp = SAS_TASK_COMPLETE;
2650 ts->stat = SAS_NAK_R_ERR;
2651 break;
2652 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2653 PM8001_IO_DBG(pm8001_ha,
2654 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2655 ts->resp = SAS_TASK_COMPLETE;
2656 ts->stat = SAS_NAK_R_ERR;
2657 break;
2658 case IO_XFER_ERROR_DMA:
2659 PM8001_IO_DBG(pm8001_ha,
2660 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2661 ts->resp = SAS_TASK_COMPLETE;
2662 ts->stat = SAS_ABORTED_TASK;
2663 break;
2664 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2665 PM8001_IO_DBG(pm8001_ha,
2666 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2667 ts->resp = SAS_TASK_UNDELIVERED;
2668 ts->stat = SAS_DEV_NO_RESPONSE;
2669 break;
2670 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2671 PM8001_IO_DBG(pm8001_ha,
2672 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2673 ts->resp = SAS_TASK_COMPLETE;
2674 ts->stat = SAS_DATA_UNDERRUN;
2675 break;
2676 case IO_XFER_OPEN_RETRY_TIMEOUT:
2677 PM8001_IO_DBG(pm8001_ha,
2678 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2679 ts->resp = SAS_TASK_COMPLETE;
2680 ts->stat = SAS_OPEN_TO;
2681 break;
2682 case IO_PORT_IN_RESET:
2683 PM8001_IO_DBG(pm8001_ha,
2684 pm8001_printk("IO_PORT_IN_RESET\n"));
2685 ts->resp = SAS_TASK_COMPLETE;
2686 ts->stat = SAS_DEV_NO_RESPONSE;
2687 break;
2688 case IO_DS_NON_OPERATIONAL:
2689 PM8001_IO_DBG(pm8001_ha,
2690 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2691 ts->resp = SAS_TASK_COMPLETE;
2692 ts->stat = SAS_DEV_NO_RESPONSE;
2693 if (!t->uldd_task) {
2694 pm8001_handle_event(pm8001_ha, pm8001_dev,
2695 IO_DS_NON_OPERATIONAL);
2696 ts->resp = SAS_TASK_UNDELIVERED;
2697 ts->stat = SAS_QUEUE_FULL;
2698 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2699 return;
2701 break;
2702 case IO_DS_IN_RECOVERY:
2703 PM8001_IO_DBG(pm8001_ha,
2704 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2705 ts->resp = SAS_TASK_COMPLETE;
2706 ts->stat = SAS_DEV_NO_RESPONSE;
2707 break;
2708 case IO_DS_IN_ERROR:
2709 PM8001_IO_DBG(pm8001_ha,
2710 pm8001_printk("IO_DS_IN_ERROR\n"));
2711 ts->resp = SAS_TASK_COMPLETE;
2712 ts->stat = SAS_DEV_NO_RESPONSE;
2713 if (!t->uldd_task) {
2714 pm8001_handle_event(pm8001_ha, pm8001_dev,
2715 IO_DS_IN_ERROR);
2716 ts->resp = SAS_TASK_UNDELIVERED;
2717 ts->stat = SAS_QUEUE_FULL;
2718 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2719 return;
2721 break;
2722 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2723 PM8001_IO_DBG(pm8001_ha,
2724 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2725 ts->resp = SAS_TASK_COMPLETE;
2726 ts->stat = SAS_OPEN_REJECT;
2727 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2728 break;
2729 default:
2730 PM8001_DEVIO_DBG(pm8001_ha,
2731 pm8001_printk("Unknown status 0x%x\n", status));
2732 /* not allowed case. Therefore, return failed status */
2733 ts->resp = SAS_TASK_COMPLETE;
2734 ts->stat = SAS_DEV_NO_RESPONSE;
2735 break;
2737 spin_lock_irqsave(&t->task_state_lock, flags);
2738 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2739 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2740 t->task_state_flags |= SAS_TASK_STATE_DONE;
2741 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2742 spin_unlock_irqrestore(&t->task_state_lock, flags);
2743 PM8001_FAIL_DBG(pm8001_ha,
2744 pm8001_printk("task 0x%p done with io_status 0x%x"
2745 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2746 t, status, ts->resp, ts->stat));
2747 if (t->slow_task)
2748 complete(&t->slow_task->completion);
2749 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2750 } else {
2751 spin_unlock_irqrestore(&t->task_state_lock, flags);
2752 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2756 /*See the comments for mpi_ssp_completion */
2757 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2759 struct sas_task *t;
2760 struct task_status_struct *ts;
2761 struct pm8001_ccb_info *ccb;
2762 struct pm8001_device *pm8001_dev;
2763 struct sata_event_resp *psataPayload =
2764 (struct sata_event_resp *)(piomb + 4);
2765 u32 event = le32_to_cpu(psataPayload->event);
2766 u32 tag = le32_to_cpu(psataPayload->tag);
2767 u32 port_id = le32_to_cpu(psataPayload->port_id);
2768 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2769 unsigned long flags;
2771 ccb = &pm8001_ha->ccb_info[tag];
2773 if (ccb) {
2774 t = ccb->task;
2775 pm8001_dev = ccb->device;
2776 } else {
2777 PM8001_FAIL_DBG(pm8001_ha,
2778 pm8001_printk("No CCB !!!. returning\n"));
2779 return;
2781 if (event)
2782 PM8001_FAIL_DBG(pm8001_ha,
2783 pm8001_printk("SATA EVENT 0x%x\n", event));
2785 /* Check if this is NCQ error */
2786 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2787 /* find device using device id */
2788 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2789 /* send read log extension */
2790 if (pm8001_dev)
2791 pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2792 return;
2795 if (unlikely(!t || !t->lldd_task || !t->dev)) {
2796 PM8001_FAIL_DBG(pm8001_ha,
2797 pm8001_printk("task or dev null\n"));
2798 return;
2801 ts = &t->task_status;
2802 PM8001_IOERR_DBG(pm8001_ha,
2803 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2804 port_id, tag, event));
2805 switch (event) {
2806 case IO_OVERFLOW:
2807 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2808 ts->resp = SAS_TASK_COMPLETE;
2809 ts->stat = SAS_DATA_OVERRUN;
2810 ts->residual = 0;
2811 if (pm8001_dev)
2812 pm8001_dev->running_req--;
2813 break;
2814 case IO_XFER_ERROR_BREAK:
2815 PM8001_IO_DBG(pm8001_ha,
2816 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2817 ts->resp = SAS_TASK_COMPLETE;
2818 ts->stat = SAS_INTERRUPTED;
2819 break;
2820 case IO_XFER_ERROR_PHY_NOT_READY:
2821 PM8001_IO_DBG(pm8001_ha,
2822 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2823 ts->resp = SAS_TASK_COMPLETE;
2824 ts->stat = SAS_OPEN_REJECT;
2825 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2826 break;
2827 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2828 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2829 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2830 ts->resp = SAS_TASK_COMPLETE;
2831 ts->stat = SAS_OPEN_REJECT;
2832 ts->open_rej_reason = SAS_OREJ_EPROTO;
2833 break;
2834 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2835 PM8001_IO_DBG(pm8001_ha,
2836 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2837 ts->resp = SAS_TASK_COMPLETE;
2838 ts->stat = SAS_OPEN_REJECT;
2839 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2840 break;
2841 case IO_OPEN_CNX_ERROR_BREAK:
2842 PM8001_IO_DBG(pm8001_ha,
2843 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2844 ts->resp = SAS_TASK_COMPLETE;
2845 ts->stat = SAS_OPEN_REJECT;
2846 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2847 break;
2848 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2849 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2850 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2851 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2852 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2853 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2854 PM8001_FAIL_DBG(pm8001_ha,
2855 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2856 ts->resp = SAS_TASK_UNDELIVERED;
2857 ts->stat = SAS_DEV_NO_RESPONSE;
2858 if (!t->uldd_task) {
2859 pm8001_handle_event(pm8001_ha,
2860 pm8001_dev,
2861 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2862 ts->resp = SAS_TASK_COMPLETE;
2863 ts->stat = SAS_QUEUE_FULL;
2864 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2865 return;
2867 break;
2868 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2869 PM8001_IO_DBG(pm8001_ha,
2870 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2871 ts->resp = SAS_TASK_UNDELIVERED;
2872 ts->stat = SAS_OPEN_REJECT;
2873 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2874 break;
2875 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2876 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2877 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2878 ts->resp = SAS_TASK_COMPLETE;
2879 ts->stat = SAS_OPEN_REJECT;
2880 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2881 break;
2882 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2883 PM8001_IO_DBG(pm8001_ha,
2884 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2885 ts->resp = SAS_TASK_COMPLETE;
2886 ts->stat = SAS_OPEN_REJECT;
2887 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2888 break;
2889 case IO_XFER_ERROR_NAK_RECEIVED:
2890 PM8001_IO_DBG(pm8001_ha,
2891 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2892 ts->resp = SAS_TASK_COMPLETE;
2893 ts->stat = SAS_NAK_R_ERR;
2894 break;
2895 case IO_XFER_ERROR_PEER_ABORTED:
2896 PM8001_IO_DBG(pm8001_ha,
2897 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2898 ts->resp = SAS_TASK_COMPLETE;
2899 ts->stat = SAS_NAK_R_ERR;
2900 break;
2901 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2902 PM8001_IO_DBG(pm8001_ha,
2903 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2904 ts->resp = SAS_TASK_COMPLETE;
2905 ts->stat = SAS_DATA_UNDERRUN;
2906 break;
2907 case IO_XFER_OPEN_RETRY_TIMEOUT:
2908 PM8001_IO_DBG(pm8001_ha,
2909 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2910 ts->resp = SAS_TASK_COMPLETE;
2911 ts->stat = SAS_OPEN_TO;
2912 break;
2913 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2914 PM8001_IO_DBG(pm8001_ha,
2915 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2916 ts->resp = SAS_TASK_COMPLETE;
2917 ts->stat = SAS_OPEN_TO;
2918 break;
2919 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2920 PM8001_IO_DBG(pm8001_ha,
2921 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2922 ts->resp = SAS_TASK_COMPLETE;
2923 ts->stat = SAS_OPEN_TO;
2924 break;
2925 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2926 PM8001_IO_DBG(pm8001_ha,
2927 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2928 ts->resp = SAS_TASK_COMPLETE;
2929 ts->stat = SAS_OPEN_TO;
2930 break;
2931 case IO_XFER_ERROR_OFFSET_MISMATCH:
2932 PM8001_IO_DBG(pm8001_ha,
2933 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2934 ts->resp = SAS_TASK_COMPLETE;
2935 ts->stat = SAS_OPEN_TO;
2936 break;
2937 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2938 PM8001_IO_DBG(pm8001_ha,
2939 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2940 ts->resp = SAS_TASK_COMPLETE;
2941 ts->stat = SAS_OPEN_TO;
2942 break;
2943 case IO_XFER_CMD_FRAME_ISSUED:
2944 PM8001_IO_DBG(pm8001_ha,
2945 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2946 break;
2947 case IO_XFER_PIO_SETUP_ERROR:
2948 PM8001_IO_DBG(pm8001_ha,
2949 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2950 ts->resp = SAS_TASK_COMPLETE;
2951 ts->stat = SAS_OPEN_TO;
2952 break;
2953 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2954 PM8001_FAIL_DBG(pm8001_ha,
2955 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2956 /* TBC: used default set values */
2957 ts->resp = SAS_TASK_COMPLETE;
2958 ts->stat = SAS_OPEN_TO;
2959 break;
2960 case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2961 PM8001_FAIL_DBG(pm8001_ha,
2962 pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n"));
2963 /* TBC: used default set values */
2964 ts->resp = SAS_TASK_COMPLETE;
2965 ts->stat = SAS_OPEN_TO;
2966 break;
2967 default:
2968 PM8001_IO_DBG(pm8001_ha,
2969 pm8001_printk("Unknown status 0x%x\n", event));
2970 /* not allowed case. Therefore, return failed status */
2971 ts->resp = SAS_TASK_COMPLETE;
2972 ts->stat = SAS_OPEN_TO;
2973 break;
2975 spin_lock_irqsave(&t->task_state_lock, flags);
2976 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2977 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2978 t->task_state_flags |= SAS_TASK_STATE_DONE;
2979 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2980 spin_unlock_irqrestore(&t->task_state_lock, flags);
2981 PM8001_FAIL_DBG(pm8001_ha,
2982 pm8001_printk("task 0x%p done with io_status 0x%x"
2983 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2984 t, event, ts->resp, ts->stat));
2985 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2986 } else {
2987 spin_unlock_irqrestore(&t->task_state_lock, flags);
2988 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2992 /*See the comments for mpi_ssp_completion */
2993 static void
2994 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2996 u32 param, i;
2997 struct sas_task *t;
2998 struct pm8001_ccb_info *ccb;
2999 unsigned long flags;
3000 u32 status;
3001 u32 tag;
3002 struct smp_completion_resp *psmpPayload;
3003 struct task_status_struct *ts;
3004 struct pm8001_device *pm8001_dev;
3005 char *pdma_respaddr = NULL;
3007 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
3008 status = le32_to_cpu(psmpPayload->status);
3009 tag = le32_to_cpu(psmpPayload->tag);
3011 ccb = &pm8001_ha->ccb_info[tag];
3012 param = le32_to_cpu(psmpPayload->param);
3013 t = ccb->task;
3014 ts = &t->task_status;
3015 pm8001_dev = ccb->device;
3016 if (status)
3017 PM8001_FAIL_DBG(pm8001_ha,
3018 pm8001_printk("smp IO status 0x%x\n", status));
3019 if (unlikely(!t || !t->lldd_task || !t->dev))
3020 return;
3022 PM8001_DEV_DBG(pm8001_ha,
3023 pm8001_printk("tag::0x%x status::0x%x\n", tag, status));
3025 switch (status) {
3027 case IO_SUCCESS:
3028 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
3029 ts->resp = SAS_TASK_COMPLETE;
3030 ts->stat = SAM_STAT_GOOD;
3031 if (pm8001_dev)
3032 pm8001_dev->running_req--;
3033 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3034 PM8001_IO_DBG(pm8001_ha,
3035 pm8001_printk("DIRECT RESPONSE Length:%d\n",
3036 param));
3037 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
3038 ((u64)sg_dma_address
3039 (&t->smp_task.smp_resp))));
3040 for (i = 0; i < param; i++) {
3041 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
3042 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3043 "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
3044 i, *(pdma_respaddr+i),
3045 psmpPayload->_r_a[i]));
3048 break;
3049 case IO_ABORTED:
3050 PM8001_IO_DBG(pm8001_ha,
3051 pm8001_printk("IO_ABORTED IOMB\n"));
3052 ts->resp = SAS_TASK_COMPLETE;
3053 ts->stat = SAS_ABORTED_TASK;
3054 if (pm8001_dev)
3055 pm8001_dev->running_req--;
3056 break;
3057 case IO_OVERFLOW:
3058 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
3059 ts->resp = SAS_TASK_COMPLETE;
3060 ts->stat = SAS_DATA_OVERRUN;
3061 ts->residual = 0;
3062 if (pm8001_dev)
3063 pm8001_dev->running_req--;
3064 break;
3065 case IO_NO_DEVICE:
3066 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
3067 ts->resp = SAS_TASK_COMPLETE;
3068 ts->stat = SAS_PHY_DOWN;
3069 break;
3070 case IO_ERROR_HW_TIMEOUT:
3071 PM8001_IO_DBG(pm8001_ha,
3072 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
3073 ts->resp = SAS_TASK_COMPLETE;
3074 ts->stat = SAM_STAT_BUSY;
3075 break;
3076 case IO_XFER_ERROR_BREAK:
3077 PM8001_IO_DBG(pm8001_ha,
3078 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
3079 ts->resp = SAS_TASK_COMPLETE;
3080 ts->stat = SAM_STAT_BUSY;
3081 break;
3082 case IO_XFER_ERROR_PHY_NOT_READY:
3083 PM8001_IO_DBG(pm8001_ha,
3084 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
3085 ts->resp = SAS_TASK_COMPLETE;
3086 ts->stat = SAM_STAT_BUSY;
3087 break;
3088 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
3089 PM8001_IO_DBG(pm8001_ha,
3090 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
3091 ts->resp = SAS_TASK_COMPLETE;
3092 ts->stat = SAS_OPEN_REJECT;
3093 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3094 break;
3095 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
3096 PM8001_IO_DBG(pm8001_ha,
3097 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
3098 ts->resp = SAS_TASK_COMPLETE;
3099 ts->stat = SAS_OPEN_REJECT;
3100 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3101 break;
3102 case IO_OPEN_CNX_ERROR_BREAK:
3103 PM8001_IO_DBG(pm8001_ha,
3104 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
3105 ts->resp = SAS_TASK_COMPLETE;
3106 ts->stat = SAS_OPEN_REJECT;
3107 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
3108 break;
3109 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
3110 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
3111 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
3112 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
3113 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
3114 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
3115 PM8001_IO_DBG(pm8001_ha,
3116 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
3117 ts->resp = SAS_TASK_COMPLETE;
3118 ts->stat = SAS_OPEN_REJECT;
3119 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3120 pm8001_handle_event(pm8001_ha,
3121 pm8001_dev,
3122 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
3123 break;
3124 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
3125 PM8001_IO_DBG(pm8001_ha,
3126 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
3127 ts->resp = SAS_TASK_COMPLETE;
3128 ts->stat = SAS_OPEN_REJECT;
3129 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
3130 break;
3131 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
3132 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
3133 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
3134 ts->resp = SAS_TASK_COMPLETE;
3135 ts->stat = SAS_OPEN_REJECT;
3136 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
3137 break;
3138 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
3139 PM8001_IO_DBG(pm8001_ha,
3140 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
3141 ts->resp = SAS_TASK_COMPLETE;
3142 ts->stat = SAS_OPEN_REJECT;
3143 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
3144 break;
3145 case IO_XFER_ERROR_RX_FRAME:
3146 PM8001_IO_DBG(pm8001_ha,
3147 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
3148 ts->resp = SAS_TASK_COMPLETE;
3149 ts->stat = SAS_DEV_NO_RESPONSE;
3150 break;
3151 case IO_XFER_OPEN_RETRY_TIMEOUT:
3152 PM8001_IO_DBG(pm8001_ha,
3153 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
3154 ts->resp = SAS_TASK_COMPLETE;
3155 ts->stat = SAS_OPEN_REJECT;
3156 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3157 break;
3158 case IO_ERROR_INTERNAL_SMP_RESOURCE:
3159 PM8001_IO_DBG(pm8001_ha,
3160 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
3161 ts->resp = SAS_TASK_COMPLETE;
3162 ts->stat = SAS_QUEUE_FULL;
3163 break;
3164 case IO_PORT_IN_RESET:
3165 PM8001_IO_DBG(pm8001_ha,
3166 pm8001_printk("IO_PORT_IN_RESET\n"));
3167 ts->resp = SAS_TASK_COMPLETE;
3168 ts->stat = SAS_OPEN_REJECT;
3169 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3170 break;
3171 case IO_DS_NON_OPERATIONAL:
3172 PM8001_IO_DBG(pm8001_ha,
3173 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
3174 ts->resp = SAS_TASK_COMPLETE;
3175 ts->stat = SAS_DEV_NO_RESPONSE;
3176 break;
3177 case IO_DS_IN_RECOVERY:
3178 PM8001_IO_DBG(pm8001_ha,
3179 pm8001_printk("IO_DS_IN_RECOVERY\n"));
3180 ts->resp = SAS_TASK_COMPLETE;
3181 ts->stat = SAS_OPEN_REJECT;
3182 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3183 break;
3184 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3185 PM8001_IO_DBG(pm8001_ha,
3186 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
3187 ts->resp = SAS_TASK_COMPLETE;
3188 ts->stat = SAS_OPEN_REJECT;
3189 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3190 break;
3191 default:
3192 PM8001_DEVIO_DBG(pm8001_ha,
3193 pm8001_printk("Unknown status 0x%x\n", status));
3194 ts->resp = SAS_TASK_COMPLETE;
3195 ts->stat = SAS_DEV_NO_RESPONSE;
3196 /* not allowed case. Therefore, return failed status */
3197 break;
3199 spin_lock_irqsave(&t->task_state_lock, flags);
3200 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3201 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3202 t->task_state_flags |= SAS_TASK_STATE_DONE;
3203 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3204 spin_unlock_irqrestore(&t->task_state_lock, flags);
3205 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
3206 "task 0x%p done with io_status 0x%x resp 0x%x"
3207 "stat 0x%x but aborted by upper layer!\n",
3208 t, status, ts->resp, ts->stat));
3209 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3210 } else {
3211 spin_unlock_irqrestore(&t->task_state_lock, flags);
3212 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3213 mb();/* in order to force CPU ordering */
3214 t->task_done(t);
3219 * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3220 * @pm8001_ha: our hba card information
3221 * @Qnum: the outbound queue message number.
3222 * @SEA: source of event to ack
3223 * @port_id: port id.
3224 * @phyId: phy id.
3225 * @param0: parameter 0.
3226 * @param1: parameter 1.
3228 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3229 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3231 struct hw_event_ack_req payload;
3232 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3234 struct inbound_queue_table *circularQ;
3236 memset((u8 *)&payload, 0, sizeof(payload));
3237 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3238 payload.tag = cpu_to_le32(1);
3239 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3240 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
3241 payload.param0 = cpu_to_le32(param0);
3242 payload.param1 = cpu_to_le32(param1);
3243 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
3244 sizeof(payload), 0);
3247 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3248 u32 phyId, u32 phy_op);
3250 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
3251 void *piomb)
3253 struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
3254 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3255 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3256 u32 lr_status_evt_portid =
3257 le32_to_cpu(pPayload->lr_status_evt_portid);
3258 u8 deviceType = pPayload->sas_identify.dev_type;
3259 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3260 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3261 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3262 struct pm8001_port *port = &pm8001_ha->port[port_id];
3264 if (deviceType == SAS_END_DEVICE) {
3265 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3266 PHY_NOTIFY_ENABLE_SPINUP);
3269 port->wide_port_phymap |= (1U << phy_id);
3270 pm8001_get_lrate_mode(phy, link_rate);
3271 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3272 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3273 phy->phy_attached = 1;
3277 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3278 * @pm8001_ha: our hba card information
3279 * @piomb: IO message buffer
3281 static void
3282 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3284 struct hw_event_resp *pPayload =
3285 (struct hw_event_resp *)(piomb + 4);
3286 u32 lr_status_evt_portid =
3287 le32_to_cpu(pPayload->lr_status_evt_portid);
3288 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3290 u8 link_rate =
3291 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3292 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3293 u8 phy_id =
3294 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3295 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3297 struct pm8001_port *port = &pm8001_ha->port[port_id];
3298 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3299 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3300 unsigned long flags;
3301 u8 deviceType = pPayload->sas_identify.dev_type;
3302 port->port_state = portstate;
3303 port->wide_port_phymap |= (1U << phy_id);
3304 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3305 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3306 "portid:%d; phyid:%d; linkrate:%d; "
3307 "portstate:%x; devicetype:%x\n",
3308 port_id, phy_id, link_rate, portstate, deviceType));
3310 switch (deviceType) {
3311 case SAS_PHY_UNUSED:
3312 PM8001_MSG_DBG(pm8001_ha,
3313 pm8001_printk("device type no device.\n"));
3314 break;
3315 case SAS_END_DEVICE:
3316 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
3317 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3318 PHY_NOTIFY_ENABLE_SPINUP);
3319 port->port_attached = 1;
3320 pm8001_get_lrate_mode(phy, link_rate);
3321 break;
3322 case SAS_EDGE_EXPANDER_DEVICE:
3323 PM8001_MSG_DBG(pm8001_ha,
3324 pm8001_printk("expander device.\n"));
3325 port->port_attached = 1;
3326 pm8001_get_lrate_mode(phy, link_rate);
3327 break;
3328 case SAS_FANOUT_EXPANDER_DEVICE:
3329 PM8001_MSG_DBG(pm8001_ha,
3330 pm8001_printk("fanout expander device.\n"));
3331 port->port_attached = 1;
3332 pm8001_get_lrate_mode(phy, link_rate);
3333 break;
3334 default:
3335 PM8001_DEVIO_DBG(pm8001_ha,
3336 pm8001_printk("unknown device type(%x)\n", deviceType));
3337 break;
3339 phy->phy_type |= PORT_TYPE_SAS;
3340 phy->identify.device_type = deviceType;
3341 phy->phy_attached = 1;
3342 if (phy->identify.device_type == SAS_END_DEVICE)
3343 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3344 else if (phy->identify.device_type != SAS_PHY_UNUSED)
3345 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3346 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3347 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3348 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3349 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3350 sizeof(struct sas_identify_frame)-4);
3351 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3352 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3353 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3354 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3355 msleep(200);/*delay a moment to wait disk to spinup*/
3356 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3360 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3361 * @pm8001_ha: our hba card information
3362 * @piomb: IO message buffer
3364 static void
3365 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3367 struct hw_event_resp *pPayload =
3368 (struct hw_event_resp *)(piomb + 4);
3369 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3370 u32 lr_status_evt_portid =
3371 le32_to_cpu(pPayload->lr_status_evt_portid);
3372 u8 link_rate =
3373 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3374 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3375 u8 phy_id =
3376 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3378 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3380 struct pm8001_port *port = &pm8001_ha->port[port_id];
3381 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3382 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3383 unsigned long flags;
3384 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
3385 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
3386 port_id, phy_id, link_rate, portstate));
3388 port->port_state = portstate;
3389 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3390 port->port_attached = 1;
3391 pm8001_get_lrate_mode(phy, link_rate);
3392 phy->phy_type |= PORT_TYPE_SATA;
3393 phy->phy_attached = 1;
3394 phy->sas_phy.oob_mode = SATA_OOB_MODE;
3395 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3396 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3397 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3398 sizeof(struct dev_to_host_fis));
3399 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3400 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3401 phy->identify.device_type = SAS_SATA_DEV;
3402 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3403 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3404 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3408 * hw_event_phy_down -we should notify the libsas the phy is down.
3409 * @pm8001_ha: our hba card information
3410 * @piomb: IO message buffer
3412 static void
3413 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3415 struct hw_event_resp *pPayload =
3416 (struct hw_event_resp *)(piomb + 4);
3418 u32 lr_status_evt_portid =
3419 le32_to_cpu(pPayload->lr_status_evt_portid);
3420 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3421 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3422 u8 phy_id =
3423 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3424 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3426 struct pm8001_port *port = &pm8001_ha->port[port_id];
3427 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3428 u32 port_sata = (phy->phy_type & PORT_TYPE_SATA);
3429 port->port_state = portstate;
3430 phy->identify.device_type = 0;
3431 phy->phy_attached = 0;
3432 switch (portstate) {
3433 case PORT_VALID:
3434 break;
3435 case PORT_INVALID:
3436 PM8001_MSG_DBG(pm8001_ha,
3437 pm8001_printk(" PortInvalid portID %d\n", port_id));
3438 PM8001_MSG_DBG(pm8001_ha,
3439 pm8001_printk(" Last phy Down and port invalid\n"));
3440 if (port_sata) {
3441 phy->phy_type = 0;
3442 port->port_attached = 0;
3443 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3444 port_id, phy_id, 0, 0);
3446 sas_phy_disconnected(&phy->sas_phy);
3447 break;
3448 case PORT_IN_RESET:
3449 PM8001_MSG_DBG(pm8001_ha,
3450 pm8001_printk(" Port In Reset portID %d\n", port_id));
3451 break;
3452 case PORT_NOT_ESTABLISHED:
3453 PM8001_MSG_DBG(pm8001_ha,
3454 pm8001_printk(" Phy Down and PORT_NOT_ESTABLISHED\n"));
3455 port->port_attached = 0;
3456 break;
3457 case PORT_LOSTCOMM:
3458 PM8001_MSG_DBG(pm8001_ha,
3459 pm8001_printk(" Phy Down and PORT_LOSTCOMM\n"));
3460 PM8001_MSG_DBG(pm8001_ha,
3461 pm8001_printk(" Last phy Down and port invalid\n"));
3462 if (port_sata) {
3463 port->port_attached = 0;
3464 phy->phy_type = 0;
3465 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3466 port_id, phy_id, 0, 0);
3468 sas_phy_disconnected(&phy->sas_phy);
3469 break;
3470 default:
3471 port->port_attached = 0;
3472 PM8001_DEVIO_DBG(pm8001_ha,
3473 pm8001_printk(" Phy Down and(default) = 0x%x\n",
3474 portstate));
3475 break;
3478 if (port_sata && (portstate != PORT_IN_RESET)) {
3479 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3481 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3485 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3487 struct phy_start_resp *pPayload =
3488 (struct phy_start_resp *)(piomb + 4);
3489 u32 status =
3490 le32_to_cpu(pPayload->status);
3491 u32 phy_id =
3492 le32_to_cpu(pPayload->phyid);
3493 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3495 PM8001_INIT_DBG(pm8001_ha,
3496 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
3497 status, phy_id));
3498 if (status == 0) {
3499 phy->phy_state = PHY_LINK_DOWN;
3500 if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3501 phy->enable_completion != NULL) {
3502 complete(phy->enable_completion);
3503 phy->enable_completion = NULL;
3506 return 0;
3511 * mpi_thermal_hw_event -The hw event has come.
3512 * @pm8001_ha: our hba card information
3513 * @piomb: IO message buffer
3515 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3517 struct thermal_hw_event *pPayload =
3518 (struct thermal_hw_event *)(piomb + 4);
3520 u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3521 u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3523 if (thermal_event & 0x40) {
3524 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3525 "Thermal Event: Local high temperature violated!\n"));
3526 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3527 "Thermal Event: Measured local high temperature %d\n",
3528 ((rht_lht & 0xFF00) >> 8)));
3530 if (thermal_event & 0x10) {
3531 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3532 "Thermal Event: Remote high temperature violated!\n"));
3533 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3534 "Thermal Event: Measured remote high temperature %d\n",
3535 ((rht_lht & 0xFF000000) >> 24)));
3537 return 0;
3541 * mpi_hw_event -The hw event has come.
3542 * @pm8001_ha: our hba card information
3543 * @piomb: IO message buffer
3545 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3547 unsigned long flags, i;
3548 struct hw_event_resp *pPayload =
3549 (struct hw_event_resp *)(piomb + 4);
3550 u32 lr_status_evt_portid =
3551 le32_to_cpu(pPayload->lr_status_evt_portid);
3552 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3553 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3554 u8 phy_id =
3555 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3556 u16 eventType =
3557 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3558 u8 status =
3559 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3560 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3561 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3562 struct pm8001_port *port = &pm8001_ha->port[port_id];
3563 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3564 PM8001_DEV_DBG(pm8001_ha,
3565 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
3566 port_id, phy_id, eventType, status));
3568 switch (eventType) {
3570 case HW_EVENT_SAS_PHY_UP:
3571 PM8001_MSG_DBG(pm8001_ha,
3572 pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3573 hw_event_sas_phy_up(pm8001_ha, piomb);
3574 break;
3575 case HW_EVENT_SATA_PHY_UP:
3576 PM8001_MSG_DBG(pm8001_ha,
3577 pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3578 hw_event_sata_phy_up(pm8001_ha, piomb);
3579 break;
3580 case HW_EVENT_SATA_SPINUP_HOLD:
3581 PM8001_MSG_DBG(pm8001_ha,
3582 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3583 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3584 break;
3585 case HW_EVENT_PHY_DOWN:
3586 PM8001_MSG_DBG(pm8001_ha,
3587 pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3588 hw_event_phy_down(pm8001_ha, piomb);
3589 if (pm8001_ha->reset_in_progress) {
3590 PM8001_MSG_DBG(pm8001_ha,
3591 pm8001_printk("Reset in progress\n"));
3592 return 0;
3594 phy->phy_attached = 0;
3595 phy->phy_state = PHY_LINK_DISABLE;
3596 break;
3597 case HW_EVENT_PORT_INVALID:
3598 PM8001_MSG_DBG(pm8001_ha,
3599 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3600 sas_phy_disconnected(sas_phy);
3601 phy->phy_attached = 0;
3602 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3603 break;
3604 /* the broadcast change primitive received, tell the LIBSAS this event
3605 to revalidate the sas domain*/
3606 case HW_EVENT_BROADCAST_CHANGE:
3607 PM8001_MSG_DBG(pm8001_ha,
3608 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3609 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3610 port_id, phy_id, 1, 0);
3611 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3612 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3613 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3614 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3615 break;
3616 case HW_EVENT_PHY_ERROR:
3617 PM8001_MSG_DBG(pm8001_ha,
3618 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3619 sas_phy_disconnected(&phy->sas_phy);
3620 phy->phy_attached = 0;
3621 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3622 break;
3623 case HW_EVENT_BROADCAST_EXP:
3624 PM8001_MSG_DBG(pm8001_ha,
3625 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3626 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3627 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3628 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3629 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3630 break;
3631 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3632 PM8001_MSG_DBG(pm8001_ha,
3633 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3634 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3635 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3636 break;
3637 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3638 PM8001_MSG_DBG(pm8001_ha,
3639 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3640 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3641 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3642 port_id, phy_id, 0, 0);
3643 break;
3644 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3645 PM8001_MSG_DBG(pm8001_ha,
3646 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3647 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3648 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3649 port_id, phy_id, 0, 0);
3650 break;
3651 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3652 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3653 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3654 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3655 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3656 port_id, phy_id, 0, 0);
3657 break;
3658 case HW_EVENT_MALFUNCTION:
3659 PM8001_MSG_DBG(pm8001_ha,
3660 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3661 break;
3662 case HW_EVENT_BROADCAST_SES:
3663 PM8001_MSG_DBG(pm8001_ha,
3664 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3665 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3666 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3667 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3668 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3669 break;
3670 case HW_EVENT_INBOUND_CRC_ERROR:
3671 PM8001_MSG_DBG(pm8001_ha,
3672 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3673 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3674 HW_EVENT_INBOUND_CRC_ERROR,
3675 port_id, phy_id, 0, 0);
3676 break;
3677 case HW_EVENT_HARD_RESET_RECEIVED:
3678 PM8001_MSG_DBG(pm8001_ha,
3679 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3680 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3681 break;
3682 case HW_EVENT_ID_FRAME_TIMEOUT:
3683 PM8001_MSG_DBG(pm8001_ha,
3684 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3685 sas_phy_disconnected(sas_phy);
3686 phy->phy_attached = 0;
3687 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3688 break;
3689 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3690 PM8001_MSG_DBG(pm8001_ha,
3691 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3692 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3693 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3694 port_id, phy_id, 0, 0);
3695 sas_phy_disconnected(sas_phy);
3696 phy->phy_attached = 0;
3697 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3698 break;
3699 case HW_EVENT_PORT_RESET_TIMER_TMO:
3700 PM8001_MSG_DBG(pm8001_ha,
3701 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3702 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3703 port_id, phy_id, 0, 0);
3704 sas_phy_disconnected(sas_phy);
3705 phy->phy_attached = 0;
3706 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3707 if (pm8001_ha->phy[phy_id].reset_completion) {
3708 pm8001_ha->phy[phy_id].port_reset_status =
3709 PORT_RESET_TMO;
3710 complete(pm8001_ha->phy[phy_id].reset_completion);
3711 pm8001_ha->phy[phy_id].reset_completion = NULL;
3713 break;
3714 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3715 PM8001_MSG_DBG(pm8001_ha,
3716 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3717 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3718 HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3719 port_id, phy_id, 0, 0);
3720 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
3721 if (port->wide_port_phymap & (1 << i)) {
3722 phy = &pm8001_ha->phy[i];
3723 sas_ha->notify_phy_event(&phy->sas_phy,
3724 PHYE_LOSS_OF_SIGNAL);
3725 port->wide_port_phymap &= ~(1 << i);
3728 break;
3729 case HW_EVENT_PORT_RECOVER:
3730 PM8001_MSG_DBG(pm8001_ha,
3731 pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3732 hw_event_port_recover(pm8001_ha, piomb);
3733 break;
3734 case HW_EVENT_PORT_RESET_COMPLETE:
3735 PM8001_MSG_DBG(pm8001_ha,
3736 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3737 if (pm8001_ha->phy[phy_id].reset_completion) {
3738 pm8001_ha->phy[phy_id].port_reset_status =
3739 PORT_RESET_SUCCESS;
3740 complete(pm8001_ha->phy[phy_id].reset_completion);
3741 pm8001_ha->phy[phy_id].reset_completion = NULL;
3743 break;
3744 case EVENT_BROADCAST_ASYNCH_EVENT:
3745 PM8001_MSG_DBG(pm8001_ha,
3746 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3747 break;
3748 default:
3749 PM8001_DEVIO_DBG(pm8001_ha,
3750 pm8001_printk("Unknown event type 0x%x\n", eventType));
3751 break;
3753 return 0;
3757 * mpi_phy_stop_resp - SPCv specific
3758 * @pm8001_ha: our hba card information
3759 * @piomb: IO message buffer
3761 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3763 struct phy_stop_resp *pPayload =
3764 (struct phy_stop_resp *)(piomb + 4);
3765 u32 status =
3766 le32_to_cpu(pPayload->status);
3767 u32 phyid =
3768 le32_to_cpu(pPayload->phyid) & 0xFF;
3769 struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3770 PM8001_MSG_DBG(pm8001_ha,
3771 pm8001_printk("phy:0x%x status:0x%x\n",
3772 phyid, status));
3773 if (status == PHY_STOP_SUCCESS ||
3774 status == PHY_STOP_ERR_DEVICE_ATTACHED)
3775 phy->phy_state = PHY_LINK_DISABLE;
3776 return 0;
3780 * mpi_set_controller_config_resp - SPCv specific
3781 * @pm8001_ha: our hba card information
3782 * @piomb: IO message buffer
3784 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3785 void *piomb)
3787 struct set_ctrl_cfg_resp *pPayload =
3788 (struct set_ctrl_cfg_resp *)(piomb + 4);
3789 u32 status = le32_to_cpu(pPayload->status);
3790 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3792 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3793 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3794 status, err_qlfr_pgcd));
3796 return 0;
3800 * mpi_get_controller_config_resp - SPCv specific
3801 * @pm8001_ha: our hba card information
3802 * @piomb: IO message buffer
3804 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3805 void *piomb)
3807 PM8001_MSG_DBG(pm8001_ha,
3808 pm8001_printk(" pm80xx_addition_functionality\n"));
3810 return 0;
3814 * mpi_get_phy_profile_resp - SPCv specific
3815 * @pm8001_ha: our hba card information
3816 * @piomb: IO message buffer
3818 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3819 void *piomb)
3821 PM8001_MSG_DBG(pm8001_ha,
3822 pm8001_printk(" pm80xx_addition_functionality\n"));
3824 return 0;
3828 * mpi_flash_op_ext_resp - SPCv specific
3829 * @pm8001_ha: our hba card information
3830 * @piomb: IO message buffer
3832 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3834 PM8001_MSG_DBG(pm8001_ha,
3835 pm8001_printk(" pm80xx_addition_functionality\n"));
3837 return 0;
3841 * mpi_set_phy_profile_resp - SPCv specific
3842 * @pm8001_ha: our hba card information
3843 * @piomb: IO message buffer
3845 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3846 void *piomb)
3848 u32 tag;
3849 u8 page_code;
3850 int rc = 0;
3851 struct set_phy_profile_resp *pPayload =
3852 (struct set_phy_profile_resp *)(piomb + 4);
3853 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3854 u32 status = le32_to_cpu(pPayload->status);
3856 tag = le32_to_cpu(pPayload->tag);
3857 page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3858 if (status) {
3859 /* status is FAILED */
3860 PM8001_FAIL_DBG(pm8001_ha,
3861 pm8001_printk("PhyProfile command failed with status "
3862 "0x%08X \n", status));
3863 rc = -1;
3864 } else {
3865 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3866 PM8001_FAIL_DBG(pm8001_ha,
3867 pm8001_printk("Invalid page code 0x%X\n",
3868 page_code));
3869 rc = -1;
3872 pm8001_tag_free(pm8001_ha, tag);
3873 return rc;
3877 * mpi_kek_management_resp - SPCv specific
3878 * @pm8001_ha: our hba card information
3879 * @piomb: IO message buffer
3881 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3882 void *piomb)
3884 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3886 u32 status = le32_to_cpu(pPayload->status);
3887 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3888 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3890 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3891 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3892 status, kidx_new_curr_ksop, err_qlfr));
3894 return 0;
3898 * mpi_dek_management_resp - SPCv specific
3899 * @pm8001_ha: our hba card information
3900 * @piomb: IO message buffer
3902 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3903 void *piomb)
3905 PM8001_MSG_DBG(pm8001_ha,
3906 pm8001_printk(" pm80xx_addition_functionality\n"));
3908 return 0;
3912 * ssp_coalesced_comp_resp - SPCv specific
3913 * @pm8001_ha: our hba card information
3914 * @piomb: IO message buffer
3916 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3917 void *piomb)
3919 PM8001_MSG_DBG(pm8001_ha,
3920 pm8001_printk(" pm80xx_addition_functionality\n"));
3922 return 0;
3926 * process_one_iomb - process one outbound Queue memory block
3927 * @pm8001_ha: our hba card information
3928 * @piomb: IO message buffer
3930 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3932 __le32 pHeader = *(__le32 *)piomb;
3933 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3935 switch (opc) {
3936 case OPC_OUB_ECHO:
3937 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3938 break;
3939 case OPC_OUB_HW_EVENT:
3940 PM8001_MSG_DBG(pm8001_ha,
3941 pm8001_printk("OPC_OUB_HW_EVENT\n"));
3942 mpi_hw_event(pm8001_ha, piomb);
3943 break;
3944 case OPC_OUB_THERM_HW_EVENT:
3945 PM8001_MSG_DBG(pm8001_ha,
3946 pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
3947 mpi_thermal_hw_event(pm8001_ha, piomb);
3948 break;
3949 case OPC_OUB_SSP_COMP:
3950 PM8001_MSG_DBG(pm8001_ha,
3951 pm8001_printk("OPC_OUB_SSP_COMP\n"));
3952 mpi_ssp_completion(pm8001_ha, piomb);
3953 break;
3954 case OPC_OUB_SMP_COMP:
3955 PM8001_MSG_DBG(pm8001_ha,
3956 pm8001_printk("OPC_OUB_SMP_COMP\n"));
3957 mpi_smp_completion(pm8001_ha, piomb);
3958 break;
3959 case OPC_OUB_LOCAL_PHY_CNTRL:
3960 PM8001_MSG_DBG(pm8001_ha,
3961 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3962 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3963 break;
3964 case OPC_OUB_DEV_REGIST:
3965 PM8001_MSG_DBG(pm8001_ha,
3966 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3967 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3968 break;
3969 case OPC_OUB_DEREG_DEV:
3970 PM8001_MSG_DBG(pm8001_ha,
3971 pm8001_printk("unregister the device\n"));
3972 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3973 break;
3974 case OPC_OUB_GET_DEV_HANDLE:
3975 PM8001_MSG_DBG(pm8001_ha,
3976 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3977 break;
3978 case OPC_OUB_SATA_COMP:
3979 PM8001_MSG_DBG(pm8001_ha,
3980 pm8001_printk("OPC_OUB_SATA_COMP\n"));
3981 mpi_sata_completion(pm8001_ha, piomb);
3982 break;
3983 case OPC_OUB_SATA_EVENT:
3984 PM8001_MSG_DBG(pm8001_ha,
3985 pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3986 mpi_sata_event(pm8001_ha, piomb);
3987 break;
3988 case OPC_OUB_SSP_EVENT:
3989 PM8001_MSG_DBG(pm8001_ha,
3990 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3991 mpi_ssp_event(pm8001_ha, piomb);
3992 break;
3993 case OPC_OUB_DEV_HANDLE_ARRIV:
3994 PM8001_MSG_DBG(pm8001_ha,
3995 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3996 /*This is for target*/
3997 break;
3998 case OPC_OUB_SSP_RECV_EVENT:
3999 PM8001_MSG_DBG(pm8001_ha,
4000 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
4001 /*This is for target*/
4002 break;
4003 case OPC_OUB_FW_FLASH_UPDATE:
4004 PM8001_MSG_DBG(pm8001_ha,
4005 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
4006 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
4007 break;
4008 case OPC_OUB_GPIO_RESPONSE:
4009 PM8001_MSG_DBG(pm8001_ha,
4010 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
4011 break;
4012 case OPC_OUB_GPIO_EVENT:
4013 PM8001_MSG_DBG(pm8001_ha,
4014 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
4015 break;
4016 case OPC_OUB_GENERAL_EVENT:
4017 PM8001_MSG_DBG(pm8001_ha,
4018 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
4019 pm8001_mpi_general_event(pm8001_ha, piomb);
4020 break;
4021 case OPC_OUB_SSP_ABORT_RSP:
4022 PM8001_MSG_DBG(pm8001_ha,
4023 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
4024 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4025 break;
4026 case OPC_OUB_SATA_ABORT_RSP:
4027 PM8001_MSG_DBG(pm8001_ha,
4028 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
4029 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4030 break;
4031 case OPC_OUB_SAS_DIAG_MODE_START_END:
4032 PM8001_MSG_DBG(pm8001_ha,
4033 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
4034 break;
4035 case OPC_OUB_SAS_DIAG_EXECUTE:
4036 PM8001_MSG_DBG(pm8001_ha,
4037 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
4038 break;
4039 case OPC_OUB_GET_TIME_STAMP:
4040 PM8001_MSG_DBG(pm8001_ha,
4041 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
4042 break;
4043 case OPC_OUB_SAS_HW_EVENT_ACK:
4044 PM8001_MSG_DBG(pm8001_ha,
4045 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
4046 break;
4047 case OPC_OUB_PORT_CONTROL:
4048 PM8001_MSG_DBG(pm8001_ha,
4049 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
4050 break;
4051 case OPC_OUB_SMP_ABORT_RSP:
4052 PM8001_MSG_DBG(pm8001_ha,
4053 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
4054 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4055 break;
4056 case OPC_OUB_GET_NVMD_DATA:
4057 PM8001_MSG_DBG(pm8001_ha,
4058 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
4059 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
4060 break;
4061 case OPC_OUB_SET_NVMD_DATA:
4062 PM8001_MSG_DBG(pm8001_ha,
4063 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
4064 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
4065 break;
4066 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
4067 PM8001_MSG_DBG(pm8001_ha,
4068 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
4069 break;
4070 case OPC_OUB_SET_DEVICE_STATE:
4071 PM8001_MSG_DBG(pm8001_ha,
4072 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
4073 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
4074 break;
4075 case OPC_OUB_GET_DEVICE_STATE:
4076 PM8001_MSG_DBG(pm8001_ha,
4077 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
4078 break;
4079 case OPC_OUB_SET_DEV_INFO:
4080 PM8001_MSG_DBG(pm8001_ha,
4081 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
4082 break;
4083 /* spcv specifc commands */
4084 case OPC_OUB_PHY_START_RESP:
4085 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4086 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
4087 mpi_phy_start_resp(pm8001_ha, piomb);
4088 break;
4089 case OPC_OUB_PHY_STOP_RESP:
4090 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4091 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
4092 mpi_phy_stop_resp(pm8001_ha, piomb);
4093 break;
4094 case OPC_OUB_SET_CONTROLLER_CONFIG:
4095 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4096 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
4097 mpi_set_controller_config_resp(pm8001_ha, piomb);
4098 break;
4099 case OPC_OUB_GET_CONTROLLER_CONFIG:
4100 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4101 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
4102 mpi_get_controller_config_resp(pm8001_ha, piomb);
4103 break;
4104 case OPC_OUB_GET_PHY_PROFILE:
4105 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4106 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
4107 mpi_get_phy_profile_resp(pm8001_ha, piomb);
4108 break;
4109 case OPC_OUB_FLASH_OP_EXT:
4110 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4111 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
4112 mpi_flash_op_ext_resp(pm8001_ha, piomb);
4113 break;
4114 case OPC_OUB_SET_PHY_PROFILE:
4115 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4116 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
4117 mpi_set_phy_profile_resp(pm8001_ha, piomb);
4118 break;
4119 case OPC_OUB_KEK_MANAGEMENT_RESP:
4120 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4121 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
4122 mpi_kek_management_resp(pm8001_ha, piomb);
4123 break;
4124 case OPC_OUB_DEK_MANAGEMENT_RESP:
4125 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4126 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
4127 mpi_dek_management_resp(pm8001_ha, piomb);
4128 break;
4129 case OPC_OUB_SSP_COALESCED_COMP_RESP:
4130 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4131 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
4132 ssp_coalesced_comp_resp(pm8001_ha, piomb);
4133 break;
4134 default:
4135 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
4136 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
4137 break;
4141 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha)
4143 PM8001_FAIL_DBG(pm8001_ha,
4144 pm8001_printk("MSGU_SCRATCH_PAD_0: 0x%x\n",
4145 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
4146 PM8001_FAIL_DBG(pm8001_ha,
4147 pm8001_printk("MSGU_SCRATCH_PAD_1:0x%x\n",
4148 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)));
4149 PM8001_FAIL_DBG(pm8001_ha,
4150 pm8001_printk("MSGU_SCRATCH_PAD_2: 0x%x\n",
4151 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)));
4152 PM8001_FAIL_DBG(pm8001_ha,
4153 pm8001_printk("MSGU_SCRATCH_PAD_3: 0x%x\n",
4154 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
4155 PM8001_FAIL_DBG(pm8001_ha,
4156 pm8001_printk("MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",
4157 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0)));
4158 PM8001_FAIL_DBG(pm8001_ha,
4159 pm8001_printk("MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",
4160 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1)));
4161 PM8001_FAIL_DBG(pm8001_ha,
4162 pm8001_printk("MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",
4163 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2)));
4164 PM8001_FAIL_DBG(pm8001_ha,
4165 pm8001_printk("MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",
4166 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3)));
4167 PM8001_FAIL_DBG(pm8001_ha,
4168 pm8001_printk("MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",
4169 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4)));
4170 PM8001_FAIL_DBG(pm8001_ha,
4171 pm8001_printk("MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",
4172 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5)));
4173 PM8001_FAIL_DBG(pm8001_ha,
4174 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",
4175 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6)));
4176 PM8001_FAIL_DBG(pm8001_ha,
4177 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",
4178 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7)));
4181 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4183 struct outbound_queue_table *circularQ;
4184 void *pMsg1 = NULL;
4185 u8 uninitialized_var(bc);
4186 u32 ret = MPI_IO_STATUS_FAIL;
4187 unsigned long flags;
4188 u32 regval;
4190 if (vec == (pm8001_ha->number_of_intr - 1)) {
4191 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
4192 if ((regval & SCRATCH_PAD_MIPSALL_READY) !=
4193 SCRATCH_PAD_MIPSALL_READY) {
4194 pm8001_ha->controller_fatal_error = true;
4195 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
4196 "Firmware Fatal error! Regval:0x%x\n", regval));
4197 print_scratchpad_registers(pm8001_ha);
4198 return ret;
4201 spin_lock_irqsave(&pm8001_ha->lock, flags);
4202 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4203 do {
4204 /* spurious interrupt during setup if kexec-ing and
4205 * driver doing a doorbell access w/ the pre-kexec oq
4206 * interrupt setup.
4208 if (!circularQ->pi_virt)
4209 break;
4210 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4211 if (MPI_IO_STATUS_SUCCESS == ret) {
4212 /* process the outbound message */
4213 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
4214 /* free the message from the outbound circular buffer */
4215 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4216 circularQ, bc);
4218 if (MPI_IO_STATUS_BUSY == ret) {
4219 /* Update the producer index from SPC */
4220 circularQ->producer_index =
4221 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4222 if (le32_to_cpu(circularQ->producer_index) ==
4223 circularQ->consumer_idx)
4224 /* OQ is empty */
4225 break;
4227 } while (1);
4228 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4229 return ret;
4232 /* DMA_... to our direction translation. */
4233 static const u8 data_dir_flags[] = {
4234 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
4235 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */
4236 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */
4237 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */
4240 static void build_smp_cmd(u32 deviceID, __le32 hTag,
4241 struct smp_req *psmp_cmd, int mode, int length)
4243 psmp_cmd->tag = hTag;
4244 psmp_cmd->device_id = cpu_to_le32(deviceID);
4245 if (mode == SMP_DIRECT) {
4246 length = length - 4; /* subtract crc */
4247 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
4248 } else {
4249 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4254 * pm8001_chip_smp_req - send a SMP task to FW
4255 * @pm8001_ha: our hba card information.
4256 * @ccb: the ccb information this request used.
4258 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4259 struct pm8001_ccb_info *ccb)
4261 int elem, rc;
4262 struct sas_task *task = ccb->task;
4263 struct domain_device *dev = task->dev;
4264 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4265 struct scatterlist *sg_req, *sg_resp;
4266 u32 req_len, resp_len;
4267 struct smp_req smp_cmd;
4268 u32 opc;
4269 struct inbound_queue_table *circularQ;
4270 char *preq_dma_addr = NULL;
4271 __le64 tmp_addr;
4272 u32 i, length;
4274 memset(&smp_cmd, 0, sizeof(smp_cmd));
4276 * DMA-map SMP request, response buffers
4278 sg_req = &task->smp_task.smp_req;
4279 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4280 if (!elem)
4281 return -ENOMEM;
4282 req_len = sg_dma_len(sg_req);
4284 sg_resp = &task->smp_task.smp_resp;
4285 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4286 if (!elem) {
4287 rc = -ENOMEM;
4288 goto err_out;
4290 resp_len = sg_dma_len(sg_resp);
4291 /* must be in dwords */
4292 if ((req_len & 0x3) || (resp_len & 0x3)) {
4293 rc = -EINVAL;
4294 goto err_out_2;
4297 opc = OPC_INB_SMP_REQUEST;
4298 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4299 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4301 length = sg_req->length;
4302 PM8001_IO_DBG(pm8001_ha,
4303 pm8001_printk("SMP Frame Length %d\n", sg_req->length));
4304 if (!(length - 8))
4305 pm8001_ha->smp_exp_mode = SMP_DIRECT;
4306 else
4307 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
4310 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4311 preq_dma_addr = (char *)phys_to_virt(tmp_addr);
4313 /* INDIRECT MODE command settings. Use DMA */
4314 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
4315 PM8001_IO_DBG(pm8001_ha,
4316 pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
4317 /* for SPCv indirect mode. Place the top 4 bytes of
4318 * SMP Request header here. */
4319 for (i = 0; i < 4; i++)
4320 smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
4321 /* exclude top 4 bytes for SMP req header */
4322 smp_cmd.long_smp_req.long_req_addr =
4323 cpu_to_le64((u64)sg_dma_address
4324 (&task->smp_task.smp_req) + 4);
4325 /* exclude 4 bytes for SMP req header and CRC */
4326 smp_cmd.long_smp_req.long_req_size =
4327 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
4328 smp_cmd.long_smp_req.long_resp_addr =
4329 cpu_to_le64((u64)sg_dma_address
4330 (&task->smp_task.smp_resp));
4331 smp_cmd.long_smp_req.long_resp_size =
4332 cpu_to_le32((u32)sg_dma_len
4333 (&task->smp_task.smp_resp)-4);
4334 } else { /* DIRECT MODE */
4335 smp_cmd.long_smp_req.long_req_addr =
4336 cpu_to_le64((u64)sg_dma_address
4337 (&task->smp_task.smp_req));
4338 smp_cmd.long_smp_req.long_req_size =
4339 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4340 smp_cmd.long_smp_req.long_resp_addr =
4341 cpu_to_le64((u64)sg_dma_address
4342 (&task->smp_task.smp_resp));
4343 smp_cmd.long_smp_req.long_resp_size =
4344 cpu_to_le32
4345 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4347 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
4348 PM8001_IO_DBG(pm8001_ha,
4349 pm8001_printk("SMP REQUEST DIRECT MODE\n"));
4350 for (i = 0; i < length; i++)
4351 if (i < 16) {
4352 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
4353 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4354 "Byte[%d]:%x (DMA data:%x)\n",
4355 i, smp_cmd.smp_req16[i],
4356 *(preq_dma_addr)));
4357 } else {
4358 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
4359 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4360 "Byte[%d]:%x (DMA data:%x)\n",
4361 i, smp_cmd.smp_req[i],
4362 *(preq_dma_addr)));
4366 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
4367 &smp_cmd, pm8001_ha->smp_exp_mode, length);
4368 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &smp_cmd,
4369 sizeof(smp_cmd), 0);
4370 if (rc)
4371 goto err_out_2;
4372 return 0;
4374 err_out_2:
4375 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4376 DMA_FROM_DEVICE);
4377 err_out:
4378 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4379 DMA_TO_DEVICE);
4380 return rc;
4383 static int check_enc_sas_cmd(struct sas_task *task)
4385 u8 cmd = task->ssp_task.cmd->cmnd[0];
4387 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
4388 return 1;
4389 else
4390 return 0;
4393 static int check_enc_sat_cmd(struct sas_task *task)
4395 int ret = 0;
4396 switch (task->ata_task.fis.command) {
4397 case ATA_CMD_FPDMA_READ:
4398 case ATA_CMD_READ_EXT:
4399 case ATA_CMD_READ:
4400 case ATA_CMD_FPDMA_WRITE:
4401 case ATA_CMD_WRITE_EXT:
4402 case ATA_CMD_WRITE:
4403 case ATA_CMD_PIO_READ:
4404 case ATA_CMD_PIO_READ_EXT:
4405 case ATA_CMD_PIO_WRITE:
4406 case ATA_CMD_PIO_WRITE_EXT:
4407 ret = 1;
4408 break;
4409 default:
4410 ret = 0;
4411 break;
4413 return ret;
4417 * pm80xx_chip_ssp_io_req - send a SSP task to FW
4418 * @pm8001_ha: our hba card information.
4419 * @ccb: the ccb information this request used.
4421 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4422 struct pm8001_ccb_info *ccb)
4424 struct sas_task *task = ccb->task;
4425 struct domain_device *dev = task->dev;
4426 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4427 struct ssp_ini_io_start_req ssp_cmd;
4428 u32 tag = ccb->ccb_tag;
4429 int ret;
4430 u64 phys_addr, start_addr, end_addr;
4431 u32 end_addr_high, end_addr_low;
4432 struct inbound_queue_table *circularQ;
4433 u32 q_index;
4434 u32 opc = OPC_INB_SSPINIIOSTART;
4435 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4436 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4437 /* data address domain added for spcv; set to 0 by host,
4438 * used internally by controller
4439 * 0 for SAS 1.1 and SAS 2.0 compatible TLR
4441 ssp_cmd.dad_dir_m_tlr =
4442 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
4443 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4444 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4445 ssp_cmd.tag = cpu_to_le32(tag);
4446 if (task->ssp_task.enable_first_burst)
4447 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4448 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4449 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4450 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4451 task->ssp_task.cmd->cmd_len);
4452 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4453 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4455 /* Check if encryption is set */
4456 if (pm8001_ha->chip->encrypt &&
4457 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
4458 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4459 "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
4460 task->ssp_task.cmd->cmnd[0]));
4461 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
4462 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
4463 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
4464 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
4466 /* fill in PRD (scatter/gather) table, if any */
4467 if (task->num_scatter > 1) {
4468 pm8001_chip_make_sg(task->scatter,
4469 ccb->n_elem, ccb->buf_prd);
4470 phys_addr = ccb->ccb_dma_handle +
4471 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4472 ssp_cmd.enc_addr_low =
4473 cpu_to_le32(lower_32_bits(phys_addr));
4474 ssp_cmd.enc_addr_high =
4475 cpu_to_le32(upper_32_bits(phys_addr));
4476 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4477 } else if (task->num_scatter == 1) {
4478 u64 dma_addr = sg_dma_address(task->scatter);
4479 ssp_cmd.enc_addr_low =
4480 cpu_to_le32(lower_32_bits(dma_addr));
4481 ssp_cmd.enc_addr_high =
4482 cpu_to_le32(upper_32_bits(dma_addr));
4483 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4484 ssp_cmd.enc_esgl = 0;
4485 /* Check 4G Boundary */
4486 start_addr = cpu_to_le64(dma_addr);
4487 end_addr = (start_addr + ssp_cmd.enc_len) - 1;
4488 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4489 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4490 if (end_addr_high != ssp_cmd.enc_addr_high) {
4491 PM8001_FAIL_DBG(pm8001_ha,
4492 pm8001_printk("The sg list address "
4493 "start_addr=0x%016llx data_len=0x%x "
4494 "end_addr_high=0x%08x end_addr_low="
4495 "0x%08x has crossed 4G boundary\n",
4496 start_addr, ssp_cmd.enc_len,
4497 end_addr_high, end_addr_low));
4498 pm8001_chip_make_sg(task->scatter, 1,
4499 ccb->buf_prd);
4500 phys_addr = ccb->ccb_dma_handle +
4501 offsetof(struct pm8001_ccb_info,
4502 buf_prd[0]);
4503 ssp_cmd.enc_addr_low =
4504 cpu_to_le32(lower_32_bits(phys_addr));
4505 ssp_cmd.enc_addr_high =
4506 cpu_to_le32(upper_32_bits(phys_addr));
4507 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4509 } else if (task->num_scatter == 0) {
4510 ssp_cmd.enc_addr_low = 0;
4511 ssp_cmd.enc_addr_high = 0;
4512 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4513 ssp_cmd.enc_esgl = 0;
4515 /* XTS mode. All other fields are 0 */
4516 ssp_cmd.key_cmode = 0x6 << 4;
4517 /* set tweak values. Should be the start lba */
4518 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4519 (task->ssp_task.cmd->cmnd[3] << 16) |
4520 (task->ssp_task.cmd->cmnd[4] << 8) |
4521 (task->ssp_task.cmd->cmnd[5]));
4522 } else {
4523 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4524 "Sending Normal SAS command 0x%x inb q %x\n",
4525 task->ssp_task.cmd->cmnd[0], q_index));
4526 /* fill in PRD (scatter/gather) table, if any */
4527 if (task->num_scatter > 1) {
4528 pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4529 ccb->buf_prd);
4530 phys_addr = ccb->ccb_dma_handle +
4531 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4532 ssp_cmd.addr_low =
4533 cpu_to_le32(lower_32_bits(phys_addr));
4534 ssp_cmd.addr_high =
4535 cpu_to_le32(upper_32_bits(phys_addr));
4536 ssp_cmd.esgl = cpu_to_le32(1<<31);
4537 } else if (task->num_scatter == 1) {
4538 u64 dma_addr = sg_dma_address(task->scatter);
4539 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4540 ssp_cmd.addr_high =
4541 cpu_to_le32(upper_32_bits(dma_addr));
4542 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4543 ssp_cmd.esgl = 0;
4544 /* Check 4G Boundary */
4545 start_addr = cpu_to_le64(dma_addr);
4546 end_addr = (start_addr + ssp_cmd.len) - 1;
4547 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4548 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4549 if (end_addr_high != ssp_cmd.addr_high) {
4550 PM8001_FAIL_DBG(pm8001_ha,
4551 pm8001_printk("The sg list address "
4552 "start_addr=0x%016llx data_len=0x%x "
4553 "end_addr_high=0x%08x end_addr_low="
4554 "0x%08x has crossed 4G boundary\n",
4555 start_addr, ssp_cmd.len,
4556 end_addr_high, end_addr_low));
4557 pm8001_chip_make_sg(task->scatter, 1,
4558 ccb->buf_prd);
4559 phys_addr = ccb->ccb_dma_handle +
4560 offsetof(struct pm8001_ccb_info,
4561 buf_prd[0]);
4562 ssp_cmd.addr_low =
4563 cpu_to_le32(lower_32_bits(phys_addr));
4564 ssp_cmd.addr_high =
4565 cpu_to_le32(upper_32_bits(phys_addr));
4566 ssp_cmd.esgl = cpu_to_le32(1<<31);
4568 } else if (task->num_scatter == 0) {
4569 ssp_cmd.addr_low = 0;
4570 ssp_cmd.addr_high = 0;
4571 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4572 ssp_cmd.esgl = 0;
4575 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4576 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4577 &ssp_cmd, sizeof(ssp_cmd), q_index);
4578 return ret;
4581 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4582 struct pm8001_ccb_info *ccb)
4584 struct sas_task *task = ccb->task;
4585 struct domain_device *dev = task->dev;
4586 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4587 u32 tag = ccb->ccb_tag;
4588 int ret;
4589 u32 q_index;
4590 struct sata_start_req sata_cmd;
4591 u32 hdr_tag, ncg_tag = 0;
4592 u64 phys_addr, start_addr, end_addr;
4593 u32 end_addr_high, end_addr_low;
4594 u32 ATAP = 0x0;
4595 u32 dir;
4596 struct inbound_queue_table *circularQ;
4597 unsigned long flags;
4598 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4599 memset(&sata_cmd, 0, sizeof(sata_cmd));
4600 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4601 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4603 if (task->data_dir == DMA_NONE) {
4604 ATAP = 0x04; /* no data*/
4605 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4606 } else if (likely(!task->ata_task.device_control_reg_update)) {
4607 if (task->ata_task.dma_xfer) {
4608 ATAP = 0x06; /* DMA */
4609 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4610 } else {
4611 ATAP = 0x05; /* PIO*/
4612 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4614 if (task->ata_task.use_ncq &&
4615 dev->sata_dev.class != ATA_DEV_ATAPI) {
4616 ATAP = 0x07; /* FPDMA */
4617 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4620 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4621 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4622 ncg_tag = hdr_tag;
4624 dir = data_dir_flags[task->data_dir] << 8;
4625 sata_cmd.tag = cpu_to_le32(tag);
4626 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4627 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4629 sata_cmd.sata_fis = task->ata_task.fis;
4630 if (likely(!task->ata_task.device_control_reg_update))
4631 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4632 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4634 /* Check if encryption is set */
4635 if (pm8001_ha->chip->encrypt &&
4636 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4637 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4638 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4639 sata_cmd.sata_fis.command));
4640 opc = OPC_INB_SATA_DIF_ENC_IO;
4642 /* set encryption bit */
4643 sata_cmd.ncqtag_atap_dir_m_dad =
4644 cpu_to_le32(((ncg_tag & 0xff)<<16)|
4645 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4646 /* dad (bit 0-1) is 0 */
4647 /* fill in PRD (scatter/gather) table, if any */
4648 if (task->num_scatter > 1) {
4649 pm8001_chip_make_sg(task->scatter,
4650 ccb->n_elem, ccb->buf_prd);
4651 phys_addr = ccb->ccb_dma_handle +
4652 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4653 sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
4654 sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
4655 sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4656 } else if (task->num_scatter == 1) {
4657 u64 dma_addr = sg_dma_address(task->scatter);
4658 sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
4659 sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
4660 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4661 sata_cmd.enc_esgl = 0;
4662 /* Check 4G Boundary */
4663 start_addr = cpu_to_le64(dma_addr);
4664 end_addr = (start_addr + sata_cmd.enc_len) - 1;
4665 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4666 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4667 if (end_addr_high != sata_cmd.enc_addr_high) {
4668 PM8001_FAIL_DBG(pm8001_ha,
4669 pm8001_printk("The sg list address "
4670 "start_addr=0x%016llx data_len=0x%x "
4671 "end_addr_high=0x%08x end_addr_low"
4672 "=0x%08x has crossed 4G boundary\n",
4673 start_addr, sata_cmd.enc_len,
4674 end_addr_high, end_addr_low));
4675 pm8001_chip_make_sg(task->scatter, 1,
4676 ccb->buf_prd);
4677 phys_addr = ccb->ccb_dma_handle +
4678 offsetof(struct pm8001_ccb_info,
4679 buf_prd[0]);
4680 sata_cmd.enc_addr_low =
4681 lower_32_bits(phys_addr);
4682 sata_cmd.enc_addr_high =
4683 upper_32_bits(phys_addr);
4684 sata_cmd.enc_esgl =
4685 cpu_to_le32(1 << 31);
4687 } else if (task->num_scatter == 0) {
4688 sata_cmd.enc_addr_low = 0;
4689 sata_cmd.enc_addr_high = 0;
4690 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4691 sata_cmd.enc_esgl = 0;
4693 /* XTS mode. All other fields are 0 */
4694 sata_cmd.key_index_mode = 0x6 << 4;
4695 /* set tweak values. Should be the start lba */
4696 sata_cmd.twk_val0 =
4697 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4698 (sata_cmd.sata_fis.lbah << 16) |
4699 (sata_cmd.sata_fis.lbam << 8) |
4700 (sata_cmd.sata_fis.lbal));
4701 sata_cmd.twk_val1 =
4702 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4703 (sata_cmd.sata_fis.lbam_exp));
4704 } else {
4705 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4706 "Sending Normal SATA command 0x%x inb %x\n",
4707 sata_cmd.sata_fis.command, q_index));
4708 /* dad (bit 0-1) is 0 */
4709 sata_cmd.ncqtag_atap_dir_m_dad =
4710 cpu_to_le32(((ncg_tag & 0xff)<<16) |
4711 ((ATAP & 0x3f) << 10) | dir);
4713 /* fill in PRD (scatter/gather) table, if any */
4714 if (task->num_scatter > 1) {
4715 pm8001_chip_make_sg(task->scatter,
4716 ccb->n_elem, ccb->buf_prd);
4717 phys_addr = ccb->ccb_dma_handle +
4718 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4719 sata_cmd.addr_low = lower_32_bits(phys_addr);
4720 sata_cmd.addr_high = upper_32_bits(phys_addr);
4721 sata_cmd.esgl = cpu_to_le32(1 << 31);
4722 } else if (task->num_scatter == 1) {
4723 u64 dma_addr = sg_dma_address(task->scatter);
4724 sata_cmd.addr_low = lower_32_bits(dma_addr);
4725 sata_cmd.addr_high = upper_32_bits(dma_addr);
4726 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4727 sata_cmd.esgl = 0;
4728 /* Check 4G Boundary */
4729 start_addr = cpu_to_le64(dma_addr);
4730 end_addr = (start_addr + sata_cmd.len) - 1;
4731 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4732 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4733 if (end_addr_high != sata_cmd.addr_high) {
4734 PM8001_FAIL_DBG(pm8001_ha,
4735 pm8001_printk("The sg list address "
4736 "start_addr=0x%016llx data_len=0x%x"
4737 "end_addr_high=0x%08x end_addr_low="
4738 "0x%08x has crossed 4G boundary\n",
4739 start_addr, sata_cmd.len,
4740 end_addr_high, end_addr_low));
4741 pm8001_chip_make_sg(task->scatter, 1,
4742 ccb->buf_prd);
4743 phys_addr = ccb->ccb_dma_handle +
4744 offsetof(struct pm8001_ccb_info,
4745 buf_prd[0]);
4746 sata_cmd.addr_low =
4747 lower_32_bits(phys_addr);
4748 sata_cmd.addr_high =
4749 upper_32_bits(phys_addr);
4750 sata_cmd.esgl = cpu_to_le32(1 << 31);
4752 } else if (task->num_scatter == 0) {
4753 sata_cmd.addr_low = 0;
4754 sata_cmd.addr_high = 0;
4755 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4756 sata_cmd.esgl = 0;
4758 /* scsi cdb */
4759 sata_cmd.atapi_scsi_cdb[0] =
4760 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4761 (task->ata_task.atapi_packet[1] << 8) |
4762 (task->ata_task.atapi_packet[2] << 16) |
4763 (task->ata_task.atapi_packet[3] << 24)));
4764 sata_cmd.atapi_scsi_cdb[1] =
4765 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4766 (task->ata_task.atapi_packet[5] << 8) |
4767 (task->ata_task.atapi_packet[6] << 16) |
4768 (task->ata_task.atapi_packet[7] << 24)));
4769 sata_cmd.atapi_scsi_cdb[2] =
4770 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4771 (task->ata_task.atapi_packet[9] << 8) |
4772 (task->ata_task.atapi_packet[10] << 16) |
4773 (task->ata_task.atapi_packet[11] << 24)));
4774 sata_cmd.atapi_scsi_cdb[3] =
4775 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4776 (task->ata_task.atapi_packet[13] << 8) |
4777 (task->ata_task.atapi_packet[14] << 16) |
4778 (task->ata_task.atapi_packet[15] << 24)));
4781 /* Check for read log for failed drive and return */
4782 if (sata_cmd.sata_fis.command == 0x2f) {
4783 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4784 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4785 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4786 struct task_status_struct *ts;
4788 pm8001_ha_dev->id &= 0xDFFFFFFF;
4789 ts = &task->task_status;
4791 spin_lock_irqsave(&task->task_state_lock, flags);
4792 ts->resp = SAS_TASK_COMPLETE;
4793 ts->stat = SAM_STAT_GOOD;
4794 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4795 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4796 task->task_state_flags |= SAS_TASK_STATE_DONE;
4797 if (unlikely((task->task_state_flags &
4798 SAS_TASK_STATE_ABORTED))) {
4799 spin_unlock_irqrestore(&task->task_state_lock,
4800 flags);
4801 PM8001_FAIL_DBG(pm8001_ha,
4802 pm8001_printk("task 0x%p resp 0x%x "
4803 " stat 0x%x but aborted by upper layer "
4804 "\n", task, ts->resp, ts->stat));
4805 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4806 return 0;
4807 } else {
4808 spin_unlock_irqrestore(&task->task_state_lock,
4809 flags);
4810 pm8001_ccb_task_free_done(pm8001_ha, task,
4811 ccb, tag);
4812 return 0;
4816 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4817 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4818 &sata_cmd, sizeof(sata_cmd), q_index);
4819 return ret;
4823 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4824 * @pm8001_ha: our hba card information.
4825 * @num: the inbound queue number
4826 * @phy_id: the phy id which we wanted to start up.
4828 static int
4829 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4831 struct phy_start_req payload;
4832 struct inbound_queue_table *circularQ;
4833 int ret;
4834 u32 tag = 0x01;
4835 u32 opcode = OPC_INB_PHYSTART;
4836 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4837 memset(&payload, 0, sizeof(payload));
4838 payload.tag = cpu_to_le32(tag);
4840 PM8001_INIT_DBG(pm8001_ha,
4841 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
4843 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4844 LINKMODE_AUTO | pm8001_ha->link_rate | phy_id);
4845 /* SSC Disable and SAS Analog ST configuration */
4847 payload.ase_sh_lm_slr_phyid =
4848 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4849 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4850 phy_id);
4851 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4854 payload.sas_identify.dev_type = SAS_END_DEVICE;
4855 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4856 memcpy(payload.sas_identify.sas_addr,
4857 &pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4858 payload.sas_identify.phy_id = phy_id;
4859 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4860 sizeof(payload), 0);
4861 return ret;
4865 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4866 * @pm8001_ha: our hba card information.
4867 * @num: the inbound queue number
4868 * @phy_id: the phy id which we wanted to start up.
4870 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4871 u8 phy_id)
4873 struct phy_stop_req payload;
4874 struct inbound_queue_table *circularQ;
4875 int ret;
4876 u32 tag = 0x01;
4877 u32 opcode = OPC_INB_PHYSTOP;
4878 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4879 memset(&payload, 0, sizeof(payload));
4880 payload.tag = cpu_to_le32(tag);
4881 payload.phy_id = cpu_to_le32(phy_id);
4882 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4883 sizeof(payload), 0);
4884 return ret;
4888 * see comments on pm8001_mpi_reg_resp.
4890 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4891 struct pm8001_device *pm8001_dev, u32 flag)
4893 struct reg_dev_req payload;
4894 u32 opc;
4895 u32 stp_sspsmp_sata = 0x4;
4896 struct inbound_queue_table *circularQ;
4897 u32 linkrate, phy_id;
4898 int rc, tag = 0xdeadbeef;
4899 struct pm8001_ccb_info *ccb;
4900 u8 retryFlag = 0x1;
4901 u16 firstBurstSize = 0;
4902 u16 ITNT = 2000;
4903 struct domain_device *dev = pm8001_dev->sas_device;
4904 struct domain_device *parent_dev = dev->parent;
4905 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4907 memset(&payload, 0, sizeof(payload));
4908 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4909 if (rc)
4910 return rc;
4911 ccb = &pm8001_ha->ccb_info[tag];
4912 ccb->device = pm8001_dev;
4913 ccb->ccb_tag = tag;
4914 payload.tag = cpu_to_le32(tag);
4916 if (flag == 1) {
4917 stp_sspsmp_sata = 0x02; /*direct attached sata */
4918 } else {
4919 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4920 stp_sspsmp_sata = 0x00; /* stp*/
4921 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4922 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4923 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4924 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4926 if (parent_dev && dev_is_expander(parent_dev->dev_type))
4927 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4928 else
4929 phy_id = pm8001_dev->attached_phy;
4931 opc = OPC_INB_REG_DEV;
4933 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4934 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4936 payload.phyid_portid =
4937 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4938 ((phy_id & 0xFF) << 8));
4940 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4941 ((linkrate & 0x0F) << 24) |
4942 ((stp_sspsmp_sata & 0x03) << 28));
4943 payload.firstburstsize_ITNexustimeout =
4944 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4946 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4947 SAS_ADDR_SIZE);
4949 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4950 sizeof(payload), 0);
4951 if (rc)
4952 pm8001_tag_free(pm8001_ha, tag);
4954 return rc;
4958 * pm80xx_chip_phy_ctl_req - support the local phy operation
4959 * @pm8001_ha: our hba card information.
4960 * @num: the inbound queue number
4961 * @phy_id: the phy id which we wanted to operate
4962 * @phy_op:
4964 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4965 u32 phyId, u32 phy_op)
4967 u32 tag;
4968 int rc;
4969 struct local_phy_ctl_req payload;
4970 struct inbound_queue_table *circularQ;
4971 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4972 memset(&payload, 0, sizeof(payload));
4973 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4974 if (rc)
4975 return rc;
4976 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4977 payload.tag = cpu_to_le32(tag);
4978 payload.phyop_phyid =
4979 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4980 return pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4981 sizeof(payload), 0);
4984 static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4986 #ifdef PM8001_USE_MSIX
4987 return 1;
4988 #else
4989 u32 value;
4991 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4992 if (value)
4993 return 1;
4994 return 0;
4995 #endif
4999 * pm8001_chip_isr - PM8001 isr handler.
5000 * @pm8001_ha: our hba card information.
5001 * @irq: irq number.
5002 * @stat: stat.
5004 static irqreturn_t
5005 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
5007 pm80xx_chip_interrupt_disable(pm8001_ha, vec);
5008 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
5009 "irq vec %d, ODMR:0x%x\n",
5010 vec, pm8001_cr32(pm8001_ha, 0, 0x30)));
5011 process_oq(pm8001_ha, vec);
5012 pm80xx_chip_interrupt_enable(pm8001_ha, vec);
5013 return IRQ_HANDLED;
5016 void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
5017 u32 operation, u32 phyid, u32 length, u32 *buf)
5019 u32 tag , i, j = 0;
5020 int rc;
5021 struct set_phy_profile_req payload;
5022 struct inbound_queue_table *circularQ;
5023 u32 opc = OPC_INB_SET_PHY_PROFILE;
5025 memset(&payload, 0, sizeof(payload));
5026 rc = pm8001_tag_alloc(pm8001_ha, &tag);
5027 if (rc)
5028 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n"));
5029 circularQ = &pm8001_ha->inbnd_q_tbl[0];
5030 payload.tag = cpu_to_le32(tag);
5031 payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF));
5032 PM8001_INIT_DBG(pm8001_ha,
5033 pm8001_printk(" phy profile command for phy %x ,length is %d\n",
5034 payload.ppc_phyid, length));
5035 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
5036 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i));
5037 j++;
5039 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
5040 sizeof(payload), 0);
5041 if (rc)
5042 pm8001_tag_free(pm8001_ha, tag);
5045 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
5046 u32 length, u8 *buf)
5048 u32 i;
5050 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
5051 mpi_set_phy_profile_req(pm8001_ha,
5052 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
5053 length = length + PHY_DWORD_LENGTH;
5055 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n"));
5058 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
5059 u32 phy, u32 length, u32 *buf)
5061 u32 tag, opc;
5062 int rc, i;
5063 struct set_phy_profile_req payload;
5064 struct inbound_queue_table *circularQ;
5066 memset(&payload, 0, sizeof(payload));
5068 rc = pm8001_tag_alloc(pm8001_ha, &tag);
5069 if (rc)
5070 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("Invalid tag"));
5072 circularQ = &pm8001_ha->inbnd_q_tbl[0];
5073 opc = OPC_INB_SET_PHY_PROFILE;
5075 payload.tag = cpu_to_le32(tag);
5076 payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
5077 | (phy & 0xFF));
5079 for (i = 0; i < length; i++)
5080 payload.reserved[i] = cpu_to_le32(*(buf + i));
5082 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
5083 sizeof(payload), 0);
5084 if (rc)
5085 pm8001_tag_free(pm8001_ha, tag);
5087 PM8001_INIT_DBG(pm8001_ha,
5088 pm8001_printk("PHY %d settings applied", phy));
5090 const struct pm8001_dispatch pm8001_80xx_dispatch = {
5091 .name = "pmc80xx",
5092 .chip_init = pm80xx_chip_init,
5093 .chip_soft_rst = pm80xx_chip_soft_rst,
5094 .chip_rst = pm80xx_hw_chip_rst,
5095 .chip_iounmap = pm8001_chip_iounmap,
5096 .isr = pm80xx_chip_isr,
5097 .is_our_interrupt = pm80xx_chip_is_our_interrupt,
5098 .isr_process_oq = process_oq,
5099 .interrupt_enable = pm80xx_chip_interrupt_enable,
5100 .interrupt_disable = pm80xx_chip_interrupt_disable,
5101 .make_prd = pm8001_chip_make_sg,
5102 .smp_req = pm80xx_chip_smp_req,
5103 .ssp_io_req = pm80xx_chip_ssp_io_req,
5104 .sata_req = pm80xx_chip_sata_req,
5105 .phy_start_req = pm80xx_chip_phy_start_req,
5106 .phy_stop_req = pm80xx_chip_phy_stop_req,
5107 .reg_dev_req = pm80xx_chip_reg_dev_req,
5108 .dereg_dev_req = pm8001_chip_dereg_dev_req,
5109 .phy_ctl_req = pm80xx_chip_phy_ctl_req,
5110 .task_abort = pm8001_chip_abort_task,
5111 .ssp_tm_req = pm8001_chip_ssp_tm_req,
5112 .get_nvmd_req = pm8001_chip_get_nvmd_req,
5113 .set_nvmd_req = pm8001_chip_set_nvmd_req,
5114 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
5115 .set_dev_state_req = pm8001_chip_set_dev_state_req,