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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / scsi / qla2xxx / qla_def.h
blob47c7a56438b541cbadc784044d7ea9b6d2991e37
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_DEF_H
8 #define __QLA_DEF_H
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
28 #include <linux/btree.h>
29
30 #include <scsi/scsi.h>
31 #include <scsi/scsi_host.h>
32 #include <scsi/scsi_device.h>
33 #include <scsi/scsi_cmnd.h>
34 #include <scsi/scsi_transport_fc.h>
35 #include <scsi/scsi_bsg_fc.h>
36
37 /* Big endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */
38 typedef struct {
39 uint8_t domain;
40 uint8_t area;
41 uint8_t al_pa;
42 } be_id_t;
43
44 /* Little endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */
45 typedef struct {
46 uint8_t al_pa;
47 uint8_t area;
48 uint8_t domain;
49 } le_id_t;
50
51 #include "qla_bsg.h"
52 #include "qla_dsd.h"
53 #include "qla_nx.h"
54 #include "qla_nx2.h"
55 #include "qla_nvme.h"
56 #define QLA2XXX_DRIVER_NAME "qla2xxx"
57 #define QLA2XXX_APIDEV "ql2xapidev"
58 #define QLA2XXX_MANUFACTURER "QLogic Corporation"
59
60 /*
61 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
62 * but that's fine as we don't look at the last 24 ones for
63 * ISP2100 HBAs.
64 */
65 #define MAILBOX_REGISTER_COUNT_2100 8
66 #define MAILBOX_REGISTER_COUNT_2200 24
67 #define MAILBOX_REGISTER_COUNT 32
68
69 #define QLA2200A_RISC_ROM_VER 4
70 #define FPM_2300 6
71 #define FPM_2310 7
72
73 #include "qla_settings.h"
74
75 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR)
76
77 /*
78 * Data bit definitions
79 */
80 #define BIT_0 0x1
81 #define BIT_1 0x2
82 #define BIT_2 0x4
83 #define BIT_3 0x8
84 #define BIT_4 0x10
85 #define BIT_5 0x20
86 #define BIT_6 0x40
87 #define BIT_7 0x80
88 #define BIT_8 0x100
89 #define BIT_9 0x200
90 #define BIT_10 0x400
91 #define BIT_11 0x800
92 #define BIT_12 0x1000
93 #define BIT_13 0x2000
94 #define BIT_14 0x4000
95 #define BIT_15 0x8000
96 #define BIT_16 0x10000
97 #define BIT_17 0x20000
98 #define BIT_18 0x40000
99 #define BIT_19 0x80000
100 #define BIT_20 0x100000
101 #define BIT_21 0x200000
102 #define BIT_22 0x400000
103 #define BIT_23 0x800000
104 #define BIT_24 0x1000000
105 #define BIT_25 0x2000000
106 #define BIT_26 0x4000000
107 #define BIT_27 0x8000000
108 #define BIT_28 0x10000000
109 #define BIT_29 0x20000000
110 #define BIT_30 0x40000000
111 #define BIT_31 0x80000000
112
113 #define LSB(x) ((uint8_t)(x))
114 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
115
116 #define LSW(x) ((uint16_t)(x))
117 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
118
119 #define LSD(x) ((uint32_t)((uint64_t)(x)))
120 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
121
122 static inline uint32_t make_handle(uint16_t x, uint16_t y)
123 {
124 return ((uint32_t)x << 16) | y;
125 }
126
127 /*
128 * I/O register
129 */
130
131 #define RD_REG_BYTE(addr) readb(addr)
132 #define RD_REG_WORD(addr) readw(addr)
133 #define RD_REG_DWORD(addr) readl(addr)
134 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
135 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
136 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
137 #define WRT_REG_BYTE(addr, data) writeb(data, addr)
138 #define WRT_REG_WORD(addr, data) writew(data, addr)
139 #define WRT_REG_DWORD(addr, data) writel(data, addr)
140
141 /*
142 * ISP83XX specific remote register addresses
143 */
144 #define QLA83XX_LED_PORT0 0x00201320
145 #define QLA83XX_LED_PORT1 0x00201328
146 #define QLA83XX_IDC_DEV_STATE 0x22102384
147 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380
148 #define QLA83XX_IDC_MINOR_VERSION 0x22102398
149 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388
150 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c
151 #define QLA83XX_IDC_CONTROL 0x22102390
152 #define QLA83XX_IDC_AUDIT 0x22102394
153 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
154 #define QLA83XX_DRIVER_LOCKID 0x22102104
155 #define QLA83XX_DRIVER_LOCK 0x8111c028
156 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c
157 #define QLA83XX_FLASH_LOCKID 0x22102100
158 #define QLA83XX_FLASH_LOCK 0x8111c010
159 #define QLA83XX_FLASH_UNLOCK 0x8111c014
160 #define QLA83XX_DEV_PARTINFO1 0x221023e0
161 #define QLA83XX_DEV_PARTINFO2 0x221023e4
162 #define QLA83XX_FW_HEARTBEAT 0x221020b0
163 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8
164 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac
165
166 /* 83XX: Macros defining 8200 AEN Reason codes */
167 #define IDC_DEVICE_STATE_CHANGE BIT_0
168 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
169 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2
170 #define IDC_HEARTBEAT_FAILURE BIT_3
171
172 /* 83XX: Macros defining 8200 AEN Error-levels */
173 #define ERR_LEVEL_NON_FATAL 0x1
174 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2
175 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
176
177 /* 83XX: Macros for IDC Version */
178 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
179 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
180
181 /* 83XX: Macros for scheduling dpc tasks */
182 #define QLA83XX_NIC_CORE_RESET 0x1
183 #define QLA83XX_IDC_STATE_HANDLER 0x2
184 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
185
186 /* 83XX: Macros for defining IDC-Control bits */
187 #define QLA83XX_IDC_RESET_DISABLED BIT_0
188 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
189
190 /* 83XX: Macros for different timeouts */
191 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
192 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
193 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
194
195 /* 83XX: Macros for defining class in DEV-Partition Info register */
196 #define QLA83XX_CLASS_TYPE_NONE 0x0
197 #define QLA83XX_CLASS_TYPE_NIC 0x1
198 #define QLA83XX_CLASS_TYPE_FCOE 0x2
199 #define QLA83XX_CLASS_TYPE_ISCSI 0x3
200
201 /* 83XX: Macros for IDC Lock-Recovery stages */
202 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for
203 * lock-recovery
204 */
205 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */
206
207 /* 83XX: Macros for IDC Audit type */
208 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of
209 * dev-state change to NEED-RESET
210 * or NEED-QUIESCENT
211 */
212 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of
213 * reset-recovery completion is
214 * second
215 */
216 /* ISP2031: Values for laser on/off */
217 #define PORT_0_2031 0x00201340
218 #define PORT_1_2031 0x00201350
219 #define LASER_ON_2031 0x01800100
220 #define LASER_OFF_2031 0x01800180
221
222 /*
223 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
224 * 133Mhz slot.
225 */
226 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
227 #define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr))
228
229 /*
230 * Fibre Channel device definitions.
231 */
232 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
233 #define MAX_FIBRE_DEVICES_2100 512
234 #define MAX_FIBRE_DEVICES_2400 2048
235 #define MAX_FIBRE_DEVICES_LOOP 128
236 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
237 #define LOOPID_MAP_SIZE (ha->max_fibre_devices)
238 #define MAX_FIBRE_LUNS 0xFFFF
239 #define MAX_HOST_COUNT 16
240
241 /*
242 * Host adapter default definitions.
243 */
244 #define MAX_BUSES 1 /* We only have one bus today */
245 #define MIN_LUNS 8
246 #define MAX_LUNS MAX_FIBRE_LUNS
247 #define MAX_CMDS_PER_LUN 255
248
249 /*
250 * Fibre Channel device definitions.
251 */
252 #define SNS_LAST_LOOP_ID_2100 0xfe
253 #define SNS_LAST_LOOP_ID_2300 0x7ff
254
255 #define LAST_LOCAL_LOOP_ID 0x7d
256 #define SNS_FL_PORT 0x7e
257 #define FABRIC_CONTROLLER 0x7f
258 #define SIMPLE_NAME_SERVER 0x80
259 #define SNS_FIRST_LOOP_ID 0x81
260 #define MANAGEMENT_SERVER 0xfe
261 #define BROADCAST 0xff
262
263 /*
264 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
265 * valid range of an N-PORT id is 0 through 0x7ef.
266 */
267 #define NPH_LAST_HANDLE 0x7ee
268 #define NPH_MGMT_SERVER 0x7ef /* FFFFEF */
269 #define NPH_SNS 0x7fc /* FFFFFC */
270 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
271 #define NPH_F_PORT 0x7fe /* FFFFFE */
272 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
273
274 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER)
275
276 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
277 #include "qla_fw.h"
278
279 struct name_list_extended {
280 struct get_name_list_extended *l;
281 dma_addr_t ldma;
282 struct list_head fcports;
283 u32 size;
284 u8 sent;
285 };
286 /*
287 * Timeout timer counts in seconds
288 */
289 #define PORT_RETRY_TIME 1
290 #define LOOP_DOWN_TIMEOUT 60
291 #define LOOP_DOWN_TIME 255 /* 240 */
292 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
293
294 #define DEFAULT_OUTSTANDING_COMMANDS 4096
295 #define MIN_OUTSTANDING_COMMANDS 128
296
297 /* ISP request and response entry counts (37-65535) */
298 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
299 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
300 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
301 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */
302 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/
303 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
304 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
305 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
306 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */
307 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
308 #define FW_DEF_EXCHANGES_CNT 2048
309 #define FW_MAX_EXCHANGES_CNT (32 * 1024)
310 #define REDUCE_EXCHANGES_CNT (8 * 1024)
311
312 struct req_que;
313 struct qla_tgt_sess;
314
315 /*
316 * SCSI Request Block
317 */
318 struct srb_cmd {
319 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
320 uint32_t request_sense_length;
321 uint32_t fw_sense_length;
322 uint8_t *request_sense_ptr;
323 struct ct6_dsd *ct6_ctx;
324 struct crc_context *crc_ctx;
325 };
326
327 /*
328 * SRB flag definitions
329 */
330 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
331 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
332 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
333 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
334 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
335 #define SRB_WAKEUP_ON_COMP BIT_6
336 #define SRB_DIF_BUNDL_DMA_VALID BIT_7 /* DIF: DMA list valid */
337
338 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
339 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
340
341 /*
342 * 24 bit port ID type definition.
343 */
344 typedef union {
345 uint32_t b24 : 24;
346
347 struct {
348 #ifdef __BIG_ENDIAN
349 uint8_t domain;
350 uint8_t area;
351 uint8_t al_pa;
352 #elif defined(__LITTLE_ENDIAN)
353 uint8_t al_pa;
354 uint8_t area;
355 uint8_t domain;
356 #else
357 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
358 #endif
359 uint8_t rsvd_1;
360 } b;
361 } port_id_t;
362 #define INVALID_PORT_ID 0xFFFFFF
363
364 static inline le_id_t be_id_to_le(be_id_t id)
365 {
366 le_id_t res;
367
368 res.domain = id.domain;
369 res.area = id.area;
370 res.al_pa = id.al_pa;
371
372 return res;
373 }
374
375 static inline be_id_t le_id_to_be(le_id_t id)
376 {
377 be_id_t res;
378
379 res.domain = id.domain;
380 res.area = id.area;
381 res.al_pa = id.al_pa;
382
383 return res;
384 }
385
386 static inline port_id_t be_to_port_id(be_id_t id)
387 {
388 port_id_t res;
389
390 res.b.domain = id.domain;
391 res.b.area = id.area;
392 res.b.al_pa = id.al_pa;
393 res.b.rsvd_1 = 0;
394
395 return res;
396 }
397
398 static inline be_id_t port_id_to_be_id(port_id_t port_id)
399 {
400 be_id_t res;
401
402 res.domain = port_id.b.domain;
403 res.area = port_id.b.area;
404 res.al_pa = port_id.b.al_pa;
405
406 return res;
407 }
408
409 struct els_logo_payload {
410 uint8_t opcode;
411 uint8_t rsvd[3];
412 uint8_t s_id[3];
413 uint8_t rsvd1[1];
414 uint8_t wwpn[WWN_SIZE];
415 };
416
417 struct els_plogi_payload {
418 uint8_t opcode;
419 uint8_t rsvd[3];
420 __be32 data[112 / 4];
421 };
422
423 struct ct_arg {
424 void *iocb;
425 u16 nport_handle;
426 dma_addr_t req_dma;
427 dma_addr_t rsp_dma;
428 u32 req_size;
429 u32 rsp_size;
430 u32 req_allocated_size;
431 u32 rsp_allocated_size;
432 void *req;
433 void *rsp;
434 port_id_t id;
435 };
436
437 /*
438 * SRB extensions.
439 */
440 struct srb_iocb {
441 union {
442 struct {
443 uint16_t flags;
444 #define SRB_LOGIN_RETRIED BIT_0
445 #define SRB_LOGIN_COND_PLOGI BIT_1
446 #define SRB_LOGIN_SKIP_PRLI BIT_2
447 #define SRB_LOGIN_NVME_PRLI BIT_3
448 #define SRB_LOGIN_PRLI_ONLY BIT_4
449 uint16_t data[2];
450 u32 iop[2];
451 } logio;
452 struct {
453 #define ELS_DCMD_TIMEOUT 20
454 #define ELS_DCMD_LOGO 0x5
455 uint32_t flags;
456 uint32_t els_cmd;
457 struct completion comp;
458 struct els_logo_payload *els_logo_pyld;
459 dma_addr_t els_logo_pyld_dma;
460 } els_logo;
461 struct els_plogi {
462 #define ELS_DCMD_PLOGI 0x3
463 uint32_t flags;
464 uint32_t els_cmd;
465 struct completion comp;
466 struct els_plogi_payload *els_plogi_pyld;
467 struct els_plogi_payload *els_resp_pyld;
468 u32 tx_size;
469 u32 rx_size;
470 dma_addr_t els_plogi_pyld_dma;
471 dma_addr_t els_resp_pyld_dma;
472 uint32_t fw_status[3];
473 __le16 comp_status;
474 __le16 len;
475 } els_plogi;
476 struct {
477 /*
478 * Values for flags field below are as
479 * defined in tsk_mgmt_entry struct
480 * for control_flags field in qla_fw.h.
481 */
482 uint64_t lun;
483 uint32_t flags;
484 uint32_t data;
485 struct completion comp;
486 __le16 comp_status;
487 } tmf;
488 struct {
489 #define SRB_FXDISC_REQ_DMA_VALID BIT_0
490 #define SRB_FXDISC_RESP_DMA_VALID BIT_1
491 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2
492 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3
493 #define FXDISC_TIMEOUT 20
494 uint8_t flags;
495 uint32_t req_len;
496 uint32_t rsp_len;
497 void *req_addr;
498 void *rsp_addr;
499 dma_addr_t req_dma_handle;
500 dma_addr_t rsp_dma_handle;
501 __le32 adapter_id;
502 __le32 adapter_id_hi;
503 __le16 req_func_type;
504 __le32 req_data;
505 __le32 req_data_extra;
506 __le32 result;
507 __le32 seq_number;
508 __le16 fw_flags;
509 struct completion fxiocb_comp;
510 __le32 reserved_0;
511 uint8_t reserved_1;
512 } fxiocb;
513 struct {
514 uint32_t cmd_hndl;
515 __le16 comp_status;
516 __le16 req_que_no;
517 struct completion comp;
518 } abt;
519 struct ct_arg ctarg;
520 #define MAX_IOCB_MB_REG 28
521 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
522 struct {
523 __le16 in_mb[MAX_IOCB_MB_REG]; /* from FW */
524 __le16 out_mb[MAX_IOCB_MB_REG]; /* to FW */
525 void *out, *in;
526 dma_addr_t out_dma, in_dma;
527 struct completion comp;
528 int rc;
529 } mbx;
530 struct {
531 struct imm_ntfy_from_isp *ntfy;
532 } nack;
533 struct {
534 __le16 comp_status;
535 uint16_t rsp_pyld_len;
536 uint8_t aen_op;
537 void *desc;
538
539 /* These are only used with ls4 requests */
540 int cmd_len;
541 int rsp_len;
542 dma_addr_t cmd_dma;
543 dma_addr_t rsp_dma;
544 enum nvmefc_fcp_datadir dir;
545 uint32_t dl;
546 uint32_t timeout_sec;
547 struct list_head entry;
548 } nvme;
549 struct {
550 u16 cmd;
551 u16 vp_index;
552 } ctrlvp;
553 } u;
554
555 struct timer_list timer;
556 void (*timeout)(void *);
557 };
558
559 /* Values for srb_ctx type */
560 #define SRB_LOGIN_CMD 1
561 #define SRB_LOGOUT_CMD 2
562 #define SRB_ELS_CMD_RPT 3
563 #define SRB_ELS_CMD_HST 4
564 #define SRB_CT_CMD 5
565 #define SRB_ADISC_CMD 6
566 #define SRB_TM_CMD 7
567 #define SRB_SCSI_CMD 8
568 #define SRB_BIDI_CMD 9
569 #define SRB_FXIOCB_DCMD 10
570 #define SRB_FXIOCB_BCMD 11
571 #define SRB_ABT_CMD 12
572 #define SRB_ELS_DCMD 13
573 #define SRB_MB_IOCB 14
574 #define SRB_CT_PTHRU_CMD 15
575 #define SRB_NACK_PLOGI 16
576 #define SRB_NACK_PRLI 17
577 #define SRB_NACK_LOGO 18
578 #define SRB_NVME_CMD 19
579 #define SRB_NVME_LS 20
580 #define SRB_PRLI_CMD 21
581 #define SRB_CTRL_VP 22
582 #define SRB_PRLO_CMD 23
583
584 enum {
585 TYPE_SRB,
586 TYPE_TGT_CMD,
587 TYPE_TGT_TMCMD, /* task management */
588 };
589
590 typedef struct srb {
591 /*
592 * Do not move cmd_type field, it needs to
593 * line up with qla_tgt_cmd->cmd_type
594 */
595 uint8_t cmd_type;
596 uint8_t pad[3];
597 struct kref cmd_kref; /* need to migrate ref_count over to this */
598 void *priv;
599 wait_queue_head_t nvme_ls_waitq;
600 struct fc_port *fcport;
601 struct scsi_qla_host *vha;
602 unsigned int start_timer:1;
603
604 uint32_t handle;
605 uint16_t flags;
606 uint16_t type;
607 const char *name;
608 int iocbs;
609 struct qla_qpair *qpair;
610 struct srb *cmd_sp;
611 struct list_head elem;
612 u32 gen1; /* scratch */
613 u32 gen2; /* scratch */
614 int rc;
615 int retry_count;
616 struct completion *comp;
617 union {
618 struct srb_iocb iocb_cmd;
619 struct bsg_job *bsg_job;
620 struct srb_cmd scmd;
621 } u;
622 /*
623 * Report completion status @res and call sp_put(@sp). @res is
624 * an NVMe status code, a SCSI result (e.g. DID_OK << 16) or a
625 * QLA_* status value.
626 */
627 void (*done)(struct srb *sp, int res);
628 /* Stop the timer and free @sp. Only used by the FCP code. */
629 void (*free)(struct srb *sp);
630 /*
631 * Call nvme_private->fd->done() and free @sp. Only used by the NVMe
632 * code.
633 */
634 void (*put_fn)(struct kref *kref);
635 } srb_t;
636
637 #define GET_CMD_SP(sp) (sp->u.scmd.cmd)
638
639 #define GET_CMD_SENSE_LEN(sp) \
640 (sp->u.scmd.request_sense_length)
641 #define SET_CMD_SENSE_LEN(sp, len) \
642 (sp->u.scmd.request_sense_length = len)
643 #define GET_CMD_SENSE_PTR(sp) \
644 (sp->u.scmd.request_sense_ptr)
645 #define SET_CMD_SENSE_PTR(sp, ptr) \
646 (sp->u.scmd.request_sense_ptr = ptr)
647 #define GET_FW_SENSE_LEN(sp) \
648 (sp->u.scmd.fw_sense_length)
649 #define SET_FW_SENSE_LEN(sp, len) \
650 (sp->u.scmd.fw_sense_length = len)
651
652 struct msg_echo_lb {
653 dma_addr_t send_dma;
654 dma_addr_t rcv_dma;
655 uint16_t req_sg_cnt;
656 uint16_t rsp_sg_cnt;
657 uint16_t options;
658 uint32_t transfer_size;
659 uint32_t iteration_count;
660 };
661
662 /*
663 * ISP I/O Register Set structure definitions.
664 */
665 struct device_reg_2xxx {
666 uint16_t flash_address; /* Flash BIOS address */
667 uint16_t flash_data; /* Flash BIOS data */
668 uint16_t unused_1[1]; /* Gap */
669 uint16_t ctrl_status; /* Control/Status */
670 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
671 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
672 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
673
674 uint16_t ictrl; /* Interrupt control */
675 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
676 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
677
678 uint16_t istatus; /* Interrupt status */
679 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
680
681 uint16_t semaphore; /* Semaphore */
682 uint16_t nvram; /* NVRAM register. */
683 #define NVR_DESELECT 0
684 #define NVR_BUSY BIT_15
685 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
686 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
687 #define NVR_DATA_IN BIT_3
688 #define NVR_DATA_OUT BIT_2
689 #define NVR_SELECT BIT_1
690 #define NVR_CLOCK BIT_0
691
692 #define NVR_WAIT_CNT 20000
693
694 union {
695 struct {
696 uint16_t mailbox0;
697 uint16_t mailbox1;
698 uint16_t mailbox2;
699 uint16_t mailbox3;
700 uint16_t mailbox4;
701 uint16_t mailbox5;
702 uint16_t mailbox6;
703 uint16_t mailbox7;
704 uint16_t unused_2[59]; /* Gap */
705 } __attribute__((packed)) isp2100;
706 struct {
707 /* Request Queue */
708 uint16_t req_q_in; /* In-Pointer */
709 uint16_t req_q_out; /* Out-Pointer */
710 /* Response Queue */
711 uint16_t rsp_q_in; /* In-Pointer */
712 uint16_t rsp_q_out; /* Out-Pointer */
713
714 /* RISC to Host Status */
715 uint32_t host_status;
716 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
717 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
718
719 /* Host to Host Semaphore */
720 uint16_t host_semaphore;
721 uint16_t unused_3[17]; /* Gap */
722 uint16_t mailbox0;
723 uint16_t mailbox1;
724 uint16_t mailbox2;
725 uint16_t mailbox3;
726 uint16_t mailbox4;
727 uint16_t mailbox5;
728 uint16_t mailbox6;
729 uint16_t mailbox7;
730 uint16_t mailbox8;
731 uint16_t mailbox9;
732 uint16_t mailbox10;
733 uint16_t mailbox11;
734 uint16_t mailbox12;
735 uint16_t mailbox13;
736 uint16_t mailbox14;
737 uint16_t mailbox15;
738 uint16_t mailbox16;
739 uint16_t mailbox17;
740 uint16_t mailbox18;
741 uint16_t mailbox19;
742 uint16_t mailbox20;
743 uint16_t mailbox21;
744 uint16_t mailbox22;
745 uint16_t mailbox23;
746 uint16_t mailbox24;
747 uint16_t mailbox25;
748 uint16_t mailbox26;
749 uint16_t mailbox27;
750 uint16_t mailbox28;
751 uint16_t mailbox29;
752 uint16_t mailbox30;
753 uint16_t mailbox31;
754 uint16_t fb_cmd;
755 uint16_t unused_4[10]; /* Gap */
756 } __attribute__((packed)) isp2300;
757 } u;
758
759 uint16_t fpm_diag_config;
760 uint16_t unused_5[0x4]; /* Gap */
761 uint16_t risc_hw;
762 uint16_t unused_5_1; /* Gap */
763 uint16_t pcr; /* Processor Control Register. */
764 uint16_t unused_6[0x5]; /* Gap */
765 uint16_t mctr; /* Memory Configuration and Timing. */
766 uint16_t unused_7[0x3]; /* Gap */
767 uint16_t fb_cmd_2100; /* Unused on 23XX */
768 uint16_t unused_8[0x3]; /* Gap */
769 uint16_t hccr; /* Host command & control register. */
770 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
771 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
772 /* HCCR commands */
773 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
774 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
775 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
776 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
777 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
778 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
779 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
780 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
781
782 uint16_t unused_9[5]; /* Gap */
783 uint16_t gpiod; /* GPIO Data register. */
784 uint16_t gpioe; /* GPIO Enable register. */
785 #define GPIO_LED_MASK 0x00C0
786 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
787 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
788 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
789 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
790 #define GPIO_LED_ALL_OFF 0x0000
791 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
792 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
793
794 union {
795 struct {
796 uint16_t unused_10[8]; /* Gap */
797 uint16_t mailbox8;
798 uint16_t mailbox9;
799 uint16_t mailbox10;
800 uint16_t mailbox11;
801 uint16_t mailbox12;
802 uint16_t mailbox13;
803 uint16_t mailbox14;
804 uint16_t mailbox15;
805 uint16_t mailbox16;
806 uint16_t mailbox17;
807 uint16_t mailbox18;
808 uint16_t mailbox19;
809 uint16_t mailbox20;
810 uint16_t mailbox21;
811 uint16_t mailbox22;
812 uint16_t mailbox23; /* Also probe reg. */
813 } __attribute__((packed)) isp2200;
814 } u_end;
815 };
816
817 struct device_reg_25xxmq {
818 uint32_t req_q_in;
819 uint32_t req_q_out;
820 uint32_t rsp_q_in;
821 uint32_t rsp_q_out;
822 uint32_t atio_q_in;
823 uint32_t atio_q_out;
824 };
825
826
827 struct device_reg_fx00 {
828 uint32_t mailbox0; /* 00 */
829 uint32_t mailbox1; /* 04 */
830 uint32_t mailbox2; /* 08 */
831 uint32_t mailbox3; /* 0C */
832 uint32_t mailbox4; /* 10 */
833 uint32_t mailbox5; /* 14 */
834 uint32_t mailbox6; /* 18 */
835 uint32_t mailbox7; /* 1C */
836 uint32_t mailbox8; /* 20 */
837 uint32_t mailbox9; /* 24 */
838 uint32_t mailbox10; /* 28 */
839 uint32_t mailbox11;
840 uint32_t mailbox12;
841 uint32_t mailbox13;
842 uint32_t mailbox14;
843 uint32_t mailbox15;
844 uint32_t mailbox16;
845 uint32_t mailbox17;
846 uint32_t mailbox18;
847 uint32_t mailbox19;
848 uint32_t mailbox20;
849 uint32_t mailbox21;
850 uint32_t mailbox22;
851 uint32_t mailbox23;
852 uint32_t mailbox24;
853 uint32_t mailbox25;
854 uint32_t mailbox26;
855 uint32_t mailbox27;
856 uint32_t mailbox28;
857 uint32_t mailbox29;
858 uint32_t mailbox30;
859 uint32_t mailbox31;
860 uint32_t aenmailbox0;
861 uint32_t aenmailbox1;
862 uint32_t aenmailbox2;
863 uint32_t aenmailbox3;
864 uint32_t aenmailbox4;
865 uint32_t aenmailbox5;
866 uint32_t aenmailbox6;
867 uint32_t aenmailbox7;
868 /* Request Queue. */
869 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */
870 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */
871 /* Response Queue. */
872 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */
873 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */
874 /* Init values shadowed on FW Up Event */
875 uint32_t initval0; /* B0 */
876 uint32_t initval1; /* B4 */
877 uint32_t initval2; /* B8 */
878 uint32_t initval3; /* BC */
879 uint32_t initval4; /* C0 */
880 uint32_t initval5; /* C4 */
881 uint32_t initval6; /* C8 */
882 uint32_t initval7; /* CC */
883 uint32_t fwheartbeat; /* D0 */
884 uint32_t pseudoaen; /* D4 */
885 };
886
887
888
889 typedef union {
890 struct device_reg_2xxx isp;
891 struct device_reg_24xx isp24;
892 struct device_reg_25xxmq isp25mq;
893 struct device_reg_82xx isp82;
894 struct device_reg_fx00 ispfx00;
895 } __iomem device_reg_t;
896
897 #define ISP_REQ_Q_IN(ha, reg) \
898 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
899 &(reg)->u.isp2100.mailbox4 : \
900 &(reg)->u.isp2300.req_q_in)
901 #define ISP_REQ_Q_OUT(ha, reg) \
902 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
903 &(reg)->u.isp2100.mailbox4 : \
904 &(reg)->u.isp2300.req_q_out)
905 #define ISP_RSP_Q_IN(ha, reg) \
906 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
907 &(reg)->u.isp2100.mailbox5 : \
908 &(reg)->u.isp2300.rsp_q_in)
909 #define ISP_RSP_Q_OUT(ha, reg) \
910 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
911 &(reg)->u.isp2100.mailbox5 : \
912 &(reg)->u.isp2300.rsp_q_out)
913
914 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
915 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
916
917 #define MAILBOX_REG(ha, reg, num) \
918 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
919 (num < 8 ? \
920 &(reg)->u.isp2100.mailbox0 + (num) : \
921 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
922 &(reg)->u.isp2300.mailbox0 + (num))
923 #define RD_MAILBOX_REG(ha, reg, num) \
924 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
925 #define WRT_MAILBOX_REG(ha, reg, num, data) \
926 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
927
928 #define FB_CMD_REG(ha, reg) \
929 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
930 &(reg)->fb_cmd_2100 : \
931 &(reg)->u.isp2300.fb_cmd)
932 #define RD_FB_CMD_REG(ha, reg) \
933 RD_REG_WORD(FB_CMD_REG(ha, reg))
934 #define WRT_FB_CMD_REG(ha, reg, data) \
935 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
936
937 typedef struct {
938 uint32_t out_mb; /* outbound from driver */
939 uint32_t in_mb; /* Incoming from RISC */
940 uint16_t mb[MAILBOX_REGISTER_COUNT];
941 long buf_size;
942 void *bufp;
943 uint32_t tov;
944 uint8_t flags;
945 #define MBX_DMA_IN BIT_0
946 #define MBX_DMA_OUT BIT_1
947 #define IOCTL_CMD BIT_2
948 } mbx_cmd_t;
949
950 struct mbx_cmd_32 {
951 uint32_t out_mb; /* outbound from driver */
952 uint32_t in_mb; /* Incoming from RISC */
953 uint32_t mb[MAILBOX_REGISTER_COUNT];
954 long buf_size;
955 void *bufp;
956 uint32_t tov;
957 uint8_t flags;
958 #define MBX_DMA_IN BIT_0
959 #define MBX_DMA_OUT BIT_1
960 #define IOCTL_CMD BIT_2
961 };
962
963
964 #define MBX_TOV_SECONDS 30
965
966 /*
967 * ISP product identification definitions in mailboxes after reset.
968 */
969 #define PROD_ID_1 0x4953
970 #define PROD_ID_2 0x0000
971 #define PROD_ID_2a 0x5020
972 #define PROD_ID_3 0x2020
973
974 /*
975 * ISP mailbox Self-Test status codes
976 */
977 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
978 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
979 #define MBS_BUSY 4 /* Busy. */
980
981 /*
982 * ISP mailbox command complete status codes
983 */
984 #define MBS_COMMAND_COMPLETE 0x4000
985 #define MBS_INVALID_COMMAND 0x4001
986 #define MBS_HOST_INTERFACE_ERROR 0x4002
987 #define MBS_TEST_FAILED 0x4003
988 #define MBS_COMMAND_ERROR 0x4005
989 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
990 #define MBS_PORT_ID_USED 0x4007
991 #define MBS_LOOP_ID_USED 0x4008
992 #define MBS_ALL_IDS_IN_USE 0x4009
993 #define MBS_NOT_LOGGED_IN 0x400A
994 #define MBS_LINK_DOWN_ERROR 0x400B
995 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
996
997 static inline bool qla2xxx_is_valid_mbs(unsigned int mbs)
998 {
999 return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR;
1000 }
1001
1002 /*
1003 * ISP mailbox asynchronous event status codes
1004 */
1005 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
1006 #define MBA_RESET 0x8001 /* Reset Detected. */
1007 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
1008 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
1009 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
1010 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
1011 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
1012 /* occurred. */
1013 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
1014 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
1015 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
1016 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
1017 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
1018 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
1019 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
1020 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
1021 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
1022 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
1023 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
1024 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
1025 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
1026 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
1027 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
1028 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
1029 /* used. */
1030 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
1031 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
1032 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
1033 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
1034 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
1035 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
1036 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
1037 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
1038 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
1039 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
1040 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
1041 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
1042 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
1043 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
1044 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */
1045 #define MBA_FW_STARTING 0x8051 /* Firmware starting */
1046 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */
1047 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */
1048 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */
1049 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */
1050 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */
1051 #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */
1052 #define MBA_TRANS_REMOVE 0x8131 /* Transceiver Removal */
1053 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */
1054 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change
1055 Notification */
1056 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */
1057 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */
1058 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */
1059 /* 83XX FCoE specific */
1060 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
1061
1062 /* Interrupt type codes */
1063 #define INTR_ROM_MB_SUCCESS 0x1
1064 #define INTR_ROM_MB_FAILED 0x2
1065 #define INTR_MB_SUCCESS 0x10
1066 #define INTR_MB_FAILED 0x11
1067 #define INTR_ASYNC_EVENT 0x12
1068 #define INTR_RSP_QUE_UPDATE 0x13
1069 #define INTR_RSP_QUE_UPDATE_83XX 0x14
1070 #define INTR_ATIO_QUE_UPDATE 0x1C
1071 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D
1072 #define INTR_ATIO_QUE_UPDATE_27XX 0x1E
1073
1074 /* ISP mailbox loopback echo diagnostic error code */
1075 #define MBS_LB_RESET 0x17
1076 /*
1077 * Firmware options 1, 2, 3.
1078 */
1079 #define FO1_AE_ON_LIPF8 BIT_0
1080 #define FO1_AE_ALL_LIP_RESET BIT_1
1081 #define FO1_CTIO_RETRY BIT_3
1082 #define FO1_DISABLE_LIP_F7_SW BIT_4
1083 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
1084 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
1085 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
1086 #define FO1_SET_EMPHASIS_SWING BIT_8
1087 #define FO1_AE_AUTO_BYPASS BIT_9
1088 #define FO1_ENABLE_PURE_IOCB BIT_10
1089 #define FO1_AE_PLOGI_RJT BIT_11
1090 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
1091 #define FO1_AE_QUEUE_FULL BIT_13
1092
1093 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
1094 #define FO2_REV_LOOPBACK BIT_1
1095
1096 #define FO3_ENABLE_EMERG_IOCB BIT_0
1097 #define FO3_AE_RND_ERROR BIT_1
1098
1099 /* 24XX additional firmware options */
1100 #define ADD_FO_COUNT 3
1101 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
1102 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
1103
1104 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
1105
1106 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
1107
1108 /*
1109 * ISP mailbox commands
1110 */
1111 #define MBC_LOAD_RAM 1 /* Load RAM. */
1112 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
1113 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
1114 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
1115 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
1116 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
1117 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
1118 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
1119 #define MBC_SECURE_FLASH_UPDATE 0xa /* Secure Flash Update(28xx) */
1120 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
1121 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
1122 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
1123 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
1124 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
1125 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
1126 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
1127 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
1128 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
1129 #define MBC_RESET 0x18 /* Reset. */
1130 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
1131 #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */
1132 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
1133 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
1134 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
1135 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
1136 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/
1137 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
1138 #define MBC_SET_GET_FC_LED_CONFIG 0x3b /* Set/Get FC LED config */
1139 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
1140 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
1141 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
1142 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
1143 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
1144 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
1145 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
1146 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
1147 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
1148 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
1149 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
1150 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
1151 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
1152 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
1153 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */
1154 #define MBC_DATA_RATE 0x5d /* Data Rate */
1155 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
1156 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
1157 /* Initialization Procedure */
1158 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
1159 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
1160 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
1161 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
1162 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
1163 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
1164 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
1165 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
1166 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
1167 #define MBC_LIP_RESET 0x6c /* LIP reset. */
1168 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
1169 /* commandd. */
1170 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
1171 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
1172 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
1173 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
1174 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
1175 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
1176 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
1177 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
1178 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
1179 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
1180 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
1181
1182 /*
1183 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones
1184 * should be defined with MBC_MR_*
1185 */
1186 #define MBC_MR_DRV_SHUTDOWN 0x6A
1187
1188 /*
1189 * ISP24xx mailbox commands
1190 */
1191 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */
1192 #define MBC_READ_SERDES 0x4 /* Read serdes word. */
1193 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */
1194 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
1195 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
1196 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
1197 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
1198 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
1199 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
1200 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
1201 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
1202 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
1203 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */
1204 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
1205 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
1206 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
1207 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
1208 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
1209 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
1210 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */
1211 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
1212 #define MBC_PORT_RESET 0x120 /* Port Reset */
1213 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
1214 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
1215
1216 /*
1217 * ISP81xx mailbox commands
1218 */
1219 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
1220
1221 /*
1222 * ISP8044 mailbox commands
1223 */
1224 #define MBC_SET_GET_ETH_SERDES_REG 0x150
1225 #define HCS_WRITE_SERDES 0x3
1226 #define HCS_READ_SERDES 0x4
1227
1228 /* Firmware return data sizes */
1229 #define FCAL_MAP_SIZE 128
1230
1231 /* Mailbox bit definitions for out_mb and in_mb */
1232 #define MBX_31 BIT_31
1233 #define MBX_30 BIT_30
1234 #define MBX_29 BIT_29
1235 #define MBX_28 BIT_28
1236 #define MBX_27 BIT_27
1237 #define MBX_26 BIT_26
1238 #define MBX_25 BIT_25
1239 #define MBX_24 BIT_24
1240 #define MBX_23 BIT_23
1241 #define MBX_22 BIT_22
1242 #define MBX_21 BIT_21
1243 #define MBX_20 BIT_20
1244 #define MBX_19 BIT_19
1245 #define MBX_18 BIT_18
1246 #define MBX_17 BIT_17
1247 #define MBX_16 BIT_16
1248 #define MBX_15 BIT_15
1249 #define MBX_14 BIT_14
1250 #define MBX_13 BIT_13
1251 #define MBX_12 BIT_12
1252 #define MBX_11 BIT_11
1253 #define MBX_10 BIT_10
1254 #define MBX_9 BIT_9
1255 #define MBX_8 BIT_8
1256 #define MBX_7 BIT_7
1257 #define MBX_6 BIT_6
1258 #define MBX_5 BIT_5
1259 #define MBX_4 BIT_4
1260 #define MBX_3 BIT_3
1261 #define MBX_2 BIT_2
1262 #define MBX_1 BIT_1
1263 #define MBX_0 BIT_0
1264
1265 #define RNID_TYPE_ELS_CMD 0x5
1266 #define RNID_TYPE_PORT_LOGIN 0x7
1267 #define RNID_BUFFER_CREDITS 0x8
1268 #define RNID_TYPE_SET_VERSION 0x9
1269 #define RNID_TYPE_ASIC_TEMP 0xC
1270
1271 #define ELS_CMD_MAP_SIZE 32
1272 #define ELS_COMMAND_RDP 0x18
1273
1274 /*
1275 * Firmware state codes from get firmware state mailbox command
1276 */
1277 #define FSTATE_CONFIG_WAIT 0
1278 #define FSTATE_WAIT_AL_PA 1
1279 #define FSTATE_WAIT_LOGIN 2
1280 #define FSTATE_READY 3
1281 #define FSTATE_LOSS_OF_SYNC 4
1282 #define FSTATE_ERROR 5
1283 #define FSTATE_REINIT 6
1284 #define FSTATE_NON_PART 7
1285
1286 #define FSTATE_CONFIG_CORRECT 0
1287 #define FSTATE_P2P_RCV_LIP 1
1288 #define FSTATE_P2P_CHOOSE_LOOP 2
1289 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
1290 #define FSTATE_FATAL_ERROR 4
1291 #define FSTATE_LOOP_BACK_CONN 5
1292
1293 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
1294 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00
1295 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
1296 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1297 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1298 #define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED
1299 #define QLA27XX_DEFAULT_IMAGE 0
1300 #define QLA27XX_PRIMARY_IMAGE 1
1301 #define QLA27XX_SECONDARY_IMAGE 2
1302
1303 /*
1304 * Port Database structure definition
1305 * Little endian except where noted.
1306 */
1307 #define PORT_DATABASE_SIZE 128 /* bytes */
1308 typedef struct {
1309 uint8_t options;
1310 uint8_t control;
1311 uint8_t master_state;
1312 uint8_t slave_state;
1313 uint8_t reserved[2];
1314 uint8_t hard_address;
1315 uint8_t reserved_1;
1316 uint8_t port_id[4];
1317 uint8_t node_name[WWN_SIZE];
1318 uint8_t port_name[WWN_SIZE];
1319 uint16_t execution_throttle;
1320 uint16_t execution_count;
1321 uint8_t reset_count;
1322 uint8_t reserved_2;
1323 uint16_t resource_allocation;
1324 uint16_t current_allocation;
1325 uint16_t queue_head;
1326 uint16_t queue_tail;
1327 uint16_t transmit_execution_list_next;
1328 uint16_t transmit_execution_list_previous;
1329 uint16_t common_features;
1330 uint16_t total_concurrent_sequences;
1331 uint16_t RO_by_information_category;
1332 uint8_t recipient;
1333 uint8_t initiator;
1334 uint16_t receive_data_size;
1335 uint16_t concurrent_sequences;
1336 uint16_t open_sequences_per_exchange;
1337 uint16_t lun_abort_flags;
1338 uint16_t lun_stop_flags;
1339 uint16_t stop_queue_head;
1340 uint16_t stop_queue_tail;
1341 uint16_t port_retry_timer;
1342 uint16_t next_sequence_id;
1343 uint16_t frame_count;
1344 uint16_t PRLI_payload_length;
1345 uint8_t prli_svc_param_word_0[2]; /* Big endian */
1346 /* Bits 15-0 of word 0 */
1347 uint8_t prli_svc_param_word_3[2]; /* Big endian */
1348 /* Bits 15-0 of word 3 */
1349 uint16_t loop_id;
1350 uint16_t extended_lun_info_list_pointer;
1351 uint16_t extended_lun_stop_list_pointer;
1352 } port_database_t;
1353
1354 /*
1355 * Port database slave/master states
1356 */
1357 #define PD_STATE_DISCOVERY 0
1358 #define PD_STATE_WAIT_DISCOVERY_ACK 1
1359 #define PD_STATE_PORT_LOGIN 2
1360 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1361 #define PD_STATE_PROCESS_LOGIN 4
1362 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1363 #define PD_STATE_PORT_LOGGED_IN 6
1364 #define PD_STATE_PORT_UNAVAILABLE 7
1365 #define PD_STATE_PROCESS_LOGOUT 8
1366 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1367 #define PD_STATE_PORT_LOGOUT 10
1368 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1369
1370
1371 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1372 #define QLA_ZIO_DISABLED 0
1373 #define QLA_ZIO_DEFAULT_TIMER 2
1374
1375 /*
1376 * ISP Initialization Control Block.
1377 * Little endian except where noted.
1378 */
1379 #define ICB_VERSION 1
1380 typedef struct {
1381 uint8_t version;
1382 uint8_t reserved_1;
1383
1384 /*
1385 * LSB BIT 0 = Enable Hard Loop Id
1386 * LSB BIT 1 = Enable Fairness
1387 * LSB BIT 2 = Enable Full-Duplex
1388 * LSB BIT 3 = Enable Fast Posting
1389 * LSB BIT 4 = Enable Target Mode
1390 * LSB BIT 5 = Disable Initiator Mode
1391 * LSB BIT 6 = Enable ADISC
1392 * LSB BIT 7 = Enable Target Inquiry Data
1393 *
1394 * MSB BIT 0 = Enable PDBC Notify
1395 * MSB BIT 1 = Non Participating LIP
1396 * MSB BIT 2 = Descending Loop ID Search
1397 * MSB BIT 3 = Acquire Loop ID in LIPA
1398 * MSB BIT 4 = Stop PortQ on Full Status
1399 * MSB BIT 5 = Full Login after LIP
1400 * MSB BIT 6 = Node Name Option
1401 * MSB BIT 7 = Ext IFWCB enable bit
1402 */
1403 uint8_t firmware_options[2];
1404
1405 uint16_t frame_payload_size;
1406 uint16_t max_iocb_allocation;
1407 uint16_t execution_throttle;
1408 uint8_t retry_count;
1409 uint8_t retry_delay; /* unused */
1410 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1411 uint16_t hard_address;
1412 uint8_t inquiry_data;
1413 uint8_t login_timeout;
1414 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1415
1416 uint16_t request_q_outpointer;
1417 uint16_t response_q_inpointer;
1418 uint16_t request_q_length;
1419 uint16_t response_q_length;
1420 __le64 request_q_address __packed;
1421 __le64 response_q_address __packed;
1422
1423 uint16_t lun_enables;
1424 uint8_t command_resource_count;
1425 uint8_t immediate_notify_resource_count;
1426 uint16_t timeout;
1427 uint8_t reserved_2[2];
1428
1429 /*
1430 * LSB BIT 0 = Timer Operation mode bit 0
1431 * LSB BIT 1 = Timer Operation mode bit 1
1432 * LSB BIT 2 = Timer Operation mode bit 2
1433 * LSB BIT 3 = Timer Operation mode bit 3
1434 * LSB BIT 4 = Init Config Mode bit 0
1435 * LSB BIT 5 = Init Config Mode bit 1
1436 * LSB BIT 6 = Init Config Mode bit 2
1437 * LSB BIT 7 = Enable Non part on LIHA failure
1438 *
1439 * MSB BIT 0 = Enable class 2
1440 * MSB BIT 1 = Enable ACK0
1441 * MSB BIT 2 =
1442 * MSB BIT 3 =
1443 * MSB BIT 4 = FC Tape Enable
1444 * MSB BIT 5 = Enable FC Confirm
1445 * MSB BIT 6 = Enable command queuing in target mode
1446 * MSB BIT 7 = No Logo On Link Down
1447 */
1448 uint8_t add_firmware_options[2];
1449
1450 uint8_t response_accumulation_timer;
1451 uint8_t interrupt_delay_timer;
1452
1453 /*
1454 * LSB BIT 0 = Enable Read xfr_rdy
1455 * LSB BIT 1 = Soft ID only
1456 * LSB BIT 2 =
1457 * LSB BIT 3 =
1458 * LSB BIT 4 = FCP RSP Payload [0]
1459 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1460 * LSB BIT 6 = Enable Out-of-Order frame handling
1461 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1462 *
1463 * MSB BIT 0 = Sbus enable - 2300
1464 * MSB BIT 1 =
1465 * MSB BIT 2 =
1466 * MSB BIT 3 =
1467 * MSB BIT 4 = LED mode
1468 * MSB BIT 5 = enable 50 ohm termination
1469 * MSB BIT 6 = Data Rate (2300 only)
1470 * MSB BIT 7 = Data Rate (2300 only)
1471 */
1472 uint8_t special_options[2];
1473
1474 uint8_t reserved_3[26];
1475 } init_cb_t;
1476
1477 /*
1478 * Get Link Status mailbox command return buffer.
1479 */
1480 #define GLSO_SEND_RPS BIT_0
1481 #define GLSO_USE_DID BIT_3
1482
1483 struct link_statistics {
1484 __le32 link_fail_cnt;
1485 __le32 loss_sync_cnt;
1486 __le32 loss_sig_cnt;
1487 __le32 prim_seq_err_cnt;
1488 __le32 inval_xmit_word_cnt;
1489 __le32 inval_crc_cnt;
1490 __le32 lip_cnt;
1491 __le32 link_up_cnt;
1492 __le32 link_down_loop_init_tmo;
1493 __le32 link_down_los;
1494 __le32 link_down_loss_rcv_clk;
1495 uint32_t reserved0[5];
1496 __le32 port_cfg_chg;
1497 uint32_t reserved1[11];
1498 __le32 rsp_q_full;
1499 __le32 atio_q_full;
1500 __le32 drop_ae;
1501 __le32 els_proto_err;
1502 __le32 reserved2;
1503 __le32 tx_frames;
1504 __le32 rx_frames;
1505 __le32 discarded_frames;
1506 __le32 dropped_frames;
1507 uint32_t reserved3;
1508 __le32 nos_rcvd;
1509 uint32_t reserved4[4];
1510 __le32 tx_prjt;
1511 __le32 rcv_exfail;
1512 __le32 rcv_abts;
1513 __le32 seq_frm_miss;
1514 __le32 corr_err;
1515 __le32 mb_rqst;
1516 __le32 nport_full;
1517 __le32 eofa;
1518 uint32_t reserved5;
1519 __le64 fpm_recv_word_cnt;
1520 __le64 fpm_disc_word_cnt;
1521 __le64 fpm_xmit_word_cnt;
1522 uint32_t reserved6[70];
1523 };
1524
1525 /*
1526 * NVRAM Command values.
1527 */
1528 #define NV_START_BIT BIT_2
1529 #define NV_WRITE_OP (BIT_26+BIT_24)
1530 #define NV_READ_OP (BIT_26+BIT_25)
1531 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1532 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1533 #define NV_DELAY_COUNT 10
1534
1535 /*
1536 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
1537 */
1538 typedef struct {
1539 /*
1540 * NVRAM header
1541 */
1542 uint8_t id[4];
1543 uint8_t nvram_version;
1544 uint8_t reserved_0;
1545
1546 /*
1547 * NVRAM RISC parameter block
1548 */
1549 uint8_t parameter_block_version;
1550 uint8_t reserved_1;
1551
1552 /*
1553 * LSB BIT 0 = Enable Hard Loop Id
1554 * LSB BIT 1 = Enable Fairness
1555 * LSB BIT 2 = Enable Full-Duplex
1556 * LSB BIT 3 = Enable Fast Posting
1557 * LSB BIT 4 = Enable Target Mode
1558 * LSB BIT 5 = Disable Initiator Mode
1559 * LSB BIT 6 = Enable ADISC
1560 * LSB BIT 7 = Enable Target Inquiry Data
1561 *
1562 * MSB BIT 0 = Enable PDBC Notify
1563 * MSB BIT 1 = Non Participating LIP
1564 * MSB BIT 2 = Descending Loop ID Search
1565 * MSB BIT 3 = Acquire Loop ID in LIPA
1566 * MSB BIT 4 = Stop PortQ on Full Status
1567 * MSB BIT 5 = Full Login after LIP
1568 * MSB BIT 6 = Node Name Option
1569 * MSB BIT 7 = Ext IFWCB enable bit
1570 */
1571 uint8_t firmware_options[2];
1572
1573 uint16_t frame_payload_size;
1574 uint16_t max_iocb_allocation;
1575 uint16_t execution_throttle;
1576 uint8_t retry_count;
1577 uint8_t retry_delay; /* unused */
1578 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1579 uint16_t hard_address;
1580 uint8_t inquiry_data;
1581 uint8_t login_timeout;
1582 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1583
1584 /*
1585 * LSB BIT 0 = Timer Operation mode bit 0
1586 * LSB BIT 1 = Timer Operation mode bit 1
1587 * LSB BIT 2 = Timer Operation mode bit 2
1588 * LSB BIT 3 = Timer Operation mode bit 3
1589 * LSB BIT 4 = Init Config Mode bit 0
1590 * LSB BIT 5 = Init Config Mode bit 1
1591 * LSB BIT 6 = Init Config Mode bit 2
1592 * LSB BIT 7 = Enable Non part on LIHA failure
1593 *
1594 * MSB BIT 0 = Enable class 2
1595 * MSB BIT 1 = Enable ACK0
1596 * MSB BIT 2 =
1597 * MSB BIT 3 =
1598 * MSB BIT 4 = FC Tape Enable
1599 * MSB BIT 5 = Enable FC Confirm
1600 * MSB BIT 6 = Enable command queuing in target mode
1601 * MSB BIT 7 = No Logo On Link Down
1602 */
1603 uint8_t add_firmware_options[2];
1604
1605 uint8_t response_accumulation_timer;
1606 uint8_t interrupt_delay_timer;
1607
1608 /*
1609 * LSB BIT 0 = Enable Read xfr_rdy
1610 * LSB BIT 1 = Soft ID only
1611 * LSB BIT 2 =
1612 * LSB BIT 3 =
1613 * LSB BIT 4 = FCP RSP Payload [0]
1614 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1615 * LSB BIT 6 = Enable Out-of-Order frame handling
1616 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1617 *
1618 * MSB BIT 0 = Sbus enable - 2300
1619 * MSB BIT 1 =
1620 * MSB BIT 2 =
1621 * MSB BIT 3 =
1622 * MSB BIT 4 = LED mode
1623 * MSB BIT 5 = enable 50 ohm termination
1624 * MSB BIT 6 = Data Rate (2300 only)
1625 * MSB BIT 7 = Data Rate (2300 only)
1626 */
1627 uint8_t special_options[2];
1628
1629 /* Reserved for expanded RISC parameter block */
1630 uint8_t reserved_2[22];
1631
1632 /*
1633 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1634 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1635 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1636 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1637 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1638 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1639 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1640 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1641 *
1642 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1643 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1644 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1645 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1646 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1647 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1648 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1649 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1650 *
1651 * LSB BIT 0 = Output Swing 1G bit 0
1652 * LSB BIT 1 = Output Swing 1G bit 1
1653 * LSB BIT 2 = Output Swing 1G bit 2
1654 * LSB BIT 3 = Output Emphasis 1G bit 0
1655 * LSB BIT 4 = Output Emphasis 1G bit 1
1656 * LSB BIT 5 = Output Swing 2G bit 0
1657 * LSB BIT 6 = Output Swing 2G bit 1
1658 * LSB BIT 7 = Output Swing 2G bit 2
1659 *
1660 * MSB BIT 0 = Output Emphasis 2G bit 0
1661 * MSB BIT 1 = Output Emphasis 2G bit 1
1662 * MSB BIT 2 = Output Enable
1663 * MSB BIT 3 =
1664 * MSB BIT 4 =
1665 * MSB BIT 5 =
1666 * MSB BIT 6 =
1667 * MSB BIT 7 =
1668 */
1669 uint8_t seriallink_options[4];
1670
1671 /*
1672 * NVRAM host parameter block
1673 *
1674 * LSB BIT 0 = Enable spinup delay
1675 * LSB BIT 1 = Disable BIOS
1676 * LSB BIT 2 = Enable Memory Map BIOS
1677 * LSB BIT 3 = Enable Selectable Boot
1678 * LSB BIT 4 = Disable RISC code load
1679 * LSB BIT 5 = Set cache line size 1
1680 * LSB BIT 6 = PCI Parity Disable
1681 * LSB BIT 7 = Enable extended logging
1682 *
1683 * MSB BIT 0 = Enable 64bit addressing
1684 * MSB BIT 1 = Enable lip reset
1685 * MSB BIT 2 = Enable lip full login
1686 * MSB BIT 3 = Enable target reset
1687 * MSB BIT 4 = Enable database storage
1688 * MSB BIT 5 = Enable cache flush read
1689 * MSB BIT 6 = Enable database load
1690 * MSB BIT 7 = Enable alternate WWN
1691 */
1692 uint8_t host_p[2];
1693
1694 uint8_t boot_node_name[WWN_SIZE];
1695 uint8_t boot_lun_number;
1696 uint8_t reset_delay;
1697 uint8_t port_down_retry_count;
1698 uint8_t boot_id_number;
1699 uint16_t max_luns_per_target;
1700 uint8_t fcode_boot_port_name[WWN_SIZE];
1701 uint8_t alternate_port_name[WWN_SIZE];
1702 uint8_t alternate_node_name[WWN_SIZE];
1703
1704 /*
1705 * BIT 0 = Selective Login
1706 * BIT 1 = Alt-Boot Enable
1707 * BIT 2 =
1708 * BIT 3 = Boot Order List
1709 * BIT 4 =
1710 * BIT 5 = Selective LUN
1711 * BIT 6 =
1712 * BIT 7 = unused
1713 */
1714 uint8_t efi_parameters;
1715
1716 uint8_t link_down_timeout;
1717
1718 uint8_t adapter_id[16];
1719
1720 uint8_t alt1_boot_node_name[WWN_SIZE];
1721 uint16_t alt1_boot_lun_number;
1722 uint8_t alt2_boot_node_name[WWN_SIZE];
1723 uint16_t alt2_boot_lun_number;
1724 uint8_t alt3_boot_node_name[WWN_SIZE];
1725 uint16_t alt3_boot_lun_number;
1726 uint8_t alt4_boot_node_name[WWN_SIZE];
1727 uint16_t alt4_boot_lun_number;
1728 uint8_t alt5_boot_node_name[WWN_SIZE];
1729 uint16_t alt5_boot_lun_number;
1730 uint8_t alt6_boot_node_name[WWN_SIZE];
1731 uint16_t alt6_boot_lun_number;
1732 uint8_t alt7_boot_node_name[WWN_SIZE];
1733 uint16_t alt7_boot_lun_number;
1734
1735 uint8_t reserved_3[2];
1736
1737 /* Offset 200-215 : Model Number */
1738 uint8_t model_number[16];
1739
1740 /* OEM related items */
1741 uint8_t oem_specific[16];
1742
1743 /*
1744 * NVRAM Adapter Features offset 232-239
1745 *
1746 * LSB BIT 0 = External GBIC
1747 * LSB BIT 1 = Risc RAM parity
1748 * LSB BIT 2 = Buffer Plus Module
1749 * LSB BIT 3 = Multi Chip Adapter
1750 * LSB BIT 4 = Internal connector
1751 * LSB BIT 5 =
1752 * LSB BIT 6 =
1753 * LSB BIT 7 =
1754 *
1755 * MSB BIT 0 =
1756 * MSB BIT 1 =
1757 * MSB BIT 2 =
1758 * MSB BIT 3 =
1759 * MSB BIT 4 =
1760 * MSB BIT 5 =
1761 * MSB BIT 6 =
1762 * MSB BIT 7 =
1763 */
1764 uint8_t adapter_features[2];
1765
1766 uint8_t reserved_4[16];
1767
1768 /* Subsystem vendor ID for ISP2200 */
1769 uint16_t subsystem_vendor_id_2200;
1770
1771 /* Subsystem device ID for ISP2200 */
1772 uint16_t subsystem_device_id_2200;
1773
1774 uint8_t reserved_5;
1775 uint8_t checksum;
1776 } nvram_t;
1777
1778 /*
1779 * ISP queue - response queue entry definition.
1780 */
1781 typedef struct {
1782 uint8_t entry_type; /* Entry type. */
1783 uint8_t entry_count; /* Entry count. */
1784 uint8_t sys_define; /* System defined. */
1785 uint8_t entry_status; /* Entry Status. */
1786 uint32_t handle; /* System defined handle */
1787 uint8_t data[52];
1788 uint32_t signature;
1789 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1790 } response_t;
1791
1792 /*
1793 * ISP queue - ATIO queue entry definition.
1794 */
1795 struct atio {
1796 uint8_t entry_type; /* Entry type. */
1797 uint8_t entry_count; /* Entry count. */
1798 __le16 attr_n_length;
1799 uint8_t data[56];
1800 uint32_t signature;
1801 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */
1802 };
1803
1804 typedef union {
1805 uint16_t extended;
1806 struct {
1807 uint8_t reserved;
1808 uint8_t standard;
1809 } id;
1810 } target_id_t;
1811
1812 #define SET_TARGET_ID(ha, to, from) \
1813 do { \
1814 if (HAS_EXTENDED_IDS(ha)) \
1815 to.extended = cpu_to_le16(from); \
1816 else \
1817 to.id.standard = (uint8_t)from; \
1818 } while (0)
1819
1820 /*
1821 * ISP queue - command entry structure definition.
1822 */
1823 #define COMMAND_TYPE 0x11 /* Command entry */
1824 typedef struct {
1825 uint8_t entry_type; /* Entry type. */
1826 uint8_t entry_count; /* Entry count. */
1827 uint8_t sys_define; /* System defined. */
1828 uint8_t entry_status; /* Entry Status. */
1829 uint32_t handle; /* System handle. */
1830 target_id_t target; /* SCSI ID */
1831 uint16_t lun; /* SCSI LUN */
1832 uint16_t control_flags; /* Control flags. */
1833 #define CF_WRITE BIT_6
1834 #define CF_READ BIT_5
1835 #define CF_SIMPLE_TAG BIT_3
1836 #define CF_ORDERED_TAG BIT_2
1837 #define CF_HEAD_TAG BIT_1
1838 uint16_t reserved_1;
1839 uint16_t timeout; /* Command timeout. */
1840 uint16_t dseg_count; /* Data segment count. */
1841 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1842 uint32_t byte_count; /* Total byte count. */
1843 union {
1844 struct dsd32 dsd32[3];
1845 struct dsd64 dsd64[2];
1846 };
1847 } cmd_entry_t;
1848
1849 /*
1850 * ISP queue - 64-Bit addressing, command entry structure definition.
1851 */
1852 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1853 typedef struct {
1854 uint8_t entry_type; /* Entry type. */
1855 uint8_t entry_count; /* Entry count. */
1856 uint8_t sys_define; /* System defined. */
1857 uint8_t entry_status; /* Entry Status. */
1858 uint32_t handle; /* System handle. */
1859 target_id_t target; /* SCSI ID */
1860 uint16_t lun; /* SCSI LUN */
1861 uint16_t control_flags; /* Control flags. */
1862 uint16_t reserved_1;
1863 uint16_t timeout; /* Command timeout. */
1864 uint16_t dseg_count; /* Data segment count. */
1865 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1866 uint32_t byte_count; /* Total byte count. */
1867 struct dsd64 dsd[2];
1868 } cmd_a64_entry_t, request_t;
1869
1870 /*
1871 * ISP queue - continuation entry structure definition.
1872 */
1873 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1874 typedef struct {
1875 uint8_t entry_type; /* Entry type. */
1876 uint8_t entry_count; /* Entry count. */
1877 uint8_t sys_define; /* System defined. */
1878 uint8_t entry_status; /* Entry Status. */
1879 uint32_t reserved;
1880 struct dsd32 dsd[7];
1881 } cont_entry_t;
1882
1883 /*
1884 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1885 */
1886 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1887 typedef struct {
1888 uint8_t entry_type; /* Entry type. */
1889 uint8_t entry_count; /* Entry count. */
1890 uint8_t sys_define; /* System defined. */
1891 uint8_t entry_status; /* Entry Status. */
1892 struct dsd64 dsd[5];
1893 } cont_a64_entry_t;
1894
1895 #define PO_MODE_DIF_INSERT 0
1896 #define PO_MODE_DIF_REMOVE 1
1897 #define PO_MODE_DIF_PASS 2
1898 #define PO_MODE_DIF_REPLACE 3
1899 #define PO_MODE_DIF_TCP_CKSUM 6
1900 #define PO_ENABLE_INCR_GUARD_SEED BIT_3
1901 #define PO_DISABLE_GUARD_CHECK BIT_4
1902 #define PO_DISABLE_INCR_REF_TAG BIT_5
1903 #define PO_DIS_HEADER_MODE BIT_7
1904 #define PO_ENABLE_DIF_BUNDLING BIT_8
1905 #define PO_DIS_FRAME_MODE BIT_9
1906 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */
1907 #define PO_DIS_VALD_APP_REF_ESC BIT_11
1908
1909 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */
1910 #define PO_DIS_REF_TAG_REPL BIT_13
1911 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */
1912 #define PO_DIS_REF_TAG_VALD BIT_15
1913
1914 /*
1915 * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
1916 */
1917 struct crc_context {
1918 uint32_t handle; /* System handle. */
1919 __le32 ref_tag;
1920 __le16 app_tag;
1921 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
1922 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
1923 __le16 guard_seed; /* Initial Guard Seed */
1924 __le16 prot_opts; /* Requested Data Protection Mode */
1925 __le16 blk_size; /* Data size in bytes */
1926 uint16_t runt_blk_guard; /* Guard value for runt block (tape
1927 * only) */
1928 __le32 byte_count; /* Total byte count/ total data
1929 * transfer count */
1930 union {
1931 struct {
1932 uint32_t reserved_1;
1933 uint16_t reserved_2;
1934 uint16_t reserved_3;
1935 uint32_t reserved_4;
1936 struct dsd64 data_dsd[1];
1937 uint32_t reserved_5[2];
1938 uint32_t reserved_6;
1939 } nobundling;
1940 struct {
1941 __le32 dif_byte_count; /* Total DIF byte
1942 * count */
1943 uint16_t reserved_1;
1944 __le16 dseg_count; /* Data segment count */
1945 uint32_t reserved_2;
1946 struct dsd64 data_dsd[1];
1947 struct dsd64 dif_dsd;
1948 } bundling;
1949 } u;
1950
1951 struct fcp_cmnd fcp_cmnd;
1952 dma_addr_t crc_ctx_dma;
1953 /* List of DMA context transfers */
1954 struct list_head dsd_list;
1955
1956 /* List of DIF Bundling context DMA address */
1957 struct list_head ldif_dsd_list;
1958 u8 no_ldif_dsd;
1959
1960 struct list_head ldif_dma_hndl_list;
1961 u32 dif_bundl_len;
1962 u8 no_dif_bundl;
1963 /* This structure should not exceed 512 bytes */
1964 };
1965
1966 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1967 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1968
1969 /*
1970 * ISP queue - status entry structure definition.
1971 */
1972 #define STATUS_TYPE 0x03 /* Status entry. */
1973 typedef struct {
1974 uint8_t entry_type; /* Entry type. */
1975 uint8_t entry_count; /* Entry count. */
1976 uint8_t sys_define; /* System defined. */
1977 uint8_t entry_status; /* Entry Status. */
1978 uint32_t handle; /* System handle. */
1979 uint16_t scsi_status; /* SCSI status. */
1980 uint16_t comp_status; /* Completion status. */
1981 uint16_t state_flags; /* State flags. */
1982 uint16_t status_flags; /* Status flags. */
1983 uint16_t rsp_info_len; /* Response Info Length. */
1984 uint16_t req_sense_length; /* Request sense data length. */
1985 uint32_t residual_length; /* Residual transfer length. */
1986 uint8_t rsp_info[8]; /* FCP response information. */
1987 uint8_t req_sense_data[32]; /* Request sense data. */
1988 } sts_entry_t;
1989
1990 /*
1991 * Status entry entry status
1992 */
1993 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1994 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1995 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1996 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1997 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1998 #define RF_BUSY BIT_1 /* Busy */
1999 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
2000 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
2001 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
2002 RF_INV_E_TYPE)
2003
2004 /*
2005 * Status entry SCSI status bit definitions.
2006 */
2007 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
2008 #define SS_RESIDUAL_UNDER BIT_11
2009 #define SS_RESIDUAL_OVER BIT_10
2010 #define SS_SENSE_LEN_VALID BIT_9
2011 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
2012 #define SS_SCSI_STATUS_BYTE 0xff
2013
2014 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
2015 #define SS_BUSY_CONDITION BIT_3
2016 #define SS_CONDITION_MET BIT_2
2017 #define SS_CHECK_CONDITION BIT_1
2018
2019 /*
2020 * Status entry completion status
2021 */
2022 #define CS_COMPLETE 0x0 /* No errors */
2023 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
2024 #define CS_DMA 0x2 /* A DMA direction error. */
2025 #define CS_TRANSPORT 0x3 /* Transport error. */
2026 #define CS_RESET 0x4 /* SCSI bus reset occurred */
2027 #define CS_ABORTED 0x5 /* System aborted command. */
2028 #define CS_TIMEOUT 0x6 /* Timeout error. */
2029 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
2030 #define CS_DIF_ERROR 0xC /* DIF error detected */
2031
2032 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
2033 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
2034 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
2035 /* (selection timeout) */
2036 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
2037 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
2038 #define CS_PORT_BUSY 0x2B /* Port Busy */
2039 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
2040 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request
2041 failure */
2042 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
2043 #define CS_UNKNOWN 0x81 /* Driver defined */
2044 #define CS_RETRY 0x82 /* Driver defined */
2045 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
2046
2047 #define CS_BIDIR_RD_OVERRUN 0x700
2048 #define CS_BIDIR_RD_WR_OVERRUN 0x707
2049 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
2050 #define CS_BIDIR_RD_UNDERRUN 0x1500
2051 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
2052 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515
2053 #define CS_BIDIR_DMA 0x200
2054 /*
2055 * Status entry status flags
2056 */
2057 #define SF_ABTS_TERMINATED BIT_10
2058 #define SF_LOGOUT_SENT BIT_13
2059
2060 /*
2061 * ISP queue - status continuation entry structure definition.
2062 */
2063 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
2064 typedef struct {
2065 uint8_t entry_type; /* Entry type. */
2066 uint8_t entry_count; /* Entry count. */
2067 uint8_t sys_define; /* System defined. */
2068 uint8_t entry_status; /* Entry Status. */
2069 uint8_t data[60]; /* data */
2070 } sts_cont_entry_t;
2071
2072 /*
2073 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
2074 * structure definition.
2075 */
2076 #define STATUS_TYPE_21 0x21 /* Status entry. */
2077 typedef struct {
2078 uint8_t entry_type; /* Entry type. */
2079 uint8_t entry_count; /* Entry count. */
2080 uint8_t handle_count; /* Handle count. */
2081 uint8_t entry_status; /* Entry Status. */
2082 uint32_t handle[15]; /* System handles. */
2083 } sts21_entry_t;
2084
2085 /*
2086 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
2087 * structure definition.
2088 */
2089 #define STATUS_TYPE_22 0x22 /* Status entry. */
2090 typedef struct {
2091 uint8_t entry_type; /* Entry type. */
2092 uint8_t entry_count; /* Entry count. */
2093 uint8_t handle_count; /* Handle count. */
2094 uint8_t entry_status; /* Entry Status. */
2095 uint16_t handle[30]; /* System handles. */
2096 } sts22_entry_t;
2097
2098 /*
2099 * ISP queue - marker entry structure definition.
2100 */
2101 #define MARKER_TYPE 0x04 /* Marker entry. */
2102 typedef struct {
2103 uint8_t entry_type; /* Entry type. */
2104 uint8_t entry_count; /* Entry count. */
2105 uint8_t handle_count; /* Handle count. */
2106 uint8_t entry_status; /* Entry Status. */
2107 uint32_t sys_define_2; /* System defined. */
2108 target_id_t target; /* SCSI ID */
2109 uint8_t modifier; /* Modifier (7-0). */
2110 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
2111 #define MK_SYNC_ID 1 /* Synchronize ID */
2112 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
2113 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
2114 /* clear port changed, */
2115 /* use sequence number. */
2116 uint8_t reserved_1;
2117 uint16_t sequence_number; /* Sequence number of event */
2118 uint16_t lun; /* SCSI LUN */
2119 uint8_t reserved_2[48];
2120 } mrk_entry_t;
2121
2122 /*
2123 * ISP queue - Management Server entry structure definition.
2124 */
2125 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
2126 typedef struct {
2127 uint8_t entry_type; /* Entry type. */
2128 uint8_t entry_count; /* Entry count. */
2129 uint8_t handle_count; /* Handle count. */
2130 uint8_t entry_status; /* Entry Status. */
2131 uint32_t handle1; /* System handle. */
2132 target_id_t loop_id;
2133 uint16_t status;
2134 uint16_t control_flags; /* Control flags. */
2135 uint16_t reserved2;
2136 uint16_t timeout;
2137 uint16_t cmd_dsd_count;
2138 uint16_t total_dsd_count;
2139 uint8_t type;
2140 uint8_t r_ctl;
2141 uint16_t rx_id;
2142 uint16_t reserved3;
2143 uint32_t handle2;
2144 uint32_t rsp_bytecount;
2145 uint32_t req_bytecount;
2146 struct dsd64 req_dsd;
2147 struct dsd64 rsp_dsd;
2148 } ms_iocb_entry_t;
2149
2150
2151 /*
2152 * ISP queue - Mailbox Command entry structure definition.
2153 */
2154 #define MBX_IOCB_TYPE 0x39
2155 struct mbx_entry {
2156 uint8_t entry_type;
2157 uint8_t entry_count;
2158 uint8_t sys_define1;
2159 /* Use sys_define1 for source type */
2160 #define SOURCE_SCSI 0x00
2161 #define SOURCE_IP 0x01
2162 #define SOURCE_VI 0x02
2163 #define SOURCE_SCTP 0x03
2164 #define SOURCE_MP 0x04
2165 #define SOURCE_MPIOCTL 0x05
2166 #define SOURCE_ASYNC_IOCB 0x07
2167
2168 uint8_t entry_status;
2169
2170 uint32_t handle;
2171 target_id_t loop_id;
2172
2173 uint16_t status;
2174 uint16_t state_flags;
2175 uint16_t status_flags;
2176
2177 uint32_t sys_define2[2];
2178
2179 uint16_t mb0;
2180 uint16_t mb1;
2181 uint16_t mb2;
2182 uint16_t mb3;
2183 uint16_t mb6;
2184 uint16_t mb7;
2185 uint16_t mb9;
2186 uint16_t mb10;
2187 uint32_t reserved_2[2];
2188 uint8_t node_name[WWN_SIZE];
2189 uint8_t port_name[WWN_SIZE];
2190 };
2191
2192 #ifndef IMMED_NOTIFY_TYPE
2193 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */
2194 /*
2195 * ISP queue - immediate notify entry structure definition.
2196 * This is sent by the ISP to the Target driver.
2197 * This IOCB would have report of events sent by the
2198 * initiator, that needs to be handled by the target
2199 * driver immediately.
2200 */
2201 struct imm_ntfy_from_isp {
2202 uint8_t entry_type; /* Entry type. */
2203 uint8_t entry_count; /* Entry count. */
2204 uint8_t sys_define; /* System defined. */
2205 uint8_t entry_status; /* Entry Status. */
2206 union {
2207 struct {
2208 uint32_t sys_define_2; /* System defined. */
2209 target_id_t target;
2210 uint16_t lun;
2211 uint8_t target_id;
2212 uint8_t reserved_1;
2213 uint16_t status_modifier;
2214 uint16_t status;
2215 uint16_t task_flags;
2216 uint16_t seq_id;
2217 uint16_t srr_rx_id;
2218 uint32_t srr_rel_offs;
2219 uint16_t srr_ui;
2220 #define SRR_IU_DATA_IN 0x1
2221 #define SRR_IU_DATA_OUT 0x5
2222 #define SRR_IU_STATUS 0x7
2223 uint16_t srr_ox_id;
2224 uint8_t reserved_2[28];
2225 } isp2x;
2226 struct {
2227 uint32_t reserved;
2228 uint16_t nport_handle;
2229 uint16_t reserved_2;
2230 uint16_t flags;
2231 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
2232 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0
2233 uint16_t srr_rx_id;
2234 uint16_t status;
2235 uint8_t status_subcode;
2236 uint8_t fw_handle;
2237 uint32_t exchange_address;
2238 uint32_t srr_rel_offs;
2239 uint16_t srr_ui;
2240 uint16_t srr_ox_id;
2241 union {
2242 struct {
2243 uint8_t node_name[8];
2244 } plogi; /* PLOGI/ADISC/PDISC */
2245 struct {
2246 /* PRLI word 3 bit 0-15 */
2247 uint16_t wd3_lo;
2248 uint8_t resv0[6];
2249 } prli;
2250 struct {
2251 uint8_t port_id[3];
2252 uint8_t resv1;
2253 uint16_t nport_handle;
2254 uint16_t resv2;
2255 } req_els;
2256 } u;
2257 uint8_t port_name[8];
2258 uint8_t resv3[3];
2259 uint8_t vp_index;
2260 uint32_t reserved_5;
2261 uint8_t port_id[3];
2262 uint8_t reserved_6;
2263 } isp24;
2264 } u;
2265 uint16_t reserved_7;
2266 uint16_t ox_id;
2267 } __packed;
2268 #endif
2269
2270 /*
2271 * ISP request and response queue entry sizes
2272 */
2273 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
2274 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
2275
2276
2277
2278 /*
2279 * Switch info gathering structure.
2280 */
2281 typedef struct {
2282 port_id_t d_id;
2283 uint8_t node_name[WWN_SIZE];
2284 uint8_t port_name[WWN_SIZE];
2285 uint8_t fabric_port_name[WWN_SIZE];
2286 uint16_t fp_speed;
2287 uint8_t fc4_type;
2288 uint8_t fc4_features;
2289 } sw_info_t;
2290
2291 /* FCP-4 types */
2292 #define FC4_TYPE_FCP_SCSI 0x08
2293 #define FC4_TYPE_NVME 0x28
2294 #define FC4_TYPE_OTHER 0x0
2295 #define FC4_TYPE_UNKNOWN 0xff
2296
2297 /* mailbox command 4G & above */
2298 struct mbx_24xx_entry {
2299 uint8_t entry_type;
2300 uint8_t entry_count;
2301 uint8_t sys_define1;
2302 uint8_t entry_status;
2303 uint32_t handle;
2304 uint16_t mb[28];
2305 };
2306
2307 #define IOCB_SIZE 64
2308
2309 /*
2310 * Fibre channel port type.
2311 */
2312 typedef enum {
2313 FCT_UNKNOWN,
2314 FCT_RSCN,
2315 FCT_SWITCH,
2316 FCT_BROADCAST,
2317 FCT_INITIATOR,
2318 FCT_TARGET,
2319 FCT_NVME_INITIATOR = 0x10,
2320 FCT_NVME_TARGET = 0x20,
2321 FCT_NVME_DISCOVERY = 0x40,
2322 FCT_NVME = 0xf0,
2323 } fc_port_type_t;
2324
2325 enum qla_sess_deletion {
2326 QLA_SESS_DELETION_NONE = 0,
2327 QLA_SESS_DELETION_IN_PROGRESS,
2328 QLA_SESS_DELETED,
2329 };
2330
2331 enum qlt_plogi_link_t {
2332 QLT_PLOGI_LINK_SAME_WWN,
2333 QLT_PLOGI_LINK_CONFLICT,
2334 QLT_PLOGI_LINK_MAX
2335 };
2336
2337 struct qlt_plogi_ack_t {
2338 struct list_head list;
2339 struct imm_ntfy_from_isp iocb;
2340 port_id_t id;
2341 int ref_count;
2342 void *fcport;
2343 };
2344
2345 struct ct_sns_desc {
2346 struct ct_sns_pkt *ct_sns;
2347 dma_addr_t ct_sns_dma;
2348 };
2349
2350 enum discovery_state {
2351 DSC_DELETED,
2352 DSC_GNN_ID,
2353 DSC_GNL,
2354 DSC_LOGIN_PEND,
2355 DSC_LOGIN_FAILED,
2356 DSC_GPDB,
2357 DSC_UPD_FCPORT,
2358 DSC_LOGIN_COMPLETE,
2359 DSC_ADISC,
2360 DSC_DELETE_PEND,
2361 };
2362
2363 enum login_state { /* FW control Target side */
2364 DSC_LS_LLIOCB_SENT = 2,
2365 DSC_LS_PLOGI_PEND,
2366 DSC_LS_PLOGI_COMP,
2367 DSC_LS_PRLI_PEND,
2368 DSC_LS_PRLI_COMP,
2369 DSC_LS_PORT_UNAVAIL,
2370 DSC_LS_PRLO_PEND = 9,
2371 DSC_LS_LOGO_PEND,
2372 };
2373
2374 enum rscn_addr_format {
2375 RSCN_PORT_ADDR,
2376 RSCN_AREA_ADDR,
2377 RSCN_DOM_ADDR,
2378 RSCN_FAB_ADDR,
2379 };
2380
2381 /*
2382 * Fibre channel port structure.
2383 */
2384 typedef struct fc_port {
2385 struct list_head list;
2386 struct scsi_qla_host *vha;
2387
2388 uint8_t node_name[WWN_SIZE];
2389 uint8_t port_name[WWN_SIZE];
2390 port_id_t d_id;
2391 uint16_t loop_id;
2392 uint16_t old_loop_id;
2393
2394 unsigned int conf_compl_supported:1;
2395 unsigned int deleted:2;
2396 unsigned int free_pending:1;
2397 unsigned int local:1;
2398 unsigned int logout_on_delete:1;
2399 unsigned int logo_ack_needed:1;
2400 unsigned int keep_nport_handle:1;
2401 unsigned int send_els_logo:1;
2402 unsigned int login_pause:1;
2403 unsigned int login_succ:1;
2404 unsigned int query:1;
2405 unsigned int id_changed:1;
2406 unsigned int scan_needed:1;
2407 unsigned int n2n_flag:1;
2408 unsigned int explicit_logout:1;
2409 unsigned int prli_pend_timer:1;
2410
2411 struct completion nvme_del_done;
2412 uint32_t nvme_prli_service_param;
2413 #define NVME_PRLI_SP_CONF BIT_7
2414 #define NVME_PRLI_SP_INITIATOR BIT_5
2415 #define NVME_PRLI_SP_TARGET BIT_4
2416 #define NVME_PRLI_SP_DISCOVERY BIT_3
2417 #define NVME_PRLI_SP_FIRST_BURST BIT_0
2418 uint8_t nvme_flag;
2419 uint32_t nvme_first_burst_size;
2420 #define NVME_FLAG_REGISTERED 4
2421 #define NVME_FLAG_DELETING 2
2422 #define NVME_FLAG_RESETTING 1
2423
2424 struct fc_port *conflict;
2425 unsigned char logout_completed;
2426 int generation;
2427
2428 struct se_session *se_sess;
2429 struct kref sess_kref;
2430 struct qla_tgt *tgt;
2431 unsigned long expires;
2432 struct list_head del_list_entry;
2433 struct work_struct free_work;
2434 struct work_struct reg_work;
2435 uint64_t jiffies_at_registration;
2436 unsigned long prli_expired;
2437 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX];
2438
2439 uint16_t tgt_id;
2440 uint16_t old_tgt_id;
2441 uint16_t sec_since_registration;
2442
2443 uint8_t fcp_prio;
2444
2445 uint8_t fabric_port_name[WWN_SIZE];
2446 uint16_t fp_speed;
2447
2448 fc_port_type_t port_type;
2449
2450 atomic_t state;
2451 uint32_t flags;
2452
2453 int login_retry;
2454
2455 struct fc_rport *rport, *drport;
2456 u32 supported_classes;
2457
2458 uint8_t fc4_type;
2459 uint8_t fc4_features;
2460 uint8_t scan_state;
2461
2462 unsigned long last_queue_full;
2463 unsigned long last_ramp_up;
2464
2465 uint16_t port_id;
2466
2467 struct nvme_fc_remote_port *nvme_remote_port;
2468
2469 unsigned long retry_delay_timestamp;
2470 struct qla_tgt_sess *tgt_session;
2471 struct ct_sns_desc ct_desc;
2472 enum discovery_state disc_state;
2473 atomic_t shadow_disc_state;
2474 enum discovery_state next_disc_state;
2475 enum login_state fw_login_state;
2476 unsigned long dm_login_expire;
2477 unsigned long plogi_nack_done_deadline;
2478
2479 u32 login_gen, last_login_gen;
2480 u32 rscn_gen, last_rscn_gen;
2481 u32 chip_reset;
2482 struct list_head gnl_entry;
2483 struct work_struct del_work;
2484 u8 iocb[IOCB_SIZE];
2485 u8 current_login_state;
2486 u8 last_login_state;
2487 u16 n2n_link_reset_cnt;
2488 u16 n2n_chip_reset;
2489 } fc_port_t;
2490
2491 enum {
2492 FC4_PRIORITY_NVME = 1,
2493 FC4_PRIORITY_FCP = 2,
2494 };
2495
2496 #define QLA_FCPORT_SCAN 1
2497 #define QLA_FCPORT_FOUND 2
2498
2499 struct event_arg {
2500 fc_port_t *fcport;
2501 srb_t *sp;
2502 port_id_t id;
2503 u16 data[2], rc;
2504 u8 port_name[WWN_SIZE];
2505 u32 iop[2];
2506 };
2507
2508 #include "qla_mr.h"
2509
2510 /*
2511 * Fibre channel port/lun states.
2512 */
2513 #define FCS_UNCONFIGURED 1
2514 #define FCS_DEVICE_DEAD 2
2515 #define FCS_DEVICE_LOST 3
2516 #define FCS_ONLINE 4
2517
2518 extern const char *const port_state_str[5];
2519
2520 static const char * const port_dstate_str[] = {
2521 "DELETED",
2522 "GNN_ID",
2523 "GNL",
2524 "LOGIN_PEND",
2525 "LOGIN_FAILED",
2526 "GPDB",
2527 "UPD_FCPORT",
2528 "LOGIN_COMPLETE",
2529 "ADISC",
2530 "DELETE_PEND"
2531 };
2532
2533 /*
2534 * FC port flags.
2535 */
2536 #define FCF_FABRIC_DEVICE BIT_0
2537 #define FCF_LOGIN_NEEDED BIT_1
2538 #define FCF_FCP2_DEVICE BIT_2
2539 #define FCF_ASYNC_SENT BIT_3
2540 #define FCF_CONF_COMP_SUPPORTED BIT_4
2541 #define FCF_ASYNC_ACTIVE BIT_5
2542
2543 /* No loop ID flag. */
2544 #define FC_NO_LOOP_ID 0x1000
2545
2546 /*
2547 * FC-CT interface
2548 *
2549 * NOTE: All structures are big-endian in form.
2550 */
2551
2552 #define CT_REJECT_RESPONSE 0x8001
2553 #define CT_ACCEPT_RESPONSE 0x8002
2554 #define CT_REASON_INVALID_COMMAND_CODE 0x01
2555 #define CT_REASON_CANNOT_PERFORM 0x09
2556 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
2557 #define CT_EXPL_ALREADY_REGISTERED 0x10
2558 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
2559 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
2560 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
2561 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
2562 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
2563 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
2564 #define CT_EXPL_HBA_NOT_REGISTERED 0x17
2565 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
2566 #define CT_EXPL_PORT_NOT_REGISTERED 0x21
2567 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
2568 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
2569
2570 #define NS_N_PORT_TYPE 0x01
2571 #define NS_NL_PORT_TYPE 0x02
2572 #define NS_NX_PORT_TYPE 0x7F
2573
2574 #define GA_NXT_CMD 0x100
2575 #define GA_NXT_REQ_SIZE (16 + 4)
2576 #define GA_NXT_RSP_SIZE (16 + 620)
2577
2578 #define GPN_FT_CMD 0x172
2579 #define GPN_FT_REQ_SIZE (16 + 4)
2580 #define GNN_FT_CMD 0x173
2581 #define GNN_FT_REQ_SIZE (16 + 4)
2582
2583 #define GID_PT_CMD 0x1A1
2584 #define GID_PT_REQ_SIZE (16 + 4)
2585
2586 #define GPN_ID_CMD 0x112
2587 #define GPN_ID_REQ_SIZE (16 + 4)
2588 #define GPN_ID_RSP_SIZE (16 + 8)
2589
2590 #define GNN_ID_CMD 0x113
2591 #define GNN_ID_REQ_SIZE (16 + 4)
2592 #define GNN_ID_RSP_SIZE (16 + 8)
2593
2594 #define GFT_ID_CMD 0x117
2595 #define GFT_ID_REQ_SIZE (16 + 4)
2596 #define GFT_ID_RSP_SIZE (16 + 32)
2597
2598 #define GID_PN_CMD 0x121
2599 #define GID_PN_REQ_SIZE (16 + 8)
2600 #define GID_PN_RSP_SIZE (16 + 4)
2601
2602 #define RFT_ID_CMD 0x217
2603 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
2604 #define RFT_ID_RSP_SIZE 16
2605
2606 #define RFF_ID_CMD 0x21F
2607 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2608 #define RFF_ID_RSP_SIZE 16
2609
2610 #define RNN_ID_CMD 0x213
2611 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
2612 #define RNN_ID_RSP_SIZE 16
2613
2614 #define RSNN_NN_CMD 0x239
2615 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2616 #define RSNN_NN_RSP_SIZE 16
2617
2618 #define GFPN_ID_CMD 0x11C
2619 #define GFPN_ID_REQ_SIZE (16 + 4)
2620 #define GFPN_ID_RSP_SIZE (16 + 8)
2621
2622 #define GPSC_CMD 0x127
2623 #define GPSC_REQ_SIZE (16 + 8)
2624 #define GPSC_RSP_SIZE (16 + 2 + 2)
2625
2626 #define GFF_ID_CMD 0x011F
2627 #define GFF_ID_REQ_SIZE (16 + 4)
2628 #define GFF_ID_RSP_SIZE (16 + 128)
2629
2630 /*
2631 * FDMI HBA attribute types.
2632 */
2633 #define FDMI1_HBA_ATTR_COUNT 9
2634 #define FDMI2_HBA_ATTR_COUNT 17
2635
2636 #define FDMI_HBA_NODE_NAME 0x1
2637 #define FDMI_HBA_MANUFACTURER 0x2
2638 #define FDMI_HBA_SERIAL_NUMBER 0x3
2639 #define FDMI_HBA_MODEL 0x4
2640 #define FDMI_HBA_MODEL_DESCRIPTION 0x5
2641 #define FDMI_HBA_HARDWARE_VERSION 0x6
2642 #define FDMI_HBA_DRIVER_VERSION 0x7
2643 #define FDMI_HBA_OPTION_ROM_VERSION 0x8
2644 #define FDMI_HBA_FIRMWARE_VERSION 0x9
2645 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2646 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
2647
2648 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
2649 #define FDMI_HBA_VENDOR_SPECIFIC_INFO 0xd
2650 #define FDMI_HBA_NUM_PORTS 0xe
2651 #define FDMI_HBA_FABRIC_NAME 0xf
2652 #define FDMI_HBA_BOOT_BIOS_NAME 0x10
2653 #define FDMI_HBA_VENDOR_IDENTIFIER 0xe0
2654
2655 struct ct_fdmi_hba_attr {
2656 uint16_t type;
2657 uint16_t len;
2658 union {
2659 uint8_t node_name[WWN_SIZE];
2660 uint8_t manufacturer[64];
2661 uint8_t serial_num[32];
2662 uint8_t model[16+1];
2663 uint8_t model_desc[80];
2664 uint8_t hw_version[32];
2665 uint8_t driver_version[32];
2666 uint8_t orom_version[16];
2667 uint8_t fw_version[32];
2668 uint8_t os_version[128];
2669 uint32_t max_ct_len;
2670
2671 uint8_t sym_name[256];
2672 uint32_t vendor_specific_info;
2673 uint32_t num_ports;
2674 uint8_t fabric_name[WWN_SIZE];
2675 uint8_t bios_name[32];
2676 uint8_t vendor_identifier[8];
2677 } a;
2678 };
2679
2680 struct ct_fdmi1_hba_attributes {
2681 uint32_t count;
2682 struct ct_fdmi_hba_attr entry[FDMI1_HBA_ATTR_COUNT];
2683 };
2684
2685 struct ct_fdmi2_hba_attributes {
2686 uint32_t count;
2687 struct ct_fdmi_hba_attr entry[FDMI2_HBA_ATTR_COUNT];
2688 };
2689
2690 /*
2691 * FDMI Port attribute types.
2692 */
2693 #define FDMI1_PORT_ATTR_COUNT 6
2694 #define FDMI2_PORT_ATTR_COUNT 16
2695 #define FDMI2_SMARTSAN_PORT_ATTR_COUNT 23
2696
2697 #define FDMI_PORT_FC4_TYPES 0x1
2698 #define FDMI_PORT_SUPPORT_SPEED 0x2
2699 #define FDMI_PORT_CURRENT_SPEED 0x3
2700 #define FDMI_PORT_MAX_FRAME_SIZE 0x4
2701 #define FDMI_PORT_OS_DEVICE_NAME 0x5
2702 #define FDMI_PORT_HOST_NAME 0x6
2703
2704 #define FDMI_PORT_NODE_NAME 0x7
2705 #define FDMI_PORT_NAME 0x8
2706 #define FDMI_PORT_SYM_NAME 0x9
2707 #define FDMI_PORT_TYPE 0xa
2708 #define FDMI_PORT_SUPP_COS 0xb
2709 #define FDMI_PORT_FABRIC_NAME 0xc
2710 #define FDMI_PORT_FC4_TYPE 0xd
2711 #define FDMI_PORT_STATE 0x101
2712 #define FDMI_PORT_COUNT 0x102
2713 #define FDMI_PORT_IDENTIFIER 0x103
2714
2715 #define FDMI_SMARTSAN_SERVICE 0xF100
2716 #define FDMI_SMARTSAN_GUID 0xF101
2717 #define FDMI_SMARTSAN_VERSION 0xF102
2718 #define FDMI_SMARTSAN_PROD_NAME 0xF103
2719 #define FDMI_SMARTSAN_PORT_INFO 0xF104
2720 #define FDMI_SMARTSAN_QOS_SUPPORT 0xF105
2721 #define FDMI_SMARTSAN_SECURITY_SUPPORT 0xF106
2722
2723 #define FDMI_PORT_SPEED_1GB 0x1
2724 #define FDMI_PORT_SPEED_2GB 0x2
2725 #define FDMI_PORT_SPEED_10GB 0x4
2726 #define FDMI_PORT_SPEED_4GB 0x8
2727 #define FDMI_PORT_SPEED_8GB 0x10
2728 #define FDMI_PORT_SPEED_16GB 0x20
2729 #define FDMI_PORT_SPEED_32GB 0x40
2730 #define FDMI_PORT_SPEED_64GB 0x80
2731 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
2732
2733 #define FC_CLASS_2 0x04
2734 #define FC_CLASS_3 0x08
2735 #define FC_CLASS_2_3 0x0C
2736
2737 struct ct_fdmi_port_attr {
2738 uint16_t type;
2739 uint16_t len;
2740 union {
2741 uint8_t fc4_types[32];
2742 uint32_t sup_speed;
2743 uint32_t cur_speed;
2744 uint32_t max_frame_size;
2745 uint8_t os_dev_name[32];
2746 uint8_t host_name[256];
2747
2748 uint8_t node_name[WWN_SIZE];
2749 uint8_t port_name[WWN_SIZE];
2750 uint8_t port_sym_name[128];
2751 uint32_t port_type;
2752 uint32_t port_supported_cos;
2753 uint8_t fabric_name[WWN_SIZE];
2754 uint8_t port_fc4_type[32];
2755 uint32_t port_state;
2756 uint32_t num_ports;
2757 uint32_t port_id;
2758
2759 uint8_t smartsan_service[24];
2760 uint8_t smartsan_guid[16];
2761 uint8_t smartsan_version[24];
2762 uint8_t smartsan_prod_name[16];
2763 uint32_t smartsan_port_info;
2764 uint32_t smartsan_qos_support;
2765 uint32_t smartsan_security_support;
2766 } a;
2767 };
2768
2769 struct ct_fdmi1_port_attributes {
2770 uint32_t count;
2771 struct ct_fdmi_port_attr entry[FDMI1_PORT_ATTR_COUNT];
2772 };
2773
2774 struct ct_fdmi2_port_attributes {
2775 uint32_t count;
2776 struct ct_fdmi_port_attr entry[FDMI2_PORT_ATTR_COUNT];
2777 };
2778
2779 #define FDMI_ATTR_TYPELEN(obj) \
2780 (sizeof((obj)->type) + sizeof((obj)->len))
2781
2782 #define FDMI_ATTR_ALIGNMENT(len) \
2783 (4 - ((len) & 3))
2784
2785 /* FDMI register call options */
2786 #define CALLOPT_FDMI1 0
2787 #define CALLOPT_FDMI2 1
2788 #define CALLOPT_FDMI2_SMARTSAN 2
2789
2790 /* FDMI definitions. */
2791 #define GRHL_CMD 0x100
2792 #define GHAT_CMD 0x101
2793 #define GRPL_CMD 0x102
2794 #define GPAT_CMD 0x110
2795
2796 #define RHBA_CMD 0x200
2797 #define RHBA_RSP_SIZE 16
2798
2799 #define RHAT_CMD 0x201
2800
2801 #define RPRT_CMD 0x210
2802 #define RPRT_RSP_SIZE 24
2803
2804 #define RPA_CMD 0x211
2805 #define RPA_RSP_SIZE 16
2806 #define SMARTSAN_RPA_RSP_SIZE 24
2807
2808 #define DHBA_CMD 0x300
2809 #define DHBA_REQ_SIZE (16 + 8)
2810 #define DHBA_RSP_SIZE 16
2811
2812 #define DHAT_CMD 0x301
2813 #define DPRT_CMD 0x310
2814 #define DPA_CMD 0x311
2815
2816 /* CT command header -- request/response common fields */
2817 struct ct_cmd_hdr {
2818 uint8_t revision;
2819 uint8_t in_id[3];
2820 uint8_t gs_type;
2821 uint8_t gs_subtype;
2822 uint8_t options;
2823 uint8_t reserved;
2824 };
2825
2826 /* CT command request */
2827 struct ct_sns_req {
2828 struct ct_cmd_hdr header;
2829 uint16_t command;
2830 uint16_t max_rsp_size;
2831 uint8_t fragment_id;
2832 uint8_t reserved[3];
2833
2834 union {
2835 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
2836 struct {
2837 uint8_t reserved;
2838 be_id_t port_id;
2839 } port_id;
2840
2841 struct {
2842 uint8_t reserved;
2843 uint8_t domain;
2844 uint8_t area;
2845 uint8_t port_type;
2846 } gpn_ft;
2847
2848 struct {
2849 uint8_t port_type;
2850 uint8_t domain;
2851 uint8_t area;
2852 uint8_t reserved;
2853 } gid_pt;
2854
2855 struct {
2856 uint8_t reserved;
2857 be_id_t port_id;
2858 uint8_t fc4_types[32];
2859 } rft_id;
2860
2861 struct {
2862 uint8_t reserved;
2863 be_id_t port_id;
2864 uint16_t reserved2;
2865 uint8_t fc4_feature;
2866 uint8_t fc4_type;
2867 } rff_id;
2868
2869 struct {
2870 uint8_t reserved;
2871 be_id_t port_id;
2872 uint8_t node_name[8];
2873 } rnn_id;
2874
2875 struct {
2876 uint8_t node_name[8];
2877 uint8_t name_len;
2878 uint8_t sym_node_name[255];
2879 } rsnn_nn;
2880
2881 struct {
2882 uint8_t hba_identifier[8];
2883 } ghat;
2884
2885 struct {
2886 uint8_t hba_identifier[8];
2887 uint32_t entry_count;
2888 uint8_t port_name[8];
2889 struct ct_fdmi2_hba_attributes attrs;
2890 } rhba;
2891
2892 struct {
2893 uint8_t hba_identifier[8];
2894 struct ct_fdmi1_hba_attributes attrs;
2895 } rhat;
2896
2897 struct {
2898 uint8_t port_name[8];
2899 struct ct_fdmi2_port_attributes attrs;
2900 } rpa;
2901
2902 struct {
2903 uint8_t hba_identifier[8];
2904 uint8_t port_name[8];
2905 struct ct_fdmi2_port_attributes attrs;
2906 } rprt;
2907
2908 struct {
2909 uint8_t port_name[8];
2910 } dhba;
2911
2912 struct {
2913 uint8_t port_name[8];
2914 } dhat;
2915
2916 struct {
2917 uint8_t port_name[8];
2918 } dprt;
2919
2920 struct {
2921 uint8_t port_name[8];
2922 } dpa;
2923
2924 struct {
2925 uint8_t port_name[8];
2926 } gpsc;
2927
2928 struct {
2929 uint8_t reserved;
2930 uint8_t port_id[3];
2931 } gff_id;
2932
2933 struct {
2934 uint8_t port_name[8];
2935 } gid_pn;
2936 } req;
2937 };
2938
2939 /* CT command response header */
2940 struct ct_rsp_hdr {
2941 struct ct_cmd_hdr header;
2942 uint16_t response;
2943 uint16_t residual;
2944 uint8_t fragment_id;
2945 uint8_t reason_code;
2946 uint8_t explanation_code;
2947 uint8_t vendor_unique;
2948 };
2949
2950 struct ct_sns_gid_pt_data {
2951 uint8_t control_byte;
2952 be_id_t port_id;
2953 };
2954
2955 /* It's the same for both GPN_FT and GNN_FT */
2956 struct ct_sns_gpnft_rsp {
2957 struct {
2958 struct ct_cmd_hdr header;
2959 uint16_t response;
2960 uint16_t residual;
2961 uint8_t fragment_id;
2962 uint8_t reason_code;
2963 uint8_t explanation_code;
2964 uint8_t vendor_unique;
2965 };
2966 /* Assume the largest number of targets for the union */
2967 struct ct_sns_gpn_ft_data {
2968 u8 control_byte;
2969 u8 port_id[3];
2970 u32 reserved;
2971 u8 port_name[8];
2972 } entries[1];
2973 };
2974
2975 /* CT command response */
2976 struct ct_sns_rsp {
2977 struct ct_rsp_hdr header;
2978
2979 union {
2980 struct {
2981 uint8_t port_type;
2982 be_id_t port_id;
2983 uint8_t port_name[8];
2984 uint8_t sym_port_name_len;
2985 uint8_t sym_port_name[255];
2986 uint8_t node_name[8];
2987 uint8_t sym_node_name_len;
2988 uint8_t sym_node_name[255];
2989 uint8_t init_proc_assoc[8];
2990 uint8_t node_ip_addr[16];
2991 uint8_t class_of_service[4];
2992 uint8_t fc4_types[32];
2993 uint8_t ip_address[16];
2994 uint8_t fabric_port_name[8];
2995 uint8_t reserved;
2996 uint8_t hard_address[3];
2997 } ga_nxt;
2998
2999 struct {
3000 /* Assume the largest number of targets for the union */
3001 struct ct_sns_gid_pt_data
3002 entries[MAX_FIBRE_DEVICES_MAX];
3003 } gid_pt;
3004
3005 struct {
3006 uint8_t port_name[8];
3007 } gpn_id;
3008
3009 struct {
3010 uint8_t node_name[8];
3011 } gnn_id;
3012
3013 struct {
3014 uint8_t fc4_types[32];
3015 } gft_id;
3016
3017 struct {
3018 uint32_t entry_count;
3019 uint8_t port_name[8];
3020 struct ct_fdmi1_hba_attributes attrs;
3021 } ghat;
3022
3023 struct {
3024 uint8_t port_name[8];
3025 } gfpn_id;
3026
3027 struct {
3028 uint16_t speeds;
3029 uint16_t speed;
3030 } gpsc;
3031
3032 #define GFF_FCP_SCSI_OFFSET 7
3033 #define GFF_NVME_OFFSET 23 /* type = 28h */
3034 struct {
3035 uint8_t fc4_features[128];
3036 } gff_id;
3037 struct {
3038 uint8_t reserved;
3039 uint8_t port_id[3];
3040 } gid_pn;
3041 } rsp;
3042 };
3043
3044 struct ct_sns_pkt {
3045 union {
3046 struct ct_sns_req req;
3047 struct ct_sns_rsp rsp;
3048 } p;
3049 };
3050
3051 struct ct_sns_gpnft_pkt {
3052 union {
3053 struct ct_sns_req req;
3054 struct ct_sns_gpnft_rsp rsp;
3055 } p;
3056 };
3057
3058 enum scan_flags_t {
3059 SF_SCANNING = BIT_0,
3060 SF_QUEUED = BIT_1,
3061 };
3062
3063 enum fc4type_t {
3064 FS_FC4TYPE_FCP = BIT_0,
3065 FS_FC4TYPE_NVME = BIT_1,
3066 FS_FCP_IS_N2N = BIT_7,
3067 };
3068
3069 struct fab_scan_rp {
3070 port_id_t id;
3071 enum fc4type_t fc4type;
3072 u8 port_name[8];
3073 u8 node_name[8];
3074 };
3075
3076 struct fab_scan {
3077 struct fab_scan_rp *l;
3078 u32 size;
3079 u16 scan_retry;
3080 #define MAX_SCAN_RETRIES 5
3081 enum scan_flags_t scan_flags;
3082 struct delayed_work scan_work;
3083 };
3084
3085 /*
3086 * SNS command structures -- for 2200 compatibility.
3087 */
3088 #define RFT_ID_SNS_SCMD_LEN 22
3089 #define RFT_ID_SNS_CMD_SIZE 60
3090 #define RFT_ID_SNS_DATA_SIZE 16
3091
3092 #define RNN_ID_SNS_SCMD_LEN 10
3093 #define RNN_ID_SNS_CMD_SIZE 36
3094 #define RNN_ID_SNS_DATA_SIZE 16
3095
3096 #define GA_NXT_SNS_SCMD_LEN 6
3097 #define GA_NXT_SNS_CMD_SIZE 28
3098 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
3099
3100 #define GID_PT_SNS_SCMD_LEN 6
3101 #define GID_PT_SNS_CMD_SIZE 28
3102 /*
3103 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older
3104 * adapters.
3105 */
3106 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
3107
3108 #define GPN_ID_SNS_SCMD_LEN 6
3109 #define GPN_ID_SNS_CMD_SIZE 28
3110 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
3111
3112 #define GNN_ID_SNS_SCMD_LEN 6
3113 #define GNN_ID_SNS_CMD_SIZE 28
3114 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
3115
3116 struct sns_cmd_pkt {
3117 union {
3118 struct {
3119 uint16_t buffer_length;
3120 uint16_t reserved_1;
3121 __le64 buffer_address __packed;
3122 uint16_t subcommand_length;
3123 uint16_t reserved_2;
3124 uint16_t subcommand;
3125 uint16_t size;
3126 uint32_t reserved_3;
3127 uint8_t param[36];
3128 } cmd;
3129
3130 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
3131 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
3132 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
3133 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
3134 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
3135 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
3136 } p;
3137 };
3138
3139 struct fw_blob {
3140 char *name;
3141 uint32_t segs[4];
3142 const struct firmware *fw;
3143 };
3144
3145 /* Return data from MBC_GET_ID_LIST call. */
3146 struct gid_list_info {
3147 uint8_t al_pa;
3148 uint8_t area;
3149 uint8_t domain;
3150 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
3151 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
3152 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
3153 };
3154
3155 /* NPIV */
3156 typedef struct vport_info {
3157 uint8_t port_name[WWN_SIZE];
3158 uint8_t node_name[WWN_SIZE];
3159 int vp_id;
3160 uint16_t loop_id;
3161 unsigned long host_no;
3162 uint8_t port_id[3];
3163 int loop_state;
3164 } vport_info_t;
3165
3166 typedef struct vport_params {
3167 uint8_t port_name[WWN_SIZE];
3168 uint8_t node_name[WWN_SIZE];
3169 uint32_t options;
3170 #define VP_OPTS_RETRY_ENABLE BIT_0
3171 #define VP_OPTS_VP_DISABLE BIT_1
3172 } vport_params_t;
3173
3174 /* NPIV - return codes of VP create and modify */
3175 #define VP_RET_CODE_OK 0
3176 #define VP_RET_CODE_FATAL 1
3177 #define VP_RET_CODE_WRONG_ID 2
3178 #define VP_RET_CODE_WWPN 3
3179 #define VP_RET_CODE_RESOURCES 4
3180 #define VP_RET_CODE_NO_MEM 5
3181 #define VP_RET_CODE_NOT_FOUND 6
3182
3183 struct qla_hw_data;
3184 struct rsp_que;
3185 /*
3186 * ISP operations
3187 */
3188 struct isp_operations {
3189
3190 int (*pci_config) (struct scsi_qla_host *);
3191 int (*reset_chip)(struct scsi_qla_host *);
3192 int (*chip_diag) (struct scsi_qla_host *);
3193 void (*config_rings) (struct scsi_qla_host *);
3194 int (*reset_adapter)(struct scsi_qla_host *);
3195 int (*nvram_config) (struct scsi_qla_host *);
3196 void (*update_fw_options) (struct scsi_qla_host *);
3197 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
3198
3199 char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t);
3200 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
3201
3202 irq_handler_t intr_handler;
3203 void (*enable_intrs) (struct qla_hw_data *);
3204 void (*disable_intrs) (struct qla_hw_data *);
3205
3206 int (*abort_command) (srb_t *);
3207 int (*target_reset) (struct fc_port *, uint64_t, int);
3208 int (*lun_reset) (struct fc_port *, uint64_t, int);
3209 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
3210 uint8_t, uint8_t, uint16_t *, uint8_t);
3211 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
3212 uint8_t, uint8_t);
3213
3214 uint16_t (*calc_req_entries) (uint16_t);
3215 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
3216 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *);
3217 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
3218 uint32_t);
3219
3220 uint8_t *(*read_nvram)(struct scsi_qla_host *, void *,
3221 uint32_t, uint32_t);
3222 int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t,
3223 uint32_t);
3224
3225 void (*fw_dump) (struct scsi_qla_host *, int);
3226
3227 int (*beacon_on) (struct scsi_qla_host *);
3228 int (*beacon_off) (struct scsi_qla_host *);
3229 void (*beacon_blink) (struct scsi_qla_host *);
3230
3231 void *(*read_optrom)(struct scsi_qla_host *, void *,
3232 uint32_t, uint32_t);
3233 int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t,
3234 uint32_t);
3235
3236 int (*get_flash_version) (struct scsi_qla_host *, void *);
3237 int (*start_scsi) (srb_t *);
3238 int (*start_scsi_mq) (srb_t *);
3239 int (*abort_isp) (struct scsi_qla_host *);
3240 int (*iospace_config)(struct qla_hw_data *);
3241 int (*initialize_adapter)(struct scsi_qla_host *);
3242 };
3243
3244 /* MSI-X Support *************************************************************/
3245
3246 #define QLA_MSIX_CHIP_REV_24XX 3
3247 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
3248 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
3249
3250 #define QLA_BASE_VECTORS 2 /* default + RSP */
3251 #define QLA_MSIX_RSP_Q 0x01
3252 #define QLA_ATIO_VECTOR 0x02
3253 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
3254 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q_HS 0x04
3255
3256 #define QLA_MIDX_DEFAULT 0
3257 #define QLA_MIDX_RSP_Q 1
3258 #define QLA_PCI_MSIX_CONTROL 0xa2
3259 #define QLA_83XX_PCI_MSIX_CONTROL 0x92
3260
3261 struct scsi_qla_host;
3262
3263
3264 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */
3265
3266 struct qla_msix_entry {
3267 int have_irq;
3268 int in_use;
3269 uint32_t vector;
3270 uint16_t entry;
3271 char name[30];
3272 void *handle;
3273 int cpuid;
3274 };
3275
3276 #define WATCH_INTERVAL 1 /* number of seconds */
3277
3278 /* Work events. */
3279 enum qla_work_type {
3280 QLA_EVT_AEN,
3281 QLA_EVT_IDC_ACK,
3282 QLA_EVT_ASYNC_LOGIN,
3283 QLA_EVT_ASYNC_LOGOUT,
3284 QLA_EVT_ASYNC_ADISC,
3285 QLA_EVT_UEVENT,
3286 QLA_EVT_AENFX,
3287 QLA_EVT_GPNID,
3288 QLA_EVT_UNMAP,
3289 QLA_EVT_NEW_SESS,
3290 QLA_EVT_GPDB,
3291 QLA_EVT_PRLI,
3292 QLA_EVT_GPSC,
3293 QLA_EVT_GNL,
3294 QLA_EVT_NACK,
3295 QLA_EVT_RELOGIN,
3296 QLA_EVT_ASYNC_PRLO,
3297 QLA_EVT_ASYNC_PRLO_DONE,
3298 QLA_EVT_GPNFT,
3299 QLA_EVT_GPNFT_DONE,
3300 QLA_EVT_GNNFT_DONE,
3301 QLA_EVT_GNNID,
3302 QLA_EVT_GFPNID,
3303 QLA_EVT_SP_RETRY,
3304 QLA_EVT_IIDMA,
3305 QLA_EVT_ELS_PLOGI,
3306 };
3307
3308
3309 struct qla_work_evt {
3310 struct list_head list;
3311 enum qla_work_type type;
3312 u32 flags;
3313 #define QLA_EVT_FLAG_FREE 0x1
3314
3315 union {
3316 struct {
3317 enum fc_host_event_code code;
3318 u32 data;
3319 } aen;
3320 struct {
3321 #define QLA_IDC_ACK_REGS 7
3322 uint16_t mb[QLA_IDC_ACK_REGS];
3323 } idc_ack;
3324 struct {
3325 struct fc_port *fcport;
3326 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
3327 u16 data[2];
3328 } logio;
3329 struct {
3330 u32 code;
3331 #define QLA_UEVENT_CODE_FW_DUMP 0
3332 } uevent;
3333 struct {
3334 uint32_t evtcode;
3335 uint32_t mbx[8];
3336 uint32_t count;
3337 } aenfx;
3338 struct {
3339 srb_t *sp;
3340 } iosb;
3341 struct {
3342 port_id_t id;
3343 } gpnid;
3344 struct {
3345 port_id_t id;
3346 u8 port_name[8];
3347 u8 node_name[8];
3348 void *pla;
3349 u8 fc4_type;
3350 } new_sess;
3351 struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */
3352 fc_port_t *fcport;
3353 u8 opt;
3354 } fcport;
3355 struct {
3356 fc_port_t *fcport;
3357 u8 iocb[IOCB_SIZE];
3358 int type;
3359 } nack;
3360 struct {
3361 u8 fc4_type;
3362 srb_t *sp;
3363 } gpnft;
3364 } u;
3365 };
3366
3367 struct qla_chip_state_84xx {
3368 struct list_head list;
3369 struct kref kref;
3370
3371 void *bus;
3372 spinlock_t access_lock;
3373 struct mutex fw_update_mutex;
3374 uint32_t fw_update;
3375 uint32_t op_fw_version;
3376 uint32_t op_fw_size;
3377 uint32_t op_fw_seq_size;
3378 uint32_t diag_fw_version;
3379 uint32_t gold_fw_version;
3380 };
3381
3382 struct qla_dif_statistics {
3383 uint64_t dif_input_bytes;
3384 uint64_t dif_output_bytes;
3385 uint64_t dif_input_requests;
3386 uint64_t dif_output_requests;
3387 uint32_t dif_guard_err;
3388 uint32_t dif_ref_tag_err;
3389 uint32_t dif_app_tag_err;
3390 };
3391
3392 struct qla_statistics {
3393 uint32_t total_isp_aborts;
3394 uint64_t input_bytes;
3395 uint64_t output_bytes;
3396 uint64_t input_requests;
3397 uint64_t output_requests;
3398 uint32_t control_requests;
3399
3400 uint64_t jiffies_at_last_reset;
3401 uint32_t stat_max_pend_cmds;
3402 uint32_t stat_max_qfull_cmds_alloc;
3403 uint32_t stat_max_qfull_cmds_dropped;
3404
3405 struct qla_dif_statistics qla_dif_stats;
3406 };
3407
3408 struct bidi_statistics {
3409 unsigned long long io_count;
3410 unsigned long long transfer_bytes;
3411 };
3412
3413 struct qla_tc_param {
3414 struct scsi_qla_host *vha;
3415 uint32_t blk_sz;
3416 uint32_t bufflen;
3417 struct scatterlist *sg;
3418 struct scatterlist *prot_sg;
3419 struct crc_context *ctx;
3420 uint8_t *ctx_dsd_alloced;
3421 };
3422
3423 /* Multi queue support */
3424 #define MBC_INITIALIZE_MULTIQ 0x1f
3425 #define QLA_QUE_PAGE 0X1000
3426 #define QLA_MQ_SIZE 32
3427 #define QLA_MAX_QUEUES 256
3428 #define ISP_QUE_REG(ha, id) \
3429 ((ha->mqenable || IS_QLA83XX(ha) || \
3430 IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \
3431 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
3432 ((void __iomem *)ha->iobase))
3433 #define QLA_REQ_QUE_ID(tag) \
3434 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
3435 #define QLA_DEFAULT_QUE_QOS 5
3436 #define QLA_PRECONFIG_VPORTS 32
3437 #define QLA_MAX_VPORTS_QLA24XX 128
3438 #define QLA_MAX_VPORTS_QLA25XX 256
3439
3440 struct qla_tgt_counters {
3441 uint64_t qla_core_sbt_cmd;
3442 uint64_t core_qla_que_buf;
3443 uint64_t qla_core_ret_ctio;
3444 uint64_t core_qla_snd_status;
3445 uint64_t qla_core_ret_sta_ctio;
3446 uint64_t core_qla_free_cmd;
3447 uint64_t num_q_full_sent;
3448 uint64_t num_alloc_iocb_failed;
3449 uint64_t num_term_xchg_sent;
3450 };
3451
3452 struct qla_qpair;
3453
3454 /* Response queue data structure */
3455 struct rsp_que {
3456 dma_addr_t dma;
3457 response_t *ring;
3458 response_t *ring_ptr;
3459 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
3460 uint32_t __iomem *rsp_q_out;
3461 uint16_t ring_index;
3462 uint16_t out_ptr;
3463 uint16_t *in_ptr; /* queue shadow in index */
3464 uint16_t length;
3465 uint16_t options;
3466 uint16_t rid;
3467 uint16_t id;
3468 uint16_t vp_idx;
3469 struct qla_hw_data *hw;
3470 struct qla_msix_entry *msix;
3471 struct req_que *req;
3472 srb_t *status_srb; /* status continuation entry */
3473 struct qla_qpair *qpair;
3474
3475 dma_addr_t dma_fx00;
3476 response_t *ring_fx00;
3477 uint16_t length_fx00;
3478 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
3479 };
3480
3481 /* Request queue data structure */
3482 struct req_que {
3483 dma_addr_t dma;
3484 request_t *ring;
3485 request_t *ring_ptr;
3486 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
3487 uint32_t __iomem *req_q_out;
3488 uint16_t ring_index;
3489 uint16_t in_ptr;
3490 uint16_t *out_ptr; /* queue shadow out index */
3491 uint16_t cnt;
3492 uint16_t length;
3493 uint16_t options;
3494 uint16_t rid;
3495 uint16_t id;
3496 uint16_t qos;
3497 uint16_t vp_idx;
3498 struct rsp_que *rsp;
3499 srb_t **outstanding_cmds;
3500 uint32_t current_outstanding_cmd;
3501 uint16_t num_outstanding_cmds;
3502 int max_q_depth;
3503
3504 dma_addr_t dma_fx00;
3505 request_t *ring_fx00;
3506 uint16_t length_fx00;
3507 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
3508 };
3509
3510 /*Queue pair data structure */
3511 struct qla_qpair {
3512 spinlock_t qp_lock;
3513 atomic_t ref_count;
3514 uint32_t lun_cnt;
3515 /*
3516 * For qpair 0, qp_lock_ptr will point at hardware_lock due to
3517 * legacy code. For other Qpair(s), it will point at qp_lock.
3518 */
3519 spinlock_t *qp_lock_ptr;
3520 struct scsi_qla_host *vha;
3521 u32 chip_reset;
3522
3523 /* distill these fields down to 'online=0/1'
3524 * ha->flags.eeh_busy
3525 * ha->flags.pci_channel_io_perm_failure
3526 * base_vha->loop_state
3527 */
3528 uint32_t online:1;
3529 /* move vha->flags.difdix_supported here */
3530 uint32_t difdix_supported:1;
3531 uint32_t delete_in_progress:1;
3532 uint32_t fw_started:1;
3533 uint32_t enable_class_2:1;
3534 uint32_t enable_explicit_conf:1;
3535 uint32_t use_shadow_reg:1;
3536
3537 uint16_t id; /* qp number used with FW */
3538 uint16_t vp_idx; /* vport ID */
3539 mempool_t *srb_mempool;
3540
3541 struct pci_dev *pdev;
3542 void (*reqq_start_iocbs)(struct qla_qpair *);
3543
3544 /* to do: New driver: move queues to here instead of pointers */
3545 struct req_que *req;
3546 struct rsp_que *rsp;
3547 struct atio_que *atio;
3548 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */
3549 struct qla_hw_data *hw;
3550 struct work_struct q_work;
3551 struct list_head qp_list_elem; /* vha->qp_list */
3552 struct list_head hints_list;
3553 uint16_t cpuid;
3554 uint16_t retry_term_cnt;
3555 uint32_t retry_term_exchg_addr;
3556 uint64_t retry_term_jiff;
3557 struct qla_tgt_counters tgt_counters;
3558 };
3559
3560 /* Place holder for FW buffer parameters */
3561 struct qlfc_fw {
3562 void *fw_buf;
3563 dma_addr_t fw_dma;
3564 uint32_t len;
3565 };
3566
3567 struct rdp_req_payload {
3568 uint32_t els_request;
3569 uint32_t desc_list_len;
3570
3571 /* NPIV descriptor */
3572 struct {
3573 uint32_t desc_tag;
3574 uint32_t desc_len;
3575 uint8_t reserved;
3576 uint8_t nport_id[3];
3577 } npiv_desc;
3578 };
3579
3580 struct rdp_rsp_payload {
3581 struct {
3582 uint32_t cmd;
3583 uint32_t len;
3584 } hdr;
3585
3586 /* LS Request Info descriptor */
3587 struct {
3588 uint32_t desc_tag;
3589 uint32_t desc_len;
3590 uint32_t req_payload_word_0;
3591 } ls_req_info_desc;
3592
3593 /* LS Request Info descriptor */
3594 struct {
3595 uint32_t desc_tag;
3596 uint32_t desc_len;
3597 uint32_t req_payload_word_0;
3598 } ls_req_info_desc2;
3599
3600 /* SFP diagnostic param descriptor */
3601 struct {
3602 uint32_t desc_tag;
3603 uint32_t desc_len;
3604 uint16_t temperature;
3605 uint16_t vcc;
3606 uint16_t tx_bias;
3607 uint16_t tx_power;
3608 uint16_t rx_power;
3609 uint16_t sfp_flags;
3610 } sfp_diag_desc;
3611
3612 /* Port Speed Descriptor */
3613 struct {
3614 uint32_t desc_tag;
3615 uint32_t desc_len;
3616 uint16_t speed_capab;
3617 uint16_t operating_speed;
3618 } port_speed_desc;
3619
3620 /* Link Error Status Descriptor */
3621 struct {
3622 uint32_t desc_tag;
3623 uint32_t desc_len;
3624 uint32_t link_fail_cnt;
3625 uint32_t loss_sync_cnt;
3626 uint32_t loss_sig_cnt;
3627 uint32_t prim_seq_err_cnt;
3628 uint32_t inval_xmit_word_cnt;
3629 uint32_t inval_crc_cnt;
3630 uint8_t pn_port_phy_type;
3631 uint8_t reserved[3];
3632 } ls_err_desc;
3633
3634 /* Port name description with diag param */
3635 struct {
3636 uint32_t desc_tag;
3637 uint32_t desc_len;
3638 uint8_t WWNN[WWN_SIZE];
3639 uint8_t WWPN[WWN_SIZE];
3640 } port_name_diag_desc;
3641
3642 /* Port Name desc for Direct attached Fx_Port or Nx_Port */
3643 struct {
3644 uint32_t desc_tag;
3645 uint32_t desc_len;
3646 uint8_t WWNN[WWN_SIZE];
3647 uint8_t WWPN[WWN_SIZE];
3648 } port_name_direct_desc;
3649
3650 /* Buffer Credit descriptor */
3651 struct {
3652 uint32_t desc_tag;
3653 uint32_t desc_len;
3654 uint32_t fcport_b2b;
3655 uint32_t attached_fcport_b2b;
3656 uint32_t fcport_rtt;
3657 } buffer_credit_desc;
3658
3659 /* Optical Element Data Descriptor */
3660 struct {
3661 uint32_t desc_tag;
3662 uint32_t desc_len;
3663 uint16_t high_alarm;
3664 uint16_t low_alarm;
3665 uint16_t high_warn;
3666 uint16_t low_warn;
3667 uint32_t element_flags;
3668 } optical_elmt_desc[5];
3669
3670 /* Optical Product Data Descriptor */
3671 struct {
3672 uint32_t desc_tag;
3673 uint32_t desc_len;
3674 uint8_t vendor_name[16];
3675 uint8_t part_number[16];
3676 uint8_t serial_number[16];
3677 uint8_t revision[4];
3678 uint8_t date[8];
3679 } optical_prod_desc;
3680 };
3681
3682 #define RDP_DESC_LEN(obj) \
3683 (sizeof(obj) - sizeof((obj).desc_tag) - sizeof((obj).desc_len))
3684
3685 #define RDP_PORT_SPEED_1GB BIT_15
3686 #define RDP_PORT_SPEED_2GB BIT_14
3687 #define RDP_PORT_SPEED_4GB BIT_13
3688 #define RDP_PORT_SPEED_10GB BIT_12
3689 #define RDP_PORT_SPEED_8GB BIT_11
3690 #define RDP_PORT_SPEED_16GB BIT_10
3691 #define RDP_PORT_SPEED_32GB BIT_9
3692 #define RDP_PORT_SPEED_64GB BIT_8
3693 #define RDP_PORT_SPEED_UNKNOWN BIT_0
3694
3695 struct scsi_qlt_host {
3696 void *target_lport_ptr;
3697 struct mutex tgt_mutex;
3698 struct mutex tgt_host_action_mutex;
3699 struct qla_tgt *qla_tgt;
3700 };
3701
3702 struct qlt_hw_data {
3703 /* Protected by hw lock */
3704 uint32_t node_name_set:1;
3705
3706 dma_addr_t atio_dma; /* Physical address. */
3707 struct atio *atio_ring; /* Base virtual address */
3708 struct atio *atio_ring_ptr; /* Current address. */
3709 uint16_t atio_ring_index; /* Current index. */
3710 uint16_t atio_q_length;
3711 uint32_t __iomem *atio_q_in;
3712 uint32_t __iomem *atio_q_out;
3713
3714 struct qla_tgt_func_tmpl *tgt_ops;
3715 struct qla_tgt_vp_map *tgt_vp_map;
3716
3717 int saved_set;
3718 uint16_t saved_exchange_count;
3719 uint32_t saved_firmware_options_1;
3720 uint32_t saved_firmware_options_2;
3721 uint32_t saved_firmware_options_3;
3722 uint8_t saved_firmware_options[2];
3723 uint8_t saved_add_firmware_options[2];
3724
3725 uint8_t tgt_node_name[WWN_SIZE];
3726
3727 struct dentry *dfs_tgt_sess;
3728 struct dentry *dfs_tgt_port_database;
3729 struct dentry *dfs_naqp;
3730
3731 struct list_head q_full_list;
3732 uint32_t num_pend_cmds;
3733 uint32_t num_qfull_cmds_alloc;
3734 uint32_t num_qfull_cmds_dropped;
3735 spinlock_t q_full_lock;
3736 uint32_t leak_exchg_thresh_hold;
3737 spinlock_t sess_lock;
3738 int num_act_qpairs;
3739 #define DEFAULT_NAQP 2
3740 spinlock_t atio_lock ____cacheline_aligned;
3741 struct btree_head32 host_map;
3742 };
3743
3744 #define MAX_QFULL_CMDS_ALLOC 8192
3745 #define Q_FULL_THRESH_HOLD_PERCENT 90
3746 #define Q_FULL_THRESH_HOLD(ha) \
3747 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
3748
3749 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */
3750
3751 /*
3752 * Qlogic host adapter specific data structure.
3753 */
3754 struct qla_hw_data {
3755 struct pci_dev *pdev;
3756 /* SRB cache. */
3757 #define SRB_MIN_REQ 128
3758 mempool_t *srb_mempool;
3759
3760 volatile struct {
3761 uint32_t mbox_int :1;
3762 uint32_t mbox_busy :1;
3763 uint32_t disable_risc_code_load :1;
3764 uint32_t enable_64bit_addressing :1;
3765 uint32_t enable_lip_reset :1;
3766 uint32_t enable_target_reset :1;
3767 uint32_t enable_lip_full_login :1;
3768 uint32_t enable_led_scheme :1;
3769
3770 uint32_t msi_enabled :1;
3771 uint32_t msix_enabled :1;
3772 uint32_t disable_serdes :1;
3773 uint32_t gpsc_supported :1;
3774 uint32_t npiv_supported :1;
3775 uint32_t pci_channel_io_perm_failure :1;
3776 uint32_t fce_enabled :1;
3777 uint32_t fac_supported :1;
3778
3779 uint32_t chip_reset_done :1;
3780 uint32_t running_gold_fw :1;
3781 uint32_t eeh_busy :1;
3782 uint32_t disable_msix_handshake :1;
3783 uint32_t fcp_prio_enabled :1;
3784 uint32_t isp82xx_fw_hung:1;
3785 uint32_t nic_core_hung:1;
3786
3787 uint32_t quiesce_owner:1;
3788 uint32_t nic_core_reset_hdlr_active:1;
3789 uint32_t nic_core_reset_owner:1;
3790 uint32_t isp82xx_no_md_cap:1;
3791 uint32_t host_shutting_down:1;
3792 uint32_t idc_compl_status:1;
3793 uint32_t mr_reset_hdlr_active:1;
3794 uint32_t mr_intr_valid:1;
3795
3796 uint32_t dport_enabled:1;
3797 uint32_t fawwpn_enabled:1;
3798 uint32_t exlogins_enabled:1;
3799 uint32_t exchoffld_enabled:1;
3800
3801 uint32_t lip_ae:1;
3802 uint32_t n2n_ae:1;
3803 uint32_t fw_started:1;
3804 uint32_t fw_init_done:1;
3805
3806 uint32_t lr_detected:1;
3807
3808 uint32_t rida_fmt2:1;
3809 uint32_t purge_mbox:1;
3810 uint32_t n2n_bigger:1;
3811 uint32_t secure_adapter:1;
3812 uint32_t secure_fw:1;
3813 } flags;
3814
3815 uint16_t max_exchg;
3816 uint16_t lr_distance; /* 32G & above */
3817 #define LR_DISTANCE_5K 1
3818 #define LR_DISTANCE_10K 0
3819
3820 /* This spinlock is used to protect "io transactions", you must
3821 * acquire it before doing any IO to the card, eg with RD_REG*() and
3822 * WRT_REG*() for the duration of your entire commandtransaction.
3823 *
3824 * This spinlock is of lower priority than the io request lock.
3825 */
3826
3827 spinlock_t hardware_lock ____cacheline_aligned;
3828 int bars;
3829 int mem_only;
3830 device_reg_t *iobase; /* Base I/O address */
3831 resource_size_t pio_address;
3832
3833 #define MIN_IOBASE_LEN 0x100
3834 dma_addr_t bar0_hdl;
3835
3836 void __iomem *cregbase;
3837 dma_addr_t bar2_hdl;
3838 #define BAR0_LEN_FX00 (1024 * 1024)
3839 #define BAR2_LEN_FX00 (128 * 1024)
3840
3841 uint32_t rqstq_intr_code;
3842 uint32_t mbx_intr_code;
3843 uint32_t req_que_len;
3844 uint32_t rsp_que_len;
3845 uint32_t req_que_off;
3846 uint32_t rsp_que_off;
3847
3848 /* Multi queue data structs */
3849 device_reg_t *mqiobase;
3850 device_reg_t *msixbase;
3851 uint16_t msix_count;
3852 uint8_t mqenable;
3853 struct req_que **req_q_map;
3854 struct rsp_que **rsp_q_map;
3855 struct qla_qpair **queue_pair_map;
3856 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3857 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3858 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
3859 / sizeof(unsigned long)];
3860 uint8_t max_req_queues;
3861 uint8_t max_rsp_queues;
3862 uint8_t max_qpairs;
3863 uint8_t num_qpairs;
3864 struct qla_qpair *base_qpair;
3865 struct qla_npiv_entry *npiv_info;
3866 uint16_t nvram_npiv_size;
3867
3868 uint16_t switch_cap;
3869 #define FLOGI_SEQ_DEL BIT_8
3870 #define FLOGI_MID_SUPPORT BIT_10
3871 #define FLOGI_VSAN_SUPPORT BIT_12
3872 #define FLOGI_SP_SUPPORT BIT_13
3873
3874 uint8_t port_no; /* Physical port of adapter */
3875 uint8_t exch_starvation;
3876
3877 /* Timeout timers. */
3878 uint8_t loop_down_abort_time; /* port down timer */
3879 atomic_t loop_down_timer; /* loop down timer */
3880 uint8_t link_down_timeout; /* link down timeout */
3881 uint16_t max_loop_id;
3882 uint16_t max_fibre_devices; /* Maximum number of targets */
3883
3884 uint16_t fb_rev;
3885 uint16_t min_external_loopid; /* First external loop Id */
3886
3887 #define PORT_SPEED_UNKNOWN 0xFFFF
3888 #define PORT_SPEED_1GB 0x00
3889 #define PORT_SPEED_2GB 0x01
3890 #define PORT_SPEED_AUTO 0x02
3891 #define PORT_SPEED_4GB 0x03
3892 #define PORT_SPEED_8GB 0x04
3893 #define PORT_SPEED_16GB 0x05
3894 #define PORT_SPEED_32GB 0x06
3895 #define PORT_SPEED_64GB 0x07
3896 #define PORT_SPEED_10GB 0x13
3897 uint16_t link_data_rate; /* F/W operating speed */
3898 uint16_t set_data_rate; /* Set by user */
3899
3900 uint8_t current_topology;
3901 uint8_t prev_topology;
3902 #define ISP_CFG_NL 1
3903 #define ISP_CFG_N 2
3904 #define ISP_CFG_FL 4
3905 #define ISP_CFG_F 8
3906
3907 uint8_t operating_mode; /* F/W operating mode */
3908 #define LOOP 0
3909 #define P2P 1
3910 #define LOOP_P2P 2
3911 #define P2P_LOOP 3
3912 uint8_t interrupts_on;
3913 uint32_t isp_abort_cnt;
3914 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
3915 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
3916 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
3917 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
3918 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
3919 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
3920 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
3921 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
3922 #define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061
3923 #define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081
3924 #define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089
3925 #define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281
3926 #define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289
3927
3928 uint32_t isp_type;
3929 #define DT_ISP2100 BIT_0
3930 #define DT_ISP2200 BIT_1
3931 #define DT_ISP2300 BIT_2
3932 #define DT_ISP2312 BIT_3
3933 #define DT_ISP2322 BIT_4
3934 #define DT_ISP6312 BIT_5
3935 #define DT_ISP6322 BIT_6
3936 #define DT_ISP2422 BIT_7
3937 #define DT_ISP2432 BIT_8
3938 #define DT_ISP5422 BIT_9
3939 #define DT_ISP5432 BIT_10
3940 #define DT_ISP2532 BIT_11
3941 #define DT_ISP8432 BIT_12
3942 #define DT_ISP8001 BIT_13
3943 #define DT_ISP8021 BIT_14
3944 #define DT_ISP2031 BIT_15
3945 #define DT_ISP8031 BIT_16
3946 #define DT_ISPFX00 BIT_17
3947 #define DT_ISP8044 BIT_18
3948 #define DT_ISP2071 BIT_19
3949 #define DT_ISP2271 BIT_20
3950 #define DT_ISP2261 BIT_21
3951 #define DT_ISP2061 BIT_22
3952 #define DT_ISP2081 BIT_23
3953 #define DT_ISP2089 BIT_24
3954 #define DT_ISP2281 BIT_25
3955 #define DT_ISP2289 BIT_26
3956 #define DT_ISP_LAST (DT_ISP2289 << 1)
3957
3958 uint32_t device_type;
3959 #define DT_T10_PI BIT_25
3960 #define DT_IIDMA BIT_26
3961 #define DT_FWI2 BIT_27
3962 #define DT_ZIO_SUPPORTED BIT_28
3963 #define DT_OEM_001 BIT_29
3964 #define DT_ISP2200A BIT_30
3965 #define DT_EXTENDED_IDS BIT_31
3966
3967 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1))
3968 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
3969 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
3970 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
3971 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
3972 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
3973 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
3974 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
3975 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
3976 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
3977 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
3978 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
3979 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
3980 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
3981 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
3982 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
3983 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
3984 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
3985 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
3986 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
3987 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
3988 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
3989 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
3990 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
3991 #define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081)
3992 #define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281)
3993
3994 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
3995 IS_QLA6312(ha) || IS_QLA6322(ha))
3996 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
3997 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
3998 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
3999 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
4000 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
4001 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
4002 #define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha))
4003 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
4004 IS_QLA84XX(ha))
4005 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
4006 IS_QLA8031(ha) || IS_QLA8044(ha))
4007 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
4008 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
4009 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
4010 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
4011 IS_QLA8044(ha) || IS_QLA27XX(ha) || \
4012 IS_QLA28XX(ha))
4013 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4014 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4015 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
4016 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4017 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4018 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4019 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4020 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
4021
4022 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
4023 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
4024 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
4025 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
4026 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
4027 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
4028 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
4029 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \
4030 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4031 #define IS_BIDI_CAPABLE(ha) \
4032 (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4033 /* Bit 21 of fw_attributes decides the MCTP capabilities */
4034 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
4035 ((ha)->fw_attributes_ext[0] & BIT_0))
4036 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
4037 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
4038 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
4039 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4040 IS_QLA28XX(ha))
4041 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
4042 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
4043 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4044 IS_QLA28XX(ha))
4045 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
4046 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha))
4047 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4048 IS_QLA28XX(ha))
4049 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4050 IS_QLA28XX(ha))
4051 #define IS_EXCHG_OFFLD_CAPABLE(ha) \
4052 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4053 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \
4054 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4055 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4056 #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\
4057 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4058
4059 /* HBA serial number */
4060 uint8_t serial0;
4061 uint8_t serial1;
4062 uint8_t serial2;
4063
4064 /* NVRAM configuration data */
4065 #define MAX_NVRAM_SIZE 4096
4066 #define VPD_OFFSET (MAX_NVRAM_SIZE / 2)
4067 uint16_t nvram_size;
4068 uint16_t nvram_base;
4069 void *nvram;
4070 uint16_t vpd_size;
4071 uint16_t vpd_base;
4072 void *vpd;
4073
4074 uint16_t loop_reset_delay;
4075 uint8_t retry_count;
4076 uint8_t login_timeout;
4077 uint16_t r_a_tov;
4078 int port_down_retry_count;
4079 uint8_t mbx_count;
4080 uint8_t aen_mbx_count;
4081 atomic_t num_pend_mbx_stage1;
4082 atomic_t num_pend_mbx_stage2;
4083 atomic_t num_pend_mbx_stage3;
4084 uint16_t frame_payload_size;
4085
4086 uint32_t login_retry_count;
4087 /* SNS command interfaces. */
4088 ms_iocb_entry_t *ms_iocb;
4089 dma_addr_t ms_iocb_dma;
4090 struct ct_sns_pkt *ct_sns;
4091 dma_addr_t ct_sns_dma;
4092 /* SNS command interfaces for 2200. */
4093 struct sns_cmd_pkt *sns_cmd;
4094 dma_addr_t sns_cmd_dma;
4095
4096 #define SFP_DEV_SIZE 512
4097 #define SFP_BLOCK_SIZE 64
4098 #define SFP_RTDI_LEN SFP_BLOCK_SIZE
4099
4100 void *sfp_data;
4101 dma_addr_t sfp_data_dma;
4102
4103 struct qla_flt_header *flt;
4104 dma_addr_t flt_dma;
4105
4106 #define XGMAC_DATA_SIZE 4096
4107 void *xgmac_data;
4108 dma_addr_t xgmac_data_dma;
4109
4110 #define DCBX_TLV_DATA_SIZE 4096
4111 void *dcbx_tlv;
4112 dma_addr_t dcbx_tlv_dma;
4113
4114 struct task_struct *dpc_thread;
4115 uint8_t dpc_active; /* DPC routine is active */
4116
4117 dma_addr_t gid_list_dma;
4118 struct gid_list_info *gid_list;
4119 int gid_list_info_size;
4120
4121 /* Small DMA pool allocations -- maximum 256 bytes in length. */
4122 #define DMA_POOL_SIZE 256
4123 struct dma_pool *s_dma_pool;
4124
4125 dma_addr_t init_cb_dma;
4126 init_cb_t *init_cb;
4127 int init_cb_size;
4128 dma_addr_t ex_init_cb_dma;
4129 struct ex_init_cb_81xx *ex_init_cb;
4130
4131 void *async_pd;
4132 dma_addr_t async_pd_dma;
4133
4134 #define ENABLE_EXTENDED_LOGIN BIT_7
4135
4136 /* Extended Logins */
4137 void *exlogin_buf;
4138 dma_addr_t exlogin_buf_dma;
4139 int exlogin_size;
4140
4141 #define ENABLE_EXCHANGE_OFFLD BIT_2
4142
4143 /* Exchange Offload */
4144 void *exchoffld_buf;
4145 dma_addr_t exchoffld_buf_dma;
4146 int exchoffld_size;
4147 int exchoffld_count;
4148
4149 /* n2n */
4150 struct els_plogi_payload plogi_els_payld;
4151
4152 void *swl;
4153
4154 /* These are used by mailbox operations. */
4155 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
4156 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
4157 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
4158
4159 mbx_cmd_t *mcp;
4160 struct mbx_cmd_32 *mcp32;
4161
4162 unsigned long mbx_cmd_flags;
4163 #define MBX_INTERRUPT 1
4164 #define MBX_INTR_WAIT 2
4165 #define MBX_UPDATE_FLASH_ACTIVE 3
4166
4167 struct mutex vport_lock; /* Virtual port synchronization */
4168 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
4169 struct mutex mq_lock; /* multi-queue synchronization */
4170 struct completion mbx_cmd_comp; /* Serialize mbx access */
4171 struct completion mbx_intr_comp; /* Used for completion notification */
4172 struct completion dcbx_comp; /* For set port config notification */
4173 struct completion lb_portup_comp; /* Used to wait for link up during
4174 * loopback */
4175 #define DCBX_COMP_TIMEOUT 20
4176 #define LB_PORTUP_COMP_TIMEOUT 10
4177
4178 int notify_dcbx_comp;
4179 int notify_lb_portup_comp;
4180 struct mutex selflogin_lock;
4181
4182 /* Basic firmware related information. */
4183 uint16_t fw_major_version;
4184 uint16_t fw_minor_version;
4185 uint16_t fw_subminor_version;
4186 uint16_t fw_attributes;
4187 uint16_t fw_attributes_h;
4188 #define FW_ATTR_H_NVME_FBURST BIT_1
4189 #define FW_ATTR_H_NVME BIT_10
4190 #define FW_ATTR_H_NVME_UPDATED BIT_14
4191
4192 uint16_t fw_attributes_ext[2];
4193 uint32_t fw_memory_size;
4194 uint32_t fw_transfer_size;
4195 uint32_t fw_srisc_address;
4196 #define RISC_START_ADDRESS_2100 0x1000
4197 #define RISC_START_ADDRESS_2300 0x800
4198 #define RISC_START_ADDRESS_2400 0x100000
4199
4200 uint16_t orig_fw_tgt_xcb_count;
4201 uint16_t cur_fw_tgt_xcb_count;
4202 uint16_t orig_fw_xcb_count;
4203 uint16_t cur_fw_xcb_count;
4204 uint16_t orig_fw_iocb_count;
4205 uint16_t cur_fw_iocb_count;
4206 uint16_t fw_max_fcf_count;
4207
4208 uint32_t fw_shared_ram_start;
4209 uint32_t fw_shared_ram_end;
4210 uint32_t fw_ddr_ram_start;
4211 uint32_t fw_ddr_ram_end;
4212
4213 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
4214 uint8_t fw_seriallink_options[4];
4215 uint16_t fw_seriallink_options24[4];
4216
4217 uint8_t serdes_version[3];
4218 uint8_t mpi_version[3];
4219 uint32_t mpi_capabilities;
4220 uint8_t phy_version[3];
4221 uint8_t pep_version[3];
4222
4223 /* Firmware dump template */
4224 struct fwdt {
4225 void *template;
4226 ulong length;
4227 ulong dump_size;
4228 } fwdt[2];
4229 struct qla2xxx_fw_dump *fw_dump;
4230 uint32_t fw_dump_len;
4231 u32 fw_dump_alloc_len;
4232 bool fw_dumped;
4233 bool fw_dump_mpi;
4234 unsigned long fw_dump_cap_flags;
4235 #define RISC_PAUSE_CMPL 0
4236 #define DMA_SHUTDOWN_CMPL 1
4237 #define ISP_RESET_CMPL 2
4238 #define RISC_RDY_AFT_RESET 3
4239 #define RISC_SRAM_DUMP_CMPL 4
4240 #define RISC_EXT_MEM_DUMP_CMPL 5
4241 #define ISP_MBX_RDY 6
4242 #define ISP_SOFT_RESET_CMPL 7
4243 int fw_dump_reading;
4244 int prev_minidump_failed;
4245 dma_addr_t eft_dma;
4246 void *eft;
4247 /* Current size of mctp dump is 0x086064 bytes */
4248 #define MCTP_DUMP_SIZE 0x086064
4249 dma_addr_t mctp_dump_dma;
4250 void *mctp_dump;
4251 int mctp_dumped;
4252 int mctp_dump_reading;
4253 uint32_t chain_offset;
4254 struct dentry *dfs_dir;
4255 struct dentry *dfs_fce;
4256 struct dentry *dfs_tgt_counters;
4257 struct dentry *dfs_fw_resource_cnt;
4258
4259 dma_addr_t fce_dma;
4260 void *fce;
4261 uint32_t fce_bufs;
4262 uint16_t fce_mb[8];
4263 uint64_t fce_wr, fce_rd;
4264 struct mutex fce_mutex;
4265
4266 uint32_t pci_attr;
4267 uint16_t chip_revision;
4268
4269 uint16_t product_id[4];
4270
4271 uint8_t model_number[16+1];
4272 char model_desc[80];
4273 uint8_t adapter_id[16+1];
4274
4275 /* Option ROM information. */
4276 char *optrom_buffer;
4277 uint32_t optrom_size;
4278 int optrom_state;
4279 #define QLA_SWAITING 0
4280 #define QLA_SREADING 1
4281 #define QLA_SWRITING 2
4282 uint32_t optrom_region_start;
4283 uint32_t optrom_region_size;
4284 struct mutex optrom_mutex;
4285
4286 /* PCI expansion ROM image information. */
4287 #define ROM_CODE_TYPE_BIOS 0
4288 #define ROM_CODE_TYPE_FCODE 1
4289 #define ROM_CODE_TYPE_EFI 3
4290 uint8_t bios_revision[2];
4291 uint8_t efi_revision[2];
4292 uint8_t fcode_revision[16];
4293 uint32_t fw_revision[4];
4294
4295 uint32_t gold_fw_version[4];
4296
4297 /* Offsets for flash/nvram access (set to ~0 if not used). */
4298 uint32_t flash_conf_off;
4299 uint32_t flash_data_off;
4300 uint32_t nvram_conf_off;
4301 uint32_t nvram_data_off;
4302
4303 uint32_t fdt_wrt_disable;
4304 uint32_t fdt_wrt_enable;
4305 uint32_t fdt_erase_cmd;
4306 uint32_t fdt_block_size;
4307 uint32_t fdt_unprotect_sec_cmd;
4308 uint32_t fdt_protect_sec_cmd;
4309 uint32_t fdt_wrt_sts_reg_cmd;
4310
4311 struct {
4312 uint32_t flt_region_flt;
4313 uint32_t flt_region_fdt;
4314 uint32_t flt_region_boot;
4315 uint32_t flt_region_boot_sec;
4316 uint32_t flt_region_fw;
4317 uint32_t flt_region_fw_sec;
4318 uint32_t flt_region_vpd_nvram;
4319 uint32_t flt_region_vpd_nvram_sec;
4320 uint32_t flt_region_vpd;
4321 uint32_t flt_region_vpd_sec;
4322 uint32_t flt_region_nvram;
4323 uint32_t flt_region_nvram_sec;
4324 uint32_t flt_region_npiv_conf;
4325 uint32_t flt_region_gold_fw;
4326 uint32_t flt_region_fcp_prio;
4327 uint32_t flt_region_bootload;
4328 uint32_t flt_region_img_status_pri;
4329 uint32_t flt_region_img_status_sec;
4330 uint32_t flt_region_aux_img_status_pri;
4331 uint32_t flt_region_aux_img_status_sec;
4332 };
4333 uint8_t active_image;
4334
4335 /* Needed for BEACON */
4336 uint16_t beacon_blink_led;
4337 uint8_t beacon_color_state;
4338 #define QLA_LED_GRN_ON 0x01
4339 #define QLA_LED_YLW_ON 0x02
4340 #define QLA_LED_ABR_ON 0x04
4341 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
4342 /* ISP2322: red, green, amber. */
4343 uint16_t zio_mode;
4344 uint16_t zio_timer;
4345
4346 struct qla_msix_entry *msix_entries;
4347
4348 struct list_head vp_list; /* list of VP */
4349 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
4350 sizeof(unsigned long)];
4351 uint16_t num_vhosts; /* number of vports created */
4352 uint16_t num_vsans; /* number of vsan created */
4353 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
4354 int cur_vport_count;
4355
4356 struct qla_chip_state_84xx *cs84xx;
4357 struct isp_operations *isp_ops;
4358 struct workqueue_struct *wq;
4359 struct qlfc_fw fw_buf;
4360
4361 /* FCP_CMND priority support */
4362 struct qla_fcp_prio_cfg *fcp_prio_cfg;
4363
4364 struct dma_pool *dl_dma_pool;
4365 #define DSD_LIST_DMA_POOL_SIZE 512
4366
4367 struct dma_pool *fcp_cmnd_dma_pool;
4368 mempool_t *ctx_mempool;
4369 #define FCP_CMND_DMA_POOL_SIZE 512
4370
4371 void __iomem *nx_pcibase; /* Base I/O address */
4372 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */
4373 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */
4374
4375 uint32_t crb_win;
4376 uint32_t curr_window;
4377 uint32_t ddr_mn_window;
4378 unsigned long mn_win_crb;
4379 unsigned long ms_win_crb;
4380 int qdr_sn_window;
4381 uint32_t fcoe_dev_init_timeout;
4382 uint32_t fcoe_reset_timeout;
4383 rwlock_t hw_lock;
4384 uint16_t portnum; /* port number */
4385 int link_width;
4386 struct fw_blob *hablob;
4387 struct qla82xx_legacy_intr_set nx_legacy_intr;
4388
4389 uint16_t gbl_dsd_inuse;
4390 uint16_t gbl_dsd_avail;
4391 struct list_head gbl_dsd_list;
4392 #define NUM_DSD_CHAIN 4096
4393
4394 uint8_t fw_type;
4395 __le32 file_prd_off; /* File firmware product offset */
4396
4397 uint32_t md_template_size;
4398 void *md_tmplt_hdr;
4399 dma_addr_t md_tmplt_hdr_dma;
4400 void *md_dump;
4401 uint32_t md_dump_size;
4402
4403 void *loop_id_map;
4404
4405 /* QLA83XX IDC specific fields */
4406 uint32_t idc_audit_ts;
4407 uint32_t idc_extend_tmo;
4408
4409 /* DPC low-priority workqueue */
4410 struct workqueue_struct *dpc_lp_wq;
4411 struct work_struct idc_aen;
4412 /* DPC high-priority workqueue */
4413 struct workqueue_struct *dpc_hp_wq;
4414 struct work_struct nic_core_reset;
4415 struct work_struct idc_state_handler;
4416 struct work_struct nic_core_unrecoverable;
4417 struct work_struct board_disable;
4418
4419 struct mr_data_fx00 mr;
4420 uint32_t chip_reset;
4421
4422 struct qlt_hw_data tgt;
4423 int allow_cna_fw_dump;
4424 uint32_t fw_ability_mask;
4425 uint16_t min_supported_speed;
4426 uint16_t max_supported_speed;
4427
4428 /* DMA pool for the DIF bundling buffers */
4429 struct dma_pool *dif_bundl_pool;
4430 #define DIF_BUNDLING_DMA_POOL_SIZE 1024
4431 struct {
4432 struct {
4433 struct list_head head;
4434 uint count;
4435 } good;
4436 struct {
4437 struct list_head head;
4438 uint count;
4439 } unusable;
4440 } pool;
4441
4442 unsigned long long dif_bundle_crossed_pages;
4443 unsigned long long dif_bundle_reads;
4444 unsigned long long dif_bundle_writes;
4445 unsigned long long dif_bundle_kallocs;
4446 unsigned long long dif_bundle_dma_allocs;
4447
4448 atomic_t nvme_active_aen_cnt;
4449 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */
4450
4451 uint8_t fc4_type_priority;
4452
4453 atomic_t zio_threshold;
4454 uint16_t last_zio_threshold;
4455
4456 #define DEFAULT_ZIO_THRESHOLD 5
4457 };
4458
4459 struct active_regions {
4460 uint8_t global;
4461 struct {
4462 uint8_t board_config;
4463 uint8_t vpd_nvram;
4464 uint8_t npiv_config_0_1;
4465 uint8_t npiv_config_2_3;
4466 } aux;
4467 };
4468
4469 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL
4470 #define FW_ABILITY_MAX_SPEED_16G 0x0
4471 #define FW_ABILITY_MAX_SPEED_32G 0x1
4472 #define FW_ABILITY_MAX_SPEED(ha) \
4473 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK)
4474
4475 #define QLA_GET_DATA_RATE 0
4476 #define QLA_SET_DATA_RATE_NOLR 1
4477 #define QLA_SET_DATA_RATE_LR 2 /* Set speed and initiate LR */
4478
4479 struct purex_item {
4480 struct list_head list;
4481 struct scsi_qla_host *vha;
4482 void (*process_item)(struct scsi_qla_host *vha, void *pkt);
4483 struct {
4484 uint8_t iocb[64];
4485 } iocb;
4486 };
4487
4488 /*
4489 * Qlogic scsi host structure
4490 */
4491 typedef struct scsi_qla_host {
4492 struct list_head list;
4493 struct list_head vp_fcports; /* list of fcports */
4494 struct list_head work_list;
4495 spinlock_t work_lock;
4496 struct work_struct iocb_work;
4497
4498 /* Commonly used flags and state information. */
4499 struct Scsi_Host *host;
4500 unsigned long host_no;
4501 uint8_t host_str[16];
4502
4503 volatile struct {
4504 uint32_t init_done :1;
4505 uint32_t online :1;
4506 uint32_t reset_active :1;
4507
4508 uint32_t management_server_logged_in :1;
4509 uint32_t process_response_queue :1;
4510 uint32_t difdix_supported:1;
4511 uint32_t delete_progress:1;
4512
4513 uint32_t fw_tgt_reported:1;
4514 uint32_t bbcr_enable:1;
4515 uint32_t qpairs_available:1;
4516 uint32_t qpairs_req_created:1;
4517 uint32_t qpairs_rsp_created:1;
4518 uint32_t nvme_enabled:1;
4519 uint32_t nvme_first_burst:1;
4520 } flags;
4521
4522 atomic_t loop_state;
4523 #define LOOP_TIMEOUT 1
4524 #define LOOP_DOWN 2
4525 #define LOOP_UP 3
4526 #define LOOP_UPDATE 4
4527 #define LOOP_READY 5
4528 #define LOOP_DEAD 6
4529
4530 unsigned long relogin_jif;
4531 unsigned long dpc_flags;
4532 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
4533 #define RESET_ACTIVE 1
4534 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
4535 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
4536 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
4537 #define LOOP_RESYNC_ACTIVE 5
4538 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
4539 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
4540 #define RELOGIN_NEEDED 8
4541 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
4542 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
4543 #define BEACON_BLINK_NEEDED 11
4544 #define REGISTER_FDMI_NEEDED 12
4545 #define FCPORT_UPDATE_NEEDED 13
4546 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
4547 #define UNLOADING 15
4548 #define NPIV_CONFIG_NEEDED 16
4549 #define ISP_UNRECOVERABLE 17
4550 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
4551 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
4552 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
4553 #define N2N_LINK_RESET 21
4554 #define PORT_UPDATE_NEEDED 22
4555 #define FX00_RESET_RECOVERY 23
4556 #define FX00_TARGET_SCAN 24
4557 #define FX00_CRITEMP_RECOVERY 25
4558 #define FX00_HOST_INFO_RESEND 26
4559 #define QPAIR_ONLINE_CHECK_NEEDED 27
4560 #define SET_NVME_ZIO_THRESHOLD_NEEDED 28
4561 #define DETECT_SFP_CHANGE 29
4562 #define N2N_LOGIN_NEEDED 30
4563 #define IOCB_WORK_ACTIVE 31
4564 #define SET_ZIO_THRESHOLD_NEEDED 32
4565 #define ISP_ABORT_TO_ROM 33
4566 #define VPORT_DELETE 34
4567
4568 #define PROCESS_PUREX_IOCB 63
4569
4570 unsigned long pci_flags;
4571 #define PFLG_DISCONNECTED 0 /* PCI device removed */
4572 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */
4573 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */
4574
4575 uint32_t device_flags;
4576 #define SWITCH_FOUND BIT_0
4577 #define DFLG_NO_CABLE BIT_1
4578 #define DFLG_DEV_FAILED BIT_5
4579
4580 /* ISP configuration data. */
4581 uint16_t loop_id; /* Host adapter loop id */
4582 uint16_t self_login_loop_id; /* host adapter loop id
4583 * get it on self login
4584 */
4585 fc_port_t bidir_fcport; /* fcport used for bidir cmnds
4586 * no need of allocating it for
4587 * each command
4588 */
4589
4590 port_id_t d_id; /* Host adapter port id */
4591 uint8_t marker_needed;
4592 uint16_t mgmt_svr_loop_id;
4593
4594
4595
4596 /* Timeout timers. */
4597 uint8_t loop_down_abort_time; /* port down timer */
4598 atomic_t loop_down_timer; /* loop down timer */
4599 uint8_t link_down_timeout; /* link down timeout */
4600
4601 uint32_t timer_active;
4602 struct timer_list timer;
4603
4604 uint8_t node_name[WWN_SIZE];
4605 uint8_t port_name[WWN_SIZE];
4606 uint8_t fabric_node_name[WWN_SIZE];
4607 uint8_t fabric_port_name[WWN_SIZE];
4608
4609 struct nvme_fc_local_port *nvme_local_port;
4610 struct completion nvme_del_done;
4611
4612 uint16_t fcoe_vlan_id;
4613 uint16_t fcoe_fcf_idx;
4614 uint8_t fcoe_vn_port_mac[6];
4615
4616 /* list of commands waiting on workqueue */
4617 struct list_head qla_cmd_list;
4618 struct list_head qla_sess_op_cmd_list;
4619 struct list_head unknown_atio_list;
4620 spinlock_t cmd_list_lock;
4621 struct delayed_work unknown_atio_work;
4622
4623 /* Counter to detect races between ELS and RSCN events */
4624 atomic_t generation_tick;
4625 /* Time when global fcport update has been scheduled */
4626 int total_fcport_update_gen;
4627 /* List of pending LOGOs, protected by tgt_mutex */
4628 struct list_head logo_list;
4629 /* List of pending PLOGI acks, protected by hw lock */
4630 struct list_head plogi_ack_list;
4631
4632 struct list_head qp_list;
4633
4634 uint32_t vp_abort_cnt;
4635
4636 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
4637 uint16_t vp_idx; /* vport ID */
4638 struct qla_qpair *qpair; /* base qpair */
4639
4640 unsigned long vp_flags;
4641 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
4642 #define VP_CREATE_NEEDED 1
4643 #define VP_BIND_NEEDED 2
4644 #define VP_DELETE_NEEDED 3
4645 #define VP_SCR_NEEDED 4 /* State Change Request registration */
4646 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */
4647 atomic_t vp_state;
4648 #define VP_OFFLINE 0
4649 #define VP_ACTIVE 1
4650 #define VP_FAILED 2
4651 // #define VP_DISABLE 3
4652 uint16_t vp_err_state;
4653 uint16_t vp_prev_err_state;
4654 #define VP_ERR_UNKWN 0
4655 #define VP_ERR_PORTDWN 1
4656 #define VP_ERR_FAB_UNSUPPORTED 2
4657 #define VP_ERR_FAB_NORESOURCES 3
4658 #define VP_ERR_FAB_LOGOUT 4
4659 #define VP_ERR_ADAP_NORESOURCES 5
4660 struct qla_hw_data *hw;
4661 struct scsi_qlt_host vha_tgt;
4662 struct req_que *req;
4663 int fw_heartbeat_counter;
4664 int seconds_since_last_heartbeat;
4665 struct fc_host_statistics fc_host_stat;
4666 struct qla_statistics qla_stats;
4667 struct bidi_statistics bidi_stats;
4668 atomic_t vref_count;
4669 struct qla8044_reset_template reset_tmplt;
4670 uint16_t bbcr;
4671
4672 uint16_t u_ql2xexchoffld;
4673 uint16_t u_ql2xiniexchg;
4674 uint16_t qlini_mode;
4675 uint16_t ql2xexchoffld;
4676 uint16_t ql2xiniexchg;
4677
4678 struct purex_list {
4679 struct list_head head;
4680 spinlock_t lock;
4681 } purex_list;
4682
4683 struct name_list_extended gnl;
4684 /* Count of active session/fcport */
4685 int fcport_count;
4686 wait_queue_head_t fcport_waitQ;
4687 wait_queue_head_t vref_waitq;
4688 uint8_t min_supported_speed;
4689 uint8_t n2n_node_name[WWN_SIZE];
4690 uint8_t n2n_port_name[WWN_SIZE];
4691 uint16_t n2n_id;
4692 __le16 dport_data[4];
4693 struct list_head gpnid_list;
4694 struct fab_scan scan;
4695
4696 unsigned int irq_offset;
4697 } scsi_qla_host_t;
4698
4699 struct qla27xx_image_status {
4700 uint8_t image_status_mask;
4701 uint16_t generation;
4702 uint8_t ver_major;
4703 uint8_t ver_minor;
4704 uint8_t bitmap; /* 28xx only */
4705 uint8_t reserved[2];
4706 uint32_t checksum;
4707 uint32_t signature;
4708 } __packed;
4709
4710 /* 28xx aux image status bimap values */
4711 #define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0
4712 #define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1
4713 #define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2
4714 #define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3
4715
4716 #define SET_VP_IDX 1
4717 #define SET_AL_PA 2
4718 #define RESET_VP_IDX 3
4719 #define RESET_AL_PA 4
4720 struct qla_tgt_vp_map {
4721 uint8_t idx;
4722 scsi_qla_host_t *vha;
4723 };
4724
4725 struct qla2_sgx {
4726 dma_addr_t dma_addr; /* OUT */
4727 uint32_t dma_len; /* OUT */
4728
4729 uint32_t tot_bytes; /* IN */
4730 struct scatterlist *cur_sg; /* IN */
4731
4732 /* for book keeping, bzero on initial invocation */
4733 uint32_t bytes_consumed;
4734 uint32_t num_bytes;
4735 uint32_t tot_partial;
4736
4737 /* for debugging */
4738 uint32_t num_sg;
4739 srb_t *sp;
4740 };
4741
4742 #define QLA_FW_STARTED(_ha) { \
4743 int i; \
4744 _ha->flags.fw_started = 1; \
4745 _ha->base_qpair->fw_started = 1; \
4746 for (i = 0; i < _ha->max_qpairs; i++) { \
4747 if (_ha->queue_pair_map[i]) \
4748 _ha->queue_pair_map[i]->fw_started = 1; \
4749 } \
4750 }
4751
4752 #define QLA_FW_STOPPED(_ha) { \
4753 int i; \
4754 _ha->flags.fw_started = 0; \
4755 _ha->base_qpair->fw_started = 0; \
4756 for (i = 0; i < _ha->max_qpairs; i++) { \
4757 if (_ha->queue_pair_map[i]) \
4758 _ha->queue_pair_map[i]->fw_started = 0; \
4759 } \
4760 }
4761
4762
4763 #define SFUB_CHECKSUM_SIZE 4
4764
4765 struct secure_flash_update_block {
4766 uint32_t block_info;
4767 uint32_t signature_lo;
4768 uint32_t signature_hi;
4769 uint32_t signature_upper[0x3e];
4770 };
4771
4772 struct secure_flash_update_block_pk {
4773 uint32_t block_info;
4774 uint32_t signature_lo;
4775 uint32_t signature_hi;
4776 uint32_t signature_upper[0x3e];
4777 uint32_t public_key[0x41];
4778 };
4779
4780 /*
4781 * Macros to help code, maintain, etc.
4782 */
4783 #define LOOP_TRANSITION(ha) \
4784 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4785 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
4786 atomic_read(&ha->loop_state) == LOOP_DOWN)
4787
4788 #define STATE_TRANSITION(ha) \
4789 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4790 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
4791
4792 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
4793 atomic_inc(&__vha->vref_count); \
4794 mb(); \
4795 if (__vha->flags.delete_progress) { \
4796 atomic_dec(&__vha->vref_count); \
4797 wake_up(&__vha->vref_waitq); \
4798 __bail = 1; \
4799 } else { \
4800 __bail = 0; \
4801 } \
4802 } while (0)
4803
4804 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
4805 atomic_dec(&__vha->vref_count); \
4806 wake_up(&__vha->vref_waitq); \
4807 } while (0) \
4808
4809 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
4810 atomic_inc(&__qpair->ref_count); \
4811 mb(); \
4812 if (__qpair->delete_in_progress) { \
4813 atomic_dec(&__qpair->ref_count); \
4814 __bail = 1; \
4815 } else { \
4816 __bail = 0; \
4817 } \
4818 } while (0)
4819
4820 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \
4821 atomic_dec(&__qpair->ref_count); \
4822
4823
4824 #define QLA_ENA_CONF(_ha) {\
4825 int i;\
4826 _ha->base_qpair->enable_explicit_conf = 1; \
4827 for (i = 0; i < _ha->max_qpairs; i++) { \
4828 if (_ha->queue_pair_map[i]) \
4829 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \
4830 } \
4831 }
4832
4833 #define QLA_DIS_CONF(_ha) {\
4834 int i;\
4835 _ha->base_qpair->enable_explicit_conf = 0; \
4836 for (i = 0; i < _ha->max_qpairs; i++) { \
4837 if (_ha->queue_pair_map[i]) \
4838 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \
4839 } \
4840 }
4841
4842 /*
4843 * qla2x00 local function return status codes
4844 */
4845 #define MBS_MASK 0x3fff
4846
4847 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
4848 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
4849 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
4850 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
4851 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
4852 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
4853 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
4854 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
4855 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
4856 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
4857
4858 #define QLA_FUNCTION_TIMEOUT 0x100
4859 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
4860 #define QLA_FUNCTION_FAILED 0x102
4861 #define QLA_MEMORY_ALLOC_FAILED 0x103
4862 #define QLA_LOCK_TIMEOUT 0x104
4863 #define QLA_ABORTED 0x105
4864 #define QLA_SUSPENDED 0x106
4865 #define QLA_BUSY 0x107
4866 #define QLA_ALREADY_REGISTERED 0x109
4867 #define QLA_OS_TIMER_EXPIRED 0x10a
4868
4869 #define NVRAM_DELAY() udelay(10)
4870
4871 /*
4872 * Flash support definitions
4873 */
4874 #define OPTROM_SIZE_2300 0x20000
4875 #define OPTROM_SIZE_2322 0x100000
4876 #define OPTROM_SIZE_24XX 0x100000
4877 #define OPTROM_SIZE_25XX 0x200000
4878 #define OPTROM_SIZE_81XX 0x400000
4879 #define OPTROM_SIZE_82XX 0x800000
4880 #define OPTROM_SIZE_83XX 0x1000000
4881 #define OPTROM_SIZE_28XX 0x2000000
4882
4883 #define OPTROM_BURST_SIZE 0x1000
4884 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
4885
4886 #define QLA_DSDS_PER_IOCB 37
4887
4888 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
4889
4890 #define QLA_SG_ALL 1024
4891
4892 enum nexus_wait_type {
4893 WAIT_HOST = 0,
4894 WAIT_TARGET,
4895 WAIT_LUN,
4896 };
4897
4898 /* Refer to SNIA SFF 8247 */
4899 struct sff_8247_a0 {
4900 u8 txid; /* transceiver id */
4901 u8 ext_txid;
4902 u8 connector;
4903 /* compliance code */
4904 u8 eth_infi_cc3; /* ethernet, inifiband */
4905 u8 sonet_cc4[2];
4906 u8 eth_cc6;
4907 /* link length */
4908 #define FC_LL_VL BIT_7 /* very long */
4909 #define FC_LL_S BIT_6 /* Short */
4910 #define FC_LL_I BIT_5 /* Intermidiate*/
4911 #define FC_LL_L BIT_4 /* Long */
4912 #define FC_LL_M BIT_3 /* Medium */
4913 #define FC_LL_SA BIT_2 /* ShortWave laser */
4914 #define FC_LL_LC BIT_1 /* LongWave laser */
4915 #define FC_LL_EL BIT_0 /* Electrical inter enclosure */
4916 u8 fc_ll_cc7;
4917 /* FC technology */
4918 #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */
4919 #define FC_TEC_SN BIT_6 /* short wave w/o OFC */
4920 #define FC_TEC_SL BIT_5 /* short wave with OFC */
4921 #define FC_TEC_LL BIT_4 /* Longwave Laser */
4922 #define FC_TEC_ACT BIT_3 /* Active cable */
4923 #define FC_TEC_PAS BIT_2 /* Passive cable */
4924 u8 fc_tec_cc8;
4925 /* Transmission Media */
4926 #define FC_MED_TW BIT_7 /* Twin Ax */
4927 #define FC_MED_TP BIT_6 /* Twited Pair */
4928 #define FC_MED_MI BIT_5 /* Min Coax */
4929 #define FC_MED_TV BIT_4 /* Video Coax */
4930 #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */
4931 #define FC_MED_M5 BIT_2 /* Multimode, 50um */
4932 #define FC_MED_SM BIT_0 /* Single Mode */
4933 u8 fc_med_cc9;
4934 /* speed FC_SP_12: 12*100M = 1200 MB/s */
4935 #define FC_SP_12 BIT_7
4936 #define FC_SP_8 BIT_6
4937 #define FC_SP_16 BIT_5
4938 #define FC_SP_4 BIT_4
4939 #define FC_SP_32 BIT_3
4940 #define FC_SP_2 BIT_2
4941 #define FC_SP_1 BIT_0
4942 u8 fc_sp_cc10;
4943 u8 encode;
4944 u8 bitrate;
4945 u8 rate_id;
4946 u8 length_km; /* offset 14/eh */
4947 u8 length_100m;
4948 u8 length_50um_10m;
4949 u8 length_62um_10m;
4950 u8 length_om4_10m;
4951 u8 length_om3_10m;
4952 #define SFF_VEN_NAME_LEN 16
4953 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */
4954 u8 tx_compat;
4955 u8 vendor_oui[3];
4956 #define SFF_PART_NAME_LEN 16
4957 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */
4958 u8 vendor_rev[4];
4959 u8 wavelength[2];
4960 u8 resv;
4961 u8 cc_base;
4962 u8 options[2]; /* offset 64 */
4963 u8 br_max;
4964 u8 br_min;
4965 u8 vendor_sn[16];
4966 u8 date_code[8];
4967 u8 diag;
4968 u8 enh_options;
4969 u8 sff_revision;
4970 u8 cc_ext;
4971 u8 vendor_specific[32];
4972 u8 resv2[128];
4973 };
4974
4975 /* BPM -- Buffer Plus Management support. */
4976 #define IS_BPM_CAPABLE(ha) \
4977 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4978 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4979 #define IS_BPM_RANGE_CAPABLE(ha) \
4980 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4981 #define IS_BPM_ENABLED(vha) \
4982 (ql2xautodetectsfp && !vha->vp_idx && IS_BPM_CAPABLE(vha->hw))
4983
4984 #define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016
4985
4986 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \
4987 (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha)))
4988
4989 #define SAVE_TOPO(_ha) { \
4990 if (_ha->current_topology) \
4991 _ha->prev_topology = _ha->current_topology; \
4992 }
4993
4994 #define N2N_TOPO(ha) \
4995 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \
4996 ha->current_topology == ISP_CFG_N || \
4997 !ha->current_topology)
4998
4999 #define NVME_TYPE(fcport) \
5000 (fcport->fc4_type & FS_FC4TYPE_NVME) \
5001
5002 #define FCP_TYPE(fcport) \
5003 (fcport->fc4_type & FS_FC4TYPE_FCP) \
5004
5005 #define NVME_ONLY_TARGET(fcport) \
5006 (NVME_TYPE(fcport) && !FCP_TYPE(fcport)) \
5007
5008 #define NVME_FCP_TARGET(fcport) \
5009 (FCP_TYPE(fcport) && NVME_TYPE(fcport)) \
5010
5011 #define NVME_TARGET(ha, fcport) \
5012 ((NVME_FCP_TARGET(fcport) && \
5013 (ha->fc4_type_priority == FC4_PRIORITY_NVME)) || \
5014 NVME_ONLY_TARGET(fcport)) \
5015
5016 #define PRLI_PHASE(_cls) \
5017 ((_cls == DSC_LS_PRLI_PEND) || (_cls == DSC_LS_PRLI_COMP))
5018
5019 #include "qla_target.h"
5020 #include "qla_gbl.h"
5021 #include "qla_dbg.h"
5022 #include "qla_inline.h"
5023 #endif
Linux with added FPC-III support