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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / scsi / qla2xxx / qla_nx.c
blob185c5f34d4c14757283a26395aadaf5ecb7131e3
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8 #include <linux/delay.h>
9 #include <linux/io-64-nonatomic-lo-hi.h>
10 #include <linux/pci.h>
11 #include <linux/ratelimit.h>
12 #include <linux/vmalloc.h>
13 #include <scsi/scsi_tcq.h>
14
15 #define MASK(n) ((1ULL<<(n))-1)
16 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
17 ((addr >> 25) & 0x3ff))
18 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
19 ((addr >> 25) & 0x3ff))
20 #define MS_WIN(addr) (addr & 0x0ffc0000)
21 #define QLA82XX_PCI_MN_2M (0)
22 #define QLA82XX_PCI_MS_2M (0x80000)
23 #define QLA82XX_PCI_OCM0_2M (0xc0000)
24 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
25 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
26 #define BLOCK_PROTECT_BITS 0x0F
27
28 /* CRB window related */
29 #define CRB_BLK(off) ((off >> 20) & 0x3f)
30 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
31 #define CRB_WINDOW_2M (0x130060)
32 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
33 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
34 ((off) & 0xf0000))
35 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
36 #define CRB_INDIRECT_2M (0x1e0000UL)
37
38 #define MAX_CRB_XFORM 60
39 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
40 static int qla82xx_crb_table_initialized;
41
42 #define qla82xx_crb_addr_transform(name) \
43 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
44 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
45
46 const int MD_MIU_TEST_AGT_RDDATA[] = {
47 0x410000A8, 0x410000AC,
48 0x410000B8, 0x410000BC
49 };
50
51 static void qla82xx_crb_addr_transform_setup(void)
52 {
53 qla82xx_crb_addr_transform(XDMA);
54 qla82xx_crb_addr_transform(TIMR);
55 qla82xx_crb_addr_transform(SRE);
56 qla82xx_crb_addr_transform(SQN3);
57 qla82xx_crb_addr_transform(SQN2);
58 qla82xx_crb_addr_transform(SQN1);
59 qla82xx_crb_addr_transform(SQN0);
60 qla82xx_crb_addr_transform(SQS3);
61 qla82xx_crb_addr_transform(SQS2);
62 qla82xx_crb_addr_transform(SQS1);
63 qla82xx_crb_addr_transform(SQS0);
64 qla82xx_crb_addr_transform(RPMX7);
65 qla82xx_crb_addr_transform(RPMX6);
66 qla82xx_crb_addr_transform(RPMX5);
67 qla82xx_crb_addr_transform(RPMX4);
68 qla82xx_crb_addr_transform(RPMX3);
69 qla82xx_crb_addr_transform(RPMX2);
70 qla82xx_crb_addr_transform(RPMX1);
71 qla82xx_crb_addr_transform(RPMX0);
72 qla82xx_crb_addr_transform(ROMUSB);
73 qla82xx_crb_addr_transform(SN);
74 qla82xx_crb_addr_transform(QMN);
75 qla82xx_crb_addr_transform(QMS);
76 qla82xx_crb_addr_transform(PGNI);
77 qla82xx_crb_addr_transform(PGND);
78 qla82xx_crb_addr_transform(PGN3);
79 qla82xx_crb_addr_transform(PGN2);
80 qla82xx_crb_addr_transform(PGN1);
81 qla82xx_crb_addr_transform(PGN0);
82 qla82xx_crb_addr_transform(PGSI);
83 qla82xx_crb_addr_transform(PGSD);
84 qla82xx_crb_addr_transform(PGS3);
85 qla82xx_crb_addr_transform(PGS2);
86 qla82xx_crb_addr_transform(PGS1);
87 qla82xx_crb_addr_transform(PGS0);
88 qla82xx_crb_addr_transform(PS);
89 qla82xx_crb_addr_transform(PH);
90 qla82xx_crb_addr_transform(NIU);
91 qla82xx_crb_addr_transform(I2Q);
92 qla82xx_crb_addr_transform(EG);
93 qla82xx_crb_addr_transform(MN);
94 qla82xx_crb_addr_transform(MS);
95 qla82xx_crb_addr_transform(CAS2);
96 qla82xx_crb_addr_transform(CAS1);
97 qla82xx_crb_addr_transform(CAS0);
98 qla82xx_crb_addr_transform(CAM);
99 qla82xx_crb_addr_transform(C2C1);
100 qla82xx_crb_addr_transform(C2C0);
101 qla82xx_crb_addr_transform(SMB);
102 qla82xx_crb_addr_transform(OCM0);
103 /*
104 * Used only in P3 just define it for P2 also.
105 */
106 qla82xx_crb_addr_transform(I2C0);
107
108 qla82xx_crb_table_initialized = 1;
109 }
110
111 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
112 {{{0, 0, 0, 0} } },
113 {{{1, 0x0100000, 0x0102000, 0x120000},
114 {1, 0x0110000, 0x0120000, 0x130000},
115 {1, 0x0120000, 0x0122000, 0x124000},
116 {1, 0x0130000, 0x0132000, 0x126000},
117 {1, 0x0140000, 0x0142000, 0x128000},
118 {1, 0x0150000, 0x0152000, 0x12a000},
119 {1, 0x0160000, 0x0170000, 0x110000},
120 {1, 0x0170000, 0x0172000, 0x12e000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {1, 0x01e0000, 0x01e0800, 0x122000},
128 {0, 0x0000000, 0x0000000, 0x000000} } } ,
129 {{{1, 0x0200000, 0x0210000, 0x180000} } },
130 {{{0, 0, 0, 0} } },
131 {{{1, 0x0400000, 0x0401000, 0x169000} } },
132 {{{1, 0x0500000, 0x0510000, 0x140000} } },
133 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
134 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
135 {{{1, 0x0800000, 0x0802000, 0x170000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {1, 0x08f0000, 0x08f2000, 0x172000} } },
151 {{{1, 0x0900000, 0x0902000, 0x174000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {1, 0x09f0000, 0x09f2000, 0x176000} } },
167 {{{0, 0x0a00000, 0x0a02000, 0x178000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
183 {{{0, 0x0b00000, 0x0b02000, 0x17c000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {0, 0x0000000, 0x0000000, 0x000000},
193 {0, 0x0000000, 0x0000000, 0x000000},
194 {0, 0x0000000, 0x0000000, 0x000000},
195 {0, 0x0000000, 0x0000000, 0x000000},
196 {0, 0x0000000, 0x0000000, 0x000000},
197 {0, 0x0000000, 0x0000000, 0x000000},
198 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
199 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
200 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
201 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
202 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
203 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
204 {{{1, 0x1100000, 0x1101000, 0x160000} } },
205 {{{1, 0x1200000, 0x1201000, 0x161000} } },
206 {{{1, 0x1300000, 0x1301000, 0x162000} } },
207 {{{1, 0x1400000, 0x1401000, 0x163000} } },
208 {{{1, 0x1500000, 0x1501000, 0x165000} } },
209 {{{1, 0x1600000, 0x1601000, 0x166000} } },
210 {{{0, 0, 0, 0} } },
211 {{{0, 0, 0, 0} } },
212 {{{0, 0, 0, 0} } },
213 {{{0, 0, 0, 0} } },
214 {{{0, 0, 0, 0} } },
215 {{{0, 0, 0, 0} } },
216 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
217 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
218 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
219 {{{0} } },
220 {{{1, 0x2100000, 0x2102000, 0x120000},
221 {1, 0x2110000, 0x2120000, 0x130000},
222 {1, 0x2120000, 0x2122000, 0x124000},
223 {1, 0x2130000, 0x2132000, 0x126000},
224 {1, 0x2140000, 0x2142000, 0x128000},
225 {1, 0x2150000, 0x2152000, 0x12a000},
226 {1, 0x2160000, 0x2170000, 0x110000},
227 {1, 0x2170000, 0x2172000, 0x12e000},
228 {0, 0x0000000, 0x0000000, 0x000000},
229 {0, 0x0000000, 0x0000000, 0x000000},
230 {0, 0x0000000, 0x0000000, 0x000000},
231 {0, 0x0000000, 0x0000000, 0x000000},
232 {0, 0x0000000, 0x0000000, 0x000000},
233 {0, 0x0000000, 0x0000000, 0x000000},
234 {0, 0x0000000, 0x0000000, 0x000000},
235 {0, 0x0000000, 0x0000000, 0x000000} } },
236 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
237 {{{0} } },
238 {{{0} } },
239 {{{0} } },
240 {{{0} } },
241 {{{0} } },
242 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
243 {{{1, 0x2900000, 0x2901000, 0x16b000} } },
244 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
245 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
246 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
247 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
248 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
249 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
250 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
251 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
252 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
253 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
254 {{{0} } },
255 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
256 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
257 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
258 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
259 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
260 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
261 {{{0} } },
262 {{{0} } },
263 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
264 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
265 {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
266 };
267
268 /*
269 * top 12 bits of crb internal address (hub, agent)
270 */
271 static unsigned qla82xx_crb_hub_agt[64] = {
272 0,
273 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
274 QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
275 QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
276 0,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
296 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
297 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
298 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
299 0,
300 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
301 QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
302 0,
303 QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
304 0,
305 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
306 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
307 0,
308 0,
309 0,
310 0,
311 0,
312 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
313 0,
314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
315 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
318 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
321 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
323 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
324 0,
325 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
326 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
327 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
328 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
329 0,
330 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
331 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
332 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
333 0,
334 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
335 0,
336 };
337
338 /* Device states */
339 static char *q_dev_state[] = {
340 "Unknown",
341 "Cold",
342 "Initializing",
343 "Ready",
344 "Need Reset",
345 "Need Quiescent",
346 "Failed",
347 "Quiescent",
348 };
349
350 char *qdev_state(uint32_t dev_state)
351 {
352 return q_dev_state[dev_state];
353 }
354
355 /*
356 * In: 'off_in' is offset from CRB space in 128M pci map
357 * Out: 'off_out' is 2M pci map addr
358 * side effect: lock crb window
359 */
360 static void
361 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong off_in,
362 void __iomem **off_out)
363 {
364 u32 win_read;
365 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
366
367 ha->crb_win = CRB_HI(off_in);
368 writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase);
369
370 /* Read back value to make sure write has gone through before trying
371 * to use it.
372 */
373 win_read = RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase);
374 if (win_read != ha->crb_win) {
375 ql_dbg(ql_dbg_p3p, vha, 0xb000,
376 "%s: Written crbwin (0x%x) "
377 "!= Read crbwin (0x%x), off=0x%lx.\n",
378 __func__, ha->crb_win, win_read, off_in);
379 }
380 *off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
381 }
382
383 static inline unsigned long
384 qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off)
385 {
386 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
387 /* See if we are currently pointing to the region we want to use next */
388 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) {
389 /* No need to change window. PCIX and PCIEregs are in both
390 * regs are in both windows.
391 */
392 return off;
393 }
394
395 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) {
396 /* We are in first CRB window */
397 if (ha->curr_window != 0)
398 WARN_ON(1);
399 return off;
400 }
401
402 if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) {
403 /* We are in second CRB window */
404 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST;
405
406 if (ha->curr_window != 1)
407 return off;
408
409 /* We are in the QM or direct access
410 * register region - do nothing
411 */
412 if ((off >= QLA82XX_PCI_DIRECT_CRB) &&
413 (off < QLA82XX_PCI_CAMQM_MAX))
414 return off;
415 }
416 /* strange address given */
417 ql_dbg(ql_dbg_p3p, vha, 0xb001,
418 "%s: Warning: unm_nic_pci_set_crbwindow "
419 "called with an unknown address(%llx).\n",
420 QLA2XXX_DRIVER_NAME, off);
421 return off;
422 }
423
424 static int
425 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong off_in,
426 void __iomem **off_out)
427 {
428 struct crb_128M_2M_sub_block_map *m;
429
430 if (off_in >= QLA82XX_CRB_MAX)
431 return -1;
432
433 if (off_in >= QLA82XX_PCI_CAMQM && off_in < QLA82XX_PCI_CAMQM_2M_END) {
434 *off_out = (off_in - QLA82XX_PCI_CAMQM) +
435 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
436 return 0;
437 }
438
439 if (off_in < QLA82XX_PCI_CRBSPACE)
440 return -1;
441
442 off_in -= QLA82XX_PCI_CRBSPACE;
443
444 /* Try direct map */
445 m = &crb_128M_2M_map[CRB_BLK(off_in)].sub_block[CRB_SUBBLK(off_in)];
446
447 if (m->valid && (m->start_128M <= off_in) && (m->end_128M > off_in)) {
448 *off_out = off_in + m->start_2M - m->start_128M + ha->nx_pcibase;
449 return 0;
450 }
451 /* Not in direct map, use crb window */
452 *off_out = (void __iomem *)off_in;
453 return 1;
454 }
455
456 #define CRB_WIN_LOCK_TIMEOUT 100000000
457 static int qla82xx_crb_win_lock(struct qla_hw_data *ha)
458 {
459 int done = 0, timeout = 0;
460
461 while (!done) {
462 /* acquire semaphore3 from PCI HW block */
463 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
464 if (done == 1)
465 break;
466 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
467 return -1;
468 timeout++;
469 }
470 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum);
471 return 0;
472 }
473
474 int
475 qla82xx_wr_32(struct qla_hw_data *ha, ulong off_in, u32 data)
476 {
477 void __iomem *off;
478 unsigned long flags = 0;
479 int rv;
480
481 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
482
483 BUG_ON(rv == -1);
484
485 if (rv == 1) {
486 #ifndef __CHECKER__
487 write_lock_irqsave(&ha->hw_lock, flags);
488 #endif
489 qla82xx_crb_win_lock(ha);
490 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
491 }
492
493 writel(data, (void __iomem *)off);
494
495 if (rv == 1) {
496 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
497 #ifndef __CHECKER__
498 write_unlock_irqrestore(&ha->hw_lock, flags);
499 #endif
500 }
501 return 0;
502 }
503
504 int
505 qla82xx_rd_32(struct qla_hw_data *ha, ulong off_in)
506 {
507 void __iomem *off;
508 unsigned long flags = 0;
509 int rv;
510 u32 data;
511
512 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
513
514 BUG_ON(rv == -1);
515
516 if (rv == 1) {
517 #ifndef __CHECKER__
518 write_lock_irqsave(&ha->hw_lock, flags);
519 #endif
520 qla82xx_crb_win_lock(ha);
521 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
522 }
523 data = RD_REG_DWORD(off);
524
525 if (rv == 1) {
526 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
527 #ifndef __CHECKER__
528 write_unlock_irqrestore(&ha->hw_lock, flags);
529 #endif
530 }
531 return data;
532 }
533
534 #define IDC_LOCK_TIMEOUT 100000000
535 int qla82xx_idc_lock(struct qla_hw_data *ha)
536 {
537 int i;
538 int done = 0, timeout = 0;
539
540 while (!done) {
541 /* acquire semaphore5 from PCI HW block */
542 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
543 if (done == 1)
544 break;
545 if (timeout >= IDC_LOCK_TIMEOUT)
546 return -1;
547
548 timeout++;
549
550 /* Yield CPU */
551 if (!in_interrupt())
552 schedule();
553 else {
554 for (i = 0; i < 20; i++)
555 cpu_relax();
556 }
557 }
558
559 return 0;
560 }
561
562 void qla82xx_idc_unlock(struct qla_hw_data *ha)
563 {
564 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
565 }
566
567 /*
568 * check memory access boundary.
569 * used by test agent. support ddr access only for now
570 */
571 static unsigned long
572 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha,
573 unsigned long long addr, int size)
574 {
575 if (!addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
576 QLA82XX_ADDR_DDR_NET_MAX) ||
577 !addr_in_range(addr + size - 1, QLA82XX_ADDR_DDR_NET,
578 QLA82XX_ADDR_DDR_NET_MAX) ||
579 ((size != 1) && (size != 2) && (size != 4) && (size != 8)))
580 return 0;
581 else
582 return 1;
583 }
584
585 static int qla82xx_pci_set_window_warning_count;
586
587 static unsigned long
588 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr)
589 {
590 int window;
591 u32 win_read;
592 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
593
594 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
595 QLA82XX_ADDR_DDR_NET_MAX)) {
596 /* DDR network side */
597 window = MN_WIN(addr);
598 ha->ddr_mn_window = window;
599 qla82xx_wr_32(ha,
600 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
601 win_read = qla82xx_rd_32(ha,
602 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
603 if ((win_read << 17) != window) {
604 ql_dbg(ql_dbg_p3p, vha, 0xb003,
605 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n",
606 __func__, window, win_read);
607 }
608 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
609 } else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
610 QLA82XX_ADDR_OCM0_MAX)) {
611 unsigned int temp1;
612
613 if ((addr & 0x00ff800) == 0xff800) {
614 ql_log(ql_log_warn, vha, 0xb004,
615 "%s: QM access not handled.\n", __func__);
616 addr = -1UL;
617 }
618 window = OCM_WIN(addr);
619 ha->ddr_mn_window = window;
620 qla82xx_wr_32(ha,
621 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
622 win_read = qla82xx_rd_32(ha,
623 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
624 temp1 = ((window & 0x1FF) << 7) |
625 ((window & 0x0FFFE0000) >> 17);
626 if (win_read != temp1) {
627 ql_log(ql_log_warn, vha, 0xb005,
628 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n",
629 __func__, temp1, win_read);
630 }
631 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
632
633 } else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET,
634 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
635 /* QDR network side */
636 window = MS_WIN(addr);
637 ha->qdr_sn_window = window;
638 qla82xx_wr_32(ha,
639 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window);
640 win_read = qla82xx_rd_32(ha,
641 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
642 if (win_read != window) {
643 ql_log(ql_log_warn, vha, 0xb006,
644 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n",
645 __func__, window, win_read);
646 }
647 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
648 } else {
649 /*
650 * peg gdb frequently accesses memory that doesn't exist,
651 * this limits the chit chat so debugging isn't slowed down.
652 */
653 if ((qla82xx_pci_set_window_warning_count++ < 8) ||
654 (qla82xx_pci_set_window_warning_count%64 == 0)) {
655 ql_log(ql_log_warn, vha, 0xb007,
656 "%s: Warning:%s Unknown address range!.\n",
657 __func__, QLA2XXX_DRIVER_NAME);
658 }
659 addr = -1UL;
660 }
661 return addr;
662 }
663
664 /* check if address is in the same windows as the previous access */
665 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha,
666 unsigned long long addr)
667 {
668 int window;
669 unsigned long long qdr_max;
670
671 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
672
673 /* DDR network side */
674 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
675 QLA82XX_ADDR_DDR_NET_MAX))
676 BUG();
677 else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
678 QLA82XX_ADDR_OCM0_MAX))
679 return 1;
680 else if (addr_in_range(addr, QLA82XX_ADDR_OCM1,
681 QLA82XX_ADDR_OCM1_MAX))
682 return 1;
683 else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) {
684 /* QDR network side */
685 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
686 if (ha->qdr_sn_window == window)
687 return 1;
688 }
689 return 0;
690 }
691
692 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
693 u64 off, void *data, int size)
694 {
695 unsigned long flags;
696 void __iomem *addr = NULL;
697 int ret = 0;
698 u64 start;
699 uint8_t __iomem *mem_ptr = NULL;
700 unsigned long mem_base;
701 unsigned long mem_page;
702 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
703
704 write_lock_irqsave(&ha->hw_lock, flags);
705
706 /*
707 * If attempting to access unknown address or straddle hw windows,
708 * do not access.
709 */
710 start = qla82xx_pci_set_window(ha, off);
711 if ((start == -1UL) ||
712 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
713 write_unlock_irqrestore(&ha->hw_lock, flags);
714 ql_log(ql_log_fatal, vha, 0xb008,
715 "%s out of bound pci memory "
716 "access, offset is 0x%llx.\n",
717 QLA2XXX_DRIVER_NAME, off);
718 return -1;
719 }
720
721 write_unlock_irqrestore(&ha->hw_lock, flags);
722 mem_base = pci_resource_start(ha->pdev, 0);
723 mem_page = start & PAGE_MASK;
724 /* Map two pages whenever user tries to access addresses in two
725 * consecutive pages.
726 */
727 if (mem_page != ((start + size - 1) & PAGE_MASK))
728 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
729 else
730 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
731 if (mem_ptr == NULL) {
732 *(u8 *)data = 0;
733 return -1;
734 }
735 addr = mem_ptr;
736 addr += start & (PAGE_SIZE - 1);
737 write_lock_irqsave(&ha->hw_lock, flags);
738
739 switch (size) {
740 case 1:
741 *(u8 *)data = readb(addr);
742 break;
743 case 2:
744 *(u16 *)data = readw(addr);
745 break;
746 case 4:
747 *(u32 *)data = readl(addr);
748 break;
749 case 8:
750 *(u64 *)data = readq(addr);
751 break;
752 default:
753 ret = -1;
754 break;
755 }
756 write_unlock_irqrestore(&ha->hw_lock, flags);
757
758 if (mem_ptr)
759 iounmap(mem_ptr);
760 return ret;
761 }
762
763 static int
764 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
765 u64 off, void *data, int size)
766 {
767 unsigned long flags;
768 void __iomem *addr = NULL;
769 int ret = 0;
770 u64 start;
771 uint8_t __iomem *mem_ptr = NULL;
772 unsigned long mem_base;
773 unsigned long mem_page;
774 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
775
776 write_lock_irqsave(&ha->hw_lock, flags);
777
778 /*
779 * If attempting to access unknown address or straddle hw windows,
780 * do not access.
781 */
782 start = qla82xx_pci_set_window(ha, off);
783 if ((start == -1UL) ||
784 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
785 write_unlock_irqrestore(&ha->hw_lock, flags);
786 ql_log(ql_log_fatal, vha, 0xb009,
787 "%s out of bound memory "
788 "access, offset is 0x%llx.\n",
789 QLA2XXX_DRIVER_NAME, off);
790 return -1;
791 }
792
793 write_unlock_irqrestore(&ha->hw_lock, flags);
794 mem_base = pci_resource_start(ha->pdev, 0);
795 mem_page = start & PAGE_MASK;
796 /* Map two pages whenever user tries to access addresses in two
797 * consecutive pages.
798 */
799 if (mem_page != ((start + size - 1) & PAGE_MASK))
800 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
801 else
802 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
803 if (mem_ptr == NULL)
804 return -1;
805
806 addr = mem_ptr;
807 addr += start & (PAGE_SIZE - 1);
808 write_lock_irqsave(&ha->hw_lock, flags);
809
810 switch (size) {
811 case 1:
812 writeb(*(u8 *)data, addr);
813 break;
814 case 2:
815 writew(*(u16 *)data, addr);
816 break;
817 case 4:
818 writel(*(u32 *)data, addr);
819 break;
820 case 8:
821 writeq(*(u64 *)data, addr);
822 break;
823 default:
824 ret = -1;
825 break;
826 }
827 write_unlock_irqrestore(&ha->hw_lock, flags);
828 if (mem_ptr)
829 iounmap(mem_ptr);
830 return ret;
831 }
832
833 #define MTU_FUDGE_FACTOR 100
834 static unsigned long
835 qla82xx_decode_crb_addr(unsigned long addr)
836 {
837 int i;
838 unsigned long base_addr, offset, pci_base;
839
840 if (!qla82xx_crb_table_initialized)
841 qla82xx_crb_addr_transform_setup();
842
843 pci_base = ADDR_ERROR;
844 base_addr = addr & 0xfff00000;
845 offset = addr & 0x000fffff;
846
847 for (i = 0; i < MAX_CRB_XFORM; i++) {
848 if (crb_addr_xform[i] == base_addr) {
849 pci_base = i << 20;
850 break;
851 }
852 }
853 if (pci_base == ADDR_ERROR)
854 return pci_base;
855 return pci_base + offset;
856 }
857
858 static long rom_max_timeout = 100;
859 static long qla82xx_rom_lock_timeout = 100;
860
861 static int
862 qla82xx_rom_lock(struct qla_hw_data *ha)
863 {
864 int done = 0, timeout = 0;
865 uint32_t lock_owner = 0;
866 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
867
868 while (!done) {
869 /* acquire semaphore2 from PCI HW block */
870 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
871 if (done == 1)
872 break;
873 if (timeout >= qla82xx_rom_lock_timeout) {
874 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
875 ql_dbg(ql_dbg_p3p, vha, 0xb157,
876 "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d",
877 __func__, ha->portnum, lock_owner);
878 return -1;
879 }
880 timeout++;
881 }
882 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum);
883 return 0;
884 }
885
886 static void
887 qla82xx_rom_unlock(struct qla_hw_data *ha)
888 {
889 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff);
890 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
891 }
892
893 static int
894 qla82xx_wait_rom_busy(struct qla_hw_data *ha)
895 {
896 long timeout = 0;
897 long done = 0 ;
898 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
899
900 while (done == 0) {
901 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
902 done &= 4;
903 timeout++;
904 if (timeout >= rom_max_timeout) {
905 ql_dbg(ql_dbg_p3p, vha, 0xb00a,
906 "%s: Timeout reached waiting for rom busy.\n",
907 QLA2XXX_DRIVER_NAME);
908 return -1;
909 }
910 }
911 return 0;
912 }
913
914 static int
915 qla82xx_wait_rom_done(struct qla_hw_data *ha)
916 {
917 long timeout = 0;
918 long done = 0 ;
919 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
920
921 while (done == 0) {
922 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
923 done &= 2;
924 timeout++;
925 if (timeout >= rom_max_timeout) {
926 ql_dbg(ql_dbg_p3p, vha, 0xb00b,
927 "%s: Timeout reached waiting for rom done.\n",
928 QLA2XXX_DRIVER_NAME);
929 return -1;
930 }
931 }
932 return 0;
933 }
934
935 static int
936 qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)
937 {
938 uint32_t off_value, rval = 0;
939
940 WRT_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000);
941
942 /* Read back value to make sure write has gone through */
943 RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase);
944 off_value = (off & 0x0000FFFF);
945
946 if (flag)
947 WRT_REG_DWORD(off_value + CRB_INDIRECT_2M + ha->nx_pcibase,
948 data);
949 else
950 rval = RD_REG_DWORD(off_value + CRB_INDIRECT_2M +
951 ha->nx_pcibase);
952
953 return rval;
954 }
955
956 static int
957 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
958 {
959 /* Dword reads to flash. */
960 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1);
961 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE +
962 (addr & 0x0000FFFF), 0, 0);
963
964 return 0;
965 }
966
967 static int
968 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
969 {
970 int ret, loops = 0;
971 uint32_t lock_owner = 0;
972 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
973
974 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
975 udelay(100);
976 schedule();
977 loops++;
978 }
979 if (loops >= 50000) {
980 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
981 ql_log(ql_log_fatal, vha, 0x00b9,
982 "Failed to acquire SEM2 lock, Lock Owner %u.\n",
983 lock_owner);
984 return -1;
985 }
986 ret = qla82xx_do_rom_fast_read(ha, addr, valp);
987 qla82xx_rom_unlock(ha);
988 return ret;
989 }
990
991 static int
992 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
993 {
994 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
995
996 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR);
997 qla82xx_wait_rom_busy(ha);
998 if (qla82xx_wait_rom_done(ha)) {
999 ql_log(ql_log_warn, vha, 0xb00c,
1000 "Error waiting for rom done.\n");
1001 return -1;
1002 }
1003 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
1004 return 0;
1005 }
1006
1007 static int
1008 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
1009 {
1010 long timeout = 0;
1011 uint32_t done = 1 ;
1012 uint32_t val;
1013 int ret = 0;
1014 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1015
1016 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1017 while ((done != 0) && (ret == 0)) {
1018 ret = qla82xx_read_status_reg(ha, &val);
1019 done = val & 1;
1020 timeout++;
1021 udelay(10);
1022 cond_resched();
1023 if (timeout >= 50000) {
1024 ql_log(ql_log_warn, vha, 0xb00d,
1025 "Timeout reached waiting for write finish.\n");
1026 return -1;
1027 }
1028 }
1029 return ret;
1030 }
1031
1032 static int
1033 qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
1034 {
1035 uint32_t val;
1036
1037 qla82xx_wait_rom_busy(ha);
1038 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1039 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN);
1040 qla82xx_wait_rom_busy(ha);
1041 if (qla82xx_wait_rom_done(ha))
1042 return -1;
1043 if (qla82xx_read_status_reg(ha, &val) != 0)
1044 return -1;
1045 if ((val & 2) != 2)
1046 return -1;
1047 return 0;
1048 }
1049
1050 static int
1051 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
1052 {
1053 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1054
1055 if (qla82xx_flash_set_write_enable(ha))
1056 return -1;
1057 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val);
1058 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1);
1059 if (qla82xx_wait_rom_done(ha)) {
1060 ql_log(ql_log_warn, vha, 0xb00e,
1061 "Error waiting for rom done.\n");
1062 return -1;
1063 }
1064 return qla82xx_flash_wait_write_finish(ha);
1065 }
1066
1067 static int
1068 qla82xx_write_disable_flash(struct qla_hw_data *ha)
1069 {
1070 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1071
1072 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI);
1073 if (qla82xx_wait_rom_done(ha)) {
1074 ql_log(ql_log_warn, vha, 0xb00f,
1075 "Error waiting for rom done.\n");
1076 return -1;
1077 }
1078 return 0;
1079 }
1080
1081 static int
1082 ql82xx_rom_lock_d(struct qla_hw_data *ha)
1083 {
1084 int loops = 0;
1085 uint32_t lock_owner = 0;
1086 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1087
1088 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
1089 udelay(100);
1090 cond_resched();
1091 loops++;
1092 }
1093 if (loops >= 50000) {
1094 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
1095 ql_log(ql_log_warn, vha, 0xb010,
1096 "ROM lock failed, Lock Owner %u.\n", lock_owner);
1097 return -1;
1098 }
1099 return 0;
1100 }
1101
1102 static int
1103 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr,
1104 uint32_t data)
1105 {
1106 int ret = 0;
1107 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1108
1109 ret = ql82xx_rom_lock_d(ha);
1110 if (ret < 0) {
1111 ql_log(ql_log_warn, vha, 0xb011,
1112 "ROM lock failed.\n");
1113 return ret;
1114 }
1115
1116 if (qla82xx_flash_set_write_enable(ha))
1117 goto done_write;
1118
1119 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data);
1120 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr);
1121 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
1122 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP);
1123 qla82xx_wait_rom_busy(ha);
1124 if (qla82xx_wait_rom_done(ha)) {
1125 ql_log(ql_log_warn, vha, 0xb012,
1126 "Error waiting for rom done.\n");
1127 ret = -1;
1128 goto done_write;
1129 }
1130
1131 ret = qla82xx_flash_wait_write_finish(ha);
1132
1133 done_write:
1134 qla82xx_rom_unlock(ha);
1135 return ret;
1136 }
1137
1138 /* This routine does CRB initialize sequence
1139 * to put the ISP into operational state
1140 */
1141 static int
1142 qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
1143 {
1144 int addr, val;
1145 int i ;
1146 struct crb_addr_pair *buf;
1147 unsigned long off;
1148 unsigned offset, n;
1149 struct qla_hw_data *ha = vha->hw;
1150
1151 struct crb_addr_pair {
1152 long addr;
1153 long data;
1154 };
1155
1156 /* Halt all the individual PEGs and other blocks of the ISP */
1157 qla82xx_rom_lock(ha);
1158
1159 /* disable all I2Q */
1160 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
1161 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
1162 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
1163 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
1164 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1165 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
1166
1167 /* disable all niu interrupts */
1168 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
1169 /* disable xge rx/tx */
1170 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
1171 /* disable xg1 rx/tx */
1172 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
1173 /* disable sideband mac */
1174 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
1175 /* disable ap0 mac */
1176 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
1177 /* disable ap1 mac */
1178 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
1179
1180 /* halt sre */
1181 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1182 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1183
1184 /* halt epg */
1185 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1186
1187 /* halt timers */
1188 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1189 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1190 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1191 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1192 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1193 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1194
1195 /* halt pegs */
1196 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1197 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1198 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1199 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1200 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1201 msleep(20);
1202
1203 /* big hammer */
1204 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
1205 /* don't reset CAM block on reset */
1206 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1207 else
1208 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1209 qla82xx_rom_unlock(ha);
1210
1211 /* Read the signature value from the flash.
1212 * Offset 0: Contain signature (0xcafecafe)
1213 * Offset 4: Offset and number of addr/value pairs
1214 * that present in CRB initialize sequence
1215 */
1216 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1217 qla82xx_rom_fast_read(ha, 4, &n) != 0) {
1218 ql_log(ql_log_fatal, vha, 0x006e,
1219 "Error Reading crb_init area: n: %08x.\n", n);
1220 return -1;
1221 }
1222
1223 /* Offset in flash = lower 16 bits
1224 * Number of entries = upper 16 bits
1225 */
1226 offset = n & 0xffffU;
1227 n = (n >> 16) & 0xffffU;
1228
1229 /* number of addr/value pair should not exceed 1024 entries */
1230 if (n >= 1024) {
1231 ql_log(ql_log_fatal, vha, 0x0071,
1232 "Card flash not initialized:n=0x%x.\n", n);
1233 return -1;
1234 }
1235
1236 ql_log(ql_log_info, vha, 0x0072,
1237 "%d CRB init values found in ROM.\n", n);
1238
1239 buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
1240 if (buf == NULL) {
1241 ql_log(ql_log_fatal, vha, 0x010c,
1242 "Unable to allocate memory.\n");
1243 return -ENOMEM;
1244 }
1245
1246 for (i = 0; i < n; i++) {
1247 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1248 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) {
1249 kfree(buf);
1250 return -1;
1251 }
1252
1253 buf[i].addr = addr;
1254 buf[i].data = val;
1255 }
1256
1257 for (i = 0; i < n; i++) {
1258 /* Translate internal CRB initialization
1259 * address to PCI bus address
1260 */
1261 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1262 QLA82XX_PCI_CRBSPACE;
1263 /* Not all CRB addr/value pair to be written,
1264 * some of them are skipped
1265 */
1266
1267 /* skipping cold reboot MAGIC */
1268 if (off == QLA82XX_CAM_RAM(0x1fc))
1269 continue;
1270
1271 /* do not reset PCI */
1272 if (off == (ROMUSB_GLB + 0xbc))
1273 continue;
1274
1275 /* skip core clock, so that firmware can increase the clock */
1276 if (off == (ROMUSB_GLB + 0xc8))
1277 continue;
1278
1279 /* skip the function enable register */
1280 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1281 continue;
1282
1283 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1284 continue;
1285
1286 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1287 continue;
1288
1289 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1290 continue;
1291
1292 if (off == ADDR_ERROR) {
1293 ql_log(ql_log_fatal, vha, 0x0116,
1294 "Unknown addr: 0x%08lx.\n", buf[i].addr);
1295 continue;
1296 }
1297
1298 qla82xx_wr_32(ha, off, buf[i].data);
1299
1300 /* ISP requires much bigger delay to settle down,
1301 * else crb_window returns 0xffffffff
1302 */
1303 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1304 msleep(1000);
1305
1306 /* ISP requires millisec delay between
1307 * successive CRB register updation
1308 */
1309 msleep(1);
1310 }
1311
1312 kfree(buf);
1313
1314 /* Resetting the data and instruction cache */
1315 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1316 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1317 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1318
1319 /* Clear all protocol processing engines */
1320 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1321 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1322 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1323 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1324 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1325 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1326 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1327 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1328 return 0;
1329 }
1330
1331 static int
1332 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
1333 u64 off, void *data, int size)
1334 {
1335 int i, j, ret = 0, loop, sz[2], off0;
1336 int scale, shift_amount, startword;
1337 uint32_t temp;
1338 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1339
1340 /*
1341 * If not MN, go check for MS or invalid.
1342 */
1343 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1344 mem_crb = QLA82XX_CRB_QDR_NET;
1345 else {
1346 mem_crb = QLA82XX_CRB_DDR_NET;
1347 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1348 return qla82xx_pci_mem_write_direct(ha,
1349 off, data, size);
1350 }
1351
1352 off0 = off & 0x7;
1353 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1354 sz[1] = size - sz[0];
1355
1356 off8 = off & 0xfffffff0;
1357 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1358 shift_amount = 4;
1359 scale = 2;
1360 startword = (off & 0xf)/8;
1361
1362 for (i = 0; i < loop; i++) {
1363 if (qla82xx_pci_mem_read_2M(ha, off8 +
1364 (i << shift_amount), &word[i * scale], 8))
1365 return -1;
1366 }
1367
1368 switch (size) {
1369 case 1:
1370 tmpw = *((uint8_t *)data);
1371 break;
1372 case 2:
1373 tmpw = *((uint16_t *)data);
1374 break;
1375 case 4:
1376 tmpw = *((uint32_t *)data);
1377 break;
1378 case 8:
1379 default:
1380 tmpw = *((uint64_t *)data);
1381 break;
1382 }
1383
1384 if (sz[0] == 8) {
1385 word[startword] = tmpw;
1386 } else {
1387 word[startword] &=
1388 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1389 word[startword] |= tmpw << (off0 * 8);
1390 }
1391 if (sz[1] != 0) {
1392 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1393 word[startword+1] |= tmpw >> (sz[0] * 8);
1394 }
1395
1396 for (i = 0; i < loop; i++) {
1397 temp = off8 + (i << shift_amount);
1398 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1399 temp = 0;
1400 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1401 temp = word[i * scale] & 0xffffffff;
1402 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1403 temp = (word[i * scale] >> 32) & 0xffffffff;
1404 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1405 temp = word[i*scale + 1] & 0xffffffff;
1406 qla82xx_wr_32(ha, mem_crb +
1407 MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
1408 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1409 qla82xx_wr_32(ha, mem_crb +
1410 MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
1411
1412 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1413 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1414 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1415 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1416
1417 for (j = 0; j < MAX_CTL_CHECK; j++) {
1418 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1419 if ((temp & MIU_TA_CTL_BUSY) == 0)
1420 break;
1421 }
1422
1423 if (j >= MAX_CTL_CHECK) {
1424 if (printk_ratelimit())
1425 dev_err(&ha->pdev->dev,
1426 "failed to write through agent.\n");
1427 ret = -1;
1428 break;
1429 }
1430 }
1431
1432 return ret;
1433 }
1434
1435 static int
1436 qla82xx_fw_load_from_flash(struct qla_hw_data *ha)
1437 {
1438 int i;
1439 long size = 0;
1440 long flashaddr = ha->flt_region_bootload << 2;
1441 long memaddr = BOOTLD_START;
1442 u64 data;
1443 u32 high, low;
1444
1445 size = (IMAGE_START - BOOTLD_START) / 8;
1446
1447 for (i = 0; i < size; i++) {
1448 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1449 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) {
1450 return -1;
1451 }
1452 data = ((u64)high << 32) | low ;
1453 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1454 flashaddr += 8;
1455 memaddr += 8;
1456
1457 if (i % 0x1000 == 0)
1458 msleep(1);
1459 }
1460 udelay(100);
1461 read_lock(&ha->hw_lock);
1462 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1463 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1464 read_unlock(&ha->hw_lock);
1465 return 0;
1466 }
1467
1468 int
1469 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha,
1470 u64 off, void *data, int size)
1471 {
1472 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1473 int shift_amount;
1474 uint32_t temp;
1475 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1476
1477 /*
1478 * If not MN, go check for MS or invalid.
1479 */
1480
1481 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1482 mem_crb = QLA82XX_CRB_QDR_NET;
1483 else {
1484 mem_crb = QLA82XX_CRB_DDR_NET;
1485 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1486 return qla82xx_pci_mem_read_direct(ha,
1487 off, data, size);
1488 }
1489
1490 off8 = off & 0xfffffff0;
1491 off0[0] = off & 0xf;
1492 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1493 shift_amount = 4;
1494 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1495 off0[1] = 0;
1496 sz[1] = size - sz[0];
1497
1498 for (i = 0; i < loop; i++) {
1499 temp = off8 + (i << shift_amount);
1500 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1501 temp = 0;
1502 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1503 temp = MIU_TA_CTL_ENABLE;
1504 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1505 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1506 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1507
1508 for (j = 0; j < MAX_CTL_CHECK; j++) {
1509 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1510 if ((temp & MIU_TA_CTL_BUSY) == 0)
1511 break;
1512 }
1513
1514 if (j >= MAX_CTL_CHECK) {
1515 if (printk_ratelimit())
1516 dev_err(&ha->pdev->dev,
1517 "failed to read through agent.\n");
1518 break;
1519 }
1520
1521 start = off0[i] >> 2;
1522 end = (off0[i] + sz[i] - 1) >> 2;
1523 for (k = start; k <= end; k++) {
1524 temp = qla82xx_rd_32(ha,
1525 mem_crb + MIU_TEST_AGT_RDDATA(k));
1526 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1527 }
1528 }
1529
1530 if (j >= MAX_CTL_CHECK)
1531 return -1;
1532
1533 if ((off0[0] & 7) == 0) {
1534 val = word[0];
1535 } else {
1536 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1537 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1538 }
1539
1540 switch (size) {
1541 case 1:
1542 *(uint8_t *)data = val;
1543 break;
1544 case 2:
1545 *(uint16_t *)data = val;
1546 break;
1547 case 4:
1548 *(uint32_t *)data = val;
1549 break;
1550 case 8:
1551 *(uint64_t *)data = val;
1552 break;
1553 }
1554 return 0;
1555 }
1556
1557
1558 static struct qla82xx_uri_table_desc *
1559 qla82xx_get_table_desc(const u8 *unirom, int section)
1560 {
1561 uint32_t i;
1562 struct qla82xx_uri_table_desc *directory =
1563 (struct qla82xx_uri_table_desc *)&unirom[0];
1564 __le32 offset;
1565 __le32 tab_type;
1566 __le32 entries = cpu_to_le32(directory->num_entries);
1567
1568 for (i = 0; i < entries; i++) {
1569 offset = cpu_to_le32(directory->findex) +
1570 (i * cpu_to_le32(directory->entry_size));
1571 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8));
1572
1573 if (tab_type == section)
1574 return (struct qla82xx_uri_table_desc *)&unirom[offset];
1575 }
1576
1577 return NULL;
1578 }
1579
1580 static struct qla82xx_uri_data_desc *
1581 qla82xx_get_data_desc(struct qla_hw_data *ha,
1582 u32 section, u32 idx_offset)
1583 {
1584 const u8 *unirom = ha->hablob->fw->data;
1585 int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset));
1586 struct qla82xx_uri_table_desc *tab_desc = NULL;
1587 __le32 offset;
1588
1589 tab_desc = qla82xx_get_table_desc(unirom, section);
1590 if (!tab_desc)
1591 return NULL;
1592
1593 offset = cpu_to_le32(tab_desc->findex) +
1594 (cpu_to_le32(tab_desc->entry_size) * idx);
1595
1596 return (struct qla82xx_uri_data_desc *)&unirom[offset];
1597 }
1598
1599 static u8 *
1600 qla82xx_get_bootld_offset(struct qla_hw_data *ha)
1601 {
1602 u32 offset = BOOTLD_START;
1603 struct qla82xx_uri_data_desc *uri_desc = NULL;
1604
1605 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1606 uri_desc = qla82xx_get_data_desc(ha,
1607 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF);
1608 if (uri_desc)
1609 offset = cpu_to_le32(uri_desc->findex);
1610 }
1611
1612 return (u8 *)&ha->hablob->fw->data[offset];
1613 }
1614
1615 static u32 qla82xx_get_fw_size(struct qla_hw_data *ha)
1616 {
1617 struct qla82xx_uri_data_desc *uri_desc = NULL;
1618
1619 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1620 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1621 QLA82XX_URI_FIRMWARE_IDX_OFF);
1622 if (uri_desc)
1623 return cpu_to_le32(uri_desc->size);
1624 }
1625
1626 return get_unaligned_le32(&ha->hablob->fw->data[FW_SIZE_OFFSET]);
1627 }
1628
1629 static u8 *
1630 qla82xx_get_fw_offs(struct qla_hw_data *ha)
1631 {
1632 u32 offset = IMAGE_START;
1633 struct qla82xx_uri_data_desc *uri_desc = NULL;
1634
1635 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1636 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1637 QLA82XX_URI_FIRMWARE_IDX_OFF);
1638 if (uri_desc)
1639 offset = cpu_to_le32(uri_desc->findex);
1640 }
1641
1642 return (u8 *)&ha->hablob->fw->data[offset];
1643 }
1644
1645 /* PCI related functions */
1646 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region)
1647 {
1648 unsigned long val = 0;
1649 u32 control;
1650
1651 switch (region) {
1652 case 0:
1653 val = 0;
1654 break;
1655 case 1:
1656 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control);
1657 val = control + QLA82XX_MSIX_TBL_SPACE;
1658 break;
1659 }
1660 return val;
1661 }
1662
1663
1664 int
1665 qla82xx_iospace_config(struct qla_hw_data *ha)
1666 {
1667 uint32_t len = 0;
1668
1669 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) {
1670 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c,
1671 "Failed to reserver selected regions.\n");
1672 goto iospace_error_exit;
1673 }
1674
1675 /* Use MMIO operations for all accesses. */
1676 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1677 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d,
1678 "Region #0 not an MMIO resource, aborting.\n");
1679 goto iospace_error_exit;
1680 }
1681
1682 len = pci_resource_len(ha->pdev, 0);
1683 ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len);
1684 if (!ha->nx_pcibase) {
1685 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e,
1686 "Cannot remap pcibase MMIO, aborting.\n");
1687 goto iospace_error_exit;
1688 }
1689
1690 /* Mapping of IO base pointer */
1691 if (IS_QLA8044(ha)) {
1692 ha->iobase = ha->nx_pcibase;
1693 } else if (IS_QLA82XX(ha)) {
1694 ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11);
1695 }
1696
1697 if (!ql2xdbwr) {
1698 ha->nxdb_wr_ptr = ioremap((pci_resource_start(ha->pdev, 4) +
1699 (ha->pdev->devfn << 12)), 4);
1700 if (!ha->nxdb_wr_ptr) {
1701 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f,
1702 "Cannot remap MMIO, aborting.\n");
1703 goto iospace_error_exit;
1704 }
1705
1706 /* Mapping of IO base pointer,
1707 * door bell read and write pointer
1708 */
1709 ha->nxdb_rd_ptr = ha->nx_pcibase + (512 * 1024) +
1710 (ha->pdev->devfn * 8);
1711 } else {
1712 ha->nxdb_wr_ptr = (void __iomem *)(ha->pdev->devfn == 6 ?
1713 QLA82XX_CAMRAM_DB1 :
1714 QLA82XX_CAMRAM_DB2);
1715 }
1716
1717 ha->max_req_queues = ha->max_rsp_queues = 1;
1718 ha->msix_count = ha->max_rsp_queues + 1;
1719 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006,
1720 "nx_pci_base=%p iobase=%p "
1721 "max_req_queues=%d msix_count=%d.\n",
1722 ha->nx_pcibase, ha->iobase,
1723 ha->max_req_queues, ha->msix_count);
1724 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010,
1725 "nx_pci_base=%p iobase=%p "
1726 "max_req_queues=%d msix_count=%d.\n",
1727 ha->nx_pcibase, ha->iobase,
1728 ha->max_req_queues, ha->msix_count);
1729 return 0;
1730
1731 iospace_error_exit:
1732 return -ENOMEM;
1733 }
1734
1735 /* GS related functions */
1736
1737 /* Initialization related functions */
1738
1739 /**
1740 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
1741 * @vha: HA context
1742 *
1743 * Returns 0 on success.
1744 */
1745 int
1746 qla82xx_pci_config(scsi_qla_host_t *vha)
1747 {
1748 struct qla_hw_data *ha = vha->hw;
1749 int ret;
1750
1751 pci_set_master(ha->pdev);
1752 ret = pci_set_mwi(ha->pdev);
1753 ha->chip_revision = ha->pdev->revision;
1754 ql_dbg(ql_dbg_init, vha, 0x0043,
1755 "Chip revision:%d; pci_set_mwi() returned %d.\n",
1756 ha->chip_revision, ret);
1757 return 0;
1758 }
1759
1760 /**
1761 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
1762 * @vha: HA context
1763 *
1764 * Returns 0 on success.
1765 */
1766 int
1767 qla82xx_reset_chip(scsi_qla_host_t *vha)
1768 {
1769 struct qla_hw_data *ha = vha->hw;
1770
1771 ha->isp_ops->disable_intrs(ha);
1772
1773 return QLA_SUCCESS;
1774 }
1775
1776 void qla82xx_config_rings(struct scsi_qla_host *vha)
1777 {
1778 struct qla_hw_data *ha = vha->hw;
1779 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1780 struct init_cb_81xx *icb;
1781 struct req_que *req = ha->req_q_map[0];
1782 struct rsp_que *rsp = ha->rsp_q_map[0];
1783
1784 /* Setup ring parameters in initialization control block. */
1785 icb = (struct init_cb_81xx *)ha->init_cb;
1786 icb->request_q_outpointer = cpu_to_le16(0);
1787 icb->response_q_inpointer = cpu_to_le16(0);
1788 icb->request_q_length = cpu_to_le16(req->length);
1789 icb->response_q_length = cpu_to_le16(rsp->length);
1790 put_unaligned_le64(req->dma, &icb->request_q_address);
1791 put_unaligned_le64(rsp->dma, &icb->response_q_address);
1792
1793 WRT_REG_DWORD(&reg->req_q_out[0], 0);
1794 WRT_REG_DWORD(&reg->rsp_q_in[0], 0);
1795 WRT_REG_DWORD(&reg->rsp_q_out[0], 0);
1796 }
1797
1798 static int
1799 qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
1800 {
1801 u64 *ptr64;
1802 u32 i, flashaddr, size;
1803 __le64 data;
1804
1805 size = (IMAGE_START - BOOTLD_START) / 8;
1806
1807 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha);
1808 flashaddr = BOOTLD_START;
1809
1810 for (i = 0; i < size; i++) {
1811 data = cpu_to_le64(ptr64[i]);
1812 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1813 return -EIO;
1814 flashaddr += 8;
1815 }
1816
1817 flashaddr = FLASH_ADDR_START;
1818 size = qla82xx_get_fw_size(ha) / 8;
1819 ptr64 = (u64 *)qla82xx_get_fw_offs(ha);
1820
1821 for (i = 0; i < size; i++) {
1822 data = cpu_to_le64(ptr64[i]);
1823
1824 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1825 return -EIO;
1826 flashaddr += 8;
1827 }
1828 udelay(100);
1829
1830 /* Write a magic value to CAMRAM register
1831 * at a specified offset to indicate
1832 * that all data is written and
1833 * ready for firmware to initialize.
1834 */
1835 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC);
1836
1837 read_lock(&ha->hw_lock);
1838 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1839 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1840 read_unlock(&ha->hw_lock);
1841 return 0;
1842 }
1843
1844 static int
1845 qla82xx_set_product_offset(struct qla_hw_data *ha)
1846 {
1847 struct qla82xx_uri_table_desc *ptab_desc = NULL;
1848 const uint8_t *unirom = ha->hablob->fw->data;
1849 uint32_t i;
1850 __le32 entries;
1851 __le32 flags, file_chiprev, offset;
1852 uint8_t chiprev = ha->chip_revision;
1853 /* Hardcoding mn_present flag for P3P */
1854 int mn_present = 0;
1855 uint32_t flagbit;
1856
1857 ptab_desc = qla82xx_get_table_desc(unirom,
1858 QLA82XX_URI_DIR_SECT_PRODUCT_TBL);
1859 if (!ptab_desc)
1860 return -1;
1861
1862 entries = cpu_to_le32(ptab_desc->num_entries);
1863
1864 for (i = 0; i < entries; i++) {
1865 offset = cpu_to_le32(ptab_desc->findex) +
1866 (i * cpu_to_le32(ptab_desc->entry_size));
1867 flags = cpu_to_le32(*((int *)&unirom[offset] +
1868 QLA82XX_URI_FLAGS_OFF));
1869 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] +
1870 QLA82XX_URI_CHIP_REV_OFF));
1871
1872 flagbit = mn_present ? 1 : 2;
1873
1874 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) {
1875 ha->file_prd_off = offset;
1876 return 0;
1877 }
1878 }
1879 return -1;
1880 }
1881
1882 static int
1883 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
1884 {
1885 uint32_t val;
1886 uint32_t min_size;
1887 struct qla_hw_data *ha = vha->hw;
1888 const struct firmware *fw = ha->hablob->fw;
1889
1890 ha->fw_type = fw_type;
1891
1892 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1893 if (qla82xx_set_product_offset(ha))
1894 return -EINVAL;
1895
1896 min_size = QLA82XX_URI_FW_MIN_SIZE;
1897 } else {
1898 val = get_unaligned_le32(&fw->data[QLA82XX_FW_MAGIC_OFFSET]);
1899 if (val != QLA82XX_BDINFO_MAGIC)
1900 return -EINVAL;
1901
1902 min_size = QLA82XX_FW_MIN_SIZE;
1903 }
1904
1905 if (fw->size < min_size)
1906 return -EINVAL;
1907 return 0;
1908 }
1909
1910 static int
1911 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha)
1912 {
1913 u32 val = 0;
1914 int retries = 60;
1915 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1916
1917 do {
1918 read_lock(&ha->hw_lock);
1919 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE);
1920 read_unlock(&ha->hw_lock);
1921
1922 switch (val) {
1923 case PHAN_INITIALIZE_COMPLETE:
1924 case PHAN_INITIALIZE_ACK:
1925 return QLA_SUCCESS;
1926 case PHAN_INITIALIZE_FAILED:
1927 break;
1928 default:
1929 break;
1930 }
1931 ql_log(ql_log_info, vha, 0x00a8,
1932 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n",
1933 val, retries);
1934
1935 msleep(500);
1936
1937 } while (--retries);
1938
1939 ql_log(ql_log_fatal, vha, 0x00a9,
1940 "Cmd Peg initialization failed: 0x%x.\n", val);
1941
1942 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1943 read_lock(&ha->hw_lock);
1944 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
1945 read_unlock(&ha->hw_lock);
1946 return QLA_FUNCTION_FAILED;
1947 }
1948
1949 static int
1950 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha)
1951 {
1952 u32 val = 0;
1953 int retries = 60;
1954 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1955
1956 do {
1957 read_lock(&ha->hw_lock);
1958 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE);
1959 read_unlock(&ha->hw_lock);
1960
1961 switch (val) {
1962 case PHAN_INITIALIZE_COMPLETE:
1963 case PHAN_INITIALIZE_ACK:
1964 return QLA_SUCCESS;
1965 case PHAN_INITIALIZE_FAILED:
1966 break;
1967 default:
1968 break;
1969 }
1970 ql_log(ql_log_info, vha, 0x00ab,
1971 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n",
1972 val, retries);
1973
1974 msleep(500);
1975
1976 } while (--retries);
1977
1978 ql_log(ql_log_fatal, vha, 0x00ac,
1979 "Rcv Peg initialization failed: 0x%x.\n", val);
1980 read_lock(&ha->hw_lock);
1981 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED);
1982 read_unlock(&ha->hw_lock);
1983 return QLA_FUNCTION_FAILED;
1984 }
1985
1986 /* ISR related functions */
1987 static struct qla82xx_legacy_intr_set legacy_intr[] =
1988 QLA82XX_LEGACY_INTR_CONFIG;
1989
1990 /*
1991 * qla82xx_mbx_completion() - Process mailbox command completions.
1992 * @ha: SCSI driver HA context
1993 * @mb0: Mailbox0 register
1994 */
1995 void
1996 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
1997 {
1998 uint16_t cnt;
1999 uint16_t __iomem *wptr;
2000 struct qla_hw_data *ha = vha->hw;
2001 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
2002
2003 wptr = (uint16_t __iomem *)&reg->mailbox_out[1];
2004
2005 /* Load return mailbox registers. */
2006 ha->flags.mbox_int = 1;
2007 ha->mailbox_out[0] = mb0;
2008
2009 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
2010 ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
2011 wptr++;
2012 }
2013
2014 if (!ha->mcp)
2015 ql_dbg(ql_dbg_async, vha, 0x5053,
2016 "MBX pointer ERROR.\n");
2017 }
2018
2019 /**
2020 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
2021 * @irq: interrupt number
2022 * @dev_id: SCSI driver HA context
2023 *
2024 * Called by system whenever the host adapter generates an interrupt.
2025 *
2026 * Returns handled flag.
2027 */
2028 irqreturn_t
2029 qla82xx_intr_handler(int irq, void *dev_id)
2030 {
2031 scsi_qla_host_t *vha;
2032 struct qla_hw_data *ha;
2033 struct rsp_que *rsp;
2034 struct device_reg_82xx __iomem *reg;
2035 int status = 0, status1 = 0;
2036 unsigned long flags;
2037 unsigned long iter;
2038 uint32_t stat = 0;
2039 uint16_t mb[8];
2040
2041 rsp = (struct rsp_que *) dev_id;
2042 if (!rsp) {
2043 ql_log(ql_log_info, NULL, 0xb053,
2044 "%s: NULL response queue pointer.\n", __func__);
2045 return IRQ_NONE;
2046 }
2047 ha = rsp->hw;
2048
2049 if (!ha->flags.msi_enabled) {
2050 status = qla82xx_rd_32(ha, ISR_INT_VECTOR);
2051 if (!(status & ha->nx_legacy_intr.int_vec_bit))
2052 return IRQ_NONE;
2053
2054 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG);
2055 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1))
2056 return IRQ_NONE;
2057 }
2058
2059 /* clear the interrupt */
2060 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
2061
2062 /* read twice to ensure write is flushed */
2063 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2064 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2065
2066 reg = &ha->iobase->isp82;
2067
2068 spin_lock_irqsave(&ha->hardware_lock, flags);
2069 vha = pci_get_drvdata(ha->pdev);
2070 for (iter = 1; iter--; ) {
2071
2072 if (RD_REG_DWORD(&reg->host_int)) {
2073 stat = RD_REG_DWORD(&reg->host_status);
2074
2075 switch (stat & 0xff) {
2076 case 0x1:
2077 case 0x2:
2078 case 0x10:
2079 case 0x11:
2080 qla82xx_mbx_completion(vha, MSW(stat));
2081 status |= MBX_INTERRUPT;
2082 break;
2083 case 0x12:
2084 mb[0] = MSW(stat);
2085 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2086 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2087 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2088 qla2x00_async_event(vha, rsp, mb);
2089 break;
2090 case 0x13:
2091 qla24xx_process_response_queue(vha, rsp);
2092 break;
2093 default:
2094 ql_dbg(ql_dbg_async, vha, 0x5054,
2095 "Unrecognized interrupt type (%d).\n",
2096 stat & 0xff);
2097 break;
2098 }
2099 }
2100 WRT_REG_DWORD(&reg->host_int, 0);
2101 }
2102
2103 qla2x00_handle_mbx_completion(ha, status);
2104 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2105
2106 if (!ha->flags.msi_enabled)
2107 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2108
2109 return IRQ_HANDLED;
2110 }
2111
2112 irqreturn_t
2113 qla82xx_msix_default(int irq, void *dev_id)
2114 {
2115 scsi_qla_host_t *vha;
2116 struct qla_hw_data *ha;
2117 struct rsp_que *rsp;
2118 struct device_reg_82xx __iomem *reg;
2119 int status = 0;
2120 unsigned long flags;
2121 uint32_t stat = 0;
2122 uint32_t host_int = 0;
2123 uint16_t mb[8];
2124
2125 rsp = (struct rsp_que *) dev_id;
2126 if (!rsp) {
2127 printk(KERN_INFO
2128 "%s(): NULL response queue pointer.\n", __func__);
2129 return IRQ_NONE;
2130 }
2131 ha = rsp->hw;
2132
2133 reg = &ha->iobase->isp82;
2134
2135 spin_lock_irqsave(&ha->hardware_lock, flags);
2136 vha = pci_get_drvdata(ha->pdev);
2137 do {
2138 host_int = RD_REG_DWORD(&reg->host_int);
2139 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2140 break;
2141 if (host_int) {
2142 stat = RD_REG_DWORD(&reg->host_status);
2143
2144 switch (stat & 0xff) {
2145 case 0x1:
2146 case 0x2:
2147 case 0x10:
2148 case 0x11:
2149 qla82xx_mbx_completion(vha, MSW(stat));
2150 status |= MBX_INTERRUPT;
2151 break;
2152 case 0x12:
2153 mb[0] = MSW(stat);
2154 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2155 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2156 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2157 qla2x00_async_event(vha, rsp, mb);
2158 break;
2159 case 0x13:
2160 qla24xx_process_response_queue(vha, rsp);
2161 break;
2162 default:
2163 ql_dbg(ql_dbg_async, vha, 0x5041,
2164 "Unrecognized interrupt type (%d).\n",
2165 stat & 0xff);
2166 break;
2167 }
2168 }
2169 WRT_REG_DWORD(&reg->host_int, 0);
2170 } while (0);
2171
2172 qla2x00_handle_mbx_completion(ha, status);
2173 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2174
2175 return IRQ_HANDLED;
2176 }
2177
2178 irqreturn_t
2179 qla82xx_msix_rsp_q(int irq, void *dev_id)
2180 {
2181 scsi_qla_host_t *vha;
2182 struct qla_hw_data *ha;
2183 struct rsp_que *rsp;
2184 struct device_reg_82xx __iomem *reg;
2185 unsigned long flags;
2186 uint32_t host_int = 0;
2187
2188 rsp = (struct rsp_que *) dev_id;
2189 if (!rsp) {
2190 printk(KERN_INFO
2191 "%s(): NULL response queue pointer.\n", __func__);
2192 return IRQ_NONE;
2193 }
2194
2195 ha = rsp->hw;
2196 reg = &ha->iobase->isp82;
2197 spin_lock_irqsave(&ha->hardware_lock, flags);
2198 vha = pci_get_drvdata(ha->pdev);
2199 host_int = RD_REG_DWORD(&reg->host_int);
2200 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2201 goto out;
2202 qla24xx_process_response_queue(vha, rsp);
2203 WRT_REG_DWORD(&reg->host_int, 0);
2204 out:
2205 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2206 return IRQ_HANDLED;
2207 }
2208
2209 void
2210 qla82xx_poll(int irq, void *dev_id)
2211 {
2212 scsi_qla_host_t *vha;
2213 struct qla_hw_data *ha;
2214 struct rsp_que *rsp;
2215 struct device_reg_82xx __iomem *reg;
2216 int status = 0;
2217 uint32_t stat;
2218 uint32_t host_int = 0;
2219 uint16_t mb[8];
2220 unsigned long flags;
2221
2222 rsp = (struct rsp_que *) dev_id;
2223 if (!rsp) {
2224 printk(KERN_INFO
2225 "%s(): NULL response queue pointer.\n", __func__);
2226 return;
2227 }
2228 ha = rsp->hw;
2229
2230 reg = &ha->iobase->isp82;
2231 spin_lock_irqsave(&ha->hardware_lock, flags);
2232 vha = pci_get_drvdata(ha->pdev);
2233
2234 host_int = RD_REG_DWORD(&reg->host_int);
2235 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2236 goto out;
2237 if (host_int) {
2238 stat = RD_REG_DWORD(&reg->host_status);
2239 switch (stat & 0xff) {
2240 case 0x1:
2241 case 0x2:
2242 case 0x10:
2243 case 0x11:
2244 qla82xx_mbx_completion(vha, MSW(stat));
2245 status |= MBX_INTERRUPT;
2246 break;
2247 case 0x12:
2248 mb[0] = MSW(stat);
2249 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2250 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2251 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2252 qla2x00_async_event(vha, rsp, mb);
2253 break;
2254 case 0x13:
2255 qla24xx_process_response_queue(vha, rsp);
2256 break;
2257 default:
2258 ql_dbg(ql_dbg_p3p, vha, 0xb013,
2259 "Unrecognized interrupt type (%d).\n",
2260 stat * 0xff);
2261 break;
2262 }
2263 WRT_REG_DWORD(&reg->host_int, 0);
2264 }
2265 out:
2266 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2267 }
2268
2269 void
2270 qla82xx_enable_intrs(struct qla_hw_data *ha)
2271 {
2272 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2273
2274 qla82xx_mbx_intr_enable(vha);
2275 spin_lock_irq(&ha->hardware_lock);
2276 if (IS_QLA8044(ha))
2277 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0);
2278 else
2279 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2280 spin_unlock_irq(&ha->hardware_lock);
2281 ha->interrupts_on = 1;
2282 }
2283
2284 void
2285 qla82xx_disable_intrs(struct qla_hw_data *ha)
2286 {
2287 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2288
2289 if (ha->interrupts_on)
2290 qla82xx_mbx_intr_disable(vha);
2291
2292 spin_lock_irq(&ha->hardware_lock);
2293 if (IS_QLA8044(ha))
2294 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1);
2295 else
2296 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
2297 spin_unlock_irq(&ha->hardware_lock);
2298 ha->interrupts_on = 0;
2299 }
2300
2301 void qla82xx_init_flags(struct qla_hw_data *ha)
2302 {
2303 struct qla82xx_legacy_intr_set *nx_legacy_intr;
2304
2305 /* ISP 8021 initializations */
2306 rwlock_init(&ha->hw_lock);
2307 ha->qdr_sn_window = -1;
2308 ha->ddr_mn_window = -1;
2309 ha->curr_window = 255;
2310 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2311 nx_legacy_intr = &legacy_intr[ha->portnum];
2312 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit;
2313 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg;
2314 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg;
2315 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg;
2316 }
2317
2318 static inline void
2319 qla82xx_set_idc_version(scsi_qla_host_t *vha)
2320 {
2321 int idc_ver;
2322 uint32_t drv_active;
2323 struct qla_hw_data *ha = vha->hw;
2324
2325 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2326 if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) {
2327 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
2328 QLA82XX_IDC_VERSION);
2329 ql_log(ql_log_info, vha, 0xb082,
2330 "IDC version updated to %d\n", QLA82XX_IDC_VERSION);
2331 } else {
2332 idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION);
2333 if (idc_ver != QLA82XX_IDC_VERSION)
2334 ql_log(ql_log_info, vha, 0xb083,
2335 "qla2xxx driver IDC version %d is not compatible "
2336 "with IDC version %d of the other drivers\n",
2337 QLA82XX_IDC_VERSION, idc_ver);
2338 }
2339 }
2340
2341 inline void
2342 qla82xx_set_drv_active(scsi_qla_host_t *vha)
2343 {
2344 uint32_t drv_active;
2345 struct qla_hw_data *ha = vha->hw;
2346
2347 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2348
2349 /* If reset value is all FF's, initialize DRV_ACTIVE */
2350 if (drv_active == 0xffffffff) {
2351 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE,
2352 QLA82XX_DRV_NOT_ACTIVE);
2353 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2354 }
2355 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2356 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2357 }
2358
2359 inline void
2360 qla82xx_clear_drv_active(struct qla_hw_data *ha)
2361 {
2362 uint32_t drv_active;
2363
2364 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2365 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2366 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2367 }
2368
2369 static inline int
2370 qla82xx_need_reset(struct qla_hw_data *ha)
2371 {
2372 uint32_t drv_state;
2373 int rval;
2374
2375 if (ha->flags.nic_core_reset_owner)
2376 return 1;
2377 else {
2378 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2379 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2380 return rval;
2381 }
2382 }
2383
2384 static inline void
2385 qla82xx_set_rst_ready(struct qla_hw_data *ha)
2386 {
2387 uint32_t drv_state;
2388 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2389
2390 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2391
2392 /* If reset value is all FF's, initialize DRV_STATE */
2393 if (drv_state == 0xffffffff) {
2394 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY);
2395 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2396 }
2397 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2398 ql_dbg(ql_dbg_init, vha, 0x00bb,
2399 "drv_state = 0x%08x.\n", drv_state);
2400 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2401 }
2402
2403 static inline void
2404 qla82xx_clear_rst_ready(struct qla_hw_data *ha)
2405 {
2406 uint32_t drv_state;
2407
2408 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2409 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2410 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2411 }
2412
2413 static inline void
2414 qla82xx_set_qsnt_ready(struct qla_hw_data *ha)
2415 {
2416 uint32_t qsnt_state;
2417
2418 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2419 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2420 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2421 }
2422
2423 void
2424 qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha)
2425 {
2426 struct qla_hw_data *ha = vha->hw;
2427 uint32_t qsnt_state;
2428
2429 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2430 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2431 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2432 }
2433
2434 static int
2435 qla82xx_load_fw(scsi_qla_host_t *vha)
2436 {
2437 int rst;
2438 struct fw_blob *blob;
2439 struct qla_hw_data *ha = vha->hw;
2440
2441 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) {
2442 ql_log(ql_log_fatal, vha, 0x009f,
2443 "Error during CRB initialization.\n");
2444 return QLA_FUNCTION_FAILED;
2445 }
2446 udelay(500);
2447
2448 /* Bring QM and CAMRAM out of reset */
2449 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
2450 rst &= ~((1 << 28) | (1 << 24));
2451 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
2452
2453 /*
2454 * FW Load priority:
2455 * 1) Operational firmware residing in flash.
2456 * 2) Firmware via request-firmware interface (.bin file).
2457 */
2458 if (ql2xfwloadbin == 2)
2459 goto try_blob_fw;
2460
2461 ql_log(ql_log_info, vha, 0x00a0,
2462 "Attempting to load firmware from flash.\n");
2463
2464 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) {
2465 ql_log(ql_log_info, vha, 0x00a1,
2466 "Firmware loaded successfully from flash.\n");
2467 return QLA_SUCCESS;
2468 } else {
2469 ql_log(ql_log_warn, vha, 0x0108,
2470 "Firmware load from flash failed.\n");
2471 }
2472
2473 try_blob_fw:
2474 ql_log(ql_log_info, vha, 0x00a2,
2475 "Attempting to load firmware from blob.\n");
2476
2477 /* Load firmware blob. */
2478 blob = ha->hablob = qla2x00_request_firmware(vha);
2479 if (!blob) {
2480 ql_log(ql_log_fatal, vha, 0x00a3,
2481 "Firmware image not present.\n");
2482 goto fw_load_failed;
2483 }
2484
2485 /* Validating firmware blob */
2486 if (qla82xx_validate_firmware_blob(vha,
2487 QLA82XX_FLASH_ROMIMAGE)) {
2488 /* Fallback to URI format */
2489 if (qla82xx_validate_firmware_blob(vha,
2490 QLA82XX_UNIFIED_ROMIMAGE)) {
2491 ql_log(ql_log_fatal, vha, 0x00a4,
2492 "No valid firmware image found.\n");
2493 return QLA_FUNCTION_FAILED;
2494 }
2495 }
2496
2497 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) {
2498 ql_log(ql_log_info, vha, 0x00a5,
2499 "Firmware loaded successfully from binary blob.\n");
2500 return QLA_SUCCESS;
2501 }
2502
2503 ql_log(ql_log_fatal, vha, 0x00a6,
2504 "Firmware load failed for binary blob.\n");
2505 blob->fw = NULL;
2506 blob = NULL;
2507
2508 fw_load_failed:
2509 return QLA_FUNCTION_FAILED;
2510 }
2511
2512 int
2513 qla82xx_start_firmware(scsi_qla_host_t *vha)
2514 {
2515 uint16_t lnk;
2516 struct qla_hw_data *ha = vha->hw;
2517
2518 /* scrub dma mask expansion register */
2519 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE);
2520
2521 /* Put both the PEG CMD and RCV PEG to default state
2522 * of 0 before resetting the hardware
2523 */
2524 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
2525 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
2526
2527 /* Overwrite stale initialization register values */
2528 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
2529 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
2530
2531 if (qla82xx_load_fw(vha) != QLA_SUCCESS) {
2532 ql_log(ql_log_fatal, vha, 0x00a7,
2533 "Error trying to start fw.\n");
2534 return QLA_FUNCTION_FAILED;
2535 }
2536
2537 /* Handshake with the card before we register the devices. */
2538 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) {
2539 ql_log(ql_log_fatal, vha, 0x00aa,
2540 "Error during card handshake.\n");
2541 return QLA_FUNCTION_FAILED;
2542 }
2543
2544 /* Negotiated Link width */
2545 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
2546 ha->link_width = (lnk >> 4) & 0x3f;
2547
2548 /* Synchronize with Receive peg */
2549 return qla82xx_check_rcvpeg_state(ha);
2550 }
2551
2552 static uint32_t *
2553 qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
2554 uint32_t length)
2555 {
2556 uint32_t i;
2557 uint32_t val;
2558 struct qla_hw_data *ha = vha->hw;
2559
2560 /* Dword reads to flash. */
2561 for (i = 0; i < length/4; i++, faddr += 4) {
2562 if (qla82xx_rom_fast_read(ha, faddr, &val)) {
2563 ql_log(ql_log_warn, vha, 0x0106,
2564 "Do ROM fast read failed.\n");
2565 goto done_read;
2566 }
2567 dwptr[i] = cpu_to_le32(val);
2568 }
2569 done_read:
2570 return dwptr;
2571 }
2572
2573 static int
2574 qla82xx_unprotect_flash(struct qla_hw_data *ha)
2575 {
2576 int ret;
2577 uint32_t val;
2578 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2579
2580 ret = ql82xx_rom_lock_d(ha);
2581 if (ret < 0) {
2582 ql_log(ql_log_warn, vha, 0xb014,
2583 "ROM Lock failed.\n");
2584 return ret;
2585 }
2586
2587 ret = qla82xx_read_status_reg(ha, &val);
2588 if (ret < 0)
2589 goto done_unprotect;
2590
2591 val &= ~(BLOCK_PROTECT_BITS << 2);
2592 ret = qla82xx_write_status_reg(ha, val);
2593 if (ret < 0) {
2594 val |= (BLOCK_PROTECT_BITS << 2);
2595 qla82xx_write_status_reg(ha, val);
2596 }
2597
2598 if (qla82xx_write_disable_flash(ha) != 0)
2599 ql_log(ql_log_warn, vha, 0xb015,
2600 "Write disable failed.\n");
2601
2602 done_unprotect:
2603 qla82xx_rom_unlock(ha);
2604 return ret;
2605 }
2606
2607 static int
2608 qla82xx_protect_flash(struct qla_hw_data *ha)
2609 {
2610 int ret;
2611 uint32_t val;
2612 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2613
2614 ret = ql82xx_rom_lock_d(ha);
2615 if (ret < 0) {
2616 ql_log(ql_log_warn, vha, 0xb016,
2617 "ROM Lock failed.\n");
2618 return ret;
2619 }
2620
2621 ret = qla82xx_read_status_reg(ha, &val);
2622 if (ret < 0)
2623 goto done_protect;
2624
2625 val |= (BLOCK_PROTECT_BITS << 2);
2626 /* LOCK all sectors */
2627 ret = qla82xx_write_status_reg(ha, val);
2628 if (ret < 0)
2629 ql_log(ql_log_warn, vha, 0xb017,
2630 "Write status register failed.\n");
2631
2632 if (qla82xx_write_disable_flash(ha) != 0)
2633 ql_log(ql_log_warn, vha, 0xb018,
2634 "Write disable failed.\n");
2635 done_protect:
2636 qla82xx_rom_unlock(ha);
2637 return ret;
2638 }
2639
2640 static int
2641 qla82xx_erase_sector(struct qla_hw_data *ha, int addr)
2642 {
2643 int ret = 0;
2644 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2645
2646 ret = ql82xx_rom_lock_d(ha);
2647 if (ret < 0) {
2648 ql_log(ql_log_warn, vha, 0xb019,
2649 "ROM Lock failed.\n");
2650 return ret;
2651 }
2652
2653 qla82xx_flash_set_write_enable(ha);
2654 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
2655 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
2656 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE);
2657
2658 if (qla82xx_wait_rom_done(ha)) {
2659 ql_log(ql_log_warn, vha, 0xb01a,
2660 "Error waiting for rom done.\n");
2661 ret = -1;
2662 goto done;
2663 }
2664 ret = qla82xx_flash_wait_write_finish(ha);
2665 done:
2666 qla82xx_rom_unlock(ha);
2667 return ret;
2668 }
2669
2670 /*
2671 * Address and length are byte address
2672 */
2673 void *
2674 qla82xx_read_optrom_data(struct scsi_qla_host *vha, void *buf,
2675 uint32_t offset, uint32_t length)
2676 {
2677 scsi_block_requests(vha->host);
2678 qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length);
2679 scsi_unblock_requests(vha->host);
2680 return buf;
2681 }
2682
2683 static int
2684 qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr,
2685 uint32_t faddr, uint32_t dwords)
2686 {
2687 int ret;
2688 uint32_t liter;
2689 uint32_t rest_addr;
2690 dma_addr_t optrom_dma;
2691 void *optrom = NULL;
2692 int page_mode = 0;
2693 struct qla_hw_data *ha = vha->hw;
2694
2695 ret = -1;
2696
2697 /* Prepare burst-capable write on supported ISPs. */
2698 if (page_mode && !(faddr & 0xfff) &&
2699 dwords > OPTROM_BURST_DWORDS) {
2700 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2701 &optrom_dma, GFP_KERNEL);
2702 if (!optrom) {
2703 ql_log(ql_log_warn, vha, 0xb01b,
2704 "Unable to allocate memory "
2705 "for optrom burst write (%x KB).\n",
2706 OPTROM_BURST_SIZE / 1024);
2707 }
2708 }
2709
2710 rest_addr = ha->fdt_block_size - 1;
2711
2712 ret = qla82xx_unprotect_flash(ha);
2713 if (ret) {
2714 ql_log(ql_log_warn, vha, 0xb01c,
2715 "Unable to unprotect flash for update.\n");
2716 goto write_done;
2717 }
2718
2719 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
2720 /* Are we at the beginning of a sector? */
2721 if ((faddr & rest_addr) == 0) {
2722
2723 ret = qla82xx_erase_sector(ha, faddr);
2724 if (ret) {
2725 ql_log(ql_log_warn, vha, 0xb01d,
2726 "Unable to erase sector: address=%x.\n",
2727 faddr);
2728 break;
2729 }
2730 }
2731
2732 /* Go with burst-write. */
2733 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
2734 /* Copy data to DMA'ble buffer. */
2735 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
2736
2737 ret = qla2x00_load_ram(vha, optrom_dma,
2738 (ha->flash_data_off | faddr),
2739 OPTROM_BURST_DWORDS);
2740 if (ret != QLA_SUCCESS) {
2741 ql_log(ql_log_warn, vha, 0xb01e,
2742 "Unable to burst-write optrom segment "
2743 "(%x/%x/%llx).\n", ret,
2744 (ha->flash_data_off | faddr),
2745 (unsigned long long)optrom_dma);
2746 ql_log(ql_log_warn, vha, 0xb01f,
2747 "Reverting to slow-write.\n");
2748
2749 dma_free_coherent(&ha->pdev->dev,
2750 OPTROM_BURST_SIZE, optrom, optrom_dma);
2751 optrom = NULL;
2752 } else {
2753 liter += OPTROM_BURST_DWORDS - 1;
2754 faddr += OPTROM_BURST_DWORDS - 1;
2755 dwptr += OPTROM_BURST_DWORDS - 1;
2756 continue;
2757 }
2758 }
2759
2760 ret = qla82xx_write_flash_dword(ha, faddr,
2761 cpu_to_le32(*dwptr));
2762 if (ret) {
2763 ql_dbg(ql_dbg_p3p, vha, 0xb020,
2764 "Unable to program flash address=%x data=%x.\n",
2765 faddr, *dwptr);
2766 break;
2767 }
2768 }
2769
2770 ret = qla82xx_protect_flash(ha);
2771 if (ret)
2772 ql_log(ql_log_warn, vha, 0xb021,
2773 "Unable to protect flash after update.\n");
2774 write_done:
2775 if (optrom)
2776 dma_free_coherent(&ha->pdev->dev,
2777 OPTROM_BURST_SIZE, optrom, optrom_dma);
2778 return ret;
2779 }
2780
2781 int
2782 qla82xx_write_optrom_data(struct scsi_qla_host *vha, void *buf,
2783 uint32_t offset, uint32_t length)
2784 {
2785 int rval;
2786
2787 /* Suspend HBA. */
2788 scsi_block_requests(vha->host);
2789 rval = qla82xx_write_flash_data(vha, buf, offset, length >> 2);
2790 scsi_unblock_requests(vha->host);
2791
2792 /* Convert return ISP82xx to generic */
2793 if (rval)
2794 rval = QLA_FUNCTION_FAILED;
2795 else
2796 rval = QLA_SUCCESS;
2797 return rval;
2798 }
2799
2800 void
2801 qla82xx_start_iocbs(scsi_qla_host_t *vha)
2802 {
2803 struct qla_hw_data *ha = vha->hw;
2804 struct req_que *req = ha->req_q_map[0];
2805 uint32_t dbval;
2806
2807 /* Adjust ring index. */
2808 req->ring_index++;
2809 if (req->ring_index == req->length) {
2810 req->ring_index = 0;
2811 req->ring_ptr = req->ring;
2812 } else
2813 req->ring_ptr++;
2814
2815 dbval = 0x04 | (ha->portnum << 5);
2816
2817 dbval = dbval | (req->id << 8) | (req->ring_index << 16);
2818 if (ql2xdbwr)
2819 qla82xx_wr_32(ha, (unsigned long)ha->nxdb_wr_ptr, dbval);
2820 else {
2821 WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);
2822 wmb();
2823 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) {
2824 WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);
2825 wmb();
2826 }
2827 }
2828 }
2829
2830 static void
2831 qla82xx_rom_lock_recovery(struct qla_hw_data *ha)
2832 {
2833 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2834 uint32_t lock_owner = 0;
2835
2836 if (qla82xx_rom_lock(ha)) {
2837 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
2838 /* Someone else is holding the lock. */
2839 ql_log(ql_log_info, vha, 0xb022,
2840 "Resetting rom_lock, Lock Owner %u.\n", lock_owner);
2841 }
2842 /*
2843 * Either we got the lock, or someone
2844 * else died while holding it.
2845 * In either case, unlock.
2846 */
2847 qla82xx_rom_unlock(ha);
2848 }
2849
2850 /*
2851 * qla82xx_device_bootstrap
2852 * Initialize device, set DEV_READY, start fw
2853 *
2854 * Note:
2855 * IDC lock must be held upon entry
2856 *
2857 * Return:
2858 * Success : 0
2859 * Failed : 1
2860 */
2861 static int
2862 qla82xx_device_bootstrap(scsi_qla_host_t *vha)
2863 {
2864 int rval = QLA_SUCCESS;
2865 int i;
2866 uint32_t old_count, count;
2867 struct qla_hw_data *ha = vha->hw;
2868 int need_reset = 0;
2869
2870 need_reset = qla82xx_need_reset(ha);
2871
2872 if (need_reset) {
2873 /* We are trying to perform a recovery here. */
2874 if (ha->flags.isp82xx_fw_hung)
2875 qla82xx_rom_lock_recovery(ha);
2876 } else {
2877 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2878 for (i = 0; i < 10; i++) {
2879 msleep(200);
2880 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2881 if (count != old_count) {
2882 rval = QLA_SUCCESS;
2883 goto dev_ready;
2884 }
2885 }
2886 qla82xx_rom_lock_recovery(ha);
2887 }
2888
2889 /* set to DEV_INITIALIZING */
2890 ql_log(ql_log_info, vha, 0x009e,
2891 "HW State: INITIALIZING.\n");
2892 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
2893
2894 qla82xx_idc_unlock(ha);
2895 rval = qla82xx_start_firmware(vha);
2896 qla82xx_idc_lock(ha);
2897
2898 if (rval != QLA_SUCCESS) {
2899 ql_log(ql_log_fatal, vha, 0x00ad,
2900 "HW State: FAILED.\n");
2901 qla82xx_clear_drv_active(ha);
2902 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED);
2903 return rval;
2904 }
2905
2906 dev_ready:
2907 ql_log(ql_log_info, vha, 0x00ae,
2908 "HW State: READY.\n");
2909 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
2910
2911 return QLA_SUCCESS;
2912 }
2913
2914 /*
2915 * qla82xx_need_qsnt_handler
2916 * Code to start quiescence sequence
2917 *
2918 * Note:
2919 * IDC lock must be held upon entry
2920 *
2921 * Return: void
2922 */
2923
2924 static void
2925 qla82xx_need_qsnt_handler(scsi_qla_host_t *vha)
2926 {
2927 struct qla_hw_data *ha = vha->hw;
2928 uint32_t dev_state, drv_state, drv_active;
2929 unsigned long reset_timeout;
2930
2931 if (vha->flags.online) {
2932 /*Block any further I/O and wait for pending cmnds to complete*/
2933 qla2x00_quiesce_io(vha);
2934 }
2935
2936 /* Set the quiescence ready bit */
2937 qla82xx_set_qsnt_ready(ha);
2938
2939 /*wait for 30 secs for other functions to ack */
2940 reset_timeout = jiffies + (30 * HZ);
2941
2942 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2943 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2944 /* Its 2 that is written when qsnt is acked, moving one bit */
2945 drv_active = drv_active << 0x01;
2946
2947 while (drv_state != drv_active) {
2948
2949 if (time_after_eq(jiffies, reset_timeout)) {
2950 /* quiescence timeout, other functions didn't ack
2951 * changing the state to DEV_READY
2952 */
2953 ql_log(ql_log_info, vha, 0xb023,
2954 "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d "
2955 "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME,
2956 drv_active, drv_state);
2957 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2958 QLA8XXX_DEV_READY);
2959 ql_log(ql_log_info, vha, 0xb025,
2960 "HW State: DEV_READY.\n");
2961 qla82xx_idc_unlock(ha);
2962 qla2x00_perform_loop_resync(vha);
2963 qla82xx_idc_lock(ha);
2964
2965 qla82xx_clear_qsnt_ready(vha);
2966 return;
2967 }
2968
2969 qla82xx_idc_unlock(ha);
2970 msleep(1000);
2971 qla82xx_idc_lock(ha);
2972
2973 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2974 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2975 drv_active = drv_active << 0x01;
2976 }
2977 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2978 /* everyone acked so set the state to DEV_QUIESCENCE */
2979 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
2980 ql_log(ql_log_info, vha, 0xb026,
2981 "HW State: DEV_QUIESCENT.\n");
2982 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT);
2983 }
2984 }
2985
2986 /*
2987 * qla82xx_wait_for_state_change
2988 * Wait for device state to change from given current state
2989 *
2990 * Note:
2991 * IDC lock must not be held upon entry
2992 *
2993 * Return:
2994 * Changed device state.
2995 */
2996 uint32_t
2997 qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state)
2998 {
2999 struct qla_hw_data *ha = vha->hw;
3000 uint32_t dev_state;
3001
3002 do {
3003 msleep(1000);
3004 qla82xx_idc_lock(ha);
3005 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3006 qla82xx_idc_unlock(ha);
3007 } while (dev_state == curr_state);
3008
3009 return dev_state;
3010 }
3011
3012 void
3013 qla8xxx_dev_failed_handler(scsi_qla_host_t *vha)
3014 {
3015 struct qla_hw_data *ha = vha->hw;
3016
3017 /* Disable the board */
3018 ql_log(ql_log_fatal, vha, 0x00b8,
3019 "Disabling the board.\n");
3020
3021 if (IS_QLA82XX(ha)) {
3022 qla82xx_clear_drv_active(ha);
3023 qla82xx_idc_unlock(ha);
3024 } else if (IS_QLA8044(ha)) {
3025 qla8044_clear_drv_active(ha);
3026 qla8044_idc_unlock(ha);
3027 }
3028
3029 /* Set DEV_FAILED flag to disable timer */
3030 vha->device_flags |= DFLG_DEV_FAILED;
3031 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3032 qla2x00_mark_all_devices_lost(vha);
3033 vha->flags.online = 0;
3034 vha->flags.init_done = 0;
3035 }
3036
3037 /*
3038 * qla82xx_need_reset_handler
3039 * Code to start reset sequence
3040 *
3041 * Note:
3042 * IDC lock must be held upon entry
3043 *
3044 * Return:
3045 * Success : 0
3046 * Failed : 1
3047 */
3048 static void
3049 qla82xx_need_reset_handler(scsi_qla_host_t *vha)
3050 {
3051 uint32_t dev_state, drv_state, drv_active;
3052 uint32_t active_mask = 0;
3053 unsigned long reset_timeout;
3054 struct qla_hw_data *ha = vha->hw;
3055 struct req_que *req = ha->req_q_map[0];
3056
3057 if (vha->flags.online) {
3058 qla82xx_idc_unlock(ha);
3059 qla2x00_abort_isp_cleanup(vha);
3060 ha->isp_ops->get_flash_version(vha, req->ring);
3061 ha->isp_ops->nvram_config(vha);
3062 qla82xx_idc_lock(ha);
3063 }
3064
3065 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3066 if (!ha->flags.nic_core_reset_owner) {
3067 ql_dbg(ql_dbg_p3p, vha, 0xb028,
3068 "reset_acknowledged by 0x%x\n", ha->portnum);
3069 qla82xx_set_rst_ready(ha);
3070 } else {
3071 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
3072 drv_active &= active_mask;
3073 ql_dbg(ql_dbg_p3p, vha, 0xb029,
3074 "active_mask: 0x%08x\n", active_mask);
3075 }
3076
3077 /* wait for 10 seconds for reset ack from all functions */
3078 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
3079
3080 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3081 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3082 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3083
3084 ql_dbg(ql_dbg_p3p, vha, 0xb02a,
3085 "drv_state: 0x%08x, drv_active: 0x%08x, "
3086 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3087 drv_state, drv_active, dev_state, active_mask);
3088
3089 while (drv_state != drv_active &&
3090 dev_state != QLA8XXX_DEV_INITIALIZING) {
3091 if (time_after_eq(jiffies, reset_timeout)) {
3092 ql_log(ql_log_warn, vha, 0x00b5,
3093 "Reset timeout.\n");
3094 break;
3095 }
3096 qla82xx_idc_unlock(ha);
3097 msleep(1000);
3098 qla82xx_idc_lock(ha);
3099 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3100 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3101 if (ha->flags.nic_core_reset_owner)
3102 drv_active &= active_mask;
3103 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3104 }
3105
3106 ql_dbg(ql_dbg_p3p, vha, 0xb02b,
3107 "drv_state: 0x%08x, drv_active: 0x%08x, "
3108 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3109 drv_state, drv_active, dev_state, active_mask);
3110
3111 ql_log(ql_log_info, vha, 0x00b6,
3112 "Device state is 0x%x = %s.\n",
3113 dev_state,
3114 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3115
3116 /* Force to DEV_COLD unless someone else is starting a reset */
3117 if (dev_state != QLA8XXX_DEV_INITIALIZING &&
3118 dev_state != QLA8XXX_DEV_COLD) {
3119 ql_log(ql_log_info, vha, 0x00b7,
3120 "HW State: COLD/RE-INIT.\n");
3121 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
3122 qla82xx_set_rst_ready(ha);
3123 if (ql2xmdenable) {
3124 if (qla82xx_md_collect(vha))
3125 ql_log(ql_log_warn, vha, 0xb02c,
3126 "Minidump not collected.\n");
3127 } else
3128 ql_log(ql_log_warn, vha, 0xb04f,
3129 "Minidump disabled.\n");
3130 }
3131 }
3132
3133 int
3134 qla82xx_check_md_needed(scsi_qla_host_t *vha)
3135 {
3136 struct qla_hw_data *ha = vha->hw;
3137 uint16_t fw_major_version, fw_minor_version, fw_subminor_version;
3138 int rval = QLA_SUCCESS;
3139
3140 fw_major_version = ha->fw_major_version;
3141 fw_minor_version = ha->fw_minor_version;
3142 fw_subminor_version = ha->fw_subminor_version;
3143
3144 rval = qla2x00_get_fw_version(vha);
3145 if (rval != QLA_SUCCESS)
3146 return rval;
3147
3148 if (ql2xmdenable) {
3149 if (!ha->fw_dumped) {
3150 if ((fw_major_version != ha->fw_major_version ||
3151 fw_minor_version != ha->fw_minor_version ||
3152 fw_subminor_version != ha->fw_subminor_version) ||
3153 (ha->prev_minidump_failed)) {
3154 ql_dbg(ql_dbg_p3p, vha, 0xb02d,
3155 "Firmware version differs Previous version: %d:%d:%d - New version: %d:%d:%d, prev_minidump_failed: %d.\n",
3156 fw_major_version, fw_minor_version,
3157 fw_subminor_version,
3158 ha->fw_major_version,
3159 ha->fw_minor_version,
3160 ha->fw_subminor_version,
3161 ha->prev_minidump_failed);
3162 /* Release MiniDump resources */
3163 qla82xx_md_free(vha);
3164 /* ALlocate MiniDump resources */
3165 qla82xx_md_prep(vha);
3166 }
3167 } else
3168 ql_log(ql_log_info, vha, 0xb02e,
3169 "Firmware dump available to retrieve\n");
3170 }
3171 return rval;
3172 }
3173
3174
3175 static int
3176 qla82xx_check_fw_alive(scsi_qla_host_t *vha)
3177 {
3178 uint32_t fw_heartbeat_counter;
3179 int status = 0;
3180
3181 fw_heartbeat_counter = qla82xx_rd_32(vha->hw,
3182 QLA82XX_PEG_ALIVE_COUNTER);
3183 /* all 0xff, assume AER/EEH in progress, ignore */
3184 if (fw_heartbeat_counter == 0xffffffff) {
3185 ql_dbg(ql_dbg_timer, vha, 0x6003,
3186 "FW heartbeat counter is 0xffffffff, "
3187 "returning status=%d.\n", status);
3188 return status;
3189 }
3190 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
3191 vha->seconds_since_last_heartbeat++;
3192 /* FW not alive after 2 seconds */
3193 if (vha->seconds_since_last_heartbeat == 2) {
3194 vha->seconds_since_last_heartbeat = 0;
3195 status = 1;
3196 }
3197 } else
3198 vha->seconds_since_last_heartbeat = 0;
3199 vha->fw_heartbeat_counter = fw_heartbeat_counter;
3200 if (status)
3201 ql_dbg(ql_dbg_timer, vha, 0x6004,
3202 "Returning status=%d.\n", status);
3203 return status;
3204 }
3205
3206 /*
3207 * qla82xx_device_state_handler
3208 * Main state handler
3209 *
3210 * Note:
3211 * IDC lock must be held upon entry
3212 *
3213 * Return:
3214 * Success : 0
3215 * Failed : 1
3216 */
3217 int
3218 qla82xx_device_state_handler(scsi_qla_host_t *vha)
3219 {
3220 uint32_t dev_state;
3221 uint32_t old_dev_state;
3222 int rval = QLA_SUCCESS;
3223 unsigned long dev_init_timeout;
3224 struct qla_hw_data *ha = vha->hw;
3225 int loopcount = 0;
3226
3227 qla82xx_idc_lock(ha);
3228 if (!vha->flags.init_done) {
3229 qla82xx_set_drv_active(vha);
3230 qla82xx_set_idc_version(vha);
3231 }
3232
3233 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3234 old_dev_state = dev_state;
3235 ql_log(ql_log_info, vha, 0x009b,
3236 "Device state is 0x%x = %s.\n",
3237 dev_state,
3238 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3239
3240 /* wait for 30 seconds for device to go ready */
3241 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
3242
3243 while (1) {
3244
3245 if (time_after_eq(jiffies, dev_init_timeout)) {
3246 ql_log(ql_log_fatal, vha, 0x009c,
3247 "Device init failed.\n");
3248 rval = QLA_FUNCTION_FAILED;
3249 break;
3250 }
3251 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3252 if (old_dev_state != dev_state) {
3253 loopcount = 0;
3254 old_dev_state = dev_state;
3255 }
3256 if (loopcount < 5) {
3257 ql_log(ql_log_info, vha, 0x009d,
3258 "Device state is 0x%x = %s.\n",
3259 dev_state,
3260 dev_state < MAX_STATES ? qdev_state(dev_state) :
3261 "Unknown");
3262 }
3263
3264 switch (dev_state) {
3265 case QLA8XXX_DEV_READY:
3266 ha->flags.nic_core_reset_owner = 0;
3267 goto rel_lock;
3268 case QLA8XXX_DEV_COLD:
3269 rval = qla82xx_device_bootstrap(vha);
3270 break;
3271 case QLA8XXX_DEV_INITIALIZING:
3272 qla82xx_idc_unlock(ha);
3273 msleep(1000);
3274 qla82xx_idc_lock(ha);
3275 break;
3276 case QLA8XXX_DEV_NEED_RESET:
3277 if (!ql2xdontresethba)
3278 qla82xx_need_reset_handler(vha);
3279 else {
3280 qla82xx_idc_unlock(ha);
3281 msleep(1000);
3282 qla82xx_idc_lock(ha);
3283 }
3284 dev_init_timeout = jiffies +
3285 (ha->fcoe_dev_init_timeout * HZ);
3286 break;
3287 case QLA8XXX_DEV_NEED_QUIESCENT:
3288 qla82xx_need_qsnt_handler(vha);
3289 /* Reset timeout value after quiescence handler */
3290 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout
3291 * HZ);
3292 break;
3293 case QLA8XXX_DEV_QUIESCENT:
3294 /* Owner will exit and other will wait for the state
3295 * to get changed
3296 */
3297 if (ha->flags.quiesce_owner)
3298 goto rel_lock;
3299
3300 qla82xx_idc_unlock(ha);
3301 msleep(1000);
3302 qla82xx_idc_lock(ha);
3303
3304 /* Reset timeout value after quiescence handler */
3305 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout
3306 * HZ);
3307 break;
3308 case QLA8XXX_DEV_FAILED:
3309 qla8xxx_dev_failed_handler(vha);
3310 rval = QLA_FUNCTION_FAILED;
3311 goto exit;
3312 default:
3313 qla82xx_idc_unlock(ha);
3314 msleep(1000);
3315 qla82xx_idc_lock(ha);
3316 }
3317 loopcount++;
3318 }
3319 rel_lock:
3320 qla82xx_idc_unlock(ha);
3321 exit:
3322 return rval;
3323 }
3324
3325 static int qla82xx_check_temp(scsi_qla_host_t *vha)
3326 {
3327 uint32_t temp, temp_state, temp_val;
3328 struct qla_hw_data *ha = vha->hw;
3329
3330 temp = qla82xx_rd_32(ha, CRB_TEMP_STATE);
3331 temp_state = qla82xx_get_temp_state(temp);
3332 temp_val = qla82xx_get_temp_val(temp);
3333
3334 if (temp_state == QLA82XX_TEMP_PANIC) {
3335 ql_log(ql_log_warn, vha, 0x600e,
3336 "Device temperature %d degrees C exceeds "
3337 " maximum allowed. Hardware has been shut down.\n",
3338 temp_val);
3339 return 1;
3340 } else if (temp_state == QLA82XX_TEMP_WARN) {
3341 ql_log(ql_log_warn, vha, 0x600f,
3342 "Device temperature %d degrees C exceeds "
3343 "operating range. Immediate action needed.\n",
3344 temp_val);
3345 }
3346 return 0;
3347 }
3348
3349 int qla82xx_read_temperature(scsi_qla_host_t *vha)
3350 {
3351 uint32_t temp;
3352
3353 temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE);
3354 return qla82xx_get_temp_val(temp);
3355 }
3356
3357 void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha)
3358 {
3359 struct qla_hw_data *ha = vha->hw;
3360
3361 if (ha->flags.mbox_busy) {
3362 ha->flags.mbox_int = 1;
3363 ha->flags.mbox_busy = 0;
3364 ql_log(ql_log_warn, vha, 0x6010,
3365 "Doing premature completion of mbx command.\n");
3366 if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags))
3367 complete(&ha->mbx_intr_comp);
3368 }
3369 }
3370
3371 void qla82xx_watchdog(scsi_qla_host_t *vha)
3372 {
3373 uint32_t dev_state, halt_status;
3374 struct qla_hw_data *ha = vha->hw;
3375
3376 /* don't poll if reset is going on */
3377 if (!ha->flags.nic_core_reset_hdlr_active) {
3378 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3379 if (qla82xx_check_temp(vha)) {
3380 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3381 ha->flags.isp82xx_fw_hung = 1;
3382 qla82xx_clear_pending_mbx(vha);
3383 } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
3384 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
3385 ql_log(ql_log_warn, vha, 0x6001,
3386 "Adapter reset needed.\n");
3387 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
3388 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
3389 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
3390 ql_log(ql_log_warn, vha, 0x6002,
3391 "Quiescent needed.\n");
3392 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
3393 } else if (dev_state == QLA8XXX_DEV_FAILED &&
3394 !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) &&
3395 vha->flags.online == 1) {
3396 ql_log(ql_log_warn, vha, 0xb055,
3397 "Adapter state is failed. Offlining.\n");
3398 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3399 ha->flags.isp82xx_fw_hung = 1;
3400 qla82xx_clear_pending_mbx(vha);
3401 } else {
3402 if (qla82xx_check_fw_alive(vha)) {
3403 ql_dbg(ql_dbg_timer, vha, 0x6011,
3404 "disabling pause transmit on port 0 & 1.\n");
3405 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
3406 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1);
3407 halt_status = qla82xx_rd_32(ha,
3408 QLA82XX_PEG_HALT_STATUS1);
3409 ql_log(ql_log_info, vha, 0x6005,
3410 "dumping hw/fw registers:.\n "
3411 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n "
3412 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n "
3413 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n "
3414 " PEG_NET_4_PC: 0x%x.\n", halt_status,
3415 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2),
3416 qla82xx_rd_32(ha,
3417 QLA82XX_CRB_PEG_NET_0 + 0x3c),
3418 qla82xx_rd_32(ha,
3419 QLA82XX_CRB_PEG_NET_1 + 0x3c),
3420 qla82xx_rd_32(ha,
3421 QLA82XX_CRB_PEG_NET_2 + 0x3c),
3422 qla82xx_rd_32(ha,
3423 QLA82XX_CRB_PEG_NET_3 + 0x3c),
3424 qla82xx_rd_32(ha,
3425 QLA82XX_CRB_PEG_NET_4 + 0x3c));
3426 if (((halt_status & 0x1fffff00) >> 8) == 0x67)
3427 ql_log(ql_log_warn, vha, 0xb052,
3428 "Firmware aborted with "
3429 "error code 0x00006700. Device is "
3430 "being reset.\n");
3431 if (halt_status & HALT_STATUS_UNRECOVERABLE) {
3432 set_bit(ISP_UNRECOVERABLE,
3433 &vha->dpc_flags);
3434 } else {
3435 ql_log(ql_log_info, vha, 0x6006,
3436 "Detect abort needed.\n");
3437 set_bit(ISP_ABORT_NEEDED,
3438 &vha->dpc_flags);
3439 }
3440 ha->flags.isp82xx_fw_hung = 1;
3441 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n");
3442 qla82xx_clear_pending_mbx(vha);
3443 }
3444 }
3445 }
3446 }
3447
3448 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
3449 {
3450 int rval = -1;
3451 struct qla_hw_data *ha = vha->hw;
3452
3453 if (IS_QLA82XX(ha))
3454 rval = qla82xx_device_state_handler(vha);
3455 else if (IS_QLA8044(ha)) {
3456 qla8044_idc_lock(ha);
3457 /* Decide the reset ownership */
3458 qla83xx_reset_ownership(vha);
3459 qla8044_idc_unlock(ha);
3460 rval = qla8044_device_state_handler(vha);
3461 }
3462 return rval;
3463 }
3464
3465 void
3466 qla82xx_set_reset_owner(scsi_qla_host_t *vha)
3467 {
3468 struct qla_hw_data *ha = vha->hw;
3469 uint32_t dev_state = 0;
3470
3471 if (IS_QLA82XX(ha))
3472 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3473 else if (IS_QLA8044(ha))
3474 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
3475
3476 if (dev_state == QLA8XXX_DEV_READY) {
3477 ql_log(ql_log_info, vha, 0xb02f,
3478 "HW State: NEED RESET\n");
3479 if (IS_QLA82XX(ha)) {
3480 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3481 QLA8XXX_DEV_NEED_RESET);
3482 ha->flags.nic_core_reset_owner = 1;
3483 ql_dbg(ql_dbg_p3p, vha, 0xb030,
3484 "reset_owner is 0x%x\n", ha->portnum);
3485 } else if (IS_QLA8044(ha))
3486 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
3487 QLA8XXX_DEV_NEED_RESET);
3488 } else
3489 ql_log(ql_log_info, vha, 0xb031,
3490 "Device state is 0x%x = %s.\n",
3491 dev_state,
3492 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3493 }
3494
3495 /*
3496 * qla82xx_abort_isp
3497 * Resets ISP and aborts all outstanding commands.
3498 *
3499 * Input:
3500 * ha = adapter block pointer.
3501 *
3502 * Returns:
3503 * 0 = success
3504 */
3505 int
3506 qla82xx_abort_isp(scsi_qla_host_t *vha)
3507 {
3508 int rval = -1;
3509 struct qla_hw_data *ha = vha->hw;
3510
3511 if (vha->device_flags & DFLG_DEV_FAILED) {
3512 ql_log(ql_log_warn, vha, 0x8024,
3513 "Device in failed state, exiting.\n");
3514 return QLA_SUCCESS;
3515 }
3516 ha->flags.nic_core_reset_hdlr_active = 1;
3517
3518 qla82xx_idc_lock(ha);
3519 qla82xx_set_reset_owner(vha);
3520 qla82xx_idc_unlock(ha);
3521
3522 if (IS_QLA82XX(ha))
3523 rval = qla82xx_device_state_handler(vha);
3524 else if (IS_QLA8044(ha)) {
3525 qla8044_idc_lock(ha);
3526 /* Decide the reset ownership */
3527 qla83xx_reset_ownership(vha);
3528 qla8044_idc_unlock(ha);
3529 rval = qla8044_device_state_handler(vha);
3530 }
3531
3532 qla82xx_idc_lock(ha);
3533 qla82xx_clear_rst_ready(ha);
3534 qla82xx_idc_unlock(ha);
3535
3536 if (rval == QLA_SUCCESS) {
3537 ha->flags.isp82xx_fw_hung = 0;
3538 ha->flags.nic_core_reset_hdlr_active = 0;
3539 qla82xx_restart_isp(vha);
3540 }
3541
3542 if (rval) {
3543 vha->flags.online = 1;
3544 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
3545 if (ha->isp_abort_cnt == 0) {
3546 ql_log(ql_log_warn, vha, 0x8027,
3547 "ISP error recover failed - board "
3548 "disabled.\n");
3549 /*
3550 * The next call disables the board
3551 * completely.
3552 */
3553 ha->isp_ops->reset_adapter(vha);
3554 vha->flags.online = 0;
3555 clear_bit(ISP_ABORT_RETRY,
3556 &vha->dpc_flags);
3557 rval = QLA_SUCCESS;
3558 } else { /* schedule another ISP abort */
3559 ha->isp_abort_cnt--;
3560 ql_log(ql_log_warn, vha, 0x8036,
3561 "ISP abort - retry remaining %d.\n",
3562 ha->isp_abort_cnt);
3563 rval = QLA_FUNCTION_FAILED;
3564 }
3565 } else {
3566 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
3567 ql_dbg(ql_dbg_taskm, vha, 0x8029,
3568 "ISP error recovery - retrying (%d) more times.\n",
3569 ha->isp_abort_cnt);
3570 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3571 rval = QLA_FUNCTION_FAILED;
3572 }
3573 }
3574 return rval;
3575 }
3576
3577 /*
3578 * qla82xx_fcoe_ctx_reset
3579 * Perform a quick reset and aborts all outstanding commands.
3580 * This will only perform an FCoE context reset and avoids a full blown
3581 * chip reset.
3582 *
3583 * Input:
3584 * ha = adapter block pointer.
3585 * is_reset_path = flag for identifying the reset path.
3586 *
3587 * Returns:
3588 * 0 = success
3589 */
3590 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha)
3591 {
3592 int rval = QLA_FUNCTION_FAILED;
3593
3594 if (vha->flags.online) {
3595 /* Abort all outstanding commands, so as to be requeued later */
3596 qla2x00_abort_isp_cleanup(vha);
3597 }
3598
3599 /* Stop currently executing firmware.
3600 * This will destroy existing FCoE context at the F/W end.
3601 */
3602 qla2x00_try_to_stop_firmware(vha);
3603
3604 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */
3605 rval = qla82xx_restart_isp(vha);
3606
3607 return rval;
3608 }
3609
3610 /*
3611 * qla2x00_wait_for_fcoe_ctx_reset
3612 * Wait till the FCoE context is reset.
3613 *
3614 * Note:
3615 * Does context switching here.
3616 * Release SPIN_LOCK (if any) before calling this routine.
3617 *
3618 * Return:
3619 * Success (fcoe_ctx reset is done) : 0
3620 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1
3621 */
3622 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha)
3623 {
3624 int status = QLA_FUNCTION_FAILED;
3625 unsigned long wait_reset;
3626
3627 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
3628 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
3629 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
3630 && time_before(jiffies, wait_reset)) {
3631
3632 set_current_state(TASK_UNINTERRUPTIBLE);
3633 schedule_timeout(HZ);
3634
3635 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) &&
3636 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
3637 status = QLA_SUCCESS;
3638 break;
3639 }
3640 }
3641 ql_dbg(ql_dbg_p3p, vha, 0xb027,
3642 "%s: status=%d.\n", __func__, status);
3643
3644 return status;
3645 }
3646
3647 void
3648 qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha)
3649 {
3650 int i, fw_state = 0;
3651 unsigned long flags;
3652 struct qla_hw_data *ha = vha->hw;
3653
3654 /* Check if 82XX firmware is alive or not
3655 * We may have arrived here from NEED_RESET
3656 * detection only
3657 */
3658 if (!ha->flags.isp82xx_fw_hung) {
3659 for (i = 0; i < 2; i++) {
3660 msleep(1000);
3661 if (IS_QLA82XX(ha))
3662 fw_state = qla82xx_check_fw_alive(vha);
3663 else if (IS_QLA8044(ha))
3664 fw_state = qla8044_check_fw_alive(vha);
3665 if (fw_state) {
3666 ha->flags.isp82xx_fw_hung = 1;
3667 qla82xx_clear_pending_mbx(vha);
3668 break;
3669 }
3670 }
3671 }
3672 ql_dbg(ql_dbg_init, vha, 0x00b0,
3673 "Entered %s fw_hung=%d.\n",
3674 __func__, ha->flags.isp82xx_fw_hung);
3675
3676 /* Abort all commands gracefully if fw NOT hung */
3677 if (!ha->flags.isp82xx_fw_hung) {
3678 int cnt, que;
3679 srb_t *sp;
3680 struct req_que *req;
3681
3682 spin_lock_irqsave(&ha->hardware_lock, flags);
3683 for (que = 0; que < ha->max_req_queues; que++) {
3684 req = ha->req_q_map[que];
3685 if (!req)
3686 continue;
3687 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
3688 sp = req->outstanding_cmds[cnt];
3689 if (sp) {
3690 if ((!sp->u.scmd.crc_ctx ||
3691 (sp->flags &
3692 SRB_FCP_CMND_DMA_VALID)) &&
3693 !ha->flags.isp82xx_fw_hung) {
3694 spin_unlock_irqrestore(
3695 &ha->hardware_lock, flags);
3696 if (ha->isp_ops->abort_command(sp)) {
3697 ql_log(ql_log_info, vha,
3698 0x00b1,
3699 "mbx abort failed.\n");
3700 } else {
3701 ql_log(ql_log_info, vha,
3702 0x00b2,
3703 "mbx abort success.\n");
3704 }
3705 spin_lock_irqsave(&ha->hardware_lock, flags);
3706 }
3707 }
3708 }
3709 }
3710 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3711
3712 /* Wait for pending cmds (physical and virtual) to complete */
3713 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0,
3714 WAIT_HOST) == QLA_SUCCESS) {
3715 ql_dbg(ql_dbg_init, vha, 0x00b3,
3716 "Done wait for "
3717 "pending commands.\n");
3718 } else {
3719 WARN_ON_ONCE(true);
3720 }
3721 }
3722 }
3723
3724 /* Minidump related functions */
3725 static int
3726 qla82xx_minidump_process_control(scsi_qla_host_t *vha,
3727 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3728 {
3729 struct qla_hw_data *ha = vha->hw;
3730 struct qla82xx_md_entry_crb *crb_entry;
3731 uint32_t read_value, opcode, poll_time;
3732 uint32_t addr, index, crb_addr;
3733 unsigned long wtime;
3734 struct qla82xx_md_template_hdr *tmplt_hdr;
3735 uint32_t rval = QLA_SUCCESS;
3736 int i;
3737
3738 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
3739 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr;
3740 crb_addr = crb_entry->addr;
3741
3742 for (i = 0; i < crb_entry->op_count; i++) {
3743 opcode = crb_entry->crb_ctrl.opcode;
3744 if (opcode & QLA82XX_DBG_OPCODE_WR) {
3745 qla82xx_md_rw_32(ha, crb_addr,
3746 crb_entry->value_1, 1);
3747 opcode &= ~QLA82XX_DBG_OPCODE_WR;
3748 }
3749
3750 if (opcode & QLA82XX_DBG_OPCODE_RW) {
3751 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3752 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3753 opcode &= ~QLA82XX_DBG_OPCODE_RW;
3754 }
3755
3756 if (opcode & QLA82XX_DBG_OPCODE_AND) {
3757 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3758 read_value &= crb_entry->value_2;
3759 opcode &= ~QLA82XX_DBG_OPCODE_AND;
3760 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3761 read_value |= crb_entry->value_3;
3762 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3763 }
3764 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3765 }
3766
3767 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3768 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3769 read_value |= crb_entry->value_3;
3770 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3771 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3772 }
3773
3774 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
3775 poll_time = crb_entry->crb_strd.poll_timeout;
3776 wtime = jiffies + poll_time;
3777 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3778
3779 do {
3780 if ((read_value & crb_entry->value_2)
3781 == crb_entry->value_1)
3782 break;
3783 else if (time_after_eq(jiffies, wtime)) {
3784 /* capturing dump failed */
3785 rval = QLA_FUNCTION_FAILED;
3786 break;
3787 } else
3788 read_value = qla82xx_md_rw_32(ha,
3789 crb_addr, 0, 0);
3790 } while (1);
3791 opcode &= ~QLA82XX_DBG_OPCODE_POLL;
3792 }
3793
3794 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
3795 if (crb_entry->crb_strd.state_index_a) {
3796 index = crb_entry->crb_strd.state_index_a;
3797 addr = tmplt_hdr->saved_state_array[index];
3798 } else
3799 addr = crb_addr;
3800
3801 read_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3802 index = crb_entry->crb_ctrl.state_index_v;
3803 tmplt_hdr->saved_state_array[index] = read_value;
3804 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
3805 }
3806
3807 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
3808 if (crb_entry->crb_strd.state_index_a) {
3809 index = crb_entry->crb_strd.state_index_a;
3810 addr = tmplt_hdr->saved_state_array[index];
3811 } else
3812 addr = crb_addr;
3813
3814 if (crb_entry->crb_ctrl.state_index_v) {
3815 index = crb_entry->crb_ctrl.state_index_v;
3816 read_value =
3817 tmplt_hdr->saved_state_array[index];
3818 } else
3819 read_value = crb_entry->value_1;
3820
3821 qla82xx_md_rw_32(ha, addr, read_value, 1);
3822 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
3823 }
3824
3825 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
3826 index = crb_entry->crb_ctrl.state_index_v;
3827 read_value = tmplt_hdr->saved_state_array[index];
3828 read_value <<= crb_entry->crb_ctrl.shl;
3829 read_value >>= crb_entry->crb_ctrl.shr;
3830 if (crb_entry->value_2)
3831 read_value &= crb_entry->value_2;
3832 read_value |= crb_entry->value_3;
3833 read_value += crb_entry->value_1;
3834 tmplt_hdr->saved_state_array[index] = read_value;
3835 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
3836 }
3837 crb_addr += crb_entry->crb_strd.addr_stride;
3838 }
3839 return rval;
3840 }
3841
3842 static void
3843 qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha,
3844 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3845 {
3846 struct qla_hw_data *ha = vha->hw;
3847 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3848 struct qla82xx_md_entry_rdocm *ocm_hdr;
3849 uint32_t *data_ptr = *d_ptr;
3850
3851 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr;
3852 r_addr = ocm_hdr->read_addr;
3853 r_stride = ocm_hdr->read_addr_stride;
3854 loop_cnt = ocm_hdr->op_count;
3855
3856 for (i = 0; i < loop_cnt; i++) {
3857 r_value = RD_REG_DWORD(r_addr + ha->nx_pcibase);
3858 *data_ptr++ = cpu_to_le32(r_value);
3859 r_addr += r_stride;
3860 }
3861 *d_ptr = data_ptr;
3862 }
3863
3864 static void
3865 qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha,
3866 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3867 {
3868 struct qla_hw_data *ha = vha->hw;
3869 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
3870 struct qla82xx_md_entry_mux *mux_hdr;
3871 uint32_t *data_ptr = *d_ptr;
3872
3873 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr;
3874 r_addr = mux_hdr->read_addr;
3875 s_addr = mux_hdr->select_addr;
3876 s_stride = mux_hdr->select_value_stride;
3877 s_value = mux_hdr->select_value;
3878 loop_cnt = mux_hdr->op_count;
3879
3880 for (i = 0; i < loop_cnt; i++) {
3881 qla82xx_md_rw_32(ha, s_addr, s_value, 1);
3882 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3883 *data_ptr++ = cpu_to_le32(s_value);
3884 *data_ptr++ = cpu_to_le32(r_value);
3885 s_value += s_stride;
3886 }
3887 *d_ptr = data_ptr;
3888 }
3889
3890 static void
3891 qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha,
3892 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3893 {
3894 struct qla_hw_data *ha = vha->hw;
3895 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3896 struct qla82xx_md_entry_crb *crb_hdr;
3897 uint32_t *data_ptr = *d_ptr;
3898
3899 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr;
3900 r_addr = crb_hdr->addr;
3901 r_stride = crb_hdr->crb_strd.addr_stride;
3902 loop_cnt = crb_hdr->op_count;
3903
3904 for (i = 0; i < loop_cnt; i++) {
3905 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3906 *data_ptr++ = cpu_to_le32(r_addr);
3907 *data_ptr++ = cpu_to_le32(r_value);
3908 r_addr += r_stride;
3909 }
3910 *d_ptr = data_ptr;
3911 }
3912
3913 static int
3914 qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha,
3915 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3916 {
3917 struct qla_hw_data *ha = vha->hw;
3918 uint32_t addr, r_addr, c_addr, t_r_addr;
3919 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3920 unsigned long p_wait, w_time, p_mask;
3921 uint32_t c_value_w, c_value_r;
3922 struct qla82xx_md_entry_cache *cache_hdr;
3923 int rval = QLA_FUNCTION_FAILED;
3924 uint32_t *data_ptr = *d_ptr;
3925
3926 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3927 loop_count = cache_hdr->op_count;
3928 r_addr = cache_hdr->read_addr;
3929 c_addr = cache_hdr->control_addr;
3930 c_value_w = cache_hdr->cache_ctrl.write_value;
3931
3932 t_r_addr = cache_hdr->tag_reg_addr;
3933 t_value = cache_hdr->addr_ctrl.init_tag_value;
3934 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3935 p_wait = cache_hdr->cache_ctrl.poll_wait;
3936 p_mask = cache_hdr->cache_ctrl.poll_mask;
3937
3938 for (i = 0; i < loop_count; i++) {
3939 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3940 if (c_value_w)
3941 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3942
3943 if (p_mask) {
3944 w_time = jiffies + p_wait;
3945 do {
3946 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0);
3947 if ((c_value_r & p_mask) == 0)
3948 break;
3949 else if (time_after_eq(jiffies, w_time)) {
3950 /* capturing dump failed */
3951 ql_dbg(ql_dbg_p3p, vha, 0xb032,
3952 "c_value_r: 0x%x, poll_mask: 0x%lx, "
3953 "w_time: 0x%lx\n",
3954 c_value_r, p_mask, w_time);
3955 return rval;
3956 }
3957 } while (1);
3958 }
3959
3960 addr = r_addr;
3961 for (k = 0; k < r_cnt; k++) {
3962 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3963 *data_ptr++ = cpu_to_le32(r_value);
3964 addr += cache_hdr->read_ctrl.read_addr_stride;
3965 }
3966 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3967 }
3968 *d_ptr = data_ptr;
3969 return QLA_SUCCESS;
3970 }
3971
3972 static void
3973 qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha,
3974 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3975 {
3976 struct qla_hw_data *ha = vha->hw;
3977 uint32_t addr, r_addr, c_addr, t_r_addr;
3978 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3979 uint32_t c_value_w;
3980 struct qla82xx_md_entry_cache *cache_hdr;
3981 uint32_t *data_ptr = *d_ptr;
3982
3983 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3984 loop_count = cache_hdr->op_count;
3985 r_addr = cache_hdr->read_addr;
3986 c_addr = cache_hdr->control_addr;
3987 c_value_w = cache_hdr->cache_ctrl.write_value;
3988
3989 t_r_addr = cache_hdr->tag_reg_addr;
3990 t_value = cache_hdr->addr_ctrl.init_tag_value;
3991 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3992
3993 for (i = 0; i < loop_count; i++) {
3994 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3995 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3996 addr = r_addr;
3997 for (k = 0; k < r_cnt; k++) {
3998 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3999 *data_ptr++ = cpu_to_le32(r_value);
4000 addr += cache_hdr->read_ctrl.read_addr_stride;
4001 }
4002 t_value += cache_hdr->addr_ctrl.tag_value_stride;
4003 }
4004 *d_ptr = data_ptr;
4005 }
4006
4007 static void
4008 qla82xx_minidump_process_queue(scsi_qla_host_t *vha,
4009 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4010 {
4011 struct qla_hw_data *ha = vha->hw;
4012 uint32_t s_addr, r_addr;
4013 uint32_t r_stride, r_value, r_cnt, qid = 0;
4014 uint32_t i, k, loop_cnt;
4015 struct qla82xx_md_entry_queue *q_hdr;
4016 uint32_t *data_ptr = *d_ptr;
4017
4018 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr;
4019 s_addr = q_hdr->select_addr;
4020 r_cnt = q_hdr->rd_strd.read_addr_cnt;
4021 r_stride = q_hdr->rd_strd.read_addr_stride;
4022 loop_cnt = q_hdr->op_count;
4023
4024 for (i = 0; i < loop_cnt; i++) {
4025 qla82xx_md_rw_32(ha, s_addr, qid, 1);
4026 r_addr = q_hdr->read_addr;
4027 for (k = 0; k < r_cnt; k++) {
4028 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
4029 *data_ptr++ = cpu_to_le32(r_value);
4030 r_addr += r_stride;
4031 }
4032 qid += q_hdr->q_strd.queue_id_stride;
4033 }
4034 *d_ptr = data_ptr;
4035 }
4036
4037 static void
4038 qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha,
4039 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4040 {
4041 struct qla_hw_data *ha = vha->hw;
4042 uint32_t r_addr, r_value;
4043 uint32_t i, loop_cnt;
4044 struct qla82xx_md_entry_rdrom *rom_hdr;
4045 uint32_t *data_ptr = *d_ptr;
4046
4047 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr;
4048 r_addr = rom_hdr->read_addr;
4049 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
4050
4051 for (i = 0; i < loop_cnt; i++) {
4052 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW,
4053 (r_addr & 0xFFFF0000), 1);
4054 r_value = qla82xx_md_rw_32(ha,
4055 MD_DIRECT_ROM_READ_BASE +
4056 (r_addr & 0x0000FFFF), 0, 0);
4057 *data_ptr++ = cpu_to_le32(r_value);
4058 r_addr += sizeof(uint32_t);
4059 }
4060 *d_ptr = data_ptr;
4061 }
4062
4063 static int
4064 qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha,
4065 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4066 {
4067 struct qla_hw_data *ha = vha->hw;
4068 uint32_t r_addr, r_value, r_data;
4069 uint32_t i, j, loop_cnt;
4070 struct qla82xx_md_entry_rdmem *m_hdr;
4071 unsigned long flags;
4072 int rval = QLA_FUNCTION_FAILED;
4073 uint32_t *data_ptr = *d_ptr;
4074
4075 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr;
4076 r_addr = m_hdr->read_addr;
4077 loop_cnt = m_hdr->read_data_size/16;
4078
4079 if (r_addr & 0xf) {
4080 ql_log(ql_log_warn, vha, 0xb033,
4081 "Read addr 0x%x not 16 bytes aligned\n", r_addr);
4082 return rval;
4083 }
4084
4085 if (m_hdr->read_data_size % 16) {
4086 ql_log(ql_log_warn, vha, 0xb034,
4087 "Read data[0x%x] not multiple of 16 bytes\n",
4088 m_hdr->read_data_size);
4089 return rval;
4090 }
4091
4092 ql_dbg(ql_dbg_p3p, vha, 0xb035,
4093 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
4094 __func__, r_addr, m_hdr->read_data_size, loop_cnt);
4095
4096 write_lock_irqsave(&ha->hw_lock, flags);
4097 for (i = 0; i < loop_cnt; i++) {
4098 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1);
4099 r_value = 0;
4100 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1);
4101 r_value = MIU_TA_CTL_ENABLE;
4102 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4103 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
4104 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4105
4106 for (j = 0; j < MAX_CTL_CHECK; j++) {
4107 r_value = qla82xx_md_rw_32(ha,
4108 MD_MIU_TEST_AGT_CTRL, 0, 0);
4109 if ((r_value & MIU_TA_CTL_BUSY) == 0)
4110 break;
4111 }
4112
4113 if (j >= MAX_CTL_CHECK) {
4114 printk_ratelimited(KERN_ERR
4115 "failed to read through agent\n");
4116 write_unlock_irqrestore(&ha->hw_lock, flags);
4117 return rval;
4118 }
4119
4120 for (j = 0; j < 4; j++) {
4121 r_data = qla82xx_md_rw_32(ha,
4122 MD_MIU_TEST_AGT_RDDATA[j], 0, 0);
4123 *data_ptr++ = cpu_to_le32(r_data);
4124 }
4125 r_addr += 16;
4126 }
4127 write_unlock_irqrestore(&ha->hw_lock, flags);
4128 *d_ptr = data_ptr;
4129 return QLA_SUCCESS;
4130 }
4131
4132 int
4133 qla82xx_validate_template_chksum(scsi_qla_host_t *vha)
4134 {
4135 struct qla_hw_data *ha = vha->hw;
4136 uint64_t chksum = 0;
4137 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr;
4138 int count = ha->md_template_size/sizeof(uint32_t);
4139
4140 while (count-- > 0)
4141 chksum += *d_ptr++;
4142 while (chksum >> 32)
4143 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32);
4144 return ~chksum;
4145 }
4146
4147 static void
4148 qla82xx_mark_entry_skipped(scsi_qla_host_t *vha,
4149 qla82xx_md_entry_hdr_t *entry_hdr, int index)
4150 {
4151 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
4152 ql_dbg(ql_dbg_p3p, vha, 0xb036,
4153 "Skipping entry[%d]: "
4154 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4155 index, entry_hdr->entry_type,
4156 entry_hdr->d_ctrl.entry_capture_mask);
4157 }
4158
4159 int
4160 qla82xx_md_collect(scsi_qla_host_t *vha)
4161 {
4162 struct qla_hw_data *ha = vha->hw;
4163 int no_entry_hdr = 0;
4164 qla82xx_md_entry_hdr_t *entry_hdr;
4165 struct qla82xx_md_template_hdr *tmplt_hdr;
4166 uint32_t *data_ptr;
4167 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0;
4168 int i = 0, rval = QLA_FUNCTION_FAILED;
4169
4170 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4171 data_ptr = (uint32_t *)ha->md_dump;
4172
4173 if (ha->fw_dumped) {
4174 ql_log(ql_log_warn, vha, 0xb037,
4175 "Firmware has been previously dumped (%p) "
4176 "-- ignoring request.\n", ha->fw_dump);
4177 goto md_failed;
4178 }
4179
4180 ha->fw_dumped = 0;
4181
4182 if (!ha->md_tmplt_hdr || !ha->md_dump) {
4183 ql_log(ql_log_warn, vha, 0xb038,
4184 "Memory not allocated for minidump capture\n");
4185 goto md_failed;
4186 }
4187
4188 if (ha->flags.isp82xx_no_md_cap) {
4189 ql_log(ql_log_warn, vha, 0xb054,
4190 "Forced reset from application, "
4191 "ignore minidump capture\n");
4192 ha->flags.isp82xx_no_md_cap = 0;
4193 goto md_failed;
4194 }
4195
4196 if (qla82xx_validate_template_chksum(vha)) {
4197 ql_log(ql_log_info, vha, 0xb039,
4198 "Template checksum validation error\n");
4199 goto md_failed;
4200 }
4201
4202 no_entry_hdr = tmplt_hdr->num_of_entries;
4203 ql_dbg(ql_dbg_p3p, vha, 0xb03a,
4204 "No of entry headers in Template: 0x%x\n", no_entry_hdr);
4205
4206 ql_dbg(ql_dbg_p3p, vha, 0xb03b,
4207 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
4208
4209 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
4210
4211 /* Validate whether required debug level is set */
4212 if ((f_capture_mask & 0x3) != 0x3) {
4213 ql_log(ql_log_warn, vha, 0xb03c,
4214 "Minimum required capture mask[0x%x] level not set\n",
4215 f_capture_mask);
4216 goto md_failed;
4217 }
4218 tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
4219
4220 tmplt_hdr->driver_info[0] = vha->host_no;
4221 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) |
4222 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) |
4223 QLA_DRIVER_BETA_VER;
4224
4225 total_data_size = ha->md_dump_size;
4226
4227 ql_dbg(ql_dbg_p3p, vha, 0xb03d,
4228 "Total minidump data_size 0x%x to be captured\n", total_data_size);
4229
4230 /* Check whether template obtained is valid */
4231 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) {
4232 ql_log(ql_log_warn, vha, 0xb04e,
4233 "Bad template header entry type: 0x%x obtained\n",
4234 tmplt_hdr->entry_type);
4235 goto md_failed;
4236 }
4237
4238 entry_hdr = (qla82xx_md_entry_hdr_t *)
4239 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
4240
4241 /* Walk through the entry headers */
4242 for (i = 0; i < no_entry_hdr; i++) {
4243
4244 if (data_collected > total_data_size) {
4245 ql_log(ql_log_warn, vha, 0xb03e,
4246 "More MiniDump data collected: [0x%x]\n",
4247 data_collected);
4248 goto md_failed;
4249 }
4250
4251 if (!(entry_hdr->d_ctrl.entry_capture_mask &
4252 ql2xmdcapmask)) {
4253 entry_hdr->d_ctrl.driver_flags |=
4254 QLA82XX_DBG_SKIPPED_FLAG;
4255 ql_dbg(ql_dbg_p3p, vha, 0xb03f,
4256 "Skipping entry[%d]: "
4257 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4258 i, entry_hdr->entry_type,
4259 entry_hdr->d_ctrl.entry_capture_mask);
4260 goto skip_nxt_entry;
4261 }
4262
4263 ql_dbg(ql_dbg_p3p, vha, 0xb040,
4264 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n"
4265 "entry_type: 0x%x, capture_mask: 0x%x\n",
4266 __func__, i, data_ptr, entry_hdr,
4267 entry_hdr->entry_type,
4268 entry_hdr->d_ctrl.entry_capture_mask);
4269
4270 ql_dbg(ql_dbg_p3p, vha, 0xb041,
4271 "Data collected: [0x%x], Dump size left:[0x%x]\n",
4272 data_collected, (ha->md_dump_size - data_collected));
4273
4274 /* Decode the entry type and take
4275 * required action to capture debug data */
4276 switch (entry_hdr->entry_type) {
4277 case QLA82XX_RDEND:
4278 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4279 break;
4280 case QLA82XX_CNTRL:
4281 rval = qla82xx_minidump_process_control(vha,
4282 entry_hdr, &data_ptr);
4283 if (rval != QLA_SUCCESS) {
4284 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4285 goto md_failed;
4286 }
4287 break;
4288 case QLA82XX_RDCRB:
4289 qla82xx_minidump_process_rdcrb(vha,
4290 entry_hdr, &data_ptr);
4291 break;
4292 case QLA82XX_RDMEM:
4293 rval = qla82xx_minidump_process_rdmem(vha,
4294 entry_hdr, &data_ptr);
4295 if (rval != QLA_SUCCESS) {
4296 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4297 goto md_failed;
4298 }
4299 break;
4300 case QLA82XX_BOARD:
4301 case QLA82XX_RDROM:
4302 qla82xx_minidump_process_rdrom(vha,
4303 entry_hdr, &data_ptr);
4304 break;
4305 case QLA82XX_L2DTG:
4306 case QLA82XX_L2ITG:
4307 case QLA82XX_L2DAT:
4308 case QLA82XX_L2INS:
4309 rval = qla82xx_minidump_process_l2tag(vha,
4310 entry_hdr, &data_ptr);
4311 if (rval != QLA_SUCCESS) {
4312 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4313 goto md_failed;
4314 }
4315 break;
4316 case QLA82XX_L1DAT:
4317 case QLA82XX_L1INS:
4318 qla82xx_minidump_process_l1cache(vha,
4319 entry_hdr, &data_ptr);
4320 break;
4321 case QLA82XX_RDOCM:
4322 qla82xx_minidump_process_rdocm(vha,
4323 entry_hdr, &data_ptr);
4324 break;
4325 case QLA82XX_RDMUX:
4326 qla82xx_minidump_process_rdmux(vha,
4327 entry_hdr, &data_ptr);
4328 break;
4329 case QLA82XX_QUEUE:
4330 qla82xx_minidump_process_queue(vha,
4331 entry_hdr, &data_ptr);
4332 break;
4333 case QLA82XX_RDNOP:
4334 default:
4335 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4336 break;
4337 }
4338
4339 ql_dbg(ql_dbg_p3p, vha, 0xb042,
4340 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr);
4341
4342 data_collected = (uint8_t *)data_ptr -
4343 (uint8_t *)ha->md_dump;
4344 skip_nxt_entry:
4345 entry_hdr = (qla82xx_md_entry_hdr_t *)
4346 (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
4347 }
4348
4349 if (data_collected != total_data_size) {
4350 ql_dbg(ql_dbg_p3p, vha, 0xb043,
4351 "MiniDump data mismatch: Data collected: [0x%x],"
4352 "total_data_size:[0x%x]\n",
4353 data_collected, total_data_size);
4354 goto md_failed;
4355 }
4356
4357 ql_log(ql_log_info, vha, 0xb044,
4358 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
4359 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
4360 ha->fw_dumped = 1;
4361 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
4362
4363 md_failed:
4364 return rval;
4365 }
4366
4367 int
4368 qla82xx_md_alloc(scsi_qla_host_t *vha)
4369 {
4370 struct qla_hw_data *ha = vha->hw;
4371 int i, k;
4372 struct qla82xx_md_template_hdr *tmplt_hdr;
4373
4374 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4375
4376 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) {
4377 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF;
4378 ql_log(ql_log_info, vha, 0xb045,
4379 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n",
4380 ql2xmdcapmask);
4381 }
4382
4383 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) {
4384 if (i & ql2xmdcapmask)
4385 ha->md_dump_size += tmplt_hdr->capture_size_array[k];
4386 }
4387
4388 if (ha->md_dump) {
4389 ql_log(ql_log_warn, vha, 0xb046,
4390 "Firmware dump previously allocated.\n");
4391 return 1;
4392 }
4393
4394 ha->md_dump = vmalloc(ha->md_dump_size);
4395 if (ha->md_dump == NULL) {
4396 ql_log(ql_log_warn, vha, 0xb047,
4397 "Unable to allocate memory for Minidump size "
4398 "(0x%x).\n", ha->md_dump_size);
4399 return 1;
4400 }
4401 return 0;
4402 }
4403
4404 void
4405 qla82xx_md_free(scsi_qla_host_t *vha)
4406 {
4407 struct qla_hw_data *ha = vha->hw;
4408
4409 /* Release the template header allocated */
4410 if (ha->md_tmplt_hdr) {
4411 ql_log(ql_log_info, vha, 0xb048,
4412 "Free MiniDump template: %p, size (%d KB)\n",
4413 ha->md_tmplt_hdr, ha->md_template_size / 1024);
4414 dma_free_coherent(&ha->pdev->dev, ha->md_template_size,
4415 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4416 ha->md_tmplt_hdr = NULL;
4417 }
4418
4419 /* Release the template data buffer allocated */
4420 if (ha->md_dump) {
4421 ql_log(ql_log_info, vha, 0xb049,
4422 "Free MiniDump memory: %p, size (%d KB)\n",
4423 ha->md_dump, ha->md_dump_size / 1024);
4424 vfree(ha->md_dump);
4425 ha->md_dump_size = 0;
4426 ha->md_dump = NULL;
4427 }
4428 }
4429
4430 void
4431 qla82xx_md_prep(scsi_qla_host_t *vha)
4432 {
4433 struct qla_hw_data *ha = vha->hw;
4434 int rval;
4435
4436 /* Get Minidump template size */
4437 rval = qla82xx_md_get_template_size(vha);
4438 if (rval == QLA_SUCCESS) {
4439 ql_log(ql_log_info, vha, 0xb04a,
4440 "MiniDump Template size obtained (%d KB)\n",
4441 ha->md_template_size / 1024);
4442
4443 /* Get Minidump template */
4444 if (IS_QLA8044(ha))
4445 rval = qla8044_md_get_template(vha);
4446 else
4447 rval = qla82xx_md_get_template(vha);
4448
4449 if (rval == QLA_SUCCESS) {
4450 ql_dbg(ql_dbg_p3p, vha, 0xb04b,
4451 "MiniDump Template obtained\n");
4452
4453 /* Allocate memory for minidump */
4454 rval = qla82xx_md_alloc(vha);
4455 if (rval == QLA_SUCCESS)
4456 ql_log(ql_log_info, vha, 0xb04c,
4457 "MiniDump memory allocated (%d KB)\n",
4458 ha->md_dump_size / 1024);
4459 else {
4460 ql_log(ql_log_info, vha, 0xb04d,
4461 "Free MiniDump template: %p, size: (%d KB)\n",
4462 ha->md_tmplt_hdr,
4463 ha->md_template_size / 1024);
4464 dma_free_coherent(&ha->pdev->dev,
4465 ha->md_template_size,
4466 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4467 ha->md_tmplt_hdr = NULL;
4468 }
4469
4470 }
4471 }
4472 }
4473
4474 int
4475 qla82xx_beacon_on(struct scsi_qla_host *vha)
4476 {
4477
4478 int rval;
4479 struct qla_hw_data *ha = vha->hw;
4480
4481 qla82xx_idc_lock(ha);
4482 rval = qla82xx_mbx_beacon_ctl(vha, 1);
4483
4484 if (rval) {
4485 ql_log(ql_log_warn, vha, 0xb050,
4486 "mbx set led config failed in %s\n", __func__);
4487 goto exit;
4488 }
4489 ha->beacon_blink_led = 1;
4490 exit:
4491 qla82xx_idc_unlock(ha);
4492 return rval;
4493 }
4494
4495 int
4496 qla82xx_beacon_off(struct scsi_qla_host *vha)
4497 {
4498
4499 int rval;
4500 struct qla_hw_data *ha = vha->hw;
4501
4502 qla82xx_idc_lock(ha);
4503 rval = qla82xx_mbx_beacon_ctl(vha, 0);
4504
4505 if (rval) {
4506 ql_log(ql_log_warn, vha, 0xb051,
4507 "mbx set led config failed in %s\n", __func__);
4508 goto exit;
4509 }
4510 ha->beacon_blink_led = 0;
4511 exit:
4512 qla82xx_idc_unlock(ha);
4513 return rval;
4514 }
4515
4516 void
4517 qla82xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
4518 {
4519 struct qla_hw_data *ha = vha->hw;
4520
4521 if (!ha->allow_cna_fw_dump)
4522 return;
4523
4524 scsi_block_requests(vha->host);
4525 ha->flags.isp82xx_no_md_cap = 1;
4526 qla82xx_idc_lock(ha);
4527 qla82xx_set_reset_owner(vha);
4528 qla82xx_idc_unlock(ha);
4529 qla2x00_wait_for_chip_reset(vha);
4530 scsi_unblock_requests(vha->host);
4531 }
Linux with added FPC-III support