drivers/scsi/ufs/ufs-mediatek.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2019 MediaTek Inc.
   4  */
   5
   6 #ifndef _UFS_MEDIATEK_H
   7 #define _UFS_MEDIATEK_H
   8
   9 #include <linux/bitops.h>
  10 #include <linux/soc/mediatek/mtk_sip_svc.h>
  11
  12 /*
  13  * Vendor specific UFSHCI Registers
  14  */
  15 #define REG_UFS_REFCLK_CTRL         0x144
  16 #define REG_UFS_EXTREG              0x2100
  17 #define REG_UFS_MPHYCTRL            0x2200
  18 #define REG_UFS_REJECT_MON          0x22AC
  19 #define REG_UFS_DEBUG_SEL           0x22C0
  20 #define REG_UFS_PROBE               0x22C8
  21
  22 /*
  23  * Ref-clk control
  24  *
  25  * Values for register REG_UFS_REFCLK_CTRL
  26  */
  27 #define REFCLK_RELEASE              0x0
  28 #define REFCLK_REQUEST              BIT(0)
  29 #define REFCLK_ACK                  BIT(1)
  30
  31 #define REFCLK_REQ_TIMEOUT_MS       3
  32
  33 /*
  34  * Vendor specific pre-defined parameters
  35  */
  36 #define UFS_MTK_LIMIT_NUM_LANES_RX  1
  37 #define UFS_MTK_LIMIT_NUM_LANES_TX  1
  38 #define UFS_MTK_LIMIT_HSGEAR_RX     UFS_HS_G3
  39 #define UFS_MTK_LIMIT_HSGEAR_TX     UFS_HS_G3
  40 #define UFS_MTK_LIMIT_PWMGEAR_RX    UFS_PWM_G4
  41 #define UFS_MTK_LIMIT_PWMGEAR_TX    UFS_PWM_G4
  42 #define UFS_MTK_LIMIT_RX_PWR_PWM    SLOW_MODE
  43 #define UFS_MTK_LIMIT_TX_PWR_PWM    SLOW_MODE
  44 #define UFS_MTK_LIMIT_RX_PWR_HS     FAST_MODE
  45 #define UFS_MTK_LIMIT_TX_PWR_HS     FAST_MODE
  46 #define UFS_MTK_LIMIT_HS_RATE       PA_HS_MODE_B
  47 #define UFS_MTK_LIMIT_DESIRED_MODE  UFS_HS_MODE
  48
  49 /*
  50  * Other attributes
  51  */
  52 #define VS_DEBUGCLOCKENABLE         0xD0A1
  53 #define VS_SAVEPOWERCONTROL         0xD0A6
  54 #define VS_UNIPROPOWERDOWNCONTROL   0xD0A8
  55
  56 /*
  57  * Vendor specific link state
  58  */
  59 enum {
  60         VS_LINK_DISABLED            = 0,
  61         VS_LINK_DOWN                = 1,
  62         VS_LINK_UP                  = 2,
  63         VS_LINK_HIBERN8             = 3,
  64         VS_LINK_LOST                = 4,
  65         VS_LINK_CFG                 = 5,
  66 };
  67
  68 /*
  69  * SiP commands
  70  */
  71 #define MTK_SIP_UFS_CONTROL               MTK_SIP_SMC_CMD(0x276)
  72 #define UFS_MTK_SIP_DEVICE_RESET          BIT(1)
  73 #define UFS_MTK_SIP_REF_CLK_NOTIFICATION  BIT(3)
  74
  75 /*
  76  * VS_DEBUGCLOCKENABLE
  77  */
  78 enum {
  79         TX_SYMBOL_CLK_REQ_FORCE = 5,
  80 };
  81
  82 /*
  83  * VS_SAVEPOWERCONTROL
  84  */
  85 enum {
  86         RX_SYMBOL_CLK_GATE_EN   = 0,
  87         SYS_CLK_GATE_EN         = 2,
  88         TX_CLK_GATE_EN          = 3,
  89 };
  90
  91 struct ufs_mtk_host {
  92         struct ufs_hba *hba;
  93         struct phy *mphy;
  94         bool unipro_lpm;
  95         bool ref_clk_enabled;
  96         u16 ref_clk_ungating_wait_us;
  97         u16 ref_clk_gating_wait_us;
  98 };
  99
 100 #endif /* !_UFS_MEDIATEK_H */