1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale SPI controller driver cpm functions.
5 * Maintainer: Kumar Gala
7 * Copyright (C) 2006 Polycom, Inc.
8 * Copyright 2010 Freescale Semiconductor, Inc.
10 * CPM SPI and QE buffer descriptors mode support:
11 * Copyright (c) 2009 MontaVista Software, Inc.
12 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
15 #include <soc/fsl/qe/qe.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/fsl_devices.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/spi/spi.h>
22 #include <linux/types.h>
23 #include <linux/platform_device.h>
25 #include "spi-fsl-cpm.h"
26 #include "spi-fsl-lib.h"
27 #include "spi-fsl-spi.h"
29 /* CPM1 and CPM2 are mutually exclusive. */
32 #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_CH_SPI, 0)
35 #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, 0, 0)
38 #define SPIE_TXB 0x00000200 /* Last char is written to tx fifo */
39 #define SPIE_RXB 0x00000100 /* Last char is written to rx buf */
41 /* SPCOM register values */
42 #define SPCOM_STR (1 << 23) /* Start transmit */
44 #define SPI_PRAM_SIZE 0x100
45 #define SPI_MRBLR ((unsigned int)PAGE_SIZE)
47 static void *fsl_dummy_rx
;
48 static DEFINE_MUTEX(fsl_dummy_rx_lock
);
49 static int fsl_dummy_rx_refcnt
;
51 void fsl_spi_cpm_reinit_txrx(struct mpc8xxx_spi
*mspi
)
53 if (mspi
->flags
& SPI_QE
) {
54 qe_issue_cmd(QE_INIT_TX_RX
, mspi
->subblock
,
55 QE_CR_PROTOCOL_UNSPECIFIED
, 0);
57 if (mspi
->flags
& SPI_CPM1
) {
58 out_be32(&mspi
->pram
->rstate
, 0);
59 out_be16(&mspi
->pram
->rbptr
,
60 in_be16(&mspi
->pram
->rbase
));
61 out_be32(&mspi
->pram
->tstate
, 0);
62 out_be16(&mspi
->pram
->tbptr
,
63 in_be16(&mspi
->pram
->tbase
));
65 cpm_command(CPM_SPI_CMD
, CPM_CR_INIT_TRX
);
69 EXPORT_SYMBOL_GPL(fsl_spi_cpm_reinit_txrx
);
71 static void fsl_spi_cpm_bufs_start(struct mpc8xxx_spi
*mspi
)
73 struct cpm_buf_desc __iomem
*tx_bd
= mspi
->tx_bd
;
74 struct cpm_buf_desc __iomem
*rx_bd
= mspi
->rx_bd
;
75 unsigned int xfer_len
= min(mspi
->count
, SPI_MRBLR
);
76 unsigned int xfer_ofs
;
77 struct fsl_spi_reg
*reg_base
= mspi
->reg_base
;
79 xfer_ofs
= mspi
->xfer_in_progress
->len
- mspi
->count
;
81 if (mspi
->rx_dma
== mspi
->dma_dummy_rx
)
82 out_be32(&rx_bd
->cbd_bufaddr
, mspi
->rx_dma
);
84 out_be32(&rx_bd
->cbd_bufaddr
, mspi
->rx_dma
+ xfer_ofs
);
85 out_be16(&rx_bd
->cbd_datlen
, 0);
86 out_be16(&rx_bd
->cbd_sc
, BD_SC_EMPTY
| BD_SC_INTRPT
| BD_SC_WRAP
);
88 if (mspi
->tx_dma
== mspi
->dma_dummy_tx
)
89 out_be32(&tx_bd
->cbd_bufaddr
, mspi
->tx_dma
);
91 out_be32(&tx_bd
->cbd_bufaddr
, mspi
->tx_dma
+ xfer_ofs
);
92 out_be16(&tx_bd
->cbd_datlen
, xfer_len
);
93 out_be16(&tx_bd
->cbd_sc
, BD_SC_READY
| BD_SC_INTRPT
| BD_SC_WRAP
|
97 mpc8xxx_spi_write_reg(®_base
->command
, SPCOM_STR
);
100 int fsl_spi_cpm_bufs(struct mpc8xxx_spi
*mspi
,
101 struct spi_transfer
*t
, bool is_dma_mapped
)
103 struct device
*dev
= mspi
->dev
;
104 struct fsl_spi_reg
*reg_base
= mspi
->reg_base
;
107 mspi
->map_tx_dma
= 0;
108 mspi
->map_rx_dma
= 0;
110 mspi
->map_tx_dma
= 1;
111 mspi
->map_rx_dma
= 1;
115 mspi
->tx_dma
= mspi
->dma_dummy_tx
;
116 mspi
->map_tx_dma
= 0;
120 mspi
->rx_dma
= mspi
->dma_dummy_rx
;
121 mspi
->map_rx_dma
= 0;
124 if (mspi
->map_tx_dma
) {
125 void *nonconst_tx
= (void *)mspi
->tx
; /* shut up gcc */
127 mspi
->tx_dma
= dma_map_single(dev
, nonconst_tx
, t
->len
,
129 if (dma_mapping_error(dev
, mspi
->tx_dma
)) {
130 dev_err(dev
, "unable to map tx dma\n");
133 } else if (t
->tx_buf
) {
134 mspi
->tx_dma
= t
->tx_dma
;
137 if (mspi
->map_rx_dma
) {
138 mspi
->rx_dma
= dma_map_single(dev
, mspi
->rx
, t
->len
,
140 if (dma_mapping_error(dev
, mspi
->rx_dma
)) {
141 dev_err(dev
, "unable to map rx dma\n");
144 } else if (t
->rx_buf
) {
145 mspi
->rx_dma
= t
->rx_dma
;
149 mpc8xxx_spi_write_reg(®_base
->mask
, SPIE_RXB
);
151 mspi
->xfer_in_progress
= t
;
152 mspi
->count
= t
->len
;
154 /* start CPM transfers */
155 fsl_spi_cpm_bufs_start(mspi
);
160 if (mspi
->map_tx_dma
)
161 dma_unmap_single(dev
, mspi
->tx_dma
, t
->len
, DMA_TO_DEVICE
);
164 EXPORT_SYMBOL_GPL(fsl_spi_cpm_bufs
);
166 void fsl_spi_cpm_bufs_complete(struct mpc8xxx_spi
*mspi
)
168 struct device
*dev
= mspi
->dev
;
169 struct spi_transfer
*t
= mspi
->xfer_in_progress
;
171 if (mspi
->map_tx_dma
)
172 dma_unmap_single(dev
, mspi
->tx_dma
, t
->len
, DMA_TO_DEVICE
);
173 if (mspi
->map_rx_dma
)
174 dma_unmap_single(dev
, mspi
->rx_dma
, t
->len
, DMA_FROM_DEVICE
);
175 mspi
->xfer_in_progress
= NULL
;
177 EXPORT_SYMBOL_GPL(fsl_spi_cpm_bufs_complete
);
179 void fsl_spi_cpm_irq(struct mpc8xxx_spi
*mspi
, u32 events
)
182 struct fsl_spi_reg
*reg_base
= mspi
->reg_base
;
184 dev_dbg(mspi
->dev
, "%s: bd datlen %d, count %d\n", __func__
,
185 in_be16(&mspi
->rx_bd
->cbd_datlen
), mspi
->count
);
187 len
= in_be16(&mspi
->rx_bd
->cbd_datlen
);
188 if (len
> mspi
->count
) {
193 /* Clear the events */
194 mpc8xxx_spi_write_reg(®_base
->event
, events
);
198 fsl_spi_cpm_bufs_start(mspi
);
200 complete(&mspi
->done
);
202 EXPORT_SYMBOL_GPL(fsl_spi_cpm_irq
);
204 static void *fsl_spi_alloc_dummy_rx(void)
206 mutex_lock(&fsl_dummy_rx_lock
);
209 fsl_dummy_rx
= kmalloc(SPI_MRBLR
, GFP_KERNEL
);
211 fsl_dummy_rx_refcnt
++;
213 mutex_unlock(&fsl_dummy_rx_lock
);
218 static void fsl_spi_free_dummy_rx(void)
220 mutex_lock(&fsl_dummy_rx_lock
);
222 switch (fsl_dummy_rx_refcnt
) {
231 fsl_dummy_rx_refcnt
--;
235 mutex_unlock(&fsl_dummy_rx_lock
);
238 static unsigned long fsl_spi_cpm_get_pram(struct mpc8xxx_spi
*mspi
)
240 struct device
*dev
= mspi
->dev
;
241 struct device_node
*np
= dev
->of_node
;
244 void __iomem
*spi_base
;
245 unsigned long pram_ofs
= -ENOMEM
;
247 /* Can't use of_address_to_resource(), QE muram isn't at 0. */
248 iprop
= of_get_property(np
, "reg", &size
);
250 /* QE with a fixed pram location? */
251 if (mspi
->flags
& SPI_QE
&& iprop
&& size
== sizeof(*iprop
) * 4)
252 return cpm_muram_alloc_fixed(iprop
[2], SPI_PRAM_SIZE
);
254 /* QE but with a dynamic pram location? */
255 if (mspi
->flags
& SPI_QE
) {
256 pram_ofs
= cpm_muram_alloc(SPI_PRAM_SIZE
, 64);
257 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE
, mspi
->subblock
,
258 QE_CR_PROTOCOL_UNSPECIFIED
, pram_ofs
);
262 spi_base
= of_iomap(np
, 1);
263 if (spi_base
== NULL
)
266 if (mspi
->flags
& SPI_CPM2
) {
267 pram_ofs
= cpm_muram_alloc(SPI_PRAM_SIZE
, 64);
268 out_be16(spi_base
, pram_ofs
);
275 int fsl_spi_cpm_init(struct mpc8xxx_spi
*mspi
)
277 struct device
*dev
= mspi
->dev
;
278 struct device_node
*np
= dev
->of_node
;
281 unsigned long bds_ofs
;
283 if (!(mspi
->flags
& SPI_CPM_MODE
))
286 if (!fsl_spi_alloc_dummy_rx())
289 if (mspi
->flags
& SPI_QE
) {
290 iprop
= of_get_property(np
, "cell-index", &size
);
291 if (iprop
&& size
== sizeof(*iprop
))
292 mspi
->subblock
= *iprop
;
294 switch (mspi
->subblock
) {
296 dev_warn(dev
, "cell-index unspecified, assuming SPI1\n");
299 mspi
->subblock
= QE_CR_SUBBLOCK_SPI1
;
302 mspi
->subblock
= QE_CR_SUBBLOCK_SPI2
;
307 if (mspi
->flags
& SPI_CPM1
) {
310 pram
= devm_platform_ioremap_resource(to_platform_device(dev
),
317 unsigned long pram_ofs
= fsl_spi_cpm_get_pram(mspi
);
319 if (IS_ERR_VALUE(pram_ofs
))
322 mspi
->pram
= cpm_muram_addr(pram_ofs
);
324 if (mspi
->pram
== NULL
) {
325 dev_err(dev
, "can't allocate spi parameter ram\n");
329 bds_ofs
= cpm_muram_alloc(sizeof(*mspi
->tx_bd
) +
330 sizeof(*mspi
->rx_bd
), 8);
331 if (IS_ERR_VALUE(bds_ofs
)) {
332 dev_err(dev
, "can't allocate bds\n");
336 mspi
->dma_dummy_tx
= dma_map_single(dev
, empty_zero_page
, PAGE_SIZE
,
338 if (dma_mapping_error(dev
, mspi
->dma_dummy_tx
)) {
339 dev_err(dev
, "unable to map dummy tx buffer\n");
343 mspi
->dma_dummy_rx
= dma_map_single(dev
, fsl_dummy_rx
, SPI_MRBLR
,
345 if (dma_mapping_error(dev
, mspi
->dma_dummy_rx
)) {
346 dev_err(dev
, "unable to map dummy rx buffer\n");
350 mspi
->tx_bd
= cpm_muram_addr(bds_ofs
);
351 mspi
->rx_bd
= cpm_muram_addr(bds_ofs
+ sizeof(*mspi
->tx_bd
));
353 /* Initialize parameter ram. */
354 out_be16(&mspi
->pram
->tbase
, cpm_muram_offset(mspi
->tx_bd
));
355 out_be16(&mspi
->pram
->rbase
, cpm_muram_offset(mspi
->rx_bd
));
356 out_8(&mspi
->pram
->tfcr
, CPMFCR_EB
| CPMFCR_GBL
);
357 out_8(&mspi
->pram
->rfcr
, CPMFCR_EB
| CPMFCR_GBL
);
358 out_be16(&mspi
->pram
->mrblr
, SPI_MRBLR
);
359 out_be32(&mspi
->pram
->rstate
, 0);
360 out_be32(&mspi
->pram
->rdp
, 0);
361 out_be16(&mspi
->pram
->rbptr
, 0);
362 out_be16(&mspi
->pram
->rbc
, 0);
363 out_be32(&mspi
->pram
->rxtmp
, 0);
364 out_be32(&mspi
->pram
->tstate
, 0);
365 out_be32(&mspi
->pram
->tdp
, 0);
366 out_be16(&mspi
->pram
->tbptr
, 0);
367 out_be16(&mspi
->pram
->tbc
, 0);
368 out_be32(&mspi
->pram
->txtmp
, 0);
373 dma_unmap_single(dev
, mspi
->dma_dummy_tx
, PAGE_SIZE
, DMA_TO_DEVICE
);
375 cpm_muram_free(bds_ofs
);
377 if (!(mspi
->flags
& SPI_CPM1
))
378 cpm_muram_free(cpm_muram_offset(mspi
->pram
));
380 fsl_spi_free_dummy_rx();
383 EXPORT_SYMBOL_GPL(fsl_spi_cpm_init
);
385 void fsl_spi_cpm_free(struct mpc8xxx_spi
*mspi
)
387 struct device
*dev
= mspi
->dev
;
389 if (!(mspi
->flags
& SPI_CPM_MODE
))
392 dma_unmap_single(dev
, mspi
->dma_dummy_rx
, SPI_MRBLR
, DMA_FROM_DEVICE
);
393 dma_unmap_single(dev
, mspi
->dma_dummy_tx
, PAGE_SIZE
, DMA_TO_DEVICE
);
394 cpm_muram_free(cpm_muram_offset(mspi
->tx_bd
));
395 if (!(mspi
->flags
& SPI_CPM1
))
396 cpm_muram_free(cpm_muram_offset(mspi
->pram
));
397 fsl_spi_free_dummy_rx();
399 EXPORT_SYMBOL_GPL(fsl_spi_cpm_free
);
401 MODULE_LICENSE("GPL");