drivers/spi/spi-nxp-fspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2
   3 /*
   4  * NXP FlexSPI(FSPI) controller driver.
   5  *
   6  * Copyright 2019 NXP.
   7  *
   8  * FlexSPI is a flexsible SPI host controller which supports two SPI
   9  * channels and up to 4 external devices. Each channel supports
  10  * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
  11  * data lines).
  12  *
  13  * FlexSPI controller is driven by the LUT(Look-up Table) registers
  14  * LUT registers are a look-up-table for sequences of instructions.
  15  * A valid sequence consists of four LUT registers.
  16  * Maximum 32 LUT sequences can be programmed simultaneously.
  17  *
  18  * LUTs are being created at run-time based on the commands passed
  19  * from the spi-mem framework, thus using single LUT index.
  20  *
  21  * Software triggered Flash read/write access by IP Bus.
  22  *
  23  * Memory mapped read access by AHB Bus.
  24  *
  25  * Based on SPI MEM interface and spi-fsl-qspi.c driver.
  26  *
  27  * Author:
  28  *     Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
  29  *     Boris Brezillon <bbrezillon@kernel.org>
  30  *     Frieder Schrempf <frieder.schrempf@kontron.de>
  31  */
  32
  33 #include <linux/bitops.h>
  34 #include <linux/clk.h>
  35 #include <linux/completion.h>
  36 #include <linux/delay.h>
  37 #include <linux/err.h>
  38 #include <linux/errno.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/io.h>
  41 #include <linux/iopoll.h>
  42 #include <linux/jiffies.h>
  43 #include <linux/kernel.h>
  44 #include <linux/module.h>
  45 #include <linux/mutex.h>
  46 #include <linux/of.h>
  47 #include <linux/of_device.h>
  48 #include <linux/platform_device.h>
  49 #include <linux/pm_qos.h>
  50 #include <linux/sizes.h>
  51
  52 #include <linux/spi/spi.h>
  53 #include <linux/spi/spi-mem.h>
  54
  55 /*
  56  * The driver only uses one single LUT entry, that is updated on
  57  * each call of exec_op(). Index 0 is preset at boot with a basic
  58  * read operation, so let's use the last entry (31).
  59  */
  60 #define SEQID_LUT                       31
  61
  62 /* Registers used by the driver */
  63 #define FSPI_MCR0                       0x00
  64 #define FSPI_MCR0_AHB_TIMEOUT(x)        ((x) << 24)
  65 #define FSPI_MCR0_IP_TIMEOUT(x)         ((x) << 16)
  66 #define FSPI_MCR0_LEARN_EN              BIT(15)
  67 #define FSPI_MCR0_SCRFRUN_EN            BIT(14)
  68 #define FSPI_MCR0_OCTCOMB_EN            BIT(13)
  69 #define FSPI_MCR0_DOZE_EN               BIT(12)
  70 #define FSPI_MCR0_HSEN                  BIT(11)
  71 #define FSPI_MCR0_SERCLKDIV             BIT(8)
  72 #define FSPI_MCR0_ATDF_EN               BIT(7)
  73 #define FSPI_MCR0_ARDF_EN               BIT(6)
  74 #define FSPI_MCR0_RXCLKSRC(x)           ((x) << 4)
  75 #define FSPI_MCR0_END_CFG(x)            ((x) << 2)
  76 #define FSPI_MCR0_MDIS                  BIT(1)
  77 #define FSPI_MCR0_SWRST                 BIT(0)
  78
  79 #define FSPI_MCR1                       0x04
  80 #define FSPI_MCR1_SEQ_TIMEOUT(x)        ((x) << 16)
  81 #define FSPI_MCR1_AHB_TIMEOUT(x)        (x)
  82
  83 #define FSPI_MCR2                       0x08
  84 #define FSPI_MCR2_IDLE_WAIT(x)          ((x) << 24)
  85 #define FSPI_MCR2_SAMEDEVICEEN          BIT(15)
  86 #define FSPI_MCR2_CLRLRPHS              BIT(14)
  87 #define FSPI_MCR2_ABRDATSZ              BIT(8)
  88 #define FSPI_MCR2_ABRLEARN              BIT(7)
  89 #define FSPI_MCR2_ABR_READ              BIT(6)
  90 #define FSPI_MCR2_ABRWRITE              BIT(5)
  91 #define FSPI_MCR2_ABRDUMMY              BIT(4)
  92 #define FSPI_MCR2_ABR_MODE              BIT(3)
  93 #define FSPI_MCR2_ABRCADDR              BIT(2)
  94 #define FSPI_MCR2_ABRRADDR              BIT(1)
  95 #define FSPI_MCR2_ABR_CMD               BIT(0)
  96
  97 #define FSPI_AHBCR                      0x0c
  98 #define FSPI_AHBCR_RDADDROPT            BIT(6)
  99 #define FSPI_AHBCR_PREF_EN              BIT(5)
 100 #define FSPI_AHBCR_BUFF_EN              BIT(4)
 101 #define FSPI_AHBCR_CACH_EN              BIT(3)
 102 #define FSPI_AHBCR_CLRTXBUF             BIT(2)
 103 #define FSPI_AHBCR_CLRRXBUF             BIT(1)
 104 #define FSPI_AHBCR_PAR_EN               BIT(0)
 105
 106 #define FSPI_INTEN                      0x10
 107 #define FSPI_INTEN_SCLKSBWR             BIT(9)
 108 #define FSPI_INTEN_SCLKSBRD             BIT(8)
 109 #define FSPI_INTEN_DATALRNFL            BIT(7)
 110 #define FSPI_INTEN_IPTXWE               BIT(6)
 111 #define FSPI_INTEN_IPRXWA               BIT(5)
 112 #define FSPI_INTEN_AHBCMDERR            BIT(4)
 113 #define FSPI_INTEN_IPCMDERR             BIT(3)
 114 #define FSPI_INTEN_AHBCMDGE             BIT(2)
 115 #define FSPI_INTEN_IPCMDGE              BIT(1)
 116 #define FSPI_INTEN_IPCMDDONE            BIT(0)
 117
 118 #define FSPI_INTR                       0x14
 119 #define FSPI_INTR_SCLKSBWR              BIT(9)
 120 #define FSPI_INTR_SCLKSBRD              BIT(8)
 121 #define FSPI_INTR_DATALRNFL             BIT(7)
 122 #define FSPI_INTR_IPTXWE                BIT(6)
 123 #define FSPI_INTR_IPRXWA                BIT(5)
 124 #define FSPI_INTR_AHBCMDERR             BIT(4)
 125 #define FSPI_INTR_IPCMDERR              BIT(3)
 126 #define FSPI_INTR_AHBCMDGE              BIT(2)
 127 #define FSPI_INTR_IPCMDGE               BIT(1)
 128 #define FSPI_INTR_IPCMDDONE             BIT(0)
 129
 130 #define FSPI_LUTKEY                     0x18
 131 #define FSPI_LUTKEY_VALUE               0x5AF05AF0
 132
 133 #define FSPI_LCKCR                      0x1C
 134
 135 #define FSPI_LCKER_LOCK                 0x1
 136 #define FSPI_LCKER_UNLOCK               0x2
 137
 138 #define FSPI_BUFXCR_INVALID_MSTRID      0xE
 139 #define FSPI_AHBRX_BUF0CR0              0x20
 140 #define FSPI_AHBRX_BUF1CR0              0x24
 141 #define FSPI_AHBRX_BUF2CR0              0x28
 142 #define FSPI_AHBRX_BUF3CR0              0x2C
 143 #define FSPI_AHBRX_BUF4CR0              0x30
 144 #define FSPI_AHBRX_BUF5CR0              0x34
 145 #define FSPI_AHBRX_BUF6CR0              0x38
 146 #define FSPI_AHBRX_BUF7CR0              0x3C
 147 #define FSPI_AHBRXBUF0CR7_PREF          BIT(31)
 148
 149 #define FSPI_AHBRX_BUF0CR1              0x40
 150 #define FSPI_AHBRX_BUF1CR1              0x44
 151 #define FSPI_AHBRX_BUF2CR1              0x48
 152 #define FSPI_AHBRX_BUF3CR1              0x4C
 153 #define FSPI_AHBRX_BUF4CR1              0x50
 154 #define FSPI_AHBRX_BUF5CR1              0x54
 155 #define FSPI_AHBRX_BUF6CR1              0x58
 156 #define FSPI_AHBRX_BUF7CR1              0x5C
 157
 158 #define FSPI_FLSHA1CR0                  0x60
 159 #define FSPI_FLSHA2CR0                  0x64
 160 #define FSPI_FLSHB1CR0                  0x68
 161 #define FSPI_FLSHB2CR0                  0x6C
 162 #define FSPI_FLSHXCR0_SZ_KB             10
 163 #define FSPI_FLSHXCR0_SZ(x)             ((x) >> FSPI_FLSHXCR0_SZ_KB)
 164
 165 #define FSPI_FLSHA1CR1                  0x70
 166 #define FSPI_FLSHA2CR1                  0x74
 167 #define FSPI_FLSHB1CR1                  0x78
 168 #define FSPI_FLSHB2CR1                  0x7C
 169 #define FSPI_FLSHXCR1_CSINTR(x)         ((x) << 16)
 170 #define FSPI_FLSHXCR1_CAS(x)            ((x) << 11)
 171 #define FSPI_FLSHXCR1_WA                BIT(10)
 172 #define FSPI_FLSHXCR1_TCSH(x)           ((x) << 5)
 173 #define FSPI_FLSHXCR1_TCSS(x)           (x)
 174
 175 #define FSPI_FLSHA1CR2                  0x80
 176 #define FSPI_FLSHA2CR2                  0x84
 177 #define FSPI_FLSHB1CR2                  0x88
 178 #define FSPI_FLSHB2CR2                  0x8C
 179 #define FSPI_FLSHXCR2_CLRINSP           BIT(24)
 180 #define FSPI_FLSHXCR2_AWRWAIT           BIT(16)
 181 #define FSPI_FLSHXCR2_AWRSEQN_SHIFT     13
 182 #define FSPI_FLSHXCR2_AWRSEQI_SHIFT     8
 183 #define FSPI_FLSHXCR2_ARDSEQN_SHIFT     5
 184 #define FSPI_FLSHXCR2_ARDSEQI_SHIFT     0
 185
 186 #define FSPI_IPCR0                      0xA0
 187
 188 #define FSPI_IPCR1                      0xA4
 189 #define FSPI_IPCR1_IPAREN               BIT(31)
 190 #define FSPI_IPCR1_SEQNUM_SHIFT         24
 191 #define FSPI_IPCR1_SEQID_SHIFT          16
 192 #define FSPI_IPCR1_IDATSZ(x)            (x)
 193
 194 #define FSPI_IPCMD                      0xB0
 195 #define FSPI_IPCMD_TRG                  BIT(0)
 196
 197 #define FSPI_DLPR                       0xB4
 198
 199 #define FSPI_IPRXFCR                    0xB8
 200 #define FSPI_IPRXFCR_CLR                BIT(0)
 201 #define FSPI_IPRXFCR_DMA_EN             BIT(1)
 202 #define FSPI_IPRXFCR_WMRK(x)            ((x) << 2)
 203
 204 #define FSPI_IPTXFCR                    0xBC
 205 #define FSPI_IPTXFCR_CLR                BIT(0)
 206 #define FSPI_IPTXFCR_DMA_EN             BIT(1)
 207 #define FSPI_IPTXFCR_WMRK(x)            ((x) << 2)
 208
 209 #define FSPI_DLLACR                     0xC0
 210 #define FSPI_DLLACR_OVRDEN              BIT(8)
 211
 212 #define FSPI_DLLBCR                     0xC4
 213 #define FSPI_DLLBCR_OVRDEN              BIT(8)
 214
 215 #define FSPI_STS0                       0xE0
 216 #define FSPI_STS0_DLPHB(x)              ((x) << 8)
 217 #define FSPI_STS0_DLPHA(x)              ((x) << 4)
 218 #define FSPI_STS0_CMD_SRC(x)            ((x) << 2)
 219 #define FSPI_STS0_ARB_IDLE              BIT(1)
 220 #define FSPI_STS0_SEQ_IDLE              BIT(0)
 221
 222 #define FSPI_STS1                       0xE4
 223 #define FSPI_STS1_IP_ERRCD(x)           ((x) << 24)
 224 #define FSPI_STS1_IP_ERRID(x)           ((x) << 16)
 225 #define FSPI_STS1_AHB_ERRCD(x)          ((x) << 8)
 226 #define FSPI_STS1_AHB_ERRID(x)          (x)
 227
 228 #define FSPI_AHBSPNST                   0xEC
 229 #define FSPI_AHBSPNST_DATLFT(x)         ((x) << 16)
 230 #define FSPI_AHBSPNST_BUFID(x)          ((x) << 1)
 231 #define FSPI_AHBSPNST_ACTIVE            BIT(0)
 232
 233 #define FSPI_IPRXFSTS                   0xF0
 234 #define FSPI_IPRXFSTS_RDCNTR(x)         ((x) << 16)
 235 #define FSPI_IPRXFSTS_FILL(x)           (x)
 236
 237 #define FSPI_IPTXFSTS                   0xF4
 238 #define FSPI_IPTXFSTS_WRCNTR(x)         ((x) << 16)
 239 #define FSPI_IPTXFSTS_FILL(x)           (x)
 240
 241 #define FSPI_RFDR                       0x100
 242 #define FSPI_TFDR                       0x180
 243
 244 #define FSPI_LUT_BASE                   0x200
 245 #define FSPI_LUT_OFFSET                 (SEQID_LUT * 4 * 4)
 246 #define FSPI_LUT_REG(idx) \
 247         (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4)
 248
 249 /* register map end */
 250
 251 /* Instruction set for the LUT register. */
 252 #define LUT_STOP                        0x00
 253 #define LUT_CMD                         0x01
 254 #define LUT_ADDR                        0x02
 255 #define LUT_CADDR_SDR                   0x03
 256 #define LUT_MODE                        0x04
 257 #define LUT_MODE2                       0x05
 258 #define LUT_MODE4                       0x06
 259 #define LUT_MODE8                       0x07
 260 #define LUT_NXP_WRITE                   0x08
 261 #define LUT_NXP_READ                    0x09
 262 #define LUT_LEARN_SDR                   0x0A
 263 #define LUT_DATSZ_SDR                   0x0B
 264 #define LUT_DUMMY                       0x0C
 265 #define LUT_DUMMY_RWDS_SDR              0x0D
 266 #define LUT_JMP_ON_CS                   0x1F
 267 #define LUT_CMD_DDR                     0x21
 268 #define LUT_ADDR_DDR                    0x22
 269 #define LUT_CADDR_DDR                   0x23
 270 #define LUT_MODE_DDR                    0x24
 271 #define LUT_MODE2_DDR                   0x25
 272 #define LUT_MODE4_DDR                   0x26
 273 #define LUT_MODE8_DDR                   0x27
 274 #define LUT_WRITE_DDR                   0x28
 275 #define LUT_READ_DDR                    0x29
 276 #define LUT_LEARN_DDR                   0x2A
 277 #define LUT_DATSZ_DDR                   0x2B
 278 #define LUT_DUMMY_DDR                   0x2C
 279 #define LUT_DUMMY_RWDS_DDR              0x2D
 280
 281 /*
 282  * Calculate number of required PAD bits for LUT register.
 283  *
 284  * The pad stands for the number of IO lines [0:7].
 285  * For example, the octal read needs eight IO lines,
 286  * so you should use LUT_PAD(8). This macro
 287  * returns 3 i.e. use eight (2^3) IP lines for read.
 288  */
 289 #define LUT_PAD(x) (fls(x) - 1)
 290
 291 /*
 292  * Macro for constructing the LUT entries with the following
 293  * register layout:
 294  *
 295  *  ---------------------------------------------------
 296  *  | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
 297  *  ---------------------------------------------------
 298  */
 299 #define PAD_SHIFT               8
 300 #define INSTR_SHIFT             10
 301 #define OPRND_SHIFT             16
 302
 303 /* Macros for constructing the LUT register. */
 304 #define LUT_DEF(idx, ins, pad, opr)                       \
 305         ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \
 306         (opr)) << (((idx) % 2) * OPRND_SHIFT))
 307
 308 #define POLL_TOUT               5000
 309 #define NXP_FSPI_MAX_CHIPSELECT         4
 310 #define NXP_FSPI_MIN_IOMAP      SZ_4M
 311
 312 struct nxp_fspi_devtype_data {
 313         unsigned int rxfifo;
 314         unsigned int txfifo;
 315         unsigned int ahb_buf_size;
 316         unsigned int quirks;
 317         bool little_endian;
 318 };
 319
 320 static const struct nxp_fspi_devtype_data lx2160a_data = {
 321         .rxfifo = SZ_512,       /* (64  * 64 bits)  */
 322         .txfifo = SZ_1K,        /* (128 * 64 bits)  */
 323         .ahb_buf_size = SZ_2K,  /* (256 * 64 bits)  */
 324         .quirks = 0,
 325         .little_endian = true,  /* little-endian    */
 326 };
 327
 328 static const struct nxp_fspi_devtype_data imx8mm_data = {
 329         .rxfifo = SZ_512,       /* (64  * 64 bits)  */
 330         .txfifo = SZ_1K,        /* (128 * 64 bits)  */
 331         .ahb_buf_size = SZ_2K,  /* (256 * 64 bits)  */
 332         .quirks = 0,
 333         .little_endian = true,  /* little-endian    */
 334 };
 335
 336 static const struct nxp_fspi_devtype_data imx8qxp_data = {
 337         .rxfifo = SZ_512,       /* (64  * 64 bits)  */
 338         .txfifo = SZ_1K,        /* (128 * 64 bits)  */
 339         .ahb_buf_size = SZ_2K,  /* (256 * 64 bits)  */
 340         .quirks = 0,
 341         .little_endian = true,  /* little-endian    */
 342 };
 343
 344 struct nxp_fspi {
 345         void __iomem *iobase;
 346         void __iomem *ahb_addr;
 347         u32 memmap_phy;
 348         u32 memmap_phy_size;
 349         u32 memmap_start;
 350         u32 memmap_len;
 351         struct clk *clk, *clk_en;
 352         struct device *dev;
 353         struct completion c;
 354         const struct nxp_fspi_devtype_data *devtype_data;
 355         struct mutex lock;
 356         struct pm_qos_request pm_qos_req;
 357         int selected;
 358 };
 359
 360 /*
 361  * R/W functions for big- or little-endian registers:
 362  * The FSPI controller's endianness is independent of
 363  * the CPU core's endianness. So far, although the CPU
 364  * core is little-endian the FSPI controller can use
 365  * big-endian or little-endian.
 366  */
 367 static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr)
 368 {
 369         if (f->devtype_data->little_endian)
 370                 iowrite32(val, addr);
 371         else
 372                 iowrite32be(val, addr);
 373 }
 374
 375 static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr)
 376 {
 377         if (f->devtype_data->little_endian)
 378                 return ioread32(addr);
 379         else
 380                 return ioread32be(addr);
 381 }
 382
 383 static irqreturn_t nxp_fspi_irq_handler(int irq, void *dev_id)
 384 {
 385         struct nxp_fspi *f = dev_id;
 386         u32 reg;
 387
 388         /* clear interrupt */
 389         reg = fspi_readl(f, f->iobase + FSPI_INTR);
 390         fspi_writel(f, FSPI_INTR_IPCMDDONE, f->iobase + FSPI_INTR);
 391
 392         if (reg & FSPI_INTR_IPCMDDONE)
 393                 complete(&f->c);
 394
 395         return IRQ_HANDLED;
 396 }
 397
 398 static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width)
 399 {
 400         switch (width) {
 401         case 1:
 402         case 2:
 403         case 4:
 404         case 8:
 405                 return 0;
 406         }
 407
 408         return -ENOTSUPP;
 409 }
 410
 411 static bool nxp_fspi_supports_op(struct spi_mem *mem,
 412                                  const struct spi_mem_op *op)
 413 {
 414         struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
 415         int ret;
 416
 417         ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth);
 418
 419         if (op->addr.nbytes)
 420                 ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth);
 421
 422         if (op->dummy.nbytes)
 423                 ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth);
 424
 425         if (op->data.nbytes)
 426                 ret |= nxp_fspi_check_buswidth(f, op->data.buswidth);
 427
 428         if (ret)
 429                 return false;
 430
 431         /*
 432          * The number of address bytes should be equal to or less than 4 bytes.
 433          */
 434         if (op->addr.nbytes > 4)
 435                 return false;
 436
 437         /*
 438          * If requested address value is greater than controller assigned
 439          * memory mapped space, return error as it didn't fit in the range
 440          * of assigned address space.
 441          */
 442         if (op->addr.val >= f->memmap_phy_size)
 443                 return false;
 444
 445         /* Max 64 dummy clock cycles supported */
 446         if (op->dummy.buswidth &&
 447             (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
 448                 return false;
 449
 450         /* Max data length, check controller limits and alignment */
 451         if (op->data.dir == SPI_MEM_DATA_IN &&
 452             (op->data.nbytes > f->devtype_data->ahb_buf_size ||
 453              (op->data.nbytes > f->devtype_data->rxfifo - 4 &&
 454               !IS_ALIGNED(op->data.nbytes, 8))))
 455                 return false;
 456
 457         if (op->data.dir == SPI_MEM_DATA_OUT &&
 458             op->data.nbytes > f->devtype_data->txfifo)
 459                 return false;
 460
 461         return spi_mem_default_supports_op(mem, op);
 462 }
 463
 464 /* Instead of busy looping invoke readl_poll_timeout functionality. */
 465 static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base,
 466                                 u32 mask, u32 delay_us,
 467                                 u32 timeout_us, bool c)
 468 {
 469         u32 reg;
 470
 471         if (!f->devtype_data->little_endian)
 472                 mask = (u32)cpu_to_be32(mask);
 473
 474         if (c)
 475                 return readl_poll_timeout(base, reg, (reg & mask),
 476                                           delay_us, timeout_us);
 477         else
 478                 return readl_poll_timeout(base, reg, !(reg & mask),
 479                                           delay_us, timeout_us);
 480 }
 481
 482 /*
 483  * If the slave device content being changed by Write/Erase, need to
 484  * invalidate the AHB buffer. This can be achieved by doing the reset
 485  * of controller after setting MCR0[SWRESET] bit.
 486  */
 487 static inline void nxp_fspi_invalid(struct nxp_fspi *f)
 488 {
 489         u32 reg;
 490         int ret;
 491
 492         reg = fspi_readl(f, f->iobase + FSPI_MCR0);
 493         fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0);
 494
 495         /* w1c register, wait unit clear */
 496         ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
 497                                    FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
 498         WARN_ON(ret);
 499 }
 500
 501 static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
 502                                  const struct spi_mem_op *op)
 503 {
 504         void __iomem *base = f->iobase;
 505         u32 lutval[4] = {};
 506         int lutidx = 1, i;
 507
 508         /* cmd */
 509         lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
 510                              op->cmd.opcode);
 511
 512         /* addr bytes */
 513         if (op->addr.nbytes) {
 514                 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
 515                                               LUT_PAD(op->addr.buswidth),
 516                                               op->addr.nbytes * 8);
 517                 lutidx++;
 518         }
 519
 520         /* dummy bytes, if needed */
 521         if (op->dummy.nbytes) {
 522                 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
 523                 /*
 524                  * Due to FlexSPI controller limitation number of PAD for dummy
 525                  * buswidth needs to be programmed as equal to data buswidth.
 526                  */
 527                                               LUT_PAD(op->data.buswidth),
 528                                               op->dummy.nbytes * 8 /
 529                                               op->dummy.buswidth);
 530                 lutidx++;
 531         }
 532
 533         /* read/write data bytes */
 534         if (op->data.nbytes) {
 535                 lutval[lutidx / 2] |= LUT_DEF(lutidx,
 536                                               op->data.dir == SPI_MEM_DATA_IN ?
 537                                               LUT_NXP_READ : LUT_NXP_WRITE,
 538                                               LUT_PAD(op->data.buswidth),
 539                                               0);
 540                 lutidx++;
 541         }
 542
 543         /* stop condition. */
 544         lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
 545
 546         /* unlock LUT */
 547         fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
 548         fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR);
 549
 550         /* fill LUT */
 551         for (i = 0; i < ARRAY_SIZE(lutval); i++)
 552                 fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i));
 553
 554         dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
 555                 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
 556
 557         /* lock LUT */
 558         fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
 559         fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR);
 560 }
 561
 562 static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f)
 563 {
 564         int ret;
 565
 566         ret = clk_prepare_enable(f->clk_en);
 567         if (ret)
 568                 return ret;
 569
 570         ret = clk_prepare_enable(f->clk);
 571         if (ret) {
 572                 clk_disable_unprepare(f->clk_en);
 573                 return ret;
 574         }
 575
 576         return 0;
 577 }
 578
 579 static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *f)
 580 {
 581         clk_disable_unprepare(f->clk);
 582         clk_disable_unprepare(f->clk_en);
 583 }
 584
 585 /*
 586  * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0
 587  * register and start base address of the slave device.
 588  *
 589  *                                                          (Higher address)
 590  *                              --------    <-- FLSHB2CR0
 591  *                              |  B2  |
 592  *                              |      |
 593  *      B2 start address -->    --------    <-- FLSHB1CR0
 594  *                              |  B1  |
 595  *                              |      |
 596  *      B1 start address -->    --------    <-- FLSHA2CR0
 597  *                              |  A2  |
 598  *                              |      |
 599  *      A2 start address -->    --------    <-- FLSHA1CR0
 600  *                              |  A1  |
 601  *                              |      |
 602  *      A1 start address -->    --------                    (Lower address)
 603  *
 604  *
 605  * Start base address defines the starting address range for given CS and
 606  * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS.
 607  *
 608  * But, different targets are having different combinations of number of CS,
 609  * some targets only have single CS or two CS covering controller's full
 610  * memory mapped space area.
 611  * Thus, implementation is being done as independent of the size and number
 612  * of the connected slave device.
 613  * Assign controller memory mapped space size as the size to the connected
 614  * slave device.
 615  * Mark FLSHxxCR0 as zero initially and then assign value only to the selected
 616  * chip-select Flash configuration register.
 617  *
 618  * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the
 619  * memory mapped size of the controller.
 620  * Value for rest of the CS FLSHxxCR0 register would be zero.
 621  *
 622  */
 623 static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi)
 624 {
 625         unsigned long rate = spi->max_speed_hz;
 626         int ret;
 627         uint64_t size_kb;
 628
 629         /*
 630          * Return, if previously selected slave device is same as current
 631          * requested slave device.
 632          */
 633         if (f->selected == spi->chip_select)
 634                 return;
 635
 636         /* Reset FLSHxxCR0 registers */
 637         fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0);
 638         fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0);
 639         fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0);
 640         fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0);
 641
 642         /* Assign controller memory mapped space as size, KBytes, of flash. */
 643         size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size);
 644
 645         fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 +
 646                     4 * spi->chip_select);
 647
 648         dev_dbg(f->dev, "Slave device [CS:%x] selected\n", spi->chip_select);
 649
 650         nxp_fspi_clk_disable_unprep(f);
 651
 652         ret = clk_set_rate(f->clk, rate);
 653         if (ret)
 654                 return;
 655
 656         ret = nxp_fspi_clk_prep_enable(f);
 657         if (ret)
 658                 return;
 659
 660         f->selected = spi->chip_select;
 661 }
 662
 663 static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op)
 664 {
 665         u32 start = op->addr.val;
 666         u32 len = op->data.nbytes;
 667
 668         /* if necessary, ioremap before AHB read */
 669         if ((!f->ahb_addr) || start < f->memmap_start ||
 670              start + len > f->memmap_start + f->memmap_len) {
 671                 if (f->ahb_addr)
 672                         iounmap(f->ahb_addr);
 673
 674                 f->memmap_start = start;
 675                 f->memmap_len = len > NXP_FSPI_MIN_IOMAP ?
 676                                 len : NXP_FSPI_MIN_IOMAP;
 677
 678                 f->ahb_addr = ioremap_wc(f->memmap_phy + f->memmap_start,
 679                                          f->memmap_len);
 680
 681                 if (!f->ahb_addr) {
 682                         dev_err(f->dev, "failed to alloc memory\n");
 683                         return -ENOMEM;
 684                 }
 685         }
 686
 687         /* Read out the data directly from the AHB buffer. */
 688         memcpy_fromio(op->data.buf.in,
 689                       f->ahb_addr + start - f->memmap_start, len);
 690
 691         return 0;
 692 }
 693
 694 static void nxp_fspi_fill_txfifo(struct nxp_fspi *f,
 695                                  const struct spi_mem_op *op)
 696 {
 697         void __iomem *base = f->iobase;
 698         int i, ret;
 699         u8 *buf = (u8 *) op->data.buf.out;
 700
 701         /* clear the TX FIFO. */
 702         fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR);
 703
 704         /*
 705          * Default value of water mark level is 8 bytes, hence in single
 706          * write request controller can write max 8 bytes of data.
 707          */
 708
 709         for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) {
 710                 /* Wait for TXFIFO empty */
 711                 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
 712                                            FSPI_INTR_IPTXWE, 0,
 713                                            POLL_TOUT, true);
 714                 WARN_ON(ret);
 715
 716                 fspi_writel(f, *(u32 *) (buf + i), base + FSPI_TFDR);
 717                 fspi_writel(f, *(u32 *) (buf + i + 4), base + FSPI_TFDR + 4);
 718                 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
 719         }
 720
 721         if (i < op->data.nbytes) {
 722                 u32 data = 0;
 723                 int j;
 724                 /* Wait for TXFIFO empty */
 725                 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
 726                                            FSPI_INTR_IPTXWE, 0,
 727                                            POLL_TOUT, true);
 728                 WARN_ON(ret);
 729
 730                 for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) {
 731                         memcpy(&data, buf + i + j, 4);
 732                         fspi_writel(f, data, base + FSPI_TFDR + j);
 733                 }
 734                 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
 735         }
 736 }
 737
 738 static void nxp_fspi_read_rxfifo(struct nxp_fspi *f,
 739                           const struct spi_mem_op *op)
 740 {
 741         void __iomem *base = f->iobase;
 742         int i, ret;
 743         int len = op->data.nbytes;
 744         u8 *buf = (u8 *) op->data.buf.in;
 745
 746         /*
 747          * Default value of water mark level is 8 bytes, hence in single
 748          * read request controller can read max 8 bytes of data.
 749          */
 750         for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) {
 751                 /* Wait for RXFIFO available */
 752                 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
 753                                            FSPI_INTR_IPRXWA, 0,
 754                                            POLL_TOUT, true);
 755                 WARN_ON(ret);
 756
 757                 *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR);
 758                 *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4);
 759                 /* move the FIFO pointer */
 760                 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
 761         }
 762
 763         if (i < len) {
 764                 u32 tmp;
 765                 int size, j;
 766
 767                 buf = op->data.buf.in + i;
 768                 /* Wait for RXFIFO available */
 769                 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
 770                                            FSPI_INTR_IPRXWA, 0,
 771                                            POLL_TOUT, true);
 772                 WARN_ON(ret);
 773
 774                 len = op->data.nbytes - i;
 775                 for (j = 0; j < op->data.nbytes - i; j += 4) {
 776                         tmp = fspi_readl(f, base + FSPI_RFDR + j);
 777                         size = min(len, 4);
 778                         memcpy(buf + j, &tmp, size);
 779                         len -= size;
 780                 }
 781         }
 782
 783         /* invalid the RXFIFO */
 784         fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR);
 785         /* move the FIFO pointer */
 786         fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
 787 }
 788
 789 static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op)
 790 {
 791         void __iomem *base = f->iobase;
 792         int seqnum = 0;
 793         int err = 0;
 794         u32 reg;
 795
 796         reg = fspi_readl(f, base + FSPI_IPRXFCR);
 797         /* invalid RXFIFO first */
 798         reg &= ~FSPI_IPRXFCR_DMA_EN;
 799         reg = reg | FSPI_IPRXFCR_CLR;
 800         fspi_writel(f, reg, base + FSPI_IPRXFCR);
 801
 802         init_completion(&f->c);
 803
 804         fspi_writel(f, op->addr.val, base + FSPI_IPCR0);
 805         /*
 806          * Always start the sequence at the same index since we update
 807          * the LUT at each exec_op() call. And also specify the DATA
 808          * length, since it's has not been specified in the LUT.
 809          */
 810         fspi_writel(f, op->data.nbytes |
 811                  (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) |
 812                  (seqnum << FSPI_IPCR1_SEQNUM_SHIFT),
 813                  base + FSPI_IPCR1);
 814
 815         /* Trigger the LUT now. */
 816         fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD);
 817
 818         /* Wait for the interrupt. */
 819         if (!wait_for_completion_timeout(&f->c, msecs_to_jiffies(1000)))
 820                 err = -ETIMEDOUT;
 821
 822         /* Invoke IP data read, if request is of data read. */
 823         if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
 824                 nxp_fspi_read_rxfifo(f, op);
 825
 826         return err;
 827 }
 828
 829 static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
 830 {
 831         struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
 832         int err = 0;
 833
 834         mutex_lock(&f->lock);
 835
 836         /* Wait for controller being ready. */
 837         err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
 838                                    FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true);
 839         WARN_ON(err);
 840
 841         nxp_fspi_select_mem(f, mem->spi);
 842
 843         nxp_fspi_prepare_lut(f, op);
 844         /*
 845          * If we have large chunks of data, we read them through the AHB bus
 846          * by accessing the mapped memory. In all other cases we use
 847          * IP commands to access the flash.
 848          */
 849         if (op->data.nbytes > (f->devtype_data->rxfifo - 4) &&
 850             op->data.dir == SPI_MEM_DATA_IN) {
 851                 err = nxp_fspi_read_ahb(f, op);
 852         } else {
 853                 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
 854                         nxp_fspi_fill_txfifo(f, op);
 855
 856                 err = nxp_fspi_do_op(f, op);
 857         }
 858
 859         /* Invalidate the data in the AHB buffer. */
 860         nxp_fspi_invalid(f);
 861
 862         mutex_unlock(&f->lock);
 863
 864         return err;
 865 }
 866
 867 static int nxp_fspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
 868 {
 869         struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
 870
 871         if (op->data.dir == SPI_MEM_DATA_OUT) {
 872                 if (op->data.nbytes > f->devtype_data->txfifo)
 873                         op->data.nbytes = f->devtype_data->txfifo;
 874         } else {
 875                 if (op->data.nbytes > f->devtype_data->ahb_buf_size)
 876                         op->data.nbytes = f->devtype_data->ahb_buf_size;
 877                 else if (op->data.nbytes > (f->devtype_data->rxfifo - 4))
 878                         op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
 879         }
 880
 881         return 0;
 882 }
 883
 884 static int nxp_fspi_default_setup(struct nxp_fspi *f)
 885 {
 886         void __iomem *base = f->iobase;
 887         int ret, i;
 888         u32 reg;
 889
 890         /* disable and unprepare clock to avoid glitch pass to controller */
 891         nxp_fspi_clk_disable_unprep(f);
 892
 893         /* the default frequency, we will change it later if necessary. */
 894         ret = clk_set_rate(f->clk, 20000000);
 895         if (ret)
 896                 return ret;
 897
 898         ret = nxp_fspi_clk_prep_enable(f);
 899         if (ret)
 900                 return ret;
 901
 902         /* Reset the module */
 903         /* w1c register, wait unit clear */
 904         ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
 905                                    FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
 906         WARN_ON(ret);
 907
 908         /* Disable the module */
 909         fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0);
 910
 911         /* Reset the DLL register to default value */
 912         fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR);
 913         fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR);
 914
 915         /* enable module */
 916         fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) |
 917                     FSPI_MCR0_IP_TIMEOUT(0xFF) | (u32) FSPI_MCR0_OCTCOMB_EN,
 918                     base + FSPI_MCR0);
 919
 920         /*
 921          * Disable same device enable bit and configure all slave devices
 922          * independently.
 923          */
 924         reg = fspi_readl(f, f->iobase + FSPI_MCR2);
 925         reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN);
 926         fspi_writel(f, reg, base + FSPI_MCR2);
 927
 928         /* AHB configuration for access buffer 0~7. */
 929         for (i = 0; i < 7; i++)
 930                 fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i);
 931
 932         /*
 933          * Set ADATSZ with the maximum AHB buffer size to improve the read
 934          * performance.
 935          */
 936         fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 |
 937                   FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0);
 938
 939         /* prefetch and no start address alignment limitation */
 940         fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT,
 941                  base + FSPI_AHBCR);
 942
 943         /* AHB Read - Set lut sequence ID for all CS. */
 944         fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2);
 945         fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2);
 946         fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2);
 947         fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2);
 948
 949         f->selected = -1;
 950
 951         /* enable the interrupt */
 952         fspi_writel(f, FSPI_INTEN_IPCMDDONE, base + FSPI_INTEN);
 953
 954         return 0;
 955 }
 956
 957 static const char *nxp_fspi_get_name(struct spi_mem *mem)
 958 {
 959         struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
 960         struct device *dev = &mem->spi->dev;
 961         const char *name;
 962
 963         // Set custom name derived from the platform_device of the controller.
 964         if (of_get_available_child_count(f->dev->of_node) == 1)
 965                 return dev_name(f->dev);
 966
 967         name = devm_kasprintf(dev, GFP_KERNEL,
 968                               "%s-%d", dev_name(f->dev),
 969                               mem->spi->chip_select);
 970
 971         if (!name) {
 972                 dev_err(dev, "failed to get memory for custom flash name\n");
 973                 return ERR_PTR(-ENOMEM);
 974         }
 975
 976         return name;
 977 }
 978
 979 static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
 980         .adjust_op_size = nxp_fspi_adjust_op_size,
 981         .supports_op = nxp_fspi_supports_op,
 982         .exec_op = nxp_fspi_exec_op,
 983         .get_name = nxp_fspi_get_name,
 984 };
 985
 986 static int nxp_fspi_probe(struct platform_device *pdev)
 987 {
 988         struct spi_controller *ctlr;
 989         struct device *dev = &pdev->dev;
 990         struct device_node *np = dev->of_node;
 991         struct resource *res;
 992         struct nxp_fspi *f;
 993         int ret;
 994
 995         ctlr = spi_alloc_master(&pdev->dev, sizeof(*f));
 996         if (!ctlr)
 997                 return -ENOMEM;
 998
 999         ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL |
1000                           SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL;
1001
1002         f = spi_controller_get_devdata(ctlr);
1003         f->dev = dev;
1004         f->devtype_data = of_device_get_match_data(dev);
1005         if (!f->devtype_data) {
1006                 ret = -ENODEV;
1007                 goto err_put_ctrl;
1008         }
1009
1010         platform_set_drvdata(pdev, f);
1011
1012         /* find the resources - configuration register address space */
1013         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fspi_base");
1014         f->iobase = devm_ioremap_resource(dev, res);
1015         if (IS_ERR(f->iobase)) {
1016                 ret = PTR_ERR(f->iobase);
1017                 goto err_put_ctrl;
1018         }
1019
1020         /* find the resources - controller memory mapped space */
1021         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fspi_mmap");
1022         if (!res) {
1023                 ret = -ENODEV;
1024                 goto err_put_ctrl;
1025         }
1026
1027         /* assign memory mapped starting address and mapped size. */
1028         f->memmap_phy = res->start;
1029         f->memmap_phy_size = resource_size(res);
1030
1031         /* find the clocks */
1032         f->clk_en = devm_clk_get(dev, "fspi_en");
1033         if (IS_ERR(f->clk_en)) {
1034                 ret = PTR_ERR(f->clk_en);
1035                 goto err_put_ctrl;
1036         }
1037
1038         f->clk = devm_clk_get(dev, "fspi");
1039         if (IS_ERR(f->clk)) {
1040                 ret = PTR_ERR(f->clk);
1041                 goto err_put_ctrl;
1042         }
1043
1044         ret = nxp_fspi_clk_prep_enable(f);
1045         if (ret) {
1046                 dev_err(dev, "can not enable the clock\n");
1047                 goto err_put_ctrl;
1048         }
1049
1050         /* find the irq */
1051         ret = platform_get_irq(pdev, 0);
1052         if (ret < 0)
1053                 goto err_disable_clk;
1054
1055         ret = devm_request_irq(dev, ret,
1056                         nxp_fspi_irq_handler, 0, pdev->name, f);
1057         if (ret) {
1058                 dev_err(dev, "failed to request irq: %d\n", ret);
1059                 goto err_disable_clk;
1060         }
1061
1062         mutex_init(&f->lock);
1063
1064         ctlr->bus_num = -1;
1065         ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT;
1066         ctlr->mem_ops = &nxp_fspi_mem_ops;
1067
1068         nxp_fspi_default_setup(f);
1069
1070         ctlr->dev.of_node = np;
1071
1072         ret = devm_spi_register_controller(&pdev->dev, ctlr);
1073         if (ret)
1074                 goto err_destroy_mutex;
1075
1076         return 0;
1077
1078 err_destroy_mutex:
1079         mutex_destroy(&f->lock);
1080
1081 err_disable_clk:
1082         nxp_fspi_clk_disable_unprep(f);
1083
1084 err_put_ctrl:
1085         spi_controller_put(ctlr);
1086
1087         dev_err(dev, "NXP FSPI probe failed\n");
1088         return ret;
1089 }
1090
1091 static int nxp_fspi_remove(struct platform_device *pdev)
1092 {
1093         struct nxp_fspi *f = platform_get_drvdata(pdev);
1094
1095         /* disable the hardware */
1096         fspi_writel(f, FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0);
1097
1098         nxp_fspi_clk_disable_unprep(f);
1099
1100         mutex_destroy(&f->lock);
1101
1102         if (f->ahb_addr)
1103                 iounmap(f->ahb_addr);
1104
1105         return 0;
1106 }
1107
1108 static int nxp_fspi_suspend(struct device *dev)
1109 {
1110         return 0;
1111 }
1112
1113 static int nxp_fspi_resume(struct device *dev)
1114 {
1115         struct nxp_fspi *f = dev_get_drvdata(dev);
1116
1117         nxp_fspi_default_setup(f);
1118
1119         return 0;
1120 }
1121
1122 static const struct of_device_id nxp_fspi_dt_ids[] = {
1123         { .compatible = "nxp,lx2160a-fspi", .data = (void *)&lx2160a_data, },
1124         { .compatible = "nxp,imx8mm-fspi", .data = (void *)&imx8mm_data, },
1125         { .compatible = "nxp,imx8qxp-fspi", .data = (void *)&imx8qxp_data, },
1126         { /* sentinel */ }
1127 };
1128 MODULE_DEVICE_TABLE(of, nxp_fspi_dt_ids);
1129
1130 static const struct dev_pm_ops nxp_fspi_pm_ops = {
1131         .suspend        = nxp_fspi_suspend,
1132         .resume         = nxp_fspi_resume,
1133 };
1134
1135 static struct platform_driver nxp_fspi_driver = {
1136         .driver = {
1137                 .name   = "nxp-fspi",
1138                 .of_match_table = nxp_fspi_dt_ids,
1139                 .pm =   &nxp_fspi_pm_ops,
1140         },
1141         .probe          = nxp_fspi_probe,
1142         .remove         = nxp_fspi_remove,
1143 };
1144 module_platform_driver(nxp_fspi_driver);
1145
1146 MODULE_DESCRIPTION("NXP FSPI Controller Driver");
1147 MODULE_AUTHOR("NXP Semiconductor");
1148 MODULE_AUTHOR("Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>");
1149 MODULE_AUTHOR("Boris Brezillon <bbrezillon@kernel.org>");
1150 MODULE_AUTHOR("Frieder Schrempf <frieder.schrempf@kontron.de>");
1151 MODULE_LICENSE("GPL v2");