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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / spi / spi-stm32.c
blob44ac6eb3298d4af6916dd4e1e6df8d6ec2e91dab
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // STMicroelectronics STM32 SPI Controller driver (master mode only)
4 //
5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 // Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
7
8 #include <linux/debugfs.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dmaengine.h>
12 #include <linux/interrupt.h>
13 #include <linux/iopoll.h>
14 #include <linux/module.h>
15 #include <linux/of_platform.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/reset.h>
18 #include <linux/spi/spi.h>
19
20 #define DRIVER_NAME "spi_stm32"
21
22 /* STM32F4 SPI registers */
23 #define STM32F4_SPI_CR1 0x00
24 #define STM32F4_SPI_CR2 0x04
25 #define STM32F4_SPI_SR 0x08
26 #define STM32F4_SPI_DR 0x0C
27 #define STM32F4_SPI_I2SCFGR 0x1C
28
29 /* STM32F4_SPI_CR1 bit fields */
30 #define STM32F4_SPI_CR1_CPHA BIT(0)
31 #define STM32F4_SPI_CR1_CPOL BIT(1)
32 #define STM32F4_SPI_CR1_MSTR BIT(2)
33 #define STM32F4_SPI_CR1_BR_SHIFT 3
34 #define STM32F4_SPI_CR1_BR GENMASK(5, 3)
35 #define STM32F4_SPI_CR1_SPE BIT(6)
36 #define STM32F4_SPI_CR1_LSBFRST BIT(7)
37 #define STM32F4_SPI_CR1_SSI BIT(8)
38 #define STM32F4_SPI_CR1_SSM BIT(9)
39 #define STM32F4_SPI_CR1_RXONLY BIT(10)
40 #define STM32F4_SPI_CR1_DFF BIT(11)
41 #define STM32F4_SPI_CR1_CRCNEXT BIT(12)
42 #define STM32F4_SPI_CR1_CRCEN BIT(13)
43 #define STM32F4_SPI_CR1_BIDIOE BIT(14)
44 #define STM32F4_SPI_CR1_BIDIMODE BIT(15)
45 #define STM32F4_SPI_CR1_BR_MIN 0
46 #define STM32F4_SPI_CR1_BR_MAX (GENMASK(5, 3) >> 3)
47
48 /* STM32F4_SPI_CR2 bit fields */
49 #define STM32F4_SPI_CR2_RXDMAEN BIT(0)
50 #define STM32F4_SPI_CR2_TXDMAEN BIT(1)
51 #define STM32F4_SPI_CR2_SSOE BIT(2)
52 #define STM32F4_SPI_CR2_FRF BIT(4)
53 #define STM32F4_SPI_CR2_ERRIE BIT(5)
54 #define STM32F4_SPI_CR2_RXNEIE BIT(6)
55 #define STM32F4_SPI_CR2_TXEIE BIT(7)
56
57 /* STM32F4_SPI_SR bit fields */
58 #define STM32F4_SPI_SR_RXNE BIT(0)
59 #define STM32F4_SPI_SR_TXE BIT(1)
60 #define STM32F4_SPI_SR_CHSIDE BIT(2)
61 #define STM32F4_SPI_SR_UDR BIT(3)
62 #define STM32F4_SPI_SR_CRCERR BIT(4)
63 #define STM32F4_SPI_SR_MODF BIT(5)
64 #define STM32F4_SPI_SR_OVR BIT(6)
65 #define STM32F4_SPI_SR_BSY BIT(7)
66 #define STM32F4_SPI_SR_FRE BIT(8)
67
68 /* STM32F4_SPI_I2SCFGR bit fields */
69 #define STM32F4_SPI_I2SCFGR_I2SMOD BIT(11)
70
71 /* STM32F4 SPI Baud Rate min/max divisor */
72 #define STM32F4_SPI_BR_DIV_MIN (2 << STM32F4_SPI_CR1_BR_MIN)
73 #define STM32F4_SPI_BR_DIV_MAX (2 << STM32F4_SPI_CR1_BR_MAX)
74
75 /* STM32H7 SPI registers */
76 #define STM32H7_SPI_CR1 0x00
77 #define STM32H7_SPI_CR2 0x04
78 #define STM32H7_SPI_CFG1 0x08
79 #define STM32H7_SPI_CFG2 0x0C
80 #define STM32H7_SPI_IER 0x10
81 #define STM32H7_SPI_SR 0x14
82 #define STM32H7_SPI_IFCR 0x18
83 #define STM32H7_SPI_TXDR 0x20
84 #define STM32H7_SPI_RXDR 0x30
85 #define STM32H7_SPI_I2SCFGR 0x50
86
87 /* STM32H7_SPI_CR1 bit fields */
88 #define STM32H7_SPI_CR1_SPE BIT(0)
89 #define STM32H7_SPI_CR1_MASRX BIT(8)
90 #define STM32H7_SPI_CR1_CSTART BIT(9)
91 #define STM32H7_SPI_CR1_CSUSP BIT(10)
92 #define STM32H7_SPI_CR1_HDDIR BIT(11)
93 #define STM32H7_SPI_CR1_SSI BIT(12)
94
95 /* STM32H7_SPI_CR2 bit fields */
96 #define STM32H7_SPI_CR2_TSIZE_SHIFT 0
97 #define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
98
99 /* STM32H7_SPI_CFG1 bit fields */
100 #define STM32H7_SPI_CFG1_DSIZE_SHIFT 0
101 #define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
102 #define STM32H7_SPI_CFG1_FTHLV_SHIFT 5
103 #define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
104 #define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
105 #define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
106 #define STM32H7_SPI_CFG1_MBR_SHIFT 28
107 #define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
108 #define STM32H7_SPI_CFG1_MBR_MIN 0
109 #define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
110
111 /* STM32H7_SPI_CFG2 bit fields */
112 #define STM32H7_SPI_CFG2_MIDI_SHIFT 4
113 #define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
114 #define STM32H7_SPI_CFG2_COMM_SHIFT 17
115 #define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
116 #define STM32H7_SPI_CFG2_SP_SHIFT 19
117 #define STM32H7_SPI_CFG2_SP GENMASK(21, 19)
118 #define STM32H7_SPI_CFG2_MASTER BIT(22)
119 #define STM32H7_SPI_CFG2_LSBFRST BIT(23)
120 #define STM32H7_SPI_CFG2_CPHA BIT(24)
121 #define STM32H7_SPI_CFG2_CPOL BIT(25)
122 #define STM32H7_SPI_CFG2_SSM BIT(26)
123 #define STM32H7_SPI_CFG2_AFCNTR BIT(31)
124
125 /* STM32H7_SPI_IER bit fields */
126 #define STM32H7_SPI_IER_RXPIE BIT(0)
127 #define STM32H7_SPI_IER_TXPIE BIT(1)
128 #define STM32H7_SPI_IER_DXPIE BIT(2)
129 #define STM32H7_SPI_IER_EOTIE BIT(3)
130 #define STM32H7_SPI_IER_TXTFIE BIT(4)
131 #define STM32H7_SPI_IER_OVRIE BIT(6)
132 #define STM32H7_SPI_IER_MODFIE BIT(9)
133 #define STM32H7_SPI_IER_ALL GENMASK(10, 0)
134
135 /* STM32H7_SPI_SR bit fields */
136 #define STM32H7_SPI_SR_RXP BIT(0)
137 #define STM32H7_SPI_SR_TXP BIT(1)
138 #define STM32H7_SPI_SR_EOT BIT(3)
139 #define STM32H7_SPI_SR_OVR BIT(6)
140 #define STM32H7_SPI_SR_MODF BIT(9)
141 #define STM32H7_SPI_SR_SUSP BIT(11)
142 #define STM32H7_SPI_SR_RXPLVL_SHIFT 13
143 #define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
144 #define STM32H7_SPI_SR_RXWNE BIT(15)
145
146 /* STM32H7_SPI_IFCR bit fields */
147 #define STM32H7_SPI_IFCR_ALL GENMASK(11, 3)
148
149 /* STM32H7_SPI_I2SCFGR bit fields */
150 #define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0)
151
152 /* STM32H7 SPI Master Baud Rate min/max divisor */
153 #define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN)
154 #define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX)
155
156 /* STM32H7 SPI Communication mode */
157 #define STM32H7_SPI_FULL_DUPLEX 0
158 #define STM32H7_SPI_SIMPLEX_TX 1
159 #define STM32H7_SPI_SIMPLEX_RX 2
160 #define STM32H7_SPI_HALF_DUPLEX 3
161
162 /* SPI Communication type */
163 #define SPI_FULL_DUPLEX 0
164 #define SPI_SIMPLEX_TX 1
165 #define SPI_SIMPLEX_RX 2
166 #define SPI_3WIRE_TX 3
167 #define SPI_3WIRE_RX 4
168
169 #define SPI_1HZ_NS 1000000000
170
171 /*
172 * use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers
173 * without fifo buffers.
174 */
175 #define SPI_DMA_MIN_BYTES 16
176
177 /**
178 * struct stm32_spi_reg - stm32 SPI register & bitfield desc
179 * @reg: register offset
180 * @mask: bitfield mask
181 * @shift: left shift
182 */
183 struct stm32_spi_reg {
184 int reg;
185 int mask;
186 int shift;
187 };
188
189 /**
190 * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
191 * @en: enable register and SPI enable bit
192 * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit
193 * @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit
194 * @cpol: clock polarity register and polarity bit
195 * @cpha: clock phase register and phase bit
196 * @lsb_first: LSB transmitted first register and bit
197 * @br: baud rate register and bitfields
198 * @rx: SPI RX data register
199 * @tx: SPI TX data register
200 */
201 struct stm32_spi_regspec {
202 const struct stm32_spi_reg en;
203 const struct stm32_spi_reg dma_rx_en;
204 const struct stm32_spi_reg dma_tx_en;
205 const struct stm32_spi_reg cpol;
206 const struct stm32_spi_reg cpha;
207 const struct stm32_spi_reg lsb_first;
208 const struct stm32_spi_reg br;
209 const struct stm32_spi_reg rx;
210 const struct stm32_spi_reg tx;
211 };
212
213 struct stm32_spi;
214
215 /**
216 * struct stm32_spi_cfg - stm32 compatible configuration data
217 * @regs: registers descriptions
218 * @get_fifo_size: routine to get fifo size
219 * @get_bpw_mask: routine to get bits per word mask
220 * @disable: routine to disable controller
221 * @config: routine to configure controller as SPI Master
222 * @set_bpw: routine to configure registers to for bits per word
223 * @set_mode: routine to configure registers to desired mode
224 * @set_data_idleness: optional routine to configure registers to desired idle
225 * time between frames (if driver has this functionality)
226 * @set_number_of_data: optional routine to configure registers to desired
227 * number of data (if driver has this functionality)
228 * @can_dma: routine to determine if the transfer is eligible for DMA use
229 * @transfer_one_dma_start: routine to start transfer a single spi_transfer
230 * using DMA
231 * @dma_rx_cb: routine to call after DMA RX channel operation is complete
232 * @dma_tx_cb: routine to call after DMA TX channel operation is complete
233 * @transfer_one_irq: routine to configure interrupts for driver
234 * @irq_handler_event: Interrupt handler for SPI controller events
235 * @irq_handler_thread: thread of interrupt handler for SPI controller
236 * @baud_rate_div_min: minimum baud rate divisor
237 * @baud_rate_div_max: maximum baud rate divisor
238 * @has_fifo: boolean to know if fifo is used for driver
239 * @has_startbit: boolean to know if start bit is used to start transfer
240 */
241 struct stm32_spi_cfg {
242 const struct stm32_spi_regspec *regs;
243 int (*get_fifo_size)(struct stm32_spi *spi);
244 int (*get_bpw_mask)(struct stm32_spi *spi);
245 void (*disable)(struct stm32_spi *spi);
246 int (*config)(struct stm32_spi *spi);
247 void (*set_bpw)(struct stm32_spi *spi);
248 int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
249 void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
250 int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
251 void (*transfer_one_dma_start)(struct stm32_spi *spi);
252 void (*dma_rx_cb)(void *data);
253 void (*dma_tx_cb)(void *data);
254 int (*transfer_one_irq)(struct stm32_spi *spi);
255 irqreturn_t (*irq_handler_event)(int irq, void *dev_id);
256 irqreturn_t (*irq_handler_thread)(int irq, void *dev_id);
257 unsigned int baud_rate_div_min;
258 unsigned int baud_rate_div_max;
259 bool has_fifo;
260 };
261
262 /**
263 * struct stm32_spi - private data of the SPI controller
264 * @dev: driver model representation of the controller
265 * @master: controller master interface
266 * @cfg: compatible configuration data
267 * @base: virtual memory area
268 * @clk: hw kernel clock feeding the SPI clock generator
269 * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
270 * @rst: SPI controller reset line
271 * @lock: prevent I/O concurrent access
272 * @irq: SPI controller interrupt line
273 * @fifo_size: size of the embedded fifo in bytes
274 * @cur_midi: master inter-data idleness in ns
275 * @cur_speed: speed configured in Hz
276 * @cur_bpw: number of bits in a single SPI data frame
277 * @cur_fthlv: fifo threshold level (data frames in a single data packet)
278 * @cur_comm: SPI communication mode
279 * @cur_xferlen: current transfer length in bytes
280 * @cur_usedma: boolean to know if dma is used in current transfer
281 * @tx_buf: data to be written, or NULL
282 * @rx_buf: data to be read, or NULL
283 * @tx_len: number of data to be written in bytes
284 * @rx_len: number of data to be read in bytes
285 * @dma_tx: dma channel for TX transfer
286 * @dma_rx: dma channel for RX transfer
287 * @phys_addr: SPI registers physical base address
288 */
289 struct stm32_spi {
290 struct device *dev;
291 struct spi_master *master;
292 const struct stm32_spi_cfg *cfg;
293 void __iomem *base;
294 struct clk *clk;
295 u32 clk_rate;
296 struct reset_control *rst;
297 spinlock_t lock; /* prevent I/O concurrent access */
298 int irq;
299 unsigned int fifo_size;
300
301 unsigned int cur_midi;
302 unsigned int cur_speed;
303 unsigned int cur_bpw;
304 unsigned int cur_fthlv;
305 unsigned int cur_comm;
306 unsigned int cur_xferlen;
307 bool cur_usedma;
308
309 const void *tx_buf;
310 void *rx_buf;
311 int tx_len;
312 int rx_len;
313 struct dma_chan *dma_tx;
314 struct dma_chan *dma_rx;
315 dma_addr_t phys_addr;
316 };
317
318 static const struct stm32_spi_regspec stm32f4_spi_regspec = {
319 .en = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE },
320
321 .dma_rx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXDMAEN },
322 .dma_tx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN },
323
324 .cpol = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPOL },
325 .cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA },
326 .lsb_first = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_LSBFRST },
327 .br = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_BR, STM32F4_SPI_CR1_BR_SHIFT },
328
329 .rx = { STM32F4_SPI_DR },
330 .tx = { STM32F4_SPI_DR },
331 };
332
333 static const struct stm32_spi_regspec stm32h7_spi_regspec = {
334 /* SPI data transfer is enabled but spi_ker_ck is idle.
335 * CFG1 and CFG2 registers are write protected when SPE is enabled.
336 */
337 .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE },
338
339 .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN },
340 .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN },
341
342 .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL },
343 .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
344 .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST },
345 .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR,
346 STM32H7_SPI_CFG1_MBR_SHIFT },
347
348 .rx = { STM32H7_SPI_RXDR },
349 .tx = { STM32H7_SPI_TXDR },
350 };
351
352 static inline void stm32_spi_set_bits(struct stm32_spi *spi,
353 u32 offset, u32 bits)
354 {
355 writel_relaxed(readl_relaxed(spi->base + offset) | bits,
356 spi->base + offset);
357 }
358
359 static inline void stm32_spi_clr_bits(struct stm32_spi *spi,
360 u32 offset, u32 bits)
361 {
362 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
363 spi->base + offset);
364 }
365
366 /**
367 * stm32h7_spi_get_fifo_size - Return fifo size
368 * @spi: pointer to the spi controller data structure
369 */
370 static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi)
371 {
372 unsigned long flags;
373 u32 count = 0;
374
375 spin_lock_irqsave(&spi->lock, flags);
376
377 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
378
379 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
380 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
381
382 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
383
384 spin_unlock_irqrestore(&spi->lock, flags);
385
386 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
387
388 return count;
389 }
390
391 /**
392 * stm32f4_spi_get_bpw_mask - Return bits per word mask
393 * @spi: pointer to the spi controller data structure
394 */
395 static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi)
396 {
397 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
398 return SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
399 }
400
401 /**
402 * stm32h7_spi_get_bpw_mask - Return bits per word mask
403 * @spi: pointer to the spi controller data structure
404 */
405 static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
406 {
407 unsigned long flags;
408 u32 cfg1, max_bpw;
409
410 spin_lock_irqsave(&spi->lock, flags);
411
412 /*
413 * The most significant bit at DSIZE bit field is reserved when the
414 * maximum data size of periperal instances is limited to 16-bit
415 */
416 stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
417
418 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
419 max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >>
420 STM32H7_SPI_CFG1_DSIZE_SHIFT;
421 max_bpw += 1;
422
423 spin_unlock_irqrestore(&spi->lock, flags);
424
425 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
426
427 return SPI_BPW_RANGE_MASK(4, max_bpw);
428 }
429
430 /**
431 * stm32_spi_prepare_mbr - Determine baud rate divisor value
432 * @spi: pointer to the spi controller data structure
433 * @speed_hz: requested speed
434 * @min_div: minimum baud rate divisor
435 * @max_div: maximum baud rate divisor
436 *
437 * Return baud rate divisor value in case of success or -EINVAL
438 */
439 static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
440 u32 min_div, u32 max_div)
441 {
442 u32 div, mbrdiv;
443
444 div = DIV_ROUND_UP(spi->clk_rate, speed_hz);
445
446 /*
447 * SPI framework set xfer->speed_hz to master->max_speed_hz if
448 * xfer->speed_hz is greater than master->max_speed_hz, and it returns
449 * an error when xfer->speed_hz is lower than master->min_speed_hz, so
450 * no need to check it there.
451 * However, we need to ensure the following calculations.
452 */
453 if ((div < min_div) || (div > max_div))
454 return -EINVAL;
455
456 /* Determine the first power of 2 greater than or equal to div */
457 if (div & (div - 1))
458 mbrdiv = fls(div);
459 else
460 mbrdiv = fls(div) - 1;
461
462 spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
463
464 return mbrdiv - 1;
465 }
466
467 /**
468 * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
469 * @spi: pointer to the spi controller data structure
470 */
471 static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi)
472 {
473 u32 fthlv, half_fifo;
474
475 /* data packet should not exceed 1/2 of fifo space */
476 half_fifo = (spi->fifo_size / 2);
477
478 if (spi->cur_bpw <= 8)
479 fthlv = half_fifo;
480 else if (spi->cur_bpw <= 16)
481 fthlv = half_fifo / 2;
482 else
483 fthlv = half_fifo / 4;
484
485 /* align packet size with data registers access */
486 if (spi->cur_bpw > 8)
487 fthlv -= (fthlv % 2); /* multiple of 2 */
488 else
489 fthlv -= (fthlv % 4); /* multiple of 4 */
490
491 return fthlv;
492 }
493
494 /**
495 * stm32f4_spi_write_tx - Write bytes to Transmit Data Register
496 * @spi: pointer to the spi controller data structure
497 *
498 * Read from tx_buf depends on remaining bytes to avoid to read beyond
499 * tx_buf end.
500 */
501 static void stm32f4_spi_write_tx(struct stm32_spi *spi)
502 {
503 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
504 STM32F4_SPI_SR_TXE)) {
505 u32 offs = spi->cur_xferlen - spi->tx_len;
506
507 if (spi->cur_bpw == 16) {
508 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
509
510 writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR);
511 spi->tx_len -= sizeof(u16);
512 } else {
513 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
514
515 writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR);
516 spi->tx_len -= sizeof(u8);
517 }
518 }
519
520 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
521 }
522
523 /**
524 * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
525 * @spi: pointer to the spi controller data structure
526 *
527 * Read from tx_buf depends on remaining bytes to avoid to read beyond
528 * tx_buf end.
529 */
530 static void stm32h7_spi_write_txfifo(struct stm32_spi *spi)
531 {
532 while ((spi->tx_len > 0) &&
533 (readl_relaxed(spi->base + STM32H7_SPI_SR) &
534 STM32H7_SPI_SR_TXP)) {
535 u32 offs = spi->cur_xferlen - spi->tx_len;
536
537 if (spi->tx_len >= sizeof(u32)) {
538 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
539
540 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
541 spi->tx_len -= sizeof(u32);
542 } else if (spi->tx_len >= sizeof(u16)) {
543 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
544
545 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
546 spi->tx_len -= sizeof(u16);
547 } else {
548 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
549
550 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
551 spi->tx_len -= sizeof(u8);
552 }
553 }
554
555 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
556 }
557
558 /**
559 * stm32f4_spi_read_rx - Read bytes from Receive Data Register
560 * @spi: pointer to the spi controller data structure
561 *
562 * Write in rx_buf depends on remaining bytes to avoid to write beyond
563 * rx_buf end.
564 */
565 static void stm32f4_spi_read_rx(struct stm32_spi *spi)
566 {
567 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
568 STM32F4_SPI_SR_RXNE)) {
569 u32 offs = spi->cur_xferlen - spi->rx_len;
570
571 if (spi->cur_bpw == 16) {
572 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
573
574 *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR);
575 spi->rx_len -= sizeof(u16);
576 } else {
577 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
578
579 *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR);
580 spi->rx_len -= sizeof(u8);
581 }
582 }
583
584 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
585 }
586
587 /**
588 * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
589 * @spi: pointer to the spi controller data structure
590 * @flush: boolean indicating that FIFO should be flushed
591 *
592 * Write in rx_buf depends on remaining bytes to avoid to write beyond
593 * rx_buf end.
594 */
595 static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
596 {
597 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
598 u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
599 STM32H7_SPI_SR_RXPLVL_SHIFT;
600
601 while ((spi->rx_len > 0) &&
602 ((sr & STM32H7_SPI_SR_RXP) ||
603 (flush && ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) {
604 u32 offs = spi->cur_xferlen - spi->rx_len;
605
606 if ((spi->rx_len >= sizeof(u32)) ||
607 (flush && (sr & STM32H7_SPI_SR_RXWNE))) {
608 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
609
610 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
611 spi->rx_len -= sizeof(u32);
612 } else if ((spi->rx_len >= sizeof(u16)) ||
613 (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) {
614 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
615
616 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
617 spi->rx_len -= sizeof(u16);
618 } else {
619 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
620
621 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
622 spi->rx_len -= sizeof(u8);
623 }
624
625 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
626 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
627 STM32H7_SPI_SR_RXPLVL_SHIFT;
628 }
629
630 dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
631 flush ? "(flush)" : "", spi->rx_len);
632 }
633
634 /**
635 * stm32_spi_enable - Enable SPI controller
636 * @spi: pointer to the spi controller data structure
637 */
638 static void stm32_spi_enable(struct stm32_spi *spi)
639 {
640 dev_dbg(spi->dev, "enable controller\n");
641
642 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg,
643 spi->cfg->regs->en.mask);
644 }
645
646 /**
647 * stm32f4_spi_disable - Disable SPI controller
648 * @spi: pointer to the spi controller data structure
649 */
650 static void stm32f4_spi_disable(struct stm32_spi *spi)
651 {
652 unsigned long flags;
653 u32 sr;
654
655 dev_dbg(spi->dev, "disable controller\n");
656
657 spin_lock_irqsave(&spi->lock, flags);
658
659 if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) &
660 STM32F4_SPI_CR1_SPE)) {
661 spin_unlock_irqrestore(&spi->lock, flags);
662 return;
663 }
664
665 /* Disable interrupts */
666 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE |
667 STM32F4_SPI_CR2_RXNEIE |
668 STM32F4_SPI_CR2_ERRIE);
669
670 /* Wait until BSY = 0 */
671 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR,
672 sr, !(sr & STM32F4_SPI_SR_BSY),
673 10, 100000) < 0) {
674 dev_warn(spi->dev, "disabling condition timeout\n");
675 }
676
677 if (spi->cur_usedma && spi->dma_tx)
678 dmaengine_terminate_all(spi->dma_tx);
679 if (spi->cur_usedma && spi->dma_rx)
680 dmaengine_terminate_all(spi->dma_rx);
681
682 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE);
683
684 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN |
685 STM32F4_SPI_CR2_RXDMAEN);
686
687 /* Sequence to clear OVR flag */
688 readl_relaxed(spi->base + STM32F4_SPI_DR);
689 readl_relaxed(spi->base + STM32F4_SPI_SR);
690
691 spin_unlock_irqrestore(&spi->lock, flags);
692 }
693
694 /**
695 * stm32h7_spi_disable - Disable SPI controller
696 * @spi: pointer to the spi controller data structure
697 *
698 * RX-Fifo is flushed when SPI controller is disabled. To prevent any data
699 * loss, use stm32h7_spi_read_rxfifo(flush) to read the remaining bytes in
700 * RX-Fifo.
701 * Normally, if TSIZE has been configured, we should relax the hardware at the
702 * reception of the EOT interrupt. But in case of error, EOT will not be
703 * raised. So the subsystem unprepare_message call allows us to properly
704 * complete the transfer from an hardware point of view.
705 */
706 static void stm32h7_spi_disable(struct stm32_spi *spi)
707 {
708 unsigned long flags;
709 u32 cr1, sr;
710
711 dev_dbg(spi->dev, "disable controller\n");
712
713 spin_lock_irqsave(&spi->lock, flags);
714
715 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
716
717 if (!(cr1 & STM32H7_SPI_CR1_SPE)) {
718 spin_unlock_irqrestore(&spi->lock, flags);
719 return;
720 }
721
722 /* Wait on EOT or suspend the flow */
723 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR,
724 sr, !(sr & STM32H7_SPI_SR_EOT),
725 10, 100000) < 0) {
726 if (cr1 & STM32H7_SPI_CR1_CSTART) {
727 writel_relaxed(cr1 | STM32H7_SPI_CR1_CSUSP,
728 spi->base + STM32H7_SPI_CR1);
729 if (readl_relaxed_poll_timeout_atomic(
730 spi->base + STM32H7_SPI_SR,
731 sr, !(sr & STM32H7_SPI_SR_SUSP),
732 10, 100000) < 0)
733 dev_warn(spi->dev,
734 "Suspend request timeout\n");
735 }
736 }
737
738 if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0))
739 stm32h7_spi_read_rxfifo(spi, true);
740
741 if (spi->cur_usedma && spi->dma_tx)
742 dmaengine_terminate_all(spi->dma_tx);
743 if (spi->cur_usedma && spi->dma_rx)
744 dmaengine_terminate_all(spi->dma_rx);
745
746 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
747
748 stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |
749 STM32H7_SPI_CFG1_RXDMAEN);
750
751 /* Disable interrupts and clear status flags */
752 writel_relaxed(0, spi->base + STM32H7_SPI_IER);
753 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
754
755 spin_unlock_irqrestore(&spi->lock, flags);
756 }
757
758 /**
759 * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
760 * @master: controller master interface
761 * @spi_dev: pointer to the spi device
762 * @transfer: pointer to spi transfer
763 *
764 * If driver has fifo and the current transfer size is greater than fifo size,
765 * use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes.
766 */
767 static bool stm32_spi_can_dma(struct spi_master *master,
768 struct spi_device *spi_dev,
769 struct spi_transfer *transfer)
770 {
771 unsigned int dma_size;
772 struct stm32_spi *spi = spi_master_get_devdata(master);
773
774 if (spi->cfg->has_fifo)
775 dma_size = spi->fifo_size;
776 else
777 dma_size = SPI_DMA_MIN_BYTES;
778
779 dev_dbg(spi->dev, "%s: %s\n", __func__,
780 (transfer->len > dma_size) ? "true" : "false");
781
782 return (transfer->len > dma_size);
783 }
784
785 /**
786 * stm32f4_spi_irq_event - Interrupt handler for SPI controller events
787 * @irq: interrupt line
788 * @dev_id: SPI controller master interface
789 */
790 static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id)
791 {
792 struct spi_master *master = dev_id;
793 struct stm32_spi *spi = spi_master_get_devdata(master);
794 u32 sr, mask = 0;
795 unsigned long flags;
796 bool end = false;
797
798 spin_lock_irqsave(&spi->lock, flags);
799
800 sr = readl_relaxed(spi->base + STM32F4_SPI_SR);
801 /*
802 * BSY flag is not handled in interrupt but it is normal behavior when
803 * this flag is set.
804 */
805 sr &= ~STM32F4_SPI_SR_BSY;
806
807 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX ||
808 spi->cur_comm == SPI_3WIRE_TX)) {
809 /* OVR flag shouldn't be handled for TX only mode */
810 sr &= ~STM32F4_SPI_SR_OVR | STM32F4_SPI_SR_RXNE;
811 mask |= STM32F4_SPI_SR_TXE;
812 }
813
814 if (!spi->cur_usedma && spi->cur_comm == SPI_FULL_DUPLEX) {
815 /* TXE flag is set and is handled when RXNE flag occurs */
816 sr &= ~STM32F4_SPI_SR_TXE;
817 mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR;
818 }
819
820 if (!(sr & mask)) {
821 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
822 spin_unlock_irqrestore(&spi->lock, flags);
823 return IRQ_NONE;
824 }
825
826 if (sr & STM32F4_SPI_SR_OVR) {
827 dev_warn(spi->dev, "Overrun: received value discarded\n");
828
829 /* Sequence to clear OVR flag */
830 readl_relaxed(spi->base + STM32F4_SPI_DR);
831 readl_relaxed(spi->base + STM32F4_SPI_SR);
832
833 /*
834 * If overrun is detected, it means that something went wrong,
835 * so stop the current transfer. Transfer can wait for next
836 * RXNE but DR is already read and end never happens.
837 */
838 end = true;
839 goto end_irq;
840 }
841
842 if (sr & STM32F4_SPI_SR_TXE) {
843 if (spi->tx_buf)
844 stm32f4_spi_write_tx(spi);
845 if (spi->tx_len == 0)
846 end = true;
847 }
848
849 if (sr & STM32F4_SPI_SR_RXNE) {
850 stm32f4_spi_read_rx(spi);
851 if (spi->rx_len == 0)
852 end = true;
853 else /* Load data for discontinuous mode */
854 stm32f4_spi_write_tx(spi);
855 }
856
857 end_irq:
858 if (end) {
859 /* Immediately disable interrupts to do not generate new one */
860 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2,
861 STM32F4_SPI_CR2_TXEIE |
862 STM32F4_SPI_CR2_RXNEIE |
863 STM32F4_SPI_CR2_ERRIE);
864 spin_unlock_irqrestore(&spi->lock, flags);
865 return IRQ_WAKE_THREAD;
866 }
867
868 spin_unlock_irqrestore(&spi->lock, flags);
869 return IRQ_HANDLED;
870 }
871
872 /**
873 * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
874 * @irq: interrupt line
875 * @dev_id: SPI controller master interface
876 */
877 static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id)
878 {
879 struct spi_master *master = dev_id;
880 struct stm32_spi *spi = spi_master_get_devdata(master);
881
882 spi_finalize_current_transfer(master);
883 stm32f4_spi_disable(spi);
884
885 return IRQ_HANDLED;
886 }
887
888 /**
889 * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
890 * @irq: interrupt line
891 * @dev_id: SPI controller master interface
892 */
893 static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
894 {
895 struct spi_master *master = dev_id;
896 struct stm32_spi *spi = spi_master_get_devdata(master);
897 u32 sr, ier, mask;
898 unsigned long flags;
899 bool end = false;
900
901 spin_lock_irqsave(&spi->lock, flags);
902
903 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
904 ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
905
906 mask = ier;
907 /* EOTIE is triggered on EOT, SUSP and TXC events. */
908 mask |= STM32H7_SPI_SR_SUSP;
909 /*
910 * When TXTF is set, DXPIE and TXPIE are cleared. So in case of
911 * Full-Duplex, need to poll RXP event to know if there are remaining
912 * data, before disabling SPI.
913 */
914 if (spi->rx_buf && !spi->cur_usedma)
915 mask |= STM32H7_SPI_SR_RXP;
916
917 if (!(sr & mask)) {
918 dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
919 sr, ier);
920 spin_unlock_irqrestore(&spi->lock, flags);
921 return IRQ_NONE;
922 }
923
924 if (sr & STM32H7_SPI_SR_SUSP) {
925 dev_warn(spi->dev, "Communication suspended\n");
926 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
927 stm32h7_spi_read_rxfifo(spi, false);
928 /*
929 * If communication is suspended while using DMA, it means
930 * that something went wrong, so stop the current transfer
931 */
932 if (spi->cur_usedma)
933 end = true;
934 }
935
936 if (sr & STM32H7_SPI_SR_MODF) {
937 dev_warn(spi->dev, "Mode fault: transfer aborted\n");
938 end = true;
939 }
940
941 if (sr & STM32H7_SPI_SR_OVR) {
942 dev_warn(spi->dev, "Overrun: received value discarded\n");
943 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
944 stm32h7_spi_read_rxfifo(spi, false);
945 /*
946 * If overrun is detected while using DMA, it means that
947 * something went wrong, so stop the current transfer
948 */
949 if (spi->cur_usedma)
950 end = true;
951 }
952
953 if (sr & STM32H7_SPI_SR_EOT) {
954 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
955 stm32h7_spi_read_rxfifo(spi, true);
956 end = true;
957 }
958
959 if (sr & STM32H7_SPI_SR_TXP)
960 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
961 stm32h7_spi_write_txfifo(spi);
962
963 if (sr & STM32H7_SPI_SR_RXP)
964 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
965 stm32h7_spi_read_rxfifo(spi, false);
966
967 writel_relaxed(mask, spi->base + STM32H7_SPI_IFCR);
968
969 spin_unlock_irqrestore(&spi->lock, flags);
970
971 if (end) {
972 spi_finalize_current_transfer(master);
973 stm32h7_spi_disable(spi);
974 }
975
976 return IRQ_HANDLED;
977 }
978
979 /**
980 * stm32_spi_prepare_msg - set up the controller to transfer a single message
981 * @master: controller master interface
982 * @msg: pointer to spi message
983 */
984 static int stm32_spi_prepare_msg(struct spi_master *master,
985 struct spi_message *msg)
986 {
987 struct stm32_spi *spi = spi_master_get_devdata(master);
988 struct spi_device *spi_dev = msg->spi;
989 struct device_node *np = spi_dev->dev.of_node;
990 unsigned long flags;
991 u32 clrb = 0, setb = 0;
992
993 /* SPI slave device may need time between data frames */
994 spi->cur_midi = 0;
995 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
996 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
997
998 if (spi_dev->mode & SPI_CPOL)
999 setb |= spi->cfg->regs->cpol.mask;
1000 else
1001 clrb |= spi->cfg->regs->cpol.mask;
1002
1003 if (spi_dev->mode & SPI_CPHA)
1004 setb |= spi->cfg->regs->cpha.mask;
1005 else
1006 clrb |= spi->cfg->regs->cpha.mask;
1007
1008 if (spi_dev->mode & SPI_LSB_FIRST)
1009 setb |= spi->cfg->regs->lsb_first.mask;
1010 else
1011 clrb |= spi->cfg->regs->lsb_first.mask;
1012
1013 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
1014 spi_dev->mode & SPI_CPOL,
1015 spi_dev->mode & SPI_CPHA,
1016 spi_dev->mode & SPI_LSB_FIRST,
1017 spi_dev->mode & SPI_CS_HIGH);
1018
1019 spin_lock_irqsave(&spi->lock, flags);
1020
1021 /* CPOL, CPHA and LSB FIRST bits have common register */
1022 if (clrb || setb)
1023 writel_relaxed(
1024 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) &
1025 ~clrb) | setb,
1026 spi->base + spi->cfg->regs->cpol.reg);
1027
1028 spin_unlock_irqrestore(&spi->lock, flags);
1029
1030 return 0;
1031 }
1032
1033 /**
1034 * stm32f4_spi_dma_tx_cb - dma callback
1035 * @data: pointer to the spi controller data structure
1036 *
1037 * DMA callback is called when the transfer is complete for DMA TX channel.
1038 */
1039 static void stm32f4_spi_dma_tx_cb(void *data)
1040 {
1041 struct stm32_spi *spi = data;
1042
1043 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1044 spi_finalize_current_transfer(spi->master);
1045 stm32f4_spi_disable(spi);
1046 }
1047 }
1048
1049 /**
1050 * stm32f4_spi_dma_rx_cb - dma callback
1051 * @data: pointer to the spi controller data structure
1052 *
1053 * DMA callback is called when the transfer is complete for DMA RX channel.
1054 */
1055 static void stm32f4_spi_dma_rx_cb(void *data)
1056 {
1057 struct stm32_spi *spi = data;
1058
1059 spi_finalize_current_transfer(spi->master);
1060 stm32f4_spi_disable(spi);
1061 }
1062
1063 /**
1064 * stm32h7_spi_dma_cb - dma callback
1065 * @data: pointer to the spi controller data structure
1066 *
1067 * DMA callback is called when the transfer is complete or when an error
1068 * occurs. If the transfer is complete, EOT flag is raised.
1069 */
1070 static void stm32h7_spi_dma_cb(void *data)
1071 {
1072 struct stm32_spi *spi = data;
1073 unsigned long flags;
1074 u32 sr;
1075
1076 spin_lock_irqsave(&spi->lock, flags);
1077
1078 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
1079
1080 spin_unlock_irqrestore(&spi->lock, flags);
1081
1082 if (!(sr & STM32H7_SPI_SR_EOT))
1083 dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr);
1084
1085 /* Now wait for EOT, or SUSP or OVR in case of error */
1086 }
1087
1088 /**
1089 * stm32_spi_dma_config - configure dma slave channel depending on current
1090 * transfer bits_per_word.
1091 * @spi: pointer to the spi controller data structure
1092 * @dma_conf: pointer to the dma_slave_config structure
1093 * @dir: direction of the dma transfer
1094 */
1095 static void stm32_spi_dma_config(struct stm32_spi *spi,
1096 struct dma_slave_config *dma_conf,
1097 enum dma_transfer_direction dir)
1098 {
1099 enum dma_slave_buswidth buswidth;
1100 u32 maxburst;
1101
1102 if (spi->cur_bpw <= 8)
1103 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1104 else if (spi->cur_bpw <= 16)
1105 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1106 else
1107 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1108
1109 if (spi->cfg->has_fifo) {
1110 /* Valid for DMA Half or Full Fifo threshold */
1111 if (spi->cur_fthlv == 2)
1112 maxburst = 1;
1113 else
1114 maxburst = spi->cur_fthlv;
1115 } else {
1116 maxburst = 1;
1117 }
1118
1119 memset(dma_conf, 0, sizeof(struct dma_slave_config));
1120 dma_conf->direction = dir;
1121 if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
1122 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg;
1123 dma_conf->src_addr_width = buswidth;
1124 dma_conf->src_maxburst = maxburst;
1125
1126 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
1127 buswidth, maxburst);
1128 } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
1129 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg;
1130 dma_conf->dst_addr_width = buswidth;
1131 dma_conf->dst_maxburst = maxburst;
1132
1133 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
1134 buswidth, maxburst);
1135 }
1136 }
1137
1138 /**
1139 * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using
1140 * interrupts
1141 * @spi: pointer to the spi controller data structure
1142 *
1143 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1144 * in progress.
1145 */
1146 static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi)
1147 {
1148 unsigned long flags;
1149 u32 cr2 = 0;
1150
1151 /* Enable the interrupts relative to the current communication mode */
1152 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1153 cr2 |= STM32F4_SPI_CR2_TXEIE;
1154 } else if (spi->cur_comm == SPI_FULL_DUPLEX) {
1155 /* In transmit-only mode, the OVR flag is set in the SR register
1156 * since the received data are never read. Therefore set OVR
1157 * interrupt only when rx buffer is available.
1158 */
1159 cr2 |= STM32F4_SPI_CR2_RXNEIE | STM32F4_SPI_CR2_ERRIE;
1160 } else {
1161 return -EINVAL;
1162 }
1163
1164 spin_lock_irqsave(&spi->lock, flags);
1165
1166 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2);
1167
1168 stm32_spi_enable(spi);
1169
1170 /* starting data transfer when buffer is loaded */
1171 if (spi->tx_buf)
1172 stm32f4_spi_write_tx(spi);
1173
1174 spin_unlock_irqrestore(&spi->lock, flags);
1175
1176 return 1;
1177 }
1178
1179 /**
1180 * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
1181 * interrupts
1182 * @spi: pointer to the spi controller data structure
1183 *
1184 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1185 * in progress.
1186 */
1187 static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
1188 {
1189 unsigned long flags;
1190 u32 ier = 0;
1191
1192 /* Enable the interrupts relative to the current communication mode */
1193 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
1194 ier |= STM32H7_SPI_IER_DXPIE;
1195 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */
1196 ier |= STM32H7_SPI_IER_TXPIE;
1197 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */
1198 ier |= STM32H7_SPI_IER_RXPIE;
1199
1200 /* Enable the interrupts relative to the end of transfer */
1201 ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
1202 STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
1203
1204 spin_lock_irqsave(&spi->lock, flags);
1205
1206 stm32_spi_enable(spi);
1207
1208 /* Be sure to have data in fifo before starting data transfer */
1209 if (spi->tx_buf)
1210 stm32h7_spi_write_txfifo(spi);
1211
1212 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1213
1214 writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
1215
1216 spin_unlock_irqrestore(&spi->lock, flags);
1217
1218 return 1;
1219 }
1220
1221 /**
1222 * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start
1223 * transfer using DMA
1224 * @spi: pointer to the spi controller data structure
1225 */
1226 static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi)
1227 {
1228 /* In DMA mode end of transfer is handled by DMA TX or RX callback. */
1229 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX ||
1230 spi->cur_comm == SPI_FULL_DUPLEX) {
1231 /*
1232 * In transmit-only mode, the OVR flag is set in the SR register
1233 * since the received data are never read. Therefore set OVR
1234 * interrupt only when rx buffer is available.
1235 */
1236 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE);
1237 }
1238
1239 stm32_spi_enable(spi);
1240 }
1241
1242 /**
1243 * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
1244 * transfer using DMA
1245 * @spi: pointer to the spi controller data structure
1246 */
1247 static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
1248 {
1249 /* Enable the interrupts relative to the end of transfer */
1250 stm32_spi_set_bits(spi, STM32H7_SPI_IER, STM32H7_SPI_IER_EOTIE |
1251 STM32H7_SPI_IER_TXTFIE |
1252 STM32H7_SPI_IER_OVRIE |
1253 STM32H7_SPI_IER_MODFIE);
1254
1255 stm32_spi_enable(spi);
1256
1257 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1258 }
1259
1260 /**
1261 * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
1262 * @spi: pointer to the spi controller data structure
1263 * @xfer: pointer to the spi_transfer structure
1264 *
1265 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1266 * in progress.
1267 */
1268 static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
1269 struct spi_transfer *xfer)
1270 {
1271 struct dma_slave_config tx_dma_conf, rx_dma_conf;
1272 struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
1273 unsigned long flags;
1274
1275 spin_lock_irqsave(&spi->lock, flags);
1276
1277 rx_dma_desc = NULL;
1278 if (spi->rx_buf && spi->dma_rx) {
1279 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
1280 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
1281
1282 /* Enable Rx DMA request */
1283 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1284 spi->cfg->regs->dma_rx_en.mask);
1285
1286 rx_dma_desc = dmaengine_prep_slave_sg(
1287 spi->dma_rx, xfer->rx_sg.sgl,
1288 xfer->rx_sg.nents,
1289 rx_dma_conf.direction,
1290 DMA_PREP_INTERRUPT);
1291 }
1292
1293 tx_dma_desc = NULL;
1294 if (spi->tx_buf && spi->dma_tx) {
1295 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
1296 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
1297
1298 tx_dma_desc = dmaengine_prep_slave_sg(
1299 spi->dma_tx, xfer->tx_sg.sgl,
1300 xfer->tx_sg.nents,
1301 tx_dma_conf.direction,
1302 DMA_PREP_INTERRUPT);
1303 }
1304
1305 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) ||
1306 (spi->rx_buf && spi->dma_rx && !rx_dma_desc))
1307 goto dma_desc_error;
1308
1309 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc))
1310 goto dma_desc_error;
1311
1312 if (rx_dma_desc) {
1313 rx_dma_desc->callback = spi->cfg->dma_rx_cb;
1314 rx_dma_desc->callback_param = spi;
1315
1316 if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
1317 dev_err(spi->dev, "Rx DMA submit failed\n");
1318 goto dma_desc_error;
1319 }
1320 /* Enable Rx DMA channel */
1321 dma_async_issue_pending(spi->dma_rx);
1322 }
1323
1324 if (tx_dma_desc) {
1325 if (spi->cur_comm == SPI_SIMPLEX_TX ||
1326 spi->cur_comm == SPI_3WIRE_TX) {
1327 tx_dma_desc->callback = spi->cfg->dma_tx_cb;
1328 tx_dma_desc->callback_param = spi;
1329 }
1330
1331 if (dma_submit_error(dmaengine_submit(tx_dma_desc))) {
1332 dev_err(spi->dev, "Tx DMA submit failed\n");
1333 goto dma_submit_error;
1334 }
1335 /* Enable Tx DMA channel */
1336 dma_async_issue_pending(spi->dma_tx);
1337
1338 /* Enable Tx DMA request */
1339 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg,
1340 spi->cfg->regs->dma_tx_en.mask);
1341 }
1342
1343 spi->cfg->transfer_one_dma_start(spi);
1344
1345 spin_unlock_irqrestore(&spi->lock, flags);
1346
1347 return 1;
1348
1349 dma_submit_error:
1350 if (spi->dma_rx)
1351 dmaengine_terminate_all(spi->dma_rx);
1352
1353 dma_desc_error:
1354 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1355 spi->cfg->regs->dma_rx_en.mask);
1356
1357 spin_unlock_irqrestore(&spi->lock, flags);
1358
1359 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
1360
1361 spi->cur_usedma = false;
1362 return spi->cfg->transfer_one_irq(spi);
1363 }
1364
1365 /**
1366 * stm32f4_spi_set_bpw - Configure bits per word
1367 * @spi: pointer to the spi controller data structure
1368 */
1369 static void stm32f4_spi_set_bpw(struct stm32_spi *spi)
1370 {
1371 if (spi->cur_bpw == 16)
1372 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1373 else
1374 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1375 }
1376
1377 /**
1378 * stm32h7_spi_set_bpw - configure bits per word
1379 * @spi: pointer to the spi controller data structure
1380 */
1381 static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
1382 {
1383 u32 bpw, fthlv;
1384 u32 cfg1_clrb = 0, cfg1_setb = 0;
1385
1386 bpw = spi->cur_bpw - 1;
1387
1388 cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
1389 cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
1390 STM32H7_SPI_CFG1_DSIZE;
1391
1392 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi);
1393 fthlv = spi->cur_fthlv - 1;
1394
1395 cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
1396 cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) &
1397 STM32H7_SPI_CFG1_FTHLV;
1398
1399 writel_relaxed(
1400 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
1401 ~cfg1_clrb) | cfg1_setb,
1402 spi->base + STM32H7_SPI_CFG1);
1403 }
1404
1405 /**
1406 * stm32_spi_set_mbr - Configure baud rate divisor in master mode
1407 * @spi: pointer to the spi controller data structure
1408 * @mbrdiv: baud rate divisor value
1409 */
1410 static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv)
1411 {
1412 u32 clrb = 0, setb = 0;
1413
1414 clrb |= spi->cfg->regs->br.mask;
1415 setb |= ((u32)mbrdiv << spi->cfg->regs->br.shift) &
1416 spi->cfg->regs->br.mask;
1417
1418 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
1419 ~clrb) | setb,
1420 spi->base + spi->cfg->regs->br.reg);
1421 }
1422
1423 /**
1424 * stm32_spi_communication_type - return transfer communication type
1425 * @spi_dev: pointer to the spi device
1426 * @transfer: pointer to spi transfer
1427 */
1428 static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev,
1429 struct spi_transfer *transfer)
1430 {
1431 unsigned int type = SPI_FULL_DUPLEX;
1432
1433 if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
1434 /*
1435 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
1436 * is forbidden and unvalidated by SPI subsystem so depending
1437 * on the valid buffer, we can determine the direction of the
1438 * transfer.
1439 */
1440 if (!transfer->tx_buf)
1441 type = SPI_3WIRE_RX;
1442 else
1443 type = SPI_3WIRE_TX;
1444 } else {
1445 if (!transfer->tx_buf)
1446 type = SPI_SIMPLEX_RX;
1447 else if (!transfer->rx_buf)
1448 type = SPI_SIMPLEX_TX;
1449 }
1450
1451 return type;
1452 }
1453
1454 /**
1455 * stm32f4_spi_set_mode - configure communication mode
1456 * @spi: pointer to the spi controller data structure
1457 * @comm_type: type of communication to configure
1458 */
1459 static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1460 {
1461 if (comm_type == SPI_3WIRE_TX || comm_type == SPI_SIMPLEX_TX) {
1462 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1463 STM32F4_SPI_CR1_BIDIMODE |
1464 STM32F4_SPI_CR1_BIDIOE);
1465 } else if (comm_type == SPI_FULL_DUPLEX) {
1466 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1467 STM32F4_SPI_CR1_BIDIMODE |
1468 STM32F4_SPI_CR1_BIDIOE);
1469 } else {
1470 return -EINVAL;
1471 }
1472
1473 return 0;
1474 }
1475
1476 /**
1477 * stm32h7_spi_set_mode - configure communication mode
1478 * @spi: pointer to the spi controller data structure
1479 * @comm_type: type of communication to configure
1480 */
1481 static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1482 {
1483 u32 mode;
1484 u32 cfg2_clrb = 0, cfg2_setb = 0;
1485
1486 if (comm_type == SPI_3WIRE_RX) {
1487 mode = STM32H7_SPI_HALF_DUPLEX;
1488 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1489 } else if (comm_type == SPI_3WIRE_TX) {
1490 mode = STM32H7_SPI_HALF_DUPLEX;
1491 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1492 } else if (comm_type == SPI_SIMPLEX_RX) {
1493 mode = STM32H7_SPI_SIMPLEX_RX;
1494 } else if (comm_type == SPI_SIMPLEX_TX) {
1495 mode = STM32H7_SPI_SIMPLEX_TX;
1496 } else {
1497 mode = STM32H7_SPI_FULL_DUPLEX;
1498 }
1499
1500 cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
1501 cfg2_setb |= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) &
1502 STM32H7_SPI_CFG2_COMM;
1503
1504 writel_relaxed(
1505 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1506 ~cfg2_clrb) | cfg2_setb,
1507 spi->base + STM32H7_SPI_CFG2);
1508
1509 return 0;
1510 }
1511
1512 /**
1513 * stm32h7_spi_data_idleness - configure minimum time delay inserted between two
1514 * consecutive data frames in master mode
1515 * @spi: pointer to the spi controller data structure
1516 * @len: transfer len
1517 */
1518 static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
1519 {
1520 u32 cfg2_clrb = 0, cfg2_setb = 0;
1521
1522 cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
1523 if ((len > 1) && (spi->cur_midi > 0)) {
1524 u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
1525 u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
1526 (u32)STM32H7_SPI_CFG2_MIDI >>
1527 STM32H7_SPI_CFG2_MIDI_SHIFT);
1528
1529 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
1530 sck_period_ns, midi, midi * sck_period_ns);
1531 cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) &
1532 STM32H7_SPI_CFG2_MIDI;
1533 }
1534
1535 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1536 ~cfg2_clrb) | cfg2_setb,
1537 spi->base + STM32H7_SPI_CFG2);
1538 }
1539
1540 /**
1541 * stm32h7_spi_number_of_data - configure number of data at current transfer
1542 * @spi: pointer to the spi controller data structure
1543 * @nb_words: transfer length (in words)
1544 */
1545 static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
1546 {
1547 u32 cr2_clrb = 0, cr2_setb = 0;
1548
1549 if (nb_words <= (STM32H7_SPI_CR2_TSIZE >>
1550 STM32H7_SPI_CR2_TSIZE_SHIFT)) {
1551 cr2_clrb |= STM32H7_SPI_CR2_TSIZE;
1552 cr2_setb = nb_words << STM32H7_SPI_CR2_TSIZE_SHIFT;
1553 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CR2) &
1554 ~cr2_clrb) | cr2_setb,
1555 spi->base + STM32H7_SPI_CR2);
1556 } else {
1557 return -EMSGSIZE;
1558 }
1559
1560 return 0;
1561 }
1562
1563 /**
1564 * stm32_spi_transfer_one_setup - common setup to transfer a single
1565 * spi_transfer either using DMA or
1566 * interrupts.
1567 * @spi: pointer to the spi controller data structure
1568 * @spi_dev: pointer to the spi device
1569 * @transfer: pointer to spi transfer
1570 */
1571 static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
1572 struct spi_device *spi_dev,
1573 struct spi_transfer *transfer)
1574 {
1575 unsigned long flags;
1576 unsigned int comm_type;
1577 int nb_words, ret = 0;
1578
1579 spin_lock_irqsave(&spi->lock, flags);
1580
1581 if (spi->cur_bpw != transfer->bits_per_word) {
1582 spi->cur_bpw = transfer->bits_per_word;
1583 spi->cfg->set_bpw(spi);
1584 }
1585
1586 if (spi->cur_speed != transfer->speed_hz) {
1587 int mbr;
1588
1589 /* Update spi->cur_speed with real clock speed */
1590 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
1591 spi->cfg->baud_rate_div_min,
1592 spi->cfg->baud_rate_div_max);
1593 if (mbr < 0) {
1594 ret = mbr;
1595 goto out;
1596 }
1597
1598 transfer->speed_hz = spi->cur_speed;
1599 stm32_spi_set_mbr(spi, mbr);
1600 }
1601
1602 comm_type = stm32_spi_communication_type(spi_dev, transfer);
1603 if (spi->cur_comm != comm_type) {
1604 ret = spi->cfg->set_mode(spi, comm_type);
1605
1606 if (ret < 0)
1607 goto out;
1608
1609 spi->cur_comm = comm_type;
1610 }
1611
1612 if (spi->cfg->set_data_idleness)
1613 spi->cfg->set_data_idleness(spi, transfer->len);
1614
1615 if (spi->cur_bpw <= 8)
1616 nb_words = transfer->len;
1617 else if (spi->cur_bpw <= 16)
1618 nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
1619 else
1620 nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
1621
1622 if (spi->cfg->set_number_of_data) {
1623 ret = spi->cfg->set_number_of_data(spi, nb_words);
1624 if (ret < 0)
1625 goto out;
1626 }
1627
1628 spi->cur_xferlen = transfer->len;
1629
1630 dev_dbg(spi->dev, "transfer communication mode set to %d\n",
1631 spi->cur_comm);
1632 dev_dbg(spi->dev,
1633 "data frame of %d-bit, data packet of %d data frames\n",
1634 spi->cur_bpw, spi->cur_fthlv);
1635 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
1636 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
1637 spi->cur_xferlen, nb_words);
1638 dev_dbg(spi->dev, "dma %s\n",
1639 (spi->cur_usedma) ? "enabled" : "disabled");
1640
1641 out:
1642 spin_unlock_irqrestore(&spi->lock, flags);
1643
1644 return ret;
1645 }
1646
1647 /**
1648 * stm32_spi_transfer_one - transfer a single spi_transfer
1649 * @master: controller master interface
1650 * @spi_dev: pointer to the spi device
1651 * @transfer: pointer to spi transfer
1652 *
1653 * It must return 0 if the transfer is finished or 1 if the transfer is still
1654 * in progress.
1655 */
1656 static int stm32_spi_transfer_one(struct spi_master *master,
1657 struct spi_device *spi_dev,
1658 struct spi_transfer *transfer)
1659 {
1660 struct stm32_spi *spi = spi_master_get_devdata(master);
1661 int ret;
1662
1663 spi->tx_buf = transfer->tx_buf;
1664 spi->rx_buf = transfer->rx_buf;
1665 spi->tx_len = spi->tx_buf ? transfer->len : 0;
1666 spi->rx_len = spi->rx_buf ? transfer->len : 0;
1667
1668 spi->cur_usedma = (master->can_dma &&
1669 master->can_dma(master, spi_dev, transfer));
1670
1671 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
1672 if (ret) {
1673 dev_err(spi->dev, "SPI transfer setup failed\n");
1674 return ret;
1675 }
1676
1677 if (spi->cur_usedma)
1678 return stm32_spi_transfer_one_dma(spi, transfer);
1679 else
1680 return spi->cfg->transfer_one_irq(spi);
1681 }
1682
1683 /**
1684 * stm32_spi_unprepare_msg - relax the hardware
1685 * @master: controller master interface
1686 * @msg: pointer to the spi message
1687 */
1688 static int stm32_spi_unprepare_msg(struct spi_master *master,
1689 struct spi_message *msg)
1690 {
1691 struct stm32_spi *spi = spi_master_get_devdata(master);
1692
1693 spi->cfg->disable(spi);
1694
1695 return 0;
1696 }
1697
1698 /**
1699 * stm32f4_spi_config - Configure SPI controller as SPI master
1700 * @spi: pointer to the spi controller data structure
1701 */
1702 static int stm32f4_spi_config(struct stm32_spi *spi)
1703 {
1704 unsigned long flags;
1705
1706 spin_lock_irqsave(&spi->lock, flags);
1707
1708 /* Ensure I2SMOD bit is kept cleared */
1709 stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR,
1710 STM32F4_SPI_I2SCFGR_I2SMOD);
1711
1712 /*
1713 * - SS input value high
1714 * - transmitter half duplex direction
1715 * - Set the master mode (default Motorola mode)
1716 * - Consider 1 master/n slaves configuration and
1717 * SS input value is determined by the SSI bit
1718 */
1719 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI |
1720 STM32F4_SPI_CR1_BIDIOE |
1721 STM32F4_SPI_CR1_MSTR |
1722 STM32F4_SPI_CR1_SSM);
1723
1724 spin_unlock_irqrestore(&spi->lock, flags);
1725
1726 return 0;
1727 }
1728
1729 /**
1730 * stm32h7_spi_config - Configure SPI controller as SPI master
1731 * @spi: pointer to the spi controller data structure
1732 */
1733 static int stm32h7_spi_config(struct stm32_spi *spi)
1734 {
1735 unsigned long flags;
1736
1737 spin_lock_irqsave(&spi->lock, flags);
1738
1739 /* Ensure I2SMOD bit is kept cleared */
1740 stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
1741 STM32H7_SPI_I2SCFGR_I2SMOD);
1742
1743 /*
1744 * - SS input value high
1745 * - transmitter half duplex direction
1746 * - automatic communication suspend when RX-Fifo is full
1747 */
1748 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI |
1749 STM32H7_SPI_CR1_HDDIR |
1750 STM32H7_SPI_CR1_MASRX);
1751
1752 /*
1753 * - Set the master mode (default Motorola mode)
1754 * - Consider 1 master/n slaves configuration and
1755 * SS input value is determined by the SSI bit
1756 * - keep control of all associated GPIOs
1757 */
1758 stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER |
1759 STM32H7_SPI_CFG2_SSM |
1760 STM32H7_SPI_CFG2_AFCNTR);
1761
1762 spin_unlock_irqrestore(&spi->lock, flags);
1763
1764 return 0;
1765 }
1766
1767 static const struct stm32_spi_cfg stm32f4_spi_cfg = {
1768 .regs = &stm32f4_spi_regspec,
1769 .get_bpw_mask = stm32f4_spi_get_bpw_mask,
1770 .disable = stm32f4_spi_disable,
1771 .config = stm32f4_spi_config,
1772 .set_bpw = stm32f4_spi_set_bpw,
1773 .set_mode = stm32f4_spi_set_mode,
1774 .transfer_one_dma_start = stm32f4_spi_transfer_one_dma_start,
1775 .dma_tx_cb = stm32f4_spi_dma_tx_cb,
1776 .dma_rx_cb = stm32f4_spi_dma_rx_cb,
1777 .transfer_one_irq = stm32f4_spi_transfer_one_irq,
1778 .irq_handler_event = stm32f4_spi_irq_event,
1779 .irq_handler_thread = stm32f4_spi_irq_thread,
1780 .baud_rate_div_min = STM32F4_SPI_BR_DIV_MIN,
1781 .baud_rate_div_max = STM32F4_SPI_BR_DIV_MAX,
1782 .has_fifo = false,
1783 };
1784
1785 static const struct stm32_spi_cfg stm32h7_spi_cfg = {
1786 .regs = &stm32h7_spi_regspec,
1787 .get_fifo_size = stm32h7_spi_get_fifo_size,
1788 .get_bpw_mask = stm32h7_spi_get_bpw_mask,
1789 .disable = stm32h7_spi_disable,
1790 .config = stm32h7_spi_config,
1791 .set_bpw = stm32h7_spi_set_bpw,
1792 .set_mode = stm32h7_spi_set_mode,
1793 .set_data_idleness = stm32h7_spi_data_idleness,
1794 .set_number_of_data = stm32h7_spi_number_of_data,
1795 .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start,
1796 .dma_rx_cb = stm32h7_spi_dma_cb,
1797 .dma_tx_cb = stm32h7_spi_dma_cb,
1798 .transfer_one_irq = stm32h7_spi_transfer_one_irq,
1799 .irq_handler_thread = stm32h7_spi_irq_thread,
1800 .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN,
1801 .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX,
1802 .has_fifo = true,
1803 };
1804
1805 static const struct of_device_id stm32_spi_of_match[] = {
1806 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
1807 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
1808 {},
1809 };
1810 MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
1811
1812 static int stm32_spi_probe(struct platform_device *pdev)
1813 {
1814 struct spi_master *master;
1815 struct stm32_spi *spi;
1816 struct resource *res;
1817 int ret;
1818
1819 master = spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
1820 if (!master) {
1821 dev_err(&pdev->dev, "spi master allocation failed\n");
1822 return -ENOMEM;
1823 }
1824 platform_set_drvdata(pdev, master);
1825
1826 spi = spi_master_get_devdata(master);
1827 spi->dev = &pdev->dev;
1828 spi->master = master;
1829 spin_lock_init(&spi->lock);
1830
1831 spi->cfg = (const struct stm32_spi_cfg *)
1832 of_match_device(pdev->dev.driver->of_match_table,
1833 &pdev->dev)->data;
1834
1835 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1836 spi->base = devm_ioremap_resource(&pdev->dev, res);
1837 if (IS_ERR(spi->base)) {
1838 ret = PTR_ERR(spi->base);
1839 goto err_master_put;
1840 }
1841
1842 spi->phys_addr = (dma_addr_t)res->start;
1843
1844 spi->irq = platform_get_irq(pdev, 0);
1845 if (spi->irq <= 0) {
1846 ret = spi->irq;
1847 if (ret != -EPROBE_DEFER)
1848 dev_err(&pdev->dev, "failed to get irq: %d\n", ret);
1849 goto err_master_put;
1850 }
1851 ret = devm_request_threaded_irq(&pdev->dev, spi->irq,
1852 spi->cfg->irq_handler_event,
1853 spi->cfg->irq_handler_thread,
1854 IRQF_ONESHOT, pdev->name, master);
1855 if (ret) {
1856 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
1857 ret);
1858 goto err_master_put;
1859 }
1860
1861 spi->clk = devm_clk_get(&pdev->dev, NULL);
1862 if (IS_ERR(spi->clk)) {
1863 ret = PTR_ERR(spi->clk);
1864 dev_err(&pdev->dev, "clk get failed: %d\n", ret);
1865 goto err_master_put;
1866 }
1867
1868 ret = clk_prepare_enable(spi->clk);
1869 if (ret) {
1870 dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
1871 goto err_master_put;
1872 }
1873 spi->clk_rate = clk_get_rate(spi->clk);
1874 if (!spi->clk_rate) {
1875 dev_err(&pdev->dev, "clk rate = 0\n");
1876 ret = -EINVAL;
1877 goto err_clk_disable;
1878 }
1879
1880 spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1881 if (!IS_ERR(spi->rst)) {
1882 reset_control_assert(spi->rst);
1883 udelay(2);
1884 reset_control_deassert(spi->rst);
1885 }
1886
1887 if (spi->cfg->has_fifo)
1888 spi->fifo_size = spi->cfg->get_fifo_size(spi);
1889
1890 ret = spi->cfg->config(spi);
1891 if (ret) {
1892 dev_err(&pdev->dev, "controller configuration failed: %d\n",
1893 ret);
1894 goto err_clk_disable;
1895 }
1896
1897 master->dev.of_node = pdev->dev.of_node;
1898 master->auto_runtime_pm = true;
1899 master->bus_num = pdev->id;
1900 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
1901 SPI_3WIRE;
1902 master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi);
1903 master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min;
1904 master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max;
1905 master->use_gpio_descriptors = true;
1906 master->prepare_message = stm32_spi_prepare_msg;
1907 master->transfer_one = stm32_spi_transfer_one;
1908 master->unprepare_message = stm32_spi_unprepare_msg;
1909
1910 spi->dma_tx = dma_request_chan(spi->dev, "tx");
1911 if (IS_ERR(spi->dma_tx)) {
1912 ret = PTR_ERR(spi->dma_tx);
1913 spi->dma_tx = NULL;
1914 if (ret == -EPROBE_DEFER)
1915 goto err_clk_disable;
1916
1917 dev_warn(&pdev->dev, "failed to request tx dma channel\n");
1918 } else {
1919 master->dma_tx = spi->dma_tx;
1920 }
1921
1922 spi->dma_rx = dma_request_chan(spi->dev, "rx");
1923 if (IS_ERR(spi->dma_rx)) {
1924 ret = PTR_ERR(spi->dma_rx);
1925 spi->dma_rx = NULL;
1926 if (ret == -EPROBE_DEFER)
1927 goto err_dma_release;
1928
1929 dev_warn(&pdev->dev, "failed to request rx dma channel\n");
1930 } else {
1931 master->dma_rx = spi->dma_rx;
1932 }
1933
1934 if (spi->dma_tx || spi->dma_rx)
1935 master->can_dma = stm32_spi_can_dma;
1936
1937 pm_runtime_set_active(&pdev->dev);
1938 pm_runtime_enable(&pdev->dev);
1939
1940 ret = devm_spi_register_master(&pdev->dev, master);
1941 if (ret) {
1942 dev_err(&pdev->dev, "spi master registration failed: %d\n",
1943 ret);
1944 goto err_pm_disable;
1945 }
1946
1947 if (!master->cs_gpiods) {
1948 dev_err(&pdev->dev, "no CS gpios available\n");
1949 ret = -EINVAL;
1950 goto err_pm_disable;
1951 }
1952
1953 dev_info(&pdev->dev, "driver initialized\n");
1954
1955 return 0;
1956
1957 err_pm_disable:
1958 pm_runtime_disable(&pdev->dev);
1959 err_dma_release:
1960 if (spi->dma_tx)
1961 dma_release_channel(spi->dma_tx);
1962 if (spi->dma_rx)
1963 dma_release_channel(spi->dma_rx);
1964 err_clk_disable:
1965 clk_disable_unprepare(spi->clk);
1966 err_master_put:
1967 spi_master_put(master);
1968
1969 return ret;
1970 }
1971
1972 static int stm32_spi_remove(struct platform_device *pdev)
1973 {
1974 struct spi_master *master = platform_get_drvdata(pdev);
1975 struct stm32_spi *spi = spi_master_get_devdata(master);
1976
1977 spi->cfg->disable(spi);
1978
1979 if (master->dma_tx)
1980 dma_release_channel(master->dma_tx);
1981 if (master->dma_rx)
1982 dma_release_channel(master->dma_rx);
1983
1984 clk_disable_unprepare(spi->clk);
1985
1986 pm_runtime_disable(&pdev->dev);
1987
1988 return 0;
1989 }
1990
1991 #ifdef CONFIG_PM
1992 static int stm32_spi_runtime_suspend(struct device *dev)
1993 {
1994 struct spi_master *master = dev_get_drvdata(dev);
1995 struct stm32_spi *spi = spi_master_get_devdata(master);
1996
1997 clk_disable_unprepare(spi->clk);
1998
1999 return 0;
2000 }
2001
2002 static int stm32_spi_runtime_resume(struct device *dev)
2003 {
2004 struct spi_master *master = dev_get_drvdata(dev);
2005 struct stm32_spi *spi = spi_master_get_devdata(master);
2006
2007 return clk_prepare_enable(spi->clk);
2008 }
2009 #endif
2010
2011 #ifdef CONFIG_PM_SLEEP
2012 static int stm32_spi_suspend(struct device *dev)
2013 {
2014 struct spi_master *master = dev_get_drvdata(dev);
2015 int ret;
2016
2017 ret = spi_master_suspend(master);
2018 if (ret)
2019 return ret;
2020
2021 return pm_runtime_force_suspend(dev);
2022 }
2023
2024 static int stm32_spi_resume(struct device *dev)
2025 {
2026 struct spi_master *master = dev_get_drvdata(dev);
2027 struct stm32_spi *spi = spi_master_get_devdata(master);
2028 int ret;
2029
2030 ret = pm_runtime_force_resume(dev);
2031 if (ret)
2032 return ret;
2033
2034 ret = spi_master_resume(master);
2035 if (ret)
2036 clk_disable_unprepare(spi->clk);
2037
2038 return ret;
2039 }
2040 #endif
2041
2042 static const struct dev_pm_ops stm32_spi_pm_ops = {
2043 SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume)
2044 SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend,
2045 stm32_spi_runtime_resume, NULL)
2046 };
2047
2048 static struct platform_driver stm32_spi_driver = {
2049 .probe = stm32_spi_probe,
2050 .remove = stm32_spi_remove,
2051 .driver = {
2052 .name = DRIVER_NAME,
2053 .pm = &stm32_spi_pm_ops,
2054 .of_match_table = stm32_spi_of_match,
2055 },
2056 };
2057
2058 module_platform_driver(stm32_spi_driver);
2059
2060 MODULE_ALIAS("platform:" DRIVER_NAME);
2061 MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");
2062 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
2063 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support