| blob | b4cdc0b7fee7664204703cf2643ade33c18ae011 |
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
4 * All rights reserved.
5 *
6 * File: baseband.c
7 *
8 * Purpose: Implement functions to access baseband
9 *
10 * Author: Kyle Hsu
11 *
12 * Date: Aug.22, 2002
13 *
14 * Functions:
15 * BBuGetFrameTime - Calculate data frame transmitting time
16 * BBvCalculateParameter - Calculate PhyLength, PhyService and Phy Signal
17 * parameter for baseband Tx
18 * BBbReadEmbedded - Embedded read baseband register via MAC
19 * BBbWriteEmbedded - Embedded write baseband register via MAC
20 * BBbVT3253Init - VIA VT3253 baseband chip init code
21 *
22 * Revision History:
23 * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
24 * 08-07-2003 Bryan YC Fan: Add MAXIM2827/2825 and RFMD2959 support.
25 * 08-26-2003 Kyle Hsu : Modify BBuGetFrameTime() and
26 * BBvCalculateParameter().
27 * cancel the setting of MAC_REG_SOFTPWRCTL on
28 * BBbVT3253Init().
29 * Add the comments.
30 * 09-01-2003 Bryan YC Fan: RF & BB tables updated.
31 * Modified BBvLoopbackOn & BBvLoopbackOff().
32 *
33 *
34 */
42 /*--------------------- Static Classes ----------------------------*/
44 /*--------------------- Static Variables --------------------------*/
46 /*--------------------- Static Functions --------------------------*/
48 /*--------------------- Export Variables --------------------------*/
50 /*--------------------- Static Definitions -------------------------*/
52 /*--------------------- Static Classes ----------------------------*/
54 /*--------------------- Static Variables --------------------------*/
56 #define CB_VT3253_INIT_FOR_RFMD 446
504 };
506 #define CB_VT3253B0_INIT_FOR_RFMD 256
764 };
766 #define CB_VT3253B0_AGC_FOR_RFMD2959 195
767 /* For RFMD2959 */
768 static
965 };
967 #define CB_VT3253B0_INIT_FOR_AIROHA2230 256
968 /* For AIROHA */
969 static
1227 };
1229 #define CB_VT3253B0_INIT_FOR_UW2451 256
1230 /* For UW2451 */
1488 };
1490 #define CB_VT3253B0_AGC 193
1491 /* For AIROHA */
1686 };
1690 };
1692 /*--------------------- Export Variables --------------------------*/
1693 /*
1694 * Description: Calculate data frame transmitting time
1695 *
1696 * Parameters:
1697 * In:
1698 * byPreambleType - Preamble Type
1699 * byPktType - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA
1700 * cbFrameLength - Baseband Type
1701 * wRate - Tx Rate
1702 * Out:
1703 *
1704 * Return Value: FrameTime
1705 *
1706 */
1710 {
1725 else
1731 uFrameTime++;
1734 }
1738 uFrameTime++;
1745 }
1747 /*
1748 * Description: Calculate Length, Service, and Signal fields of Phy for Tx
1749 *
1750 * Parameters:
1751 * In:
1752 * priv - Device Structure
1753 * frame_length - Tx Frame Length
1754 * tx_rate - Tx Rate
1755 * Out:
1756 * struct vnt_phy_field *phy
1757 * - pointer to Phy Length field
1758 * - pointer to Phy Service field
1759 * - pointer to Phy Signal field
1760 *
1761 * Return Value: none
1762 *
1763 */
1766 {
1767 u32 bit_count;
1769 u32 tmp;
1788 else
1797 count++;
1801 else
1810 count++;
1814 }
1818 else
1825 else
1832 else
1839 else
1846 else
1853 else
1860 else
1867 else
1874 else
1880 else
1883 }
1893 }
1894 }
1896 /*
1897 * Description: Read a byte from BASEBAND, by embedded programming
1898 *
1899 * Parameters:
1900 * In:
1901 * iobase - I/O base address
1902 * byBBAddr - address of register in Baseband
1903 * Out:
1904 * pbyData - data read
1905 *
1906 * Return Value: true if succeeded; false if failed.
1907 *
1908 */
1911 {
1916 /* BB reg offset */
1919 /* turn on REGR */
1921 /* W_MAX_TIMEOUT is the timeout period */
1926 }
1928 /* get BB data */
1934 }
1936 }
1938 /*
1939 * Description: Write a Byte to BASEBAND, by embedded programming
1940 *
1941 * Parameters:
1942 * In:
1943 * iobase - I/O base address
1944 * byBBAddr - address of register in Baseband
1945 * byData - data to write
1946 * Out:
1947 * none
1948 *
1949 * Return Value: true if succeeded; false if failed.
1950 *
1951 */
1954 {
1959 /* BB reg offset */
1961 /* set BB data */
1964 /* turn on BBREGCTL_REGW */
1966 /* W_MAX_TIMEOUT is the timeout period */
1971 }
1976 }
1978 }
1980 /*
1981 * Description: VIA VT3253 Baseband chip init function
1982 *
1983 * Parameters:
1984 * In:
1985 * iobase - I/O base address
1986 * byRevId - Revision ID
1987 * byRFType - RF type
1988 * Out:
1989 * none
1990 *
1991 * Return Value: true if succeeded; false if failed.
1992 *
1993 */
1996 {
2023 }
2078 /* Init ANT B select,
2079 * TX Config CR09 = 0x61->0x45,
2080 * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2081 */
2083 /*bResult &= BBbWriteEmbedded(iobase,0x09,0x41);*/
2085 /* Init ANT B select,
2086 * RX Config CR10 = 0x28->0x2A,
2087 * 0x2A->0x28(VC1/VC2 define,
2088 * make the ANT_A, ANT_B inverted)
2089 */
2091 /*bResult &= BBbWriteEmbedded(iobase,0x0a,0x28);*/
2092 /* Select VC1/VC2, CR215 = 0x02->0x06 */
2095 /* {{RobertYu:20050125, request by Jack */
2098 /* }} */
2100 /* {{RobertYu:20050221, request by Jack */
2103 /* }} */
2118 /* }} RobertYu */
2138 /* Fix VT3226 DFC system timing issue */
2140 /* {{ RobertYu: 20050104 */
2147 /* {{ RobertYu:20050223, request by JerryChung */
2148 /* Init ANT B select,TX Config CR09 = 0x61->0x45,
2149 * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2150 */
2151 /*bResult &= BBbWriteEmbedded(iobase,0x09,0x41);*/
2152 /* Init ANT B select,RX Config CR10 = 0x28->0x2A,
2153 * 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2154 */
2155 /*bResult &= BBbWriteEmbedded(iobase,0x0a,0x28);*/
2156 /* Select VC1/VC2, CR215 = 0x02->0x06 */
2158 /* }} */
2172 /* }} RobertYu */
2174 /* No VGA Table now */
2177 }
2182 }
2185 }
2187 /*
2188 * Description: Set ShortSlotTime mode
2189 *
2190 * Parameters:
2191 * In:
2192 * priv - Device Structure
2193 * Out:
2194 * none
2195 *
2196 * Return Value: none
2197 *
2198 */
2199 void
2201 {
2209 else
2212 /* patch for 3253B0 Baseband with Cardbus module */
2218 }
2221 {
2227 /* patch for 3253B0 Baseband with Cardbus module */
2232 else
2236 }
2238 /*
2239 * Description: Baseband SoftwareReset
2240 *
2241 * Parameters:
2242 * In:
2243 * iobase - I/O base address
2244 * Out:
2245 * none
2246 *
2247 * Return Value: none
2248 *
2249 */
2250 void
2252 {
2257 }
2259 /*
2260 * Description: Baseband Power Save Mode ON
2261 *
2262 * Parameters:
2263 * In:
2264 * iobase - I/O base address
2265 * Out:
2266 * none
2267 *
2268 * Return Value: none
2269 *
2270 */
2271 void
2273 {
2279 }
2281 /*
2282 * Description: Baseband Power Save Mode OFF
2283 *
2284 * Parameters:
2285 * In:
2286 * iobase - I/O base address
2287 * Out:
2288 * none
2289 *
2290 * Return Value: none
2291 *
2292 */
2293 void
2295 {
2301 }
2303 /*
2304 * Description: Set Tx Antenna mode
2305 *
2306 * Parameters:
2307 * In:
2308 * priv - Device Structure
2309 * byAntennaMode - Antenna Mode
2310 * Out:
2311 * none
2312 *
2313 * Return Value: none
2314 *
2315 */
2317 void
2319 {
2324 /* bit 1 is diversity */
2327 /* bit 2 is ANTSEL */
2332 }
2334 }
2336 /*
2337 * Description: Set Rx Antenna mode
2338 *
2339 * Parameters:
2340 * In:
2341 * priv - Device Structure
2342 * byAntennaMode - Antenna Mode
2343 * Out:
2344 * none
2345 *
2346 * Return Value: none
2347 *
2348 */
2350 void
2352 {
2364 }
2366 }
2368 /*
2369 * Description: BBvSetDeepSleep
2370 *
2371 * Parameters:
2372 * In:
2373 * priv - Device Structure
2374 * Out:
2375 * none
2376 *
2377 * Return Value: none
2378 *
2379 */
2380 void
2382 {
2385 }
2387 void
2389 {
2392 }