drivers/staging/vt6655/mac.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
   4  * All rights reserved.
   5  *
   6  * File: mac.c
   7  *
   8  * Purpose:  MAC routines
   9  *
  10  * Author: Tevin Chen
  11  *
  12  * Date: May 21, 1996
  13  *
  14  * Functions:
  15  *      MACbIsRegBitsOff - Test if All test Bits Off
  16  *      MACbIsIntDisable - Test if MAC interrupt disable
  17  *      MACvSetShortRetryLimit - Set 802.11 Short Retry limit
  18  *      MACvSetLongRetryLimit - Set 802.11 Long Retry limit
  19  *      MACvSetLoopbackMode - Set MAC Loopback Mode
  20  *      MACvSaveContext - Save Context of MAC Registers
  21  *      MACvRestoreContext - Restore Context of MAC Registers
  22  *      MACbSoftwareReset - Software Reset MAC
  23  *      MACbSafeRxOff - Turn Off MAC Rx
  24  *      MACbSafeTxOff - Turn Off MAC Tx
  25  *      MACbSafeStop - Stop MAC function
  26  *      MACbShutdown - Shut down MAC
  27  *      MACvInitialize - Initialize MAC
  28  *      MACvSetCurrRxDescAddr - Set Rx Descriptors Address
  29  *      MACvSetCurrTx0DescAddr - Set Tx0 Descriptors Address
  30  *      MACvSetCurrTx1DescAddr - Set Tx1 Descriptors Address
  31  *      MACvTimer0MicroSDelay - Micro Second Delay Loop by MAC
  32  *
  33  * Revision History:
  34  *      08-22-2003 Kyle Hsu     :  Porting MAC functions from sim53
  35  *      09-03-2003 Bryan YC Fan :  Add MACvClearBusSusInd()&
  36  *                                 MACvEnableBusSusEn()
  37  *      09-18-2003 Jerry Chen   :  Add MACvSetKeyEntry & MACvDisableKeyEntry
  38  *
  39  */
  40
  41 #include "tmacro.h"
  42 #include "mac.h"
  43
  44 /*
  45  * Description:
  46  *      Test if all test bits off
  47  *
  48  * Parameters:
  49  *  In:
  50  *      io_base    - Base Address for MAC
  51  *      byRegOfs    - Offset of MAC Register
  52  *      byTestBits  - Test bits
  53  *  Out:
  54  *      none
  55  *
  56  * Return Value: true if all test bits Off; otherwise false
  57  *
  58  */
  59 bool MACbIsRegBitsOff(struct vnt_private *priv, unsigned char byRegOfs,
  60                       unsigned char byTestBits)
  61 {
  62         void __iomem *io_base = priv->PortOffset;
  63
  64         return !(ioread8(io_base + byRegOfs) & byTestBits);
  65 }
  66
  67 /*
  68  * Description:
  69  *      Test if MAC interrupt disable
  70  *
  71  * Parameters:
  72  *  In:
  73  *      io_base    - Base Address for MAC
  74  *  Out:
  75  *      none
  76  *
  77  * Return Value: true if interrupt is disable; otherwise false
  78  *
  79  */
  80 bool MACbIsIntDisable(struct vnt_private *priv)
  81 {
  82         void __iomem *io_base = priv->PortOffset;
  83
  84         if (ioread32(io_base + MAC_REG_IMR))
  85                 return false;
  86
  87         return true;
  88 }
  89
  90 /*
  91  * Description:
  92  *      Set 802.11 Short Retry Limit
  93  *
  94  * Parameters:
  95  *  In:
  96  *      io_base    - Base Address for MAC
  97  *      byRetryLimit- Retry Limit
  98  *  Out:
  99  *      none
 100  *
 101  * Return Value: none
 102  *
 103  */
 104 void MACvSetShortRetryLimit(struct vnt_private *priv,
 105                             unsigned char byRetryLimit)
 106 {
 107         void __iomem *io_base = priv->PortOffset;
 108         /* set SRT */
 109         iowrite8(byRetryLimit, io_base + MAC_REG_SRT);
 110 }
 111
 112 /*
 113  * Description:
 114  *      Set 802.11 Long Retry Limit
 115  *
 116  * Parameters:
 117  *  In:
 118  *      io_base    - Base Address for MAC
 119  *      byRetryLimit- Retry Limit
 120  *  Out:
 121  *      none
 122  *
 123  * Return Value: none
 124  *
 125  */
 126 void MACvSetLongRetryLimit(struct vnt_private *priv,
 127                            unsigned char byRetryLimit)
 128 {
 129         void __iomem *io_base = priv->PortOffset;
 130         /* set LRT */
 131         iowrite8(byRetryLimit, io_base + MAC_REG_LRT);
 132 }
 133
 134 /*
 135  * Description:
 136  *      Set MAC Loopback mode
 137  *
 138  * Parameters:
 139  *  In:
 140  *      io_base        - Base Address for MAC
 141  *      byLoopbackMode  - Loopback Mode
 142  *  Out:
 143  *      none
 144  *
 145  * Return Value: none
 146  *
 147  */
 148 void MACvSetLoopbackMode(struct vnt_private *priv, unsigned char byLoopbackMode)
 149 {
 150         void __iomem *io_base = priv->PortOffset;
 151
 152         byLoopbackMode <<= 6;
 153         /* set TCR */
 154         iowrite8((ioread8(io_base + MAC_REG_TEST) & 0x3f) | byLoopbackMode,
 155                  io_base + MAC_REG_TEST);
 156 }
 157
 158 /*
 159  * Description:
 160  *      Save MAC registers to context buffer
 161  *
 162  * Parameters:
 163  *  In:
 164  *      io_base    - Base Address for MAC
 165  *  Out:
 166  *      cxt_buf   - Context buffer
 167  *
 168  * Return Value: none
 169  *
 170  */
 171 void MACvSaveContext(struct vnt_private *priv, unsigned char *cxt_buf)
 172 {
 173         void __iomem *io_base = priv->PortOffset;
 174
 175         /* read page0 register */
 176         memcpy_fromio(cxt_buf, io_base, MAC_MAX_CONTEXT_SIZE_PAGE0);
 177
 178         MACvSelectPage1(io_base);
 179
 180         /* read page1 register */
 181         memcpy_fromio(cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0, io_base,
 182                       MAC_MAX_CONTEXT_SIZE_PAGE1);
 183
 184         MACvSelectPage0(io_base);
 185 }
 186
 187 /*
 188  * Description:
 189  *      Restore MAC registers from context buffer
 190  *
 191  * Parameters:
 192  *  In:
 193  *      io_base    - Base Address for MAC
 194  *      cxt_buf   - Context buffer
 195  *  Out:
 196  *      none
 197  *
 198  * Return Value: none
 199  *
 200  */
 201 void MACvRestoreContext(struct vnt_private *priv, unsigned char *cxt_buf)
 202 {
 203         void __iomem *io_base = priv->PortOffset;
 204
 205         MACvSelectPage1(io_base);
 206         /* restore page1 */
 207         memcpy_toio(io_base, cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0,
 208                     MAC_MAX_CONTEXT_SIZE_PAGE1);
 209
 210         MACvSelectPage0(io_base);
 211
 212         /* restore RCR,TCR,IMR... */
 213         memcpy_toio(io_base + MAC_REG_RCR, cxt_buf + MAC_REG_RCR,
 214                     MAC_REG_ISR - MAC_REG_RCR);
 215
 216         /* restore MAC Config. */
 217         memcpy_toio(io_base + MAC_REG_LRT, cxt_buf + MAC_REG_LRT,
 218                     MAC_REG_PAGE1SEL - MAC_REG_LRT);
 219
 220         iowrite8(*(cxt_buf + MAC_REG_CFG), io_base + MAC_REG_CFG);
 221
 222         /* restore PS Config. */
 223         memcpy_toio(io_base + MAC_REG_PSCFG, cxt_buf + MAC_REG_PSCFG,
 224                     MAC_REG_BBREGCTL - MAC_REG_PSCFG);
 225
 226         /* restore CURR_RX_DESC_ADDR, CURR_TX_DESC_ADDR */
 227         iowrite32(*(u32 *)(cxt_buf + MAC_REG_TXDMAPTR0),
 228                   io_base + MAC_REG_TXDMAPTR0);
 229         iowrite32(*(u32 *)(cxt_buf + MAC_REG_AC0DMAPTR),
 230                   io_base + MAC_REG_AC0DMAPTR);
 231         iowrite32(*(u32 *)(cxt_buf + MAC_REG_BCNDMAPTR),
 232                   io_base + MAC_REG_BCNDMAPTR);
 233         iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR0),
 234                   io_base + MAC_REG_RXDMAPTR0);
 235         iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR1),
 236                   io_base + MAC_REG_RXDMAPTR1);
 237 }
 238
 239 /*
 240  * Description:
 241  *      Software Reset MAC
 242  *
 243  * Parameters:
 244  *  In:
 245  *      io_base    - Base Address for MAC
 246  *  Out:
 247  *      none
 248  *
 249  * Return Value: true if Reset Success; otherwise false
 250  *
 251  */
 252 bool MACbSoftwareReset(struct vnt_private *priv)
 253 {
 254         void __iomem *io_base = priv->PortOffset;
 255         unsigned short ww;
 256
 257         /* turn on HOSTCR_SOFTRST, just write 0x01 to reset */
 258         iowrite8(0x01, io_base + MAC_REG_HOSTCR);
 259
 260         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 261                 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_SOFTRST))
 262                         break;
 263         }
 264         if (ww == W_MAX_TIMEOUT)
 265                 return false;
 266         return true;
 267 }
 268
 269 /*
 270  * Description:
 271  *      save some important register's value, then do reset, then restore
 272  *      register's value
 273  *
 274  * Parameters:
 275  *  In:
 276  *      io_base    - Base Address for MAC
 277  *  Out:
 278  *      none
 279  *
 280  * Return Value: true if success; otherwise false
 281  *
 282  */
 283 bool MACbSafeSoftwareReset(struct vnt_private *priv)
 284 {
 285         unsigned char abyTmpRegData[MAC_MAX_CONTEXT_SIZE_PAGE0 + MAC_MAX_CONTEXT_SIZE_PAGE1];
 286         bool bRetVal;
 287
 288         /* PATCH....
 289          * save some important register's value, then do
 290          * reset, then restore register's value
 291          */
 292         /* save MAC context */
 293         MACvSaveContext(priv, abyTmpRegData);
 294         /* do reset */
 295         bRetVal = MACbSoftwareReset(priv);
 296         /* restore MAC context, except CR0 */
 297         MACvRestoreContext(priv, abyTmpRegData);
 298
 299         return bRetVal;
 300 }
 301
 302 /*
 303  * Description:
 304  *      Turn Off MAC Rx
 305  *
 306  * Parameters:
 307  *  In:
 308  *      io_base    - Base Address for MAC
 309  *  Out:
 310  *      none
 311  *
 312  * Return Value: true if success; otherwise false
 313  *
 314  */
 315 bool MACbSafeRxOff(struct vnt_private *priv)
 316 {
 317         void __iomem *io_base = priv->PortOffset;
 318         unsigned short ww;
 319
 320         /* turn off wow temp for turn off Rx safely */
 321
 322         /* Clear RX DMA0,1 */
 323         iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL0);
 324         iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL1);
 325         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 326                 if (!(ioread32(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
 327                         break;
 328         }
 329         if (ww == W_MAX_TIMEOUT) {
 330                 pr_debug(" DBG_PORT80(0x10)\n");
 331                 return false;
 332         }
 333         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 334                 if (!(ioread32(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
 335                         break;
 336         }
 337         if (ww == W_MAX_TIMEOUT) {
 338                 pr_debug(" DBG_PORT80(0x11)\n");
 339                 return false;
 340         }
 341
 342         /* try to safe shutdown RX */
 343         MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_RXON);
 344         /* W_MAX_TIMEOUT is the timeout period */
 345         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 346                 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_RXONST))
 347                         break;
 348         }
 349         if (ww == W_MAX_TIMEOUT) {
 350                 pr_debug(" DBG_PORT80(0x12)\n");
 351                 return false;
 352         }
 353         return true;
 354 }
 355
 356 /*
 357  * Description:
 358  *      Turn Off MAC Tx
 359  *
 360  * Parameters:
 361  *  In:
 362  *      io_base    - Base Address for MAC
 363  *  Out:
 364  *      none
 365  *
 366  * Return Value: true if success; otherwise false
 367  *
 368  */
 369 bool MACbSafeTxOff(struct vnt_private *priv)
 370 {
 371         void __iomem *io_base = priv->PortOffset;
 372         unsigned short ww;
 373
 374         /* Clear TX DMA */
 375         /* Tx0 */
 376         iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_TXDMACTL0);
 377         /* AC0 */
 378         iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_AC0DMACTL);
 379
 380         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 381                 if (!(ioread32(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
 382                         break;
 383         }
 384         if (ww == W_MAX_TIMEOUT) {
 385                 pr_debug(" DBG_PORT80(0x20)\n");
 386                 return false;
 387         }
 388         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 389                 if (!(ioread32(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
 390                         break;
 391         }
 392         if (ww == W_MAX_TIMEOUT) {
 393                 pr_debug(" DBG_PORT80(0x21)\n");
 394                 return false;
 395         }
 396
 397         /* try to safe shutdown TX */
 398         MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_TXON);
 399
 400         /* W_MAX_TIMEOUT is the timeout period */
 401         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 402                 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_TXONST))
 403                         break;
 404         }
 405         if (ww == W_MAX_TIMEOUT) {
 406                 pr_debug(" DBG_PORT80(0x24)\n");
 407                 return false;
 408         }
 409         return true;
 410 }
 411
 412 /*
 413  * Description:
 414  *      Stop MAC function
 415  *
 416  * Parameters:
 417  *  In:
 418  *      io_base    - Base Address for MAC
 419  *  Out:
 420  *      none
 421  *
 422  * Return Value: true if success; otherwise false
 423  *
 424  */
 425 bool MACbSafeStop(struct vnt_private *priv)
 426 {
 427         void __iomem *io_base = priv->PortOffset;
 428
 429         MACvRegBitsOff(io_base, MAC_REG_TCR, TCR_AUTOBCNTX);
 430
 431         if (!MACbSafeRxOff(priv)) {
 432                 pr_debug(" MACbSafeRxOff == false)\n");
 433                 MACbSafeSoftwareReset(priv);
 434                 return false;
 435         }
 436         if (!MACbSafeTxOff(priv)) {
 437                 pr_debug(" MACbSafeTxOff == false)\n");
 438                 MACbSafeSoftwareReset(priv);
 439                 return false;
 440         }
 441
 442         MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_MACEN);
 443
 444         return true;
 445 }
 446
 447 /*
 448  * Description:
 449  *      Shut Down MAC
 450  *
 451  * Parameters:
 452  *  In:
 453  *      io_base    - Base Address for MAC
 454  *  Out:
 455  *      none
 456  *
 457  * Return Value: true if success; otherwise false
 458  *
 459  */
 460 bool MACbShutdown(struct vnt_private *priv)
 461 {
 462         void __iomem *io_base = priv->PortOffset;
 463         /* disable MAC IMR */
 464         MACvIntDisable(io_base);
 465         MACvSetLoopbackMode(priv, MAC_LB_INTERNAL);
 466         /* stop the adapter */
 467         if (!MACbSafeStop(priv)) {
 468                 MACvSetLoopbackMode(priv, MAC_LB_NONE);
 469                 return false;
 470         }
 471         MACvSetLoopbackMode(priv, MAC_LB_NONE);
 472         return true;
 473 }
 474
 475 /*
 476  * Description:
 477  *      Initialize MAC
 478  *
 479  * Parameters:
 480  *  In:
 481  *      io_base    - Base Address for MAC
 482  *  Out:
 483  *      none
 484  *
 485  * Return Value: none
 486  *
 487  */
 488 void MACvInitialize(struct vnt_private *priv)
 489 {
 490         void __iomem *io_base = priv->PortOffset;
 491         /* clear sticky bits */
 492         MACvClearStckDS(io_base);
 493         /* disable force PME-enable */
 494         iowrite8(PME_OVR, io_base + MAC_REG_PMC1);
 495         /* only 3253 A */
 496
 497         /* do reset */
 498         MACbSoftwareReset(priv);
 499
 500         /* reset TSF counter */
 501         iowrite8(TFTCTL_TSFCNTRST, io_base + MAC_REG_TFTCTL);
 502         /* enable TSF counter */
 503         iowrite8(TFTCTL_TSFCNTREN, io_base + MAC_REG_TFTCTL);
 504 }
 505
 506 /*
 507  * Description:
 508  *      Set the chip with current rx descriptor address
 509  *
 510  * Parameters:
 511  *  In:
 512  *      io_base        - Base Address for MAC
 513  *      curr_desc_addr  - Descriptor Address
 514  *  Out:
 515  *      none
 516  *
 517  * Return Value: none
 518  *
 519  */
 520 void MACvSetCurrRx0DescAddr(struct vnt_private *priv, u32 curr_desc_addr)
 521 {
 522         void __iomem *io_base = priv->PortOffset;
 523         unsigned short ww;
 524         unsigned char org_dma_ctl;
 525
 526         org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL0);
 527         if (org_dma_ctl & DMACTL_RUN)
 528                 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0 + 2);
 529
 530         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 531                 if (!(ioread8(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
 532                         break;
 533         }
 534
 535         iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR0);
 536         if (org_dma_ctl & DMACTL_RUN)
 537                 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0);
 538 }
 539
 540 /*
 541  * Description:
 542  *      Set the chip with current rx descriptor address
 543  *
 544  * Parameters:
 545  *  In:
 546  *      io_base        - Base Address for MAC
 547  *      curr_desc_addr  - Descriptor Address
 548  *  Out:
 549  *      none
 550  *
 551  * Return Value: none
 552  *
 553  */
 554 void MACvSetCurrRx1DescAddr(struct vnt_private *priv, u32 curr_desc_addr)
 555 {
 556         void __iomem *io_base = priv->PortOffset;
 557         unsigned short ww;
 558         unsigned char org_dma_ctl;
 559
 560         org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL1);
 561         if (org_dma_ctl & DMACTL_RUN)
 562                 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1 + 2);
 563
 564         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 565                 if (!(ioread8(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
 566                         break;
 567         }
 568
 569         iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR1);
 570         if (org_dma_ctl & DMACTL_RUN)
 571                 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1);
 572 }
 573
 574 /*
 575  * Description:
 576  *      Set the chip with current tx0 descriptor address
 577  *
 578  * Parameters:
 579  *  In:
 580  *      io_base        - Base Address for MAC
 581  *      curr_desc_addr  - Descriptor Address
 582  *  Out:
 583  *      none
 584  *
 585  * Return Value: none
 586  *
 587  */
 588 void MACvSetCurrTx0DescAddrEx(struct vnt_private *priv,
 589                               u32 curr_desc_addr)
 590 {
 591         void __iomem *io_base = priv->PortOffset;
 592         unsigned short ww;
 593         unsigned char org_dma_ctl;
 594
 595         org_dma_ctl = ioread8(io_base + MAC_REG_TXDMACTL0);
 596         if (org_dma_ctl & DMACTL_RUN)
 597                 iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0 + 2);
 598
 599         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 600                 if (!(ioread8(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
 601                         break;
 602         }
 603
 604         iowrite32(curr_desc_addr, io_base + MAC_REG_TXDMAPTR0);
 605         if (org_dma_ctl & DMACTL_RUN)
 606                 iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0);
 607 }
 608
 609 /*
 610  * Description:
 611  *      Set the chip with current AC0 descriptor address
 612  *
 613  * Parameters:
 614  *  In:
 615  *      io_base        - Base Address for MAC
 616  *      curr_desc_addr  - Descriptor Address
 617  *  Out:
 618  *      none
 619  *
 620  * Return Value: none
 621  *
 622  */
 623 /* TxDMA1 = AC0DMA */
 624 void MACvSetCurrAC0DescAddrEx(struct vnt_private *priv,
 625                               u32 curr_desc_addr)
 626 {
 627         void __iomem *io_base = priv->PortOffset;
 628         unsigned short ww;
 629         unsigned char org_dma_ctl;
 630
 631         org_dma_ctl = ioread8(io_base + MAC_REG_AC0DMACTL);
 632         if (org_dma_ctl & DMACTL_RUN)
 633                 iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL + 2);
 634
 635         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 636                 if (!(ioread8(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
 637                         break;
 638         }
 639         if (ww == W_MAX_TIMEOUT)
 640                 pr_debug(" DBG_PORT80(0x26)\n");
 641         iowrite32(curr_desc_addr, io_base + MAC_REG_AC0DMAPTR);
 642         if (org_dma_ctl & DMACTL_RUN)
 643                 iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL);
 644 }
 645
 646 void MACvSetCurrTXDescAddr(int iTxType, struct vnt_private *priv,
 647                            u32 curr_desc_addr)
 648 {
 649         if (iTxType == TYPE_AC0DMA)
 650                 MACvSetCurrAC0DescAddrEx(priv, curr_desc_addr);
 651         else if (iTxType == TYPE_TXDMA0)
 652                 MACvSetCurrTx0DescAddrEx(priv, curr_desc_addr);
 653 }
 654
 655 /*
 656  * Description:
 657  *      Micro Second Delay via MAC
 658  *
 659  * Parameters:
 660  *  In:
 661  *      io_base    - Base Address for MAC
 662  *      uDelay      - Delay time (timer resolution is 4 us)
 663  *  Out:
 664  *      none
 665  *
 666  * Return Value: none
 667  *
 668  */
 669 void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay)
 670 {
 671         void __iomem *io_base = priv->PortOffset;
 672         unsigned char byValue;
 673         unsigned int uu, ii;
 674
 675         iowrite8(0, io_base + MAC_REG_TMCTL0);
 676         iowrite32(uDelay, io_base + MAC_REG_TMDATA0);
 677         iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL0);
 678         for (ii = 0; ii < 66; ii++) {  /* assume max PCI clock is 66Mhz */
 679                 for (uu = 0; uu < uDelay; uu++) {
 680                         byValue = ioread8(io_base + MAC_REG_TMCTL0);
 681                         if ((byValue == 0) ||
 682                             (byValue & TMCTL_TSUSP)) {
 683                                 iowrite8(0, io_base + MAC_REG_TMCTL0);
 684                                 return;
 685                         }
 686                 }
 687         }
 688         iowrite8(0, io_base + MAC_REG_TMCTL0);
 689 }
 690
 691 /*
 692  * Description:
 693  *      Micro Second One shot timer via MAC
 694  *
 695  * Parameters:
 696  *  In:
 697  *      io_base    - Base Address for MAC
 698  *      uDelay      - Delay time
 699  *  Out:
 700  *      none
 701  *
 702  * Return Value: none
 703  *
 704  */
 705 void MACvOneShotTimer1MicroSec(struct vnt_private *priv,
 706                                unsigned int uDelayTime)
 707 {
 708         void __iomem *io_base = priv->PortOffset;
 709
 710         iowrite8(0, io_base + MAC_REG_TMCTL1);
 711         iowrite32(uDelayTime, io_base + MAC_REG_TMDATA1);
 712         iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL1);
 713 }
 714
 715 void MACvSetMISCFifo(struct vnt_private *priv, unsigned short offset,
 716                      u32 data)
 717 {
 718         void __iomem *io_base = priv->PortOffset;
 719
 720         if (offset > 273)
 721                 return;
 722         iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
 723         iowrite32(data, io_base + MAC_REG_MISCFFDATA);
 724         iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
 725 }
 726
 727 bool MACbPSWakeup(struct vnt_private *priv)
 728 {
 729         void __iomem *io_base = priv->PortOffset;
 730         unsigned int ww;
 731         /* Read PSCTL */
 732         if (MACbIsRegBitsOff(priv, MAC_REG_PSCTL, PSCTL_PS))
 733                 return true;
 734
 735         /* Disable PS */
 736         MACvRegBitsOff(io_base, MAC_REG_PSCTL, PSCTL_PSEN);
 737
 738         /* Check if SyncFlushOK */
 739         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 740                 if (ioread8(io_base + MAC_REG_PSCTL) & PSCTL_WAKEDONE)
 741                         break;
 742         }
 743         if (ww == W_MAX_TIMEOUT) {
 744                 pr_debug(" DBG_PORT80(0x33)\n");
 745                 return false;
 746         }
 747         return true;
 748 }
 749
 750 /*
 751  * Description:
 752  *      Set the Key by MISCFIFO
 753  *
 754  * Parameters:
 755  *  In:
 756  *      io_base        - Base Address for MAC
 757  *
 758  *  Out:
 759  *      none
 760  *
 761  * Return Value: none
 762  *
 763  */
 764
 765 void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl,
 766                      unsigned int uEntryIdx, unsigned int uKeyIdx,
 767                      unsigned char *pbyAddr, u32 *pdwKey,
 768                      unsigned char byLocalID)
 769 {
 770         void __iomem *io_base = priv->PortOffset;
 771         unsigned short offset;
 772         u32 data;
 773         int     ii;
 774
 775         if (byLocalID <= 1)
 776                 return;
 777
 778         pr_debug("%s\n", __func__);
 779         offset = MISCFIFO_KEYETRY0;
 780         offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
 781
 782         data = 0;
 783         data |= wKeyCtl;
 784         data <<= 16;
 785         data |= MAKEWORD(*(pbyAddr + 4), *(pbyAddr + 5));
 786         pr_debug("1. offset: %d, Data: %X, KeyCtl:%X\n",
 787                  offset, data, wKeyCtl);
 788
 789         iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
 790         iowrite32(data, io_base + MAC_REG_MISCFFDATA);
 791         iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
 792         offset++;
 793
 794         data = 0;
 795         data |= *(pbyAddr + 3);
 796         data <<= 8;
 797         data |= *(pbyAddr + 2);
 798         data <<= 8;
 799         data |= *(pbyAddr + 1);
 800         data <<= 8;
 801         data |= *pbyAddr;
 802         pr_debug("2. offset: %d, Data: %X\n", offset, data);
 803
 804         iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
 805         iowrite32(data, io_base + MAC_REG_MISCFFDATA);
 806         iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
 807         offset++;
 808
 809         offset += (uKeyIdx * 4);
 810         for (ii = 0; ii < 4; ii++) {
 811                 /* always push 128 bits */
 812                 pr_debug("3.(%d) offset: %d, Data: %X\n",
 813                          ii, offset + ii, *pdwKey);
 814                 iowrite16(offset + ii, io_base + MAC_REG_MISCFFNDEX);
 815                 iowrite32(*pdwKey++, io_base + MAC_REG_MISCFFDATA);
 816                 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
 817         }
 818 }
 819
 820 /*
 821  * Description:
 822  *      Disable the Key Entry by MISCFIFO
 823  *
 824  * Parameters:
 825  *  In:
 826  *      io_base        - Base Address for MAC
 827  *
 828  *  Out:
 829  *      none
 830  *
 831  * Return Value: none
 832  *
 833  */
 834 void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx)
 835 {
 836         void __iomem *io_base = priv->PortOffset;
 837         unsigned short offset;
 838
 839         offset = MISCFIFO_KEYETRY0;
 840         offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
 841
 842         iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
 843         iowrite32(0, io_base + MAC_REG_MISCFFDATA);
 844         iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
 845 }