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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / staging / vt6656 / rf.c
blob43237b7e1dbe1f5f6ae66b564d810556d9d9bc75
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
4 * All rights reserved.
5 *
6 * File: rf.c
7 *
8 * Purpose: rf function code
9 *
10 * Author: Jerry Chen
11 *
12 * Date: Feb. 19, 2004
13 *
14 * Functions:
15 * vnt_rf_write_embedded - Embedded write RF register via MAC
16 *
17 * Revision History:
18 * RF_VT3226: RobertYu:20051111, VT3226C0 and before
19 * RF_VT3226D0: RobertYu:20051228
20 * RF_VT3342A0: RobertYu:20060609
21 *
22 */
23
24 #include "mac.h"
25 #include "rf.h"
26 #include "baseband.h"
27 #include "usbpipe.h"
28
29 #define CB_AL2230_INIT_SEQ 15
30 #define AL2230_PWR_IDX_LEN 64
31
32 #define CB_AL7230_INIT_SEQ 16
33 #define AL7230_PWR_IDX_LEN 64
34
35 #define CB_VT3226_INIT_SEQ 11
36 #define VT3226_PWR_IDX_LEN 64
37
38 #define CB_VT3342_INIT_SEQ 13
39 #define VT3342_PWR_IDX_LEN 64
40
41 static u8 al2230_init_table[CB_AL2230_INIT_SEQ][3] = {
42 {0x03, 0xf7, 0x90},
43 {0x03, 0x33, 0x31},
44 {0x01, 0xb8, 0x02},
45 {0x00, 0xff, 0xf3},
46 {0x00, 0x05, 0xa4},
47 {0x0f, 0x4d, 0xc5},
48 {0x08, 0x05, 0xb6},
49 {0x01, 0x47, 0xc7},
50 {0x00, 0x06, 0x88},
51 {0x04, 0x03, 0xb9},
52 {0x00, 0xdb, 0xba},
53 {0x00, 0x09, 0x9b},
54 {0x0b, 0xdf, 0xfc},
55 {0x00, 0x00, 0x0d},
56 {0x00, 0x58, 0x0f}
57 };
58
59 static u8 al2230_channel_table0[CB_MAX_CHANNEL_24G][3] = {
60 {0x03, 0xf7, 0x90},
61 {0x03, 0xf7, 0x90},
62 {0x03, 0xe7, 0x90},
63 {0x03, 0xe7, 0x90},
64 {0x03, 0xf7, 0xa0},
65 {0x03, 0xf7, 0xa0},
66 {0x03, 0xe7, 0xa0},
67 {0x03, 0xe7, 0xa0},
68 {0x03, 0xf7, 0xb0},
69 {0x03, 0xf7, 0xb0},
70 {0x03, 0xe7, 0xb0},
71 {0x03, 0xe7, 0xb0},
72 {0x03, 0xf7, 0xc0},
73 {0x03, 0xe7, 0xc0}
74 };
75
76 static u8 al2230_channel_table1[CB_MAX_CHANNEL_24G][3] = {
77 {0x03, 0x33, 0x31},
78 {0x0b, 0x33, 0x31},
79 {0x03, 0x33, 0x31},
80 {0x0b, 0x33, 0x31},
81 {0x03, 0x33, 0x31},
82 {0x0b, 0x33, 0x31},
83 {0x03, 0x33, 0x31},
84 {0x0b, 0x33, 0x31},
85 {0x03, 0x33, 0x31},
86 {0x0b, 0x33, 0x31},
87 {0x03, 0x33, 0x31},
88 {0x0b, 0x33, 0x31},
89 {0x03, 0x33, 0x31},
90 {0x06, 0x66, 0x61}
91 };
92
93 static u8 al7230_init_table[CB_AL7230_INIT_SEQ][3] = {
94 {0x20, 0x37, 0x90},
95 {0x13, 0x33, 0x31},
96 {0x84, 0x1f, 0xf2},
97 {0x3f, 0xdf, 0xa3},
98 {0x7f, 0xd7, 0x84},
99 {0x80, 0x2b, 0x55},
100 {0x56, 0xaf, 0x36},
101 {0xce, 0x02, 0x07},
102 {0x6e, 0xbc, 0x98},
103 {0x22, 0x1b, 0xb9},
104 {0xe0, 0x00, 0x0a},
105 {0x08, 0x03, 0x1b},
106 {0x00, 0x0a, 0x3c},
107 {0xff, 0xff, 0xfd},
108 {0x00, 0x00, 0x0e},
109 {0x1a, 0xba, 0x8f}
110 };
111
112 static u8 al7230_init_table_amode[CB_AL7230_INIT_SEQ][3] = {
113 {0x2f, 0xf5, 0x20},
114 {0x00, 0x00, 0x01},
115 {0x45, 0x1f, 0xe2},
116 {0x5f, 0xdf, 0xa3},
117 {0x6f, 0xd7, 0x84},
118 {0x85, 0x3f, 0x55},
119 {0x56, 0xaf, 0x36},
120 {0xce, 0x02, 0x07},
121 {0x6e, 0xbc, 0x98},
122 {0x22, 0x1b, 0xb9},
123 {0xe0, 0x60, 0x0a},
124 {0x08, 0x03, 0x1b},
125 {0x00, 0x14, 0x7c},
126 {0xff, 0xff, 0xfd},
127 {0x00, 0x00, 0x0e},
128 {0x12, 0xba, 0xcf}
129 };
130
131 static u8 al7230_channel_table0[CB_MAX_CHANNEL][3] = {
132 {0x20, 0x37, 0x90},
133 {0x20, 0x37, 0x90},
134 {0x20, 0x37, 0x90},
135 {0x20, 0x37, 0x90},
136 {0x20, 0x37, 0xa0},
137 {0x20, 0x37, 0xa0},
138 {0x20, 0x37, 0xa0},
139 {0x20, 0x37, 0xa0},
140 {0x20, 0x37, 0xb0},
141 {0x20, 0x37, 0xb0},
142 {0x20, 0x37, 0xb0},
143 {0x20, 0x37, 0xb0},
144 {0x20, 0x37, 0xc0},
145 {0x20, 0x37, 0xc0},
146 {0x0f, 0xf5, 0x20}, /* channel 15 Tf = 4915MHz */
147 {0x2f, 0xf5, 0x20},
148 {0x0f, 0xf5, 0x20},
149 {0x0f, 0xf5, 0x20},
150 {0x2f, 0xf5, 0x20},
151 {0x0f, 0xf5, 0x20},
152 {0x2f, 0xf5, 0x30},
153 {0x2f, 0xf5, 0x30},
154 {0x0f, 0xf5, 0x40},
155 {0x2f, 0xf5, 0x40},
156 {0x0f, 0xf5, 0x40},
157 {0x0f, 0xf5, 0x40},
158 {0x2f, 0xf5, 0x40},
159 {0x2f, 0xf5, 0x50},
160 {0x2f, 0xf5, 0x60},
161 {0x2f, 0xf5, 0x60},
162 {0x2f, 0xf5, 0x70},
163 {0x2f, 0xf5, 0x70},
164 {0x2f, 0xf5, 0x70},
165 {0x2f, 0xf5, 0x70},
166 {0x2f, 0xf5, 0x70},
167 {0x2f, 0xf5, 0x70},
168 {0x2f, 0xf5, 0x80},
169 {0x2f, 0xf5, 0x80},
170 {0x2f, 0xf5, 0x80},
171 {0x2f, 0xf5, 0x90},
172 {0x2f, 0xf5, 0xc0},
173 {0x2f, 0xf5, 0xc0},
174 {0x2f, 0xf5, 0xc0},
175 {0x2f, 0xf5, 0xd0},
176 {0x2f, 0xf5, 0xd0},
177 {0x2f, 0xf5, 0xd0},
178 {0x2f, 0xf5, 0xe0},
179 {0x2f, 0xf5, 0xe0},
180 {0x2f, 0xf5, 0xe0},
181 {0x2f, 0xf5, 0xf0},
182 {0x2f, 0xf5, 0xf0},
183 {0x2f, 0xf6, 0x00},
184 {0x2f, 0xf6, 0x00},
185 {0x2f, 0xf6, 0x00},
186 {0x2f, 0xf6, 0x10},
187 {0x2f, 0xf6, 0x10}
188 };
189
190 static u8 al7230_channel_table1[CB_MAX_CHANNEL][3] = {
191 {0x13, 0x33, 0x31},
192 {0x1b, 0x33, 0x31},
193 {0x03, 0x33, 0x31},
194 {0x0b, 0x33, 0x31},
195 {0x13, 0x33, 0x31},
196 {0x1b, 0x33, 0x31},
197 {0x03, 0x33, 0x31},
198 {0x0b, 0x33, 0x31},
199 {0x13, 0x33, 0x31},
200 {0x1b, 0x33, 0x31},
201 {0x03, 0x33, 0x31},
202 {0x0b, 0x33, 0x31},
203 {0x13, 0x33, 0x31},
204 {0x06, 0x66, 0x61},
205 {0x1d, 0x55, 0x51}, /* channel = 15, Tf = 4915MHz */
206 {0x00, 0x00, 0x01},
207 {0x02, 0xaa, 0xa1},
208 {0x08, 0x00, 0x01},
209 {0x0a, 0xaa, 0xa1},
210 {0x0d, 0x55, 0x51},
211 {0x15, 0x55, 0x51},
212 {0x00, 0x00, 0x01},
213 {0x1d, 0x55, 0x51},
214 {0x00, 0x00, 0x01},
215 {0x02, 0xaa, 0xa1},
216 {0x08, 0x00, 0x01},
217 {0x0a, 0xaa, 0xa1},
218 {0x15, 0x55, 0x51},
219 {0x05, 0x55, 0x51},
220 {0x0a, 0xaa, 0xa1},
221 {0x10, 0x00, 0x01},
222 {0x15, 0x55, 0x51},
223 {0x1a, 0xaa, 0xa1},
224 {0x00, 0x00, 0x01},
225 {0x05, 0x55, 0x51},
226 {0x0a, 0xaa, 0xa1},
227 {0x15, 0x55, 0x51},
228 {0x00, 0x00, 0x01},
229 {0x0a, 0xaa, 0xa1},
230 {0x15, 0x55, 0x51},
231 {0x15, 0x55, 0x51},
232 {0x00, 0x00, 0x01},
233 {0x0a, 0xaa, 0xa1},
234 {0x15, 0x55, 0x51},
235 {0x00, 0x00, 0x01},
236 {0x0a, 0xaa, 0xa1},
237 {0x15, 0x55, 0x51},
238 {0x00, 0x00, 0x01},
239 {0x0a, 0xaa, 0xa1},
240 {0x15, 0x55, 0x51},
241 {0x00, 0x00, 0x01},
242 {0x18, 0x00, 0x01},
243 {0x02, 0xaa, 0xa1},
244 {0x0d, 0x55, 0x51},
245 {0x18, 0x00, 0x01},
246 {0x02, 0xaa, 0xb1}
247 };
248
249 static u8 al7230_channel_table2[CB_MAX_CHANNEL][3] = {
250 {0x7f, 0xd7, 0x84},
251 {0x7f, 0xd7, 0x84},
252 {0x7f, 0xd7, 0x84},
253 {0x7f, 0xd7, 0x84},
254 {0x7f, 0xd7, 0x84},
255 {0x7f, 0xd7, 0x84},
256 {0x7f, 0xd7, 0x84},
257 {0x7f, 0xd7, 0x84},
258 {0x7f, 0xd7, 0x84},
259 {0x7f, 0xd7, 0x84},
260 {0x7f, 0xd7, 0x84},
261 {0x7f, 0xd7, 0x84},
262 {0x7f, 0xd7, 0x84},
263 {0x7f, 0xd7, 0x84},
264 {0x7f, 0xd7, 0x84}, /* channel = 15 Tf = 4915MHz */
265 {0x6f, 0xd7, 0x84},
266 {0x7f, 0xd7, 0x84},
267 {0x7f, 0xd7, 0x84},
268 {0x7f, 0xd7, 0x84},
269 {0x7f, 0xd7, 0x84},
270 {0x7f, 0xd7, 0x84},
271 {0x6f, 0xd7, 0x84},
272 {0x7f, 0xd7, 0x84},
273 {0x6f, 0xd7, 0x84},
274 {0x7f, 0xd7, 0x84},
275 {0x7f, 0xd7, 0x84},
276 {0x7f, 0xd7, 0x84},
277 {0x7f, 0xd7, 0x84},
278 {0x7f, 0xd7, 0x84},
279 {0x7f, 0xd7, 0x84},
280 {0x7f, 0xd7, 0x84},
281 {0x7f, 0xd7, 0x84},
282 {0x7f, 0xd7, 0x84},
283 {0x6f, 0xd7, 0x84},
284 {0x7f, 0xd7, 0x84},
285 {0x7f, 0xd7, 0x84},
286 {0x7f, 0xd7, 0x84},
287 {0x6f, 0xd7, 0x84},
288 {0x7f, 0xd7, 0x84},
289 {0x7f, 0xd7, 0x84},
290 {0x7f, 0xd7, 0x84},
291 {0x6f, 0xd7, 0x84},
292 {0x7f, 0xd7, 0x84},
293 {0x7f, 0xd7, 0x84},
294 {0x6f, 0xd7, 0x84},
295 {0x7f, 0xd7, 0x84},
296 {0x7f, 0xd7, 0x84},
297 {0x6f, 0xd7, 0x84},
298 {0x7f, 0xd7, 0x84},
299 {0x7f, 0xd7, 0x84},
300 {0x6f, 0xd7, 0x84},
301 {0x7f, 0xd7, 0x84},
302 {0x7f, 0xd7, 0x84},
303 {0x7f, 0xd7, 0x84},
304 {0x7f, 0xd7, 0x84},
305 {0x7f, 0xd7, 0x84}
306 };
307
308 static u8 vt3226_init_table[CB_VT3226_INIT_SEQ][3] = {
309 {0x03, 0xff, 0x80},
310 {0x02, 0x82, 0xa1},
311 {0x03, 0xc6, 0xa2},
312 {0x01, 0x97, 0x93},
313 {0x03, 0x66, 0x64},
314 {0x00, 0x61, 0xa5},
315 {0x01, 0x7b, 0xd6},
316 {0x00, 0x80, 0x17},
317 {0x03, 0xf8, 0x08},
318 {0x00, 0x02, 0x39},
319 {0x02, 0x00, 0x2a}
320 };
321
322 static u8 vt3226d0_init_table[CB_VT3226_INIT_SEQ][3] = {
323 {0x03, 0xff, 0x80},
324 {0x03, 0x02, 0x21},
325 {0x03, 0xc6, 0xa2},
326 {0x01, 0x97, 0x93},
327 {0x03, 0x66, 0x64},
328 {0x00, 0x71, 0xa5},
329 {0x01, 0x15, 0xc6},
330 {0x01, 0x2e, 0x07},
331 {0x00, 0x58, 0x08},
332 {0x00, 0x02, 0x79},
333 {0x02, 0x01, 0xaa}
334 };
335
336 static u8 vt3226_channel_table0[CB_MAX_CHANNEL_24G][3] = {
337 {0x01, 0x97, 0x83},
338 {0x01, 0x97, 0x83},
339 {0x01, 0x97, 0x93},
340 {0x01, 0x97, 0x93},
341 {0x01, 0x97, 0x93},
342 {0x01, 0x97, 0x93},
343 {0x01, 0x97, 0xa3},
344 {0x01, 0x97, 0xa3},
345 {0x01, 0x97, 0xa3},
346 {0x01, 0x97, 0xa3},
347 {0x01, 0x97, 0xb3},
348 {0x01, 0x97, 0xb3},
349 {0x01, 0x97, 0xb3},
350 {0x03, 0x37, 0xc3}
351 };
352
353 static u8 vt3226_channel_table1[CB_MAX_CHANNEL_24G][3] = {
354 {0x02, 0x66, 0x64},
355 {0x03, 0x66, 0x64},
356 {0x00, 0x66, 0x64},
357 {0x01, 0x66, 0x64},
358 {0x02, 0x66, 0x64},
359 {0x03, 0x66, 0x64},
360 {0x00, 0x66, 0x64},
361 {0x01, 0x66, 0x64},
362 {0x02, 0x66, 0x64},
363 {0x03, 0x66, 0x64},
364 {0x00, 0x66, 0x64},
365 {0x01, 0x66, 0x64},
366 {0x02, 0x66, 0x64},
367 {0x00, 0xcc, 0xc4}
368 };
369
370 static const u32 vt3226d0_lo_current_table[CB_MAX_CHANNEL_24G] = {
371 0x0135c600,
372 0x0135c600,
373 0x0235c600,
374 0x0235c600,
375 0x0235c600,
376 0x0335c600,
377 0x0335c600,
378 0x0335c600,
379 0x0335c600,
380 0x0335c600,
381 0x0335c600,
382 0x0335c600,
383 0x0335c600,
384 0x0135c600
385 };
386
387 static u8 vt3342a0_init_table[CB_VT3342_INIT_SEQ][3] = { /* 11b/g mode */
388 {0x03, 0xff, 0x80},
389 {0x02, 0x08, 0x81},
390 {0x00, 0xc6, 0x02},
391 {0x03, 0xc5, 0x13},
392 {0x00, 0xee, 0xe4},
393 {0x00, 0x71, 0xa5},
394 {0x01, 0x75, 0x46},
395 {0x01, 0x40, 0x27},
396 {0x01, 0x54, 0x08},
397 {0x00, 0x01, 0x69},
398 {0x02, 0x00, 0xaa},
399 {0x00, 0x08, 0xcb},
400 {0x01, 0x70, 0x0c}
401 };
402
403 static u8 vt3342_channel_table0[CB_MAX_CHANNEL][3] = {
404 {0x02, 0x05, 0x03},
405 {0x01, 0x15, 0x03},
406 {0x03, 0xc5, 0x03},
407 {0x02, 0x65, 0x03},
408 {0x01, 0x15, 0x13},
409 {0x03, 0xc5, 0x13},
410 {0x02, 0x05, 0x13},
411 {0x01, 0x15, 0x13},
412 {0x03, 0xc5, 0x13},
413 {0x02, 0x65, 0x13},
414 {0x01, 0x15, 0x23},
415 {0x03, 0xc5, 0x23},
416 {0x02, 0x05, 0x23},
417 {0x00, 0xd5, 0x23},
418 {0x01, 0x15, 0x13}, /* channel = 15 Tf = 4915MHz */
419 {0x01, 0x15, 0x13},
420 {0x01, 0x15, 0x13},
421 {0x01, 0x15, 0x13},
422 {0x01, 0x15, 0x13},
423 {0x01, 0x15, 0x13},
424 {0x01, 0x15, 0x13},
425 {0x01, 0x15, 0x13},
426 {0x01, 0x15, 0x13},
427 {0x01, 0x15, 0x13},
428 {0x01, 0x15, 0x13},
429 {0x01, 0x15, 0x13},
430 {0x01, 0x15, 0x13},
431 {0x01, 0x15, 0x13},
432 {0x01, 0x15, 0x13},
433 {0x01, 0x55, 0x63},
434 {0x01, 0x55, 0x63},
435 {0x02, 0xa5, 0x63},
436 {0x02, 0xa5, 0x63},
437 {0x00, 0x05, 0x73},
438 {0x00, 0x05, 0x73},
439 {0x01, 0x55, 0x73},
440 {0x02, 0xa5, 0x73},
441 {0x00, 0x05, 0x83},
442 {0x01, 0x55, 0x83},
443 {0x02, 0xa5, 0x83},
444 {0x02, 0xa5, 0x83},
445 {0x02, 0xa5, 0x83},
446 {0x02, 0xa5, 0x83},
447 {0x02, 0xa5, 0x83},
448 {0x02, 0xa5, 0x83},
449 {0x02, 0xa5, 0x83},
450 {0x02, 0xa5, 0x83},
451 {0x02, 0xa5, 0x83},
452 {0x02, 0xa5, 0x83},
453 {0x02, 0xa5, 0x83},
454 {0x02, 0xa5, 0x83},
455 {0x00, 0x05, 0xF3},
456 {0x01, 0x56, 0x03},
457 {0x02, 0xa6, 0x03},
458 {0x00, 0x06, 0x03},
459 {0x00, 0x06, 0x03}
460 };
461
462 static u8 vt3342_channel_table1[CB_MAX_CHANNEL][3] = {
463 {0x01, 0x99, 0x94},
464 {0x02, 0x44, 0x44},
465 {0x02, 0xee, 0xe4},
466 {0x03, 0x99, 0x94},
467 {0x00, 0x44, 0x44},
468 {0x00, 0xee, 0xe4},
469 {0x01, 0x99, 0x94},
470 {0x02, 0x44, 0x44},
471 {0x02, 0xee, 0xe4},
472 {0x03, 0x99, 0x94},
473 {0x00, 0x44, 0x44},
474 {0x00, 0xee, 0xe4},
475 {0x01, 0x99, 0x94},
476 {0x03, 0x33, 0x34},
477 {0x00, 0x44, 0x44}, /* channel = 15 Tf = 4915MHz */
478 {0x00, 0x44, 0x44},
479 {0x00, 0x44, 0x44},
480 {0x00, 0x44, 0x44},
481 {0x00, 0x44, 0x44},
482 {0x00, 0x44, 0x44},
483 {0x00, 0x44, 0x44},
484 {0x00, 0x44, 0x44},
485 {0x00, 0x44, 0x44},
486 {0x00, 0x44, 0x44},
487 {0x00, 0x44, 0x44},
488 {0x00, 0x44, 0x44},
489 {0x00, 0x44, 0x44},
490 {0x00, 0x44, 0x44},
491 {0x00, 0x44, 0x44},
492 {0x01, 0x55, 0x54},
493 {0x01, 0x55, 0x54},
494 {0x02, 0xaa, 0xa4},
495 {0x02, 0xaa, 0xa4},
496 {0x00, 0x00, 0x04},
497 {0x00, 0x00, 0x04},
498 {0x01, 0x55, 0x54},
499 {0x02, 0xaa, 0xa4},
500 {0x00, 0x00, 0x04},
501 {0x01, 0x55, 0x54},
502 {0x02, 0xaa, 0xa4},
503 {0x02, 0xaa, 0xa4},
504 {0x02, 0xaa, 0xa4},
505 {0x02, 0xaa, 0xa4},
506 {0x02, 0xaa, 0xa4},
507 {0x02, 0xaa, 0xa4},
508 {0x02, 0xaa, 0xa4},
509 {0x02, 0xaa, 0xa4},
510 {0x02, 0xaa, 0xa4},
511 {0x02, 0xaa, 0xa4},
512 {0x02, 0xaa, 0xa4},
513 {0x02, 0xaa, 0xa4},
514 {0x03, 0x00, 0x04},
515 {0x00, 0x55, 0x54},
516 {0x01, 0xaa, 0xa4},
517 {0x03, 0x00, 0x04},
518 {0x03, 0x00, 0x04}
519 };
520
521 /* Power Table */
522 static const u32 al2230_power_table[AL2230_PWR_IDX_LEN] = {
523 0x04040900,
524 0x04041900,
525 0x04042900,
526 0x04043900,
527 0x04044900,
528 0x04045900,
529 0x04046900,
530 0x04047900,
531 0x04048900,
532 0x04049900,
533 0x0404a900,
534 0x0404b900,
535 0x0404c900,
536 0x0404d900,
537 0x0404e900,
538 0x0404f900,
539 0x04050900,
540 0x04051900,
541 0x04052900,
542 0x04053900,
543 0x04054900,
544 0x04055900,
545 0x04056900,
546 0x04057900,
547 0x04058900,
548 0x04059900,
549 0x0405a900,
550 0x0405b900,
551 0x0405c900,
552 0x0405d900,
553 0x0405e900,
554 0x0405f900,
555 0x04060900,
556 0x04061900,
557 0x04062900,
558 0x04063900,
559 0x04064900,
560 0x04065900,
561 0x04066900,
562 0x04067900,
563 0x04068900,
564 0x04069900,
565 0x0406a900,
566 0x0406b900,
567 0x0406c900,
568 0x0406d900,
569 0x0406e900,
570 0x0406f900,
571 0x04070900,
572 0x04071900,
573 0x04072900,
574 0x04073900,
575 0x04074900,
576 0x04075900,
577 0x04076900,
578 0x04077900,
579 0x04078900,
580 0x04079900,
581 0x0407a900,
582 0x0407b900,
583 0x0407c900,
584 0x0407d900,
585 0x0407e900,
586 0x0407f900
587 };
588
589 /*
590 * Description: Write to IF/RF, by embedded programming
591 */
592 int vnt_rf_write_embedded(struct vnt_private *priv, u32 data)
593 {
594 u8 reg_data[4];
595
596 data |= (VNT_RF_REG_LEN << 3) | IFREGCTL_REGW;
597
598 reg_data[0] = (u8)data;
599 reg_data[1] = (u8)(data >> 8);
600 reg_data[2] = (u8)(data >> 16);
601 reg_data[3] = (u8)(data >> 24);
602
603 vnt_control_out(priv, MESSAGE_TYPE_WRITE_IFRF,
604 0, 0, ARRAY_SIZE(reg_data), reg_data);
605
606 return true;
607 }
608
609 /* Set Tx power by rate and channel number */
610 int vnt_rf_setpower(struct vnt_private *priv, u32 rate, u32 channel)
611 {
612 u8 power = priv->cck_pwr;
613
614 if (channel == 0)
615 return -EINVAL;
616
617 switch (rate) {
618 case RATE_1M:
619 case RATE_2M:
620 case RATE_5M:
621 case RATE_11M:
622 channel--;
623
624 if (channel < sizeof(priv->cck_pwr_tbl))
625 power = priv->cck_pwr_tbl[channel];
626 break;
627 case RATE_6M:
628 case RATE_9M:
629 case RATE_12M:
630 case RATE_18M:
631 case RATE_24M:
632 case RATE_36M:
633 case RATE_48M:
634 case RATE_54M:
635 if (channel > CB_MAX_CHANNEL_24G)
636 power = priv->ofdm_a_pwr_tbl[channel - 15];
637 else
638 power = priv->ofdm_pwr_tbl[channel - 1];
639 break;
640 }
641
642 return vnt_rf_set_txpower(priv, power, rate);
643 }
644
645 static u8 vnt_rf_addpower(struct vnt_private *priv)
646 {
647 s32 rssi = -priv->current_rssi;
648
649 if (!rssi)
650 return 7;
651
652 if (priv->rf_type == RF_VT3226D0) {
653 if (rssi < -70)
654 return 9;
655 else if (rssi < -65)
656 return 7;
657 else if (rssi < -60)
658 return 5;
659 } else {
660 if (rssi < -80)
661 return 9;
662 else if (rssi < -75)
663 return 7;
664 else if (rssi < -70)
665 return 5;
666 }
667
668 return 0;
669 }
670
671 /* Set Tx power by power level and rate */
672 int vnt_rf_set_txpower(struct vnt_private *priv, u8 power, u32 rate)
673 {
674 u32 power_setting = 0;
675 int ret = true;
676
677 power += vnt_rf_addpower(priv);
678 if (power > VNT_RF_MAX_POWER)
679 power = VNT_RF_MAX_POWER;
680
681 if (priv->power == power)
682 return true;
683
684 priv->power = power;
685
686 switch (priv->rf_type) {
687 case RF_AL2230:
688 if (power >= AL2230_PWR_IDX_LEN)
689 return false;
690
691 ret &= vnt_rf_write_embedded(priv, al2230_power_table[power]);
692
693 if (rate <= RATE_11M)
694 ret &= vnt_rf_write_embedded(priv, 0x0001b400);
695 else
696 ret &= vnt_rf_write_embedded(priv, 0x0005a400);
697 break;
698 case RF_AL2230S:
699 if (power >= AL2230_PWR_IDX_LEN)
700 return false;
701
702 ret &= vnt_rf_write_embedded(priv, al2230_power_table[power]);
703
704 if (rate <= RATE_11M) {
705 ret &= vnt_rf_write_embedded(priv, 0x040c1400);
706 ret &= vnt_rf_write_embedded(priv, 0x00299b00);
707 } else {
708 ret &= vnt_rf_write_embedded(priv, 0x0005a400);
709 ret &= vnt_rf_write_embedded(priv, 0x00099b00);
710 }
711 break;
712
713 case RF_AIROHA7230:
714 if (rate <= RATE_11M)
715 ret &= vnt_rf_write_embedded(priv, 0x111bb900);
716 else
717 ret &= vnt_rf_write_embedded(priv, 0x221bb900);
718
719 if (power >= AL7230_PWR_IDX_LEN)
720 return false;
721
722 /*
723 * 0x080F1B00 for 3 wire control TxGain(D10)
724 * and 0x31 as TX Gain value
725 */
726 power_setting = 0x080c0b00 | (power << 12);
727
728 ret &= vnt_rf_write_embedded(priv, power_setting);
729
730 break;
731
732 case RF_VT3226:
733 if (power >= VT3226_PWR_IDX_LEN)
734 return false;
735 power_setting = ((0x3f - power) << 20) | (0x17 << 8);
736
737 ret &= vnt_rf_write_embedded(priv, power_setting);
738
739 break;
740 case RF_VT3226D0:
741 if (power >= VT3226_PWR_IDX_LEN)
742 return false;
743
744 if (rate <= RATE_11M) {
745 u16 hw_value = priv->hw->conf.chandef.chan->hw_value;
746
747 power_setting = ((0x3f - power) << 20) | (0xe07 << 8);
748
749 ret &= vnt_rf_write_embedded(priv, power_setting);
750 ret &= vnt_rf_write_embedded(priv, 0x03c6a200);
751
752 dev_dbg(&priv->usb->dev,
753 "%s 11b channel [%d]\n", __func__, hw_value);
754
755 hw_value--;
756
757 if (hw_value < ARRAY_SIZE(vt3226d0_lo_current_table))
758 ret &= vnt_rf_write_embedded(priv,
759 vt3226d0_lo_current_table[hw_value]);
760
761 ret &= vnt_rf_write_embedded(priv, 0x015C0800);
762 } else {
763 dev_dbg(&priv->usb->dev,
764 "@@@@ %s> 11G mode\n", __func__);
765
766 power_setting = ((0x3f - power) << 20) | (0x7 << 8);
767
768 ret &= vnt_rf_write_embedded(priv, power_setting);
769 ret &= vnt_rf_write_embedded(priv, 0x00C6A200);
770 ret &= vnt_rf_write_embedded(priv, 0x016BC600);
771 ret &= vnt_rf_write_embedded(priv, 0x00900800);
772 }
773 break;
774
775 case RF_VT3342A0:
776 if (power >= VT3342_PWR_IDX_LEN)
777 return false;
778
779 power_setting = ((0x3f - power) << 20) | (0x27 << 8);
780
781 ret &= vnt_rf_write_embedded(priv, power_setting);
782
783 break;
784 default:
785 break;
786 }
787 return ret;
788 }
789
790 /* Convert rssi to dbm */
791 void vnt_rf_rssi_to_dbm(struct vnt_private *priv, u8 rssi, long *dbm)
792 {
793 u8 idx = ((rssi & 0xc0) >> 6) & 0x03;
794 long b = rssi & 0x3f;
795 long a = 0;
796 u8 airoharf[4] = {0, 18, 0, 40};
797
798 switch (priv->rf_type) {
799 case RF_AL2230:
800 case RF_AL2230S:
801 case RF_AIROHA7230:
802 case RF_VT3226:
803 case RF_VT3226D0:
804 case RF_VT3342A0:
805 a = airoharf[idx];
806 break;
807 default:
808 break;
809 }
810
811 *dbm = -1 * (a + b * 2);
812 }
813
814 int vnt_rf_table_download(struct vnt_private *priv)
815 {
816 int ret = 0;
817 u16 length1 = 0, length2 = 0, length3 = 0;
818 u8 *addr1 = NULL, *addr2 = NULL, *addr3 = NULL;
819 u16 length, value;
820 u8 array[256];
821
822 switch (priv->rf_type) {
823 case RF_AL2230:
824 case RF_AL2230S:
825 length1 = CB_AL2230_INIT_SEQ * 3;
826 length2 = CB_MAX_CHANNEL_24G * 3;
827 length3 = CB_MAX_CHANNEL_24G * 3;
828 addr1 = &al2230_init_table[0][0];
829 addr2 = &al2230_channel_table0[0][0];
830 addr3 = &al2230_channel_table1[0][0];
831 break;
832 case RF_AIROHA7230:
833 length1 = CB_AL7230_INIT_SEQ * 3;
834 length2 = CB_MAX_CHANNEL * 3;
835 length3 = CB_MAX_CHANNEL * 3;
836 addr1 = &al7230_init_table[0][0];
837 addr2 = &al7230_channel_table0[0][0];
838 addr3 = &al7230_channel_table1[0][0];
839 break;
840 case RF_VT3226:
841 length1 = CB_VT3226_INIT_SEQ * 3;
842 length2 = CB_MAX_CHANNEL_24G * 3;
843 length3 = CB_MAX_CHANNEL_24G * 3;
844 addr1 = &vt3226_init_table[0][0];
845 addr2 = &vt3226_channel_table0[0][0];
846 addr3 = &vt3226_channel_table1[0][0];
847 break;
848 case RF_VT3226D0:
849 length1 = CB_VT3226_INIT_SEQ * 3;
850 length2 = CB_MAX_CHANNEL_24G * 3;
851 length3 = CB_MAX_CHANNEL_24G * 3;
852 addr1 = &vt3226d0_init_table[0][0];
853 addr2 = &vt3226_channel_table0[0][0];
854 addr3 = &vt3226_channel_table1[0][0];
855 break;
856 case RF_VT3342A0:
857 length1 = CB_VT3342_INIT_SEQ * 3;
858 length2 = CB_MAX_CHANNEL * 3;
859 length3 = CB_MAX_CHANNEL * 3;
860 addr1 = &vt3342a0_init_table[0][0];
861 addr2 = &vt3342_channel_table0[0][0];
862 addr3 = &vt3342_channel_table1[0][0];
863 break;
864 }
865
866 /* Init Table */
867 memcpy(array, addr1, length1);
868
869 ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, 0,
870 MESSAGE_REQUEST_RF_INIT, length1, array);
871 if (ret)
872 goto end;
873
874 /* Channel Table 0 */
875 value = 0;
876 while (length2 > 0) {
877 if (length2 >= 64)
878 length = 64;
879 else
880 length = length2;
881
882 memcpy(array, addr2, length);
883
884 ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, value,
885 MESSAGE_REQUEST_RF_CH0, length, array);
886 if (ret)
887 goto end;
888
889 length2 -= length;
890 value += length;
891 addr2 += length;
892 }
893
894 /* Channel table 1 */
895 value = 0;
896 while (length3 > 0) {
897 if (length3 >= 64)
898 length = 64;
899 else
900 length = length3;
901
902 memcpy(array, addr3, length);
903
904 ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, value,
905 MESSAGE_REQUEST_RF_CH1, length, array);
906 if (ret)
907 goto end;
908
909 length3 -= length;
910 value += length;
911 addr3 += length;
912 }
913
914 if (priv->rf_type == RF_AIROHA7230) {
915 length1 = CB_AL7230_INIT_SEQ * 3;
916 length2 = CB_MAX_CHANNEL * 3;
917 addr1 = &al7230_init_table_amode[0][0];
918 addr2 = &al7230_channel_table2[0][0];
919
920 memcpy(array, addr1, length1);
921
922 /* Init Table 2 */
923 ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, 0,
924 MESSAGE_REQUEST_RF_INIT2, length1, array);
925 if (ret)
926 goto end;
927
928 /* Channel Table 0 */
929 value = 0;
930 while (length2 > 0) {
931 if (length2 >= 64)
932 length = 64;
933 else
934 length = length2;
935
936 memcpy(array, addr2, length);
937
938 ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, value,
939 MESSAGE_REQUEST_RF_CH2, length,
940 array);
941 if (ret)
942 goto end;
943
944 length2 -= length;
945 value += length;
946 addr2 += length;
947 }
948 }
949
950 end:
951 return ret;
952 }
Linux with added FPC-III support