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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / staging / wilc1000 / sdio.c
blob36eb589263bfd8deafc6cd42d71e15675c9ae2d0
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
4 * All rights reserved.
5 */
6
7 #include <linux/clk.h>
8 #include <linux/mmc/sdio_func.h>
9 #include <linux/mmc/host.h>
10 #include <linux/mmc/sdio.h>
11 #include <linux/of_irq.h>
12
13 #include "netdev.h"
14 #include "cfg80211.h"
15
16 #define SDIO_MODALIAS "wilc1000_sdio"
17
18 #define SDIO_VENDOR_ID_WILC 0x0296
19 #define SDIO_DEVICE_ID_WILC 0x5347
20
21 static const struct sdio_device_id wilc_sdio_ids[] = {
22 { SDIO_DEVICE(SDIO_VENDOR_ID_WILC, SDIO_DEVICE_ID_WILC) },
23 { },
24 };
25
26 #define WILC_SDIO_BLOCK_SIZE 512
27
28 struct wilc_sdio {
29 bool irq_gpio;
30 u32 block_size;
31 int has_thrpt_enh3;
32 };
33
34 struct sdio_cmd52 {
35 u32 read_write: 1;
36 u32 function: 3;
37 u32 raw: 1;
38 u32 address: 17;
39 u32 data: 8;
40 };
41
42 struct sdio_cmd53 {
43 u32 read_write: 1;
44 u32 function: 3;
45 u32 block_mode: 1;
46 u32 increment: 1;
47 u32 address: 17;
48 u32 count: 9;
49 u8 *buffer;
50 u32 block_size;
51 };
52
53 static const struct wilc_hif_func wilc_hif_sdio;
54
55 static void wilc_sdio_interrupt(struct sdio_func *func)
56 {
57 sdio_release_host(func);
58 wilc_handle_isr(sdio_get_drvdata(func));
59 sdio_claim_host(func);
60 }
61
62 static int wilc_sdio_cmd52(struct wilc *wilc, struct sdio_cmd52 *cmd)
63 {
64 struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev);
65 int ret;
66 u8 data;
67
68 sdio_claim_host(func);
69
70 func->num = cmd->function;
71 if (cmd->read_write) { /* write */
72 if (cmd->raw) {
73 sdio_writeb(func, cmd->data, cmd->address, &ret);
74 data = sdio_readb(func, cmd->address, &ret);
75 cmd->data = data;
76 } else {
77 sdio_writeb(func, cmd->data, cmd->address, &ret);
78 }
79 } else { /* read */
80 data = sdio_readb(func, cmd->address, &ret);
81 cmd->data = data;
82 }
83
84 sdio_release_host(func);
85
86 if (ret)
87 dev_err(&func->dev, "%s..failed, err(%d)\n", __func__, ret);
88 return ret;
89 }
90
91 static int wilc_sdio_cmd53(struct wilc *wilc, struct sdio_cmd53 *cmd)
92 {
93 struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev);
94 int size, ret;
95
96 sdio_claim_host(func);
97
98 func->num = cmd->function;
99 func->cur_blksize = cmd->block_size;
100 if (cmd->block_mode)
101 size = cmd->count * cmd->block_size;
102 else
103 size = cmd->count;
104
105 if (cmd->read_write) { /* write */
106 ret = sdio_memcpy_toio(func, cmd->address,
107 (void *)cmd->buffer, size);
108 } else { /* read */
109 ret = sdio_memcpy_fromio(func, (void *)cmd->buffer,
110 cmd->address, size);
111 }
112
113 sdio_release_host(func);
114
115 if (ret)
116 dev_err(&func->dev, "%s..failed, err(%d)\n", __func__, ret);
117
118 return ret;
119 }
120
121 static int wilc_sdio_probe(struct sdio_func *func,
122 const struct sdio_device_id *id)
123 {
124 struct wilc *wilc;
125 int ret;
126 struct wilc_sdio *sdio_priv;
127
128 sdio_priv = kzalloc(sizeof(*sdio_priv), GFP_KERNEL);
129 if (!sdio_priv)
130 return -ENOMEM;
131
132 ret = wilc_cfg80211_init(&wilc, &func->dev, WILC_HIF_SDIO,
133 &wilc_hif_sdio);
134 if (ret) {
135 kfree(sdio_priv);
136 return ret;
137 }
138
139 if (IS_ENABLED(CONFIG_WILC1000_HW_OOB_INTR)) {
140 struct device_node *np = func->card->dev.of_node;
141 int irq_num = of_irq_get(np, 0);
142
143 if (irq_num > 0) {
144 wilc->dev_irq_num = irq_num;
145 sdio_priv->irq_gpio = true;
146 }
147 }
148
149 sdio_set_drvdata(func, wilc);
150 wilc->bus_data = sdio_priv;
151 wilc->dev = &func->dev;
152
153 wilc->rtc_clk = devm_clk_get(&func->card->dev, "rtc");
154 if (PTR_ERR_OR_ZERO(wilc->rtc_clk) == -EPROBE_DEFER)
155 return -EPROBE_DEFER;
156 else if (!IS_ERR(wilc->rtc_clk))
157 clk_prepare_enable(wilc->rtc_clk);
158
159 dev_info(&func->dev, "Driver Initializing success\n");
160 return 0;
161 }
162
163 static void wilc_sdio_remove(struct sdio_func *func)
164 {
165 struct wilc *wilc = sdio_get_drvdata(func);
166
167 if (!IS_ERR(wilc->rtc_clk))
168 clk_disable_unprepare(wilc->rtc_clk);
169
170 wilc_netdev_cleanup(wilc);
171 }
172
173 static int wilc_sdio_reset(struct wilc *wilc)
174 {
175 struct sdio_cmd52 cmd;
176 int ret;
177 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
178
179 cmd.read_write = 1;
180 cmd.function = 0;
181 cmd.raw = 0;
182 cmd.address = SDIO_CCCR_ABORT;
183 cmd.data = WILC_SDIO_CCCR_ABORT_RESET;
184 ret = wilc_sdio_cmd52(wilc, &cmd);
185 if (ret) {
186 dev_err(&func->dev, "Fail cmd 52, reset cmd ...\n");
187 return ret;
188 }
189 return 0;
190 }
191
192 static int wilc_sdio_suspend(struct device *dev)
193 {
194 struct sdio_func *func = dev_to_sdio_func(dev);
195 struct wilc *wilc = sdio_get_drvdata(func);
196 int ret;
197
198 dev_info(dev, "sdio suspend\n");
199 chip_wakeup(wilc);
200
201 if (!IS_ERR(wilc->rtc_clk))
202 clk_disable_unprepare(wilc->rtc_clk);
203
204 if (wilc->suspend_event) {
205 host_sleep_notify(wilc);
206 chip_allow_sleep(wilc);
207 }
208
209 ret = wilc_sdio_reset(wilc);
210 if (ret) {
211 dev_err(&func->dev, "Fail reset sdio\n");
212 return ret;
213 }
214 sdio_claim_host(func);
215
216 return 0;
217 }
218
219 static int wilc_sdio_enable_interrupt(struct wilc *dev)
220 {
221 struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev);
222 int ret = 0;
223
224 sdio_claim_host(func);
225 ret = sdio_claim_irq(func, wilc_sdio_interrupt);
226 sdio_release_host(func);
227
228 if (ret < 0) {
229 dev_err(&func->dev, "can't claim sdio_irq, err(%d)\n", ret);
230 ret = -EIO;
231 }
232 return ret;
233 }
234
235 static void wilc_sdio_disable_interrupt(struct wilc *dev)
236 {
237 struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev);
238 int ret;
239
240 sdio_claim_host(func);
241 ret = sdio_release_irq(func);
242 if (ret < 0)
243 dev_err(&func->dev, "can't release sdio_irq, err(%d)\n", ret);
244 sdio_release_host(func);
245 }
246
247 /********************************************
248 *
249 * Function 0
250 *
251 ********************************************/
252
253 static int wilc_sdio_set_func0_csa_address(struct wilc *wilc, u32 adr)
254 {
255 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
256 struct sdio_cmd52 cmd;
257 int ret;
258
259 /**
260 * Review: BIG ENDIAN
261 **/
262 cmd.read_write = 1;
263 cmd.function = 0;
264 cmd.raw = 0;
265 cmd.address = WILC_SDIO_FBR_CSA_REG;
266 cmd.data = (u8)adr;
267 ret = wilc_sdio_cmd52(wilc, &cmd);
268 if (ret) {
269 dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
270 cmd.address);
271 return ret;
272 }
273
274 cmd.address = WILC_SDIO_FBR_CSA_REG + 1;
275 cmd.data = (u8)(adr >> 8);
276 ret = wilc_sdio_cmd52(wilc, &cmd);
277 if (ret) {
278 dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
279 cmd.address);
280 return ret;
281 }
282
283 cmd.address = WILC_SDIO_FBR_CSA_REG + 2;
284 cmd.data = (u8)(adr >> 16);
285 ret = wilc_sdio_cmd52(wilc, &cmd);
286 if (ret) {
287 dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
288 cmd.address);
289 return ret;
290 }
291
292 return 0;
293 }
294
295 static int wilc_sdio_set_block_size(struct wilc *wilc, u8 func_num,
296 u32 block_size)
297 {
298 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
299 struct sdio_cmd52 cmd;
300 int ret;
301
302 cmd.read_write = 1;
303 cmd.function = 0;
304 cmd.raw = 0;
305 cmd.address = SDIO_FBR_BASE(func_num) + SDIO_CCCR_BLKSIZE;
306 cmd.data = (u8)block_size;
307 ret = wilc_sdio_cmd52(wilc, &cmd);
308 if (ret) {
309 dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
310 cmd.address);
311 return ret;
312 }
313
314 cmd.address = SDIO_FBR_BASE(func_num) + SDIO_CCCR_BLKSIZE + 1;
315 cmd.data = (u8)(block_size >> 8);
316 ret = wilc_sdio_cmd52(wilc, &cmd);
317 if (ret) {
318 dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
319 cmd.address);
320 return ret;
321 }
322
323 return 0;
324 }
325
326 /********************************************
327 *
328 * Sdio interfaces
329 *
330 ********************************************/
331 static int wilc_sdio_write_reg(struct wilc *wilc, u32 addr, u32 data)
332 {
333 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
334 struct wilc_sdio *sdio_priv = wilc->bus_data;
335 int ret;
336
337 cpu_to_le32s(&data);
338
339 if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */
340 struct sdio_cmd52 cmd;
341
342 cmd.read_write = 1;
343 cmd.function = 0;
344 cmd.raw = 0;
345 cmd.address = addr;
346 cmd.data = data;
347 ret = wilc_sdio_cmd52(wilc, &cmd);
348 if (ret)
349 dev_err(&func->dev,
350 "Failed cmd 52, read reg (%08x) ...\n", addr);
351 } else {
352 struct sdio_cmd53 cmd;
353
354 /**
355 * set the AHB address
356 **/
357 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
358 if (ret)
359 return ret;
360
361 cmd.read_write = 1;
362 cmd.function = 0;
363 cmd.address = WILC_SDIO_FBR_DATA_REG;
364 cmd.block_mode = 0;
365 cmd.increment = 1;
366 cmd.count = 4;
367 cmd.buffer = (u8 *)&data;
368 cmd.block_size = sdio_priv->block_size;
369 ret = wilc_sdio_cmd53(wilc, &cmd);
370 if (ret)
371 dev_err(&func->dev,
372 "Failed cmd53, write reg (%08x)...\n", addr);
373 }
374
375 return ret;
376 }
377
378 static int wilc_sdio_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
379 {
380 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
381 struct wilc_sdio *sdio_priv = wilc->bus_data;
382 u32 block_size = sdio_priv->block_size;
383 struct sdio_cmd53 cmd;
384 int nblk, nleft, ret;
385
386 cmd.read_write = 1;
387 if (addr > 0) {
388 /**
389 * func 0 access
390 **/
391 cmd.function = 0;
392 cmd.address = WILC_SDIO_FBR_DATA_REG;
393 } else {
394 /**
395 * func 1 access
396 **/
397 cmd.function = 1;
398 cmd.address = WILC_SDIO_F1_DATA_REG;
399 }
400
401 size = ALIGN(size, 4);
402 nblk = size / block_size;
403 nleft = size % block_size;
404
405 if (nblk > 0) {
406 cmd.block_mode = 1;
407 cmd.increment = 1;
408 cmd.count = nblk;
409 cmd.buffer = buf;
410 cmd.block_size = block_size;
411 if (addr > 0) {
412 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
413 if (ret)
414 return ret;
415 }
416 ret = wilc_sdio_cmd53(wilc, &cmd);
417 if (ret) {
418 dev_err(&func->dev,
419 "Failed cmd53 [%x], block send...\n", addr);
420 return ret;
421 }
422 if (addr > 0)
423 addr += nblk * block_size;
424 buf += nblk * block_size;
425 }
426
427 if (nleft > 0) {
428 cmd.block_mode = 0;
429 cmd.increment = 1;
430 cmd.count = nleft;
431 cmd.buffer = buf;
432
433 cmd.block_size = block_size;
434
435 if (addr > 0) {
436 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
437 if (ret)
438 return ret;
439 }
440 ret = wilc_sdio_cmd53(wilc, &cmd);
441 if (ret) {
442 dev_err(&func->dev,
443 "Failed cmd53 [%x], bytes send...\n", addr);
444 return ret;
445 }
446 }
447
448 return 0;
449 }
450
451 static int wilc_sdio_read_reg(struct wilc *wilc, u32 addr, u32 *data)
452 {
453 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
454 struct wilc_sdio *sdio_priv = wilc->bus_data;
455 int ret;
456
457 if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */
458 struct sdio_cmd52 cmd;
459
460 cmd.read_write = 0;
461 cmd.function = 0;
462 cmd.raw = 0;
463 cmd.address = addr;
464 ret = wilc_sdio_cmd52(wilc, &cmd);
465 if (ret) {
466 dev_err(&func->dev,
467 "Failed cmd 52, read reg (%08x) ...\n", addr);
468 return ret;
469 }
470 *data = cmd.data;
471 } else {
472 struct sdio_cmd53 cmd;
473
474 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
475 if (ret)
476 return ret;
477
478 cmd.read_write = 0;
479 cmd.function = 0;
480 cmd.address = WILC_SDIO_FBR_DATA_REG;
481 cmd.block_mode = 0;
482 cmd.increment = 1;
483 cmd.count = 4;
484 cmd.buffer = (u8 *)data;
485
486 cmd.block_size = sdio_priv->block_size;
487 ret = wilc_sdio_cmd53(wilc, &cmd);
488 if (ret) {
489 dev_err(&func->dev,
490 "Failed cmd53, read reg (%08x)...\n", addr);
491 return ret;
492 }
493 }
494
495 le32_to_cpus(data);
496 return 0;
497 }
498
499 static int wilc_sdio_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
500 {
501 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
502 struct wilc_sdio *sdio_priv = wilc->bus_data;
503 u32 block_size = sdio_priv->block_size;
504 struct sdio_cmd53 cmd;
505 int nblk, nleft, ret;
506
507 cmd.read_write = 0;
508 if (addr > 0) {
509 /**
510 * func 0 access
511 **/
512 cmd.function = 0;
513 cmd.address = WILC_SDIO_FBR_DATA_REG;
514 } else {
515 /**
516 * func 1 access
517 **/
518 cmd.function = 1;
519 cmd.address = WILC_SDIO_F1_DATA_REG;
520 }
521
522 size = ALIGN(size, 4);
523 nblk = size / block_size;
524 nleft = size % block_size;
525
526 if (nblk > 0) {
527 cmd.block_mode = 1;
528 cmd.increment = 1;
529 cmd.count = nblk;
530 cmd.buffer = buf;
531 cmd.block_size = block_size;
532 if (addr > 0) {
533 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
534 if (ret)
535 return ret;
536 }
537 ret = wilc_sdio_cmd53(wilc, &cmd);
538 if (ret) {
539 dev_err(&func->dev,
540 "Failed cmd53 [%x], block read...\n", addr);
541 return ret;
542 }
543 if (addr > 0)
544 addr += nblk * block_size;
545 buf += nblk * block_size;
546 } /* if (nblk > 0) */
547
548 if (nleft > 0) {
549 cmd.block_mode = 0;
550 cmd.increment = 1;
551 cmd.count = nleft;
552 cmd.buffer = buf;
553
554 cmd.block_size = block_size;
555
556 if (addr > 0) {
557 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
558 if (ret)
559 return ret;
560 }
561 ret = wilc_sdio_cmd53(wilc, &cmd);
562 if (ret) {
563 dev_err(&func->dev,
564 "Failed cmd53 [%x], bytes read...\n", addr);
565 return ret;
566 }
567 }
568
569 return 0;
570 }
571
572 /********************************************
573 *
574 * Bus interfaces
575 *
576 ********************************************/
577
578 static int wilc_sdio_deinit(struct wilc *wilc)
579 {
580 return 0;
581 }
582
583 static int wilc_sdio_init(struct wilc *wilc, bool resume)
584 {
585 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
586 struct wilc_sdio *sdio_priv = wilc->bus_data;
587 struct sdio_cmd52 cmd;
588 int loop, ret;
589 u32 chipid;
590
591 /**
592 * function 0 csa enable
593 **/
594 cmd.read_write = 1;
595 cmd.function = 0;
596 cmd.raw = 1;
597 cmd.address = SDIO_FBR_BASE(func->num);
598 cmd.data = SDIO_FBR_ENABLE_CSA;
599 ret = wilc_sdio_cmd52(wilc, &cmd);
600 if (ret) {
601 dev_err(&func->dev, "Fail cmd 52, enable csa...\n");
602 return ret;
603 }
604
605 /**
606 * function 0 block size
607 **/
608 ret = wilc_sdio_set_block_size(wilc, 0, WILC_SDIO_BLOCK_SIZE);
609 if (ret) {
610 dev_err(&func->dev, "Fail cmd 52, set func 0 block size...\n");
611 return ret;
612 }
613 sdio_priv->block_size = WILC_SDIO_BLOCK_SIZE;
614
615 /**
616 * enable func1 IO
617 **/
618 cmd.read_write = 1;
619 cmd.function = 0;
620 cmd.raw = 1;
621 cmd.address = SDIO_CCCR_IOEx;
622 cmd.data = WILC_SDIO_CCCR_IO_EN_FUNC1;
623 ret = wilc_sdio_cmd52(wilc, &cmd);
624 if (ret) {
625 dev_err(&func->dev,
626 "Fail cmd 52, set IOE register...\n");
627 return ret;
628 }
629
630 /**
631 * make sure func 1 is up
632 **/
633 cmd.read_write = 0;
634 cmd.function = 0;
635 cmd.raw = 0;
636 cmd.address = SDIO_CCCR_IORx;
637 loop = 3;
638 do {
639 cmd.data = 0;
640 ret = wilc_sdio_cmd52(wilc, &cmd);
641 if (ret) {
642 dev_err(&func->dev,
643 "Fail cmd 52, get IOR register...\n");
644 return ret;
645 }
646 if (cmd.data == WILC_SDIO_CCCR_IO_EN_FUNC1)
647 break;
648 } while (loop--);
649
650 if (loop <= 0) {
651 dev_err(&func->dev, "Fail func 1 is not ready...\n");
652 return -EINVAL;
653 }
654
655 /**
656 * func 1 is ready, set func 1 block size
657 **/
658 ret = wilc_sdio_set_block_size(wilc, 1, WILC_SDIO_BLOCK_SIZE);
659 if (ret) {
660 dev_err(&func->dev, "Fail set func 1 block size...\n");
661 return ret;
662 }
663
664 /**
665 * func 1 interrupt enable
666 **/
667 cmd.read_write = 1;
668 cmd.function = 0;
669 cmd.raw = 1;
670 cmd.address = SDIO_CCCR_IENx;
671 cmd.data = WILC_SDIO_CCCR_IEN_MASTER | WILC_SDIO_CCCR_IEN_FUNC1;
672 ret = wilc_sdio_cmd52(wilc, &cmd);
673 if (ret) {
674 dev_err(&func->dev, "Fail cmd 52, set IEN register...\n");
675 return ret;
676 }
677
678 /**
679 * make sure can read back chip id correctly
680 **/
681 if (!resume) {
682 int rev;
683
684 ret = wilc_sdio_read_reg(wilc, WILC_CHIPID, &chipid);
685 if (ret) {
686 dev_err(&func->dev, "Fail cmd read chip id...\n");
687 return ret;
688 }
689 dev_err(&func->dev, "chipid (%08x)\n", chipid);
690 rev = FIELD_GET(WILC_CHIP_REV_FIELD, chipid);
691 if (rev > FIELD_GET(WILC_CHIP_REV_FIELD, WILC_1000_BASE_ID_2A))
692 sdio_priv->has_thrpt_enh3 = 1;
693 else
694 sdio_priv->has_thrpt_enh3 = 0;
695 dev_info(&func->dev, "has_thrpt_enh3 = %d...\n",
696 sdio_priv->has_thrpt_enh3);
697 }
698
699 return 0;
700 }
701
702 static int wilc_sdio_read_size(struct wilc *wilc, u32 *size)
703 {
704 u32 tmp;
705 struct sdio_cmd52 cmd;
706
707 /**
708 * Read DMA count in words
709 **/
710 cmd.read_write = 0;
711 cmd.function = 0;
712 cmd.raw = 0;
713 cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG;
714 cmd.data = 0;
715 wilc_sdio_cmd52(wilc, &cmd);
716 tmp = cmd.data;
717
718 cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG + 1;
719 cmd.data = 0;
720 wilc_sdio_cmd52(wilc, &cmd);
721 tmp |= (cmd.data << 8);
722
723 *size = tmp;
724 return 0;
725 }
726
727 static int wilc_sdio_read_int(struct wilc *wilc, u32 *int_status)
728 {
729 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
730 struct wilc_sdio *sdio_priv = wilc->bus_data;
731 u32 tmp;
732 u8 irq_flags;
733 struct sdio_cmd52 cmd;
734
735 wilc_sdio_read_size(wilc, &tmp);
736
737 /**
738 * Read IRQ flags
739 **/
740 if (!sdio_priv->irq_gpio) {
741 cmd.function = 1;
742 cmd.address = WILC_SDIO_EXT_IRQ_FLAG_REG;
743 } else {
744 cmd.function = 0;
745 cmd.address = WILC_SDIO_IRQ_FLAG_REG;
746 }
747 cmd.raw = 0;
748 cmd.read_write = 0;
749 cmd.data = 0;
750 wilc_sdio_cmd52(wilc, &cmd);
751 irq_flags = cmd.data;
752 tmp |= FIELD_PREP(IRG_FLAGS_MASK, cmd.data);
753
754 if (FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags))
755 dev_err(&func->dev, "Unexpected interrupt (1) int=%lx\n",
756 FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags));
757
758 *int_status = tmp;
759
760 return 0;
761 }
762
763 static int wilc_sdio_clear_int_ext(struct wilc *wilc, u32 val)
764 {
765 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
766 struct wilc_sdio *sdio_priv = wilc->bus_data;
767 int ret;
768 int vmm_ctl;
769
770 if (sdio_priv->has_thrpt_enh3) {
771 u32 reg = 0;
772
773 if (sdio_priv->irq_gpio)
774 reg = val & (BIT(MAX_NUM_INT) - 1);
775
776 /* select VMM table 0 */
777 if (val & SEL_VMM_TBL0)
778 reg |= BIT(5);
779 /* select VMM table 1 */
780 if (val & SEL_VMM_TBL1)
781 reg |= BIT(6);
782 /* enable VMM */
783 if (val & EN_VMM)
784 reg |= BIT(7);
785 if (reg) {
786 struct sdio_cmd52 cmd;
787
788 cmd.read_write = 1;
789 cmd.function = 0;
790 cmd.raw = 0;
791 cmd.address = WILC_SDIO_IRQ_CLEAR_FLAG_REG;
792 cmd.data = reg;
793
794 ret = wilc_sdio_cmd52(wilc, &cmd);
795 if (ret) {
796 dev_err(&func->dev,
797 "Failed cmd52, set (%02x) data (%d) ...\n",
798 cmd.address, __LINE__);
799 return ret;
800 }
801 }
802 return 0;
803 }
804 if (sdio_priv->irq_gpio) {
805 /* has_thrpt_enh2 uses register 0xf8 to clear interrupts. */
806 /*
807 * Cannot clear multiple interrupts.
808 * Must clear each interrupt individually.
809 */
810 u32 flags;
811 int i;
812
813 flags = val & (BIT(MAX_NUM_INT) - 1);
814 for (i = 0; i < NUM_INT_EXT && flags; i++) {
815 if (flags & BIT(i)) {
816 struct sdio_cmd52 cmd;
817
818 cmd.read_write = 1;
819 cmd.function = 0;
820 cmd.raw = 0;
821 cmd.address = WILC_SDIO_IRQ_CLEAR_FLAG_REG;
822 cmd.data = BIT(i);
823
824 ret = wilc_sdio_cmd52(wilc, &cmd);
825 if (ret) {
826 dev_err(&func->dev,
827 "Failed cmd52, set (%02x) data (%d) ...\n",
828 cmd.address, __LINE__);
829 return ret;
830 }
831 flags &= ~BIT(i);
832 }
833 }
834
835 for (i = NUM_INT_EXT; i < MAX_NUM_INT && flags; i++) {
836 if (flags & BIT(i)) {
837 dev_err(&func->dev,
838 "Unexpected interrupt cleared %d...\n",
839 i);
840 flags &= ~BIT(i);
841 }
842 }
843 }
844
845 vmm_ctl = 0;
846 /* select VMM table 0 */
847 if (val & SEL_VMM_TBL0)
848 vmm_ctl |= BIT(0);
849 /* select VMM table 1 */
850 if (val & SEL_VMM_TBL1)
851 vmm_ctl |= BIT(1);
852 /* enable VMM */
853 if (val & EN_VMM)
854 vmm_ctl |= BIT(2);
855
856 if (vmm_ctl) {
857 struct sdio_cmd52 cmd;
858
859 cmd.read_write = 1;
860 cmd.function = 0;
861 cmd.raw = 0;
862 cmd.address = WILC_SDIO_VMM_TBL_CTRL_REG;
863 cmd.data = vmm_ctl;
864 ret = wilc_sdio_cmd52(wilc, &cmd);
865 if (ret) {
866 dev_err(&func->dev,
867 "Failed cmd52, set (%02x) data (%d) ...\n",
868 cmd.address, __LINE__);
869 return ret;
870 }
871 }
872 return 0;
873 }
874
875 static int wilc_sdio_sync_ext(struct wilc *wilc, int nint)
876 {
877 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
878 struct wilc_sdio *sdio_priv = wilc->bus_data;
879 u32 reg;
880
881 if (nint > MAX_NUM_INT) {
882 dev_err(&func->dev, "Too many interrupts (%d)...\n", nint);
883 return -EINVAL;
884 }
885
886 /**
887 * Disable power sequencer
888 **/
889 if (wilc_sdio_read_reg(wilc, WILC_MISC, &reg)) {
890 dev_err(&func->dev, "Failed read misc reg...\n");
891 return -EINVAL;
892 }
893
894 reg &= ~BIT(8);
895 if (wilc_sdio_write_reg(wilc, WILC_MISC, reg)) {
896 dev_err(&func->dev, "Failed write misc reg...\n");
897 return -EINVAL;
898 }
899
900 if (sdio_priv->irq_gpio) {
901 u32 reg;
902 int ret, i;
903
904 /**
905 * interrupt pin mux select
906 **/
907 ret = wilc_sdio_read_reg(wilc, WILC_PIN_MUX_0, &reg);
908 if (ret) {
909 dev_err(&func->dev, "Failed read reg (%08x)...\n",
910 WILC_PIN_MUX_0);
911 return ret;
912 }
913 reg |= BIT(8);
914 ret = wilc_sdio_write_reg(wilc, WILC_PIN_MUX_0, reg);
915 if (ret) {
916 dev_err(&func->dev, "Failed write reg (%08x)...\n",
917 WILC_PIN_MUX_0);
918 return ret;
919 }
920
921 /**
922 * interrupt enable
923 **/
924 ret = wilc_sdio_read_reg(wilc, WILC_INTR_ENABLE, &reg);
925 if (ret) {
926 dev_err(&func->dev, "Failed read reg (%08x)...\n",
927 WILC_INTR_ENABLE);
928 return ret;
929 }
930
931 for (i = 0; (i < 5) && (nint > 0); i++, nint--)
932 reg |= BIT((27 + i));
933 ret = wilc_sdio_write_reg(wilc, WILC_INTR_ENABLE, reg);
934 if (ret) {
935 dev_err(&func->dev, "Failed write reg (%08x)...\n",
936 WILC_INTR_ENABLE);
937 return ret;
938 }
939 if (nint) {
940 ret = wilc_sdio_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
941 if (ret) {
942 dev_err(&func->dev,
943 "Failed read reg (%08x)...\n",
944 WILC_INTR2_ENABLE);
945 return ret;
946 }
947
948 for (i = 0; (i < 3) && (nint > 0); i++, nint--)
949 reg |= BIT(i);
950
951 ret = wilc_sdio_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
952 if (ret) {
953 dev_err(&func->dev,
954 "Failed write reg (%08x)...\n",
955 WILC_INTR2_ENABLE);
956 return ret;
957 }
958 }
959 }
960 return 0;
961 }
962
963 /* Global sdio HIF function table */
964 static const struct wilc_hif_func wilc_hif_sdio = {
965 .hif_init = wilc_sdio_init,
966 .hif_deinit = wilc_sdio_deinit,
967 .hif_read_reg = wilc_sdio_read_reg,
968 .hif_write_reg = wilc_sdio_write_reg,
969 .hif_block_rx = wilc_sdio_read,
970 .hif_block_tx = wilc_sdio_write,
971 .hif_read_int = wilc_sdio_read_int,
972 .hif_clear_int_ext = wilc_sdio_clear_int_ext,
973 .hif_read_size = wilc_sdio_read_size,
974 .hif_block_tx_ext = wilc_sdio_write,
975 .hif_block_rx_ext = wilc_sdio_read,
976 .hif_sync_ext = wilc_sdio_sync_ext,
977 .enable_interrupt = wilc_sdio_enable_interrupt,
978 .disable_interrupt = wilc_sdio_disable_interrupt,
979 };
980
981 static int wilc_sdio_resume(struct device *dev)
982 {
983 struct sdio_func *func = dev_to_sdio_func(dev);
984 struct wilc *wilc = sdio_get_drvdata(func);
985
986 dev_info(dev, "sdio resume\n");
987 sdio_release_host(func);
988 chip_wakeup(wilc);
989 wilc_sdio_init(wilc, true);
990
991 if (wilc->suspend_event)
992 host_wakeup_notify(wilc);
993
994 chip_allow_sleep(wilc);
995
996 return 0;
997 }
998
999 static const struct of_device_id wilc_of_match[] = {
1000 { .compatible = "microchip,wilc1000", },
1001 { /* sentinel */ }
1002 };
1003 MODULE_DEVICE_TABLE(of, wilc_of_match);
1004
1005 static const struct dev_pm_ops wilc_sdio_pm_ops = {
1006 .suspend = wilc_sdio_suspend,
1007 .resume = wilc_sdio_resume,
1008 };
1009
1010 static struct sdio_driver wilc_sdio_driver = {
1011 .name = SDIO_MODALIAS,
1012 .id_table = wilc_sdio_ids,
1013 .probe = wilc_sdio_probe,
1014 .remove = wilc_sdio_remove,
1015 .drv = {
1016 .pm = &wilc_sdio_pm_ops,
1017 .of_match_table = wilc_of_match,
1018 }
1019 };
1020 module_driver(wilc_sdio_driver,
1021 sdio_register_driver,
1022 sdio_unregister_driver);
1023 MODULE_LICENSE("GPL");
Linux with added FPC-III support