1 // SPDX-License-Identifier: GPL-2.0
3 * Thunderbolt link controller support
5 * Copyright (C) 2019, Intel Corporation
6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
12 * tb_lc_read_uuid() - Read switch UUID from link controller common register
13 * @sw: Switch whose UUID is read
14 * @uuid: UUID is placed here
16 int tb_lc_read_uuid(struct tb_switch
*sw
, u32
*uuid
)
20 return tb_sw_read(sw
, uuid
, TB_CFG_SWITCH
, sw
->cap_lc
+ TB_LC_FUSE
, 4);
23 static int read_lc_desc(struct tb_switch
*sw
, u32
*desc
)
27 return tb_sw_read(sw
, desc
, TB_CFG_SWITCH
, sw
->cap_lc
+ TB_LC_DESC
, 1);
30 static int find_port_lc_cap(struct tb_port
*port
)
32 struct tb_switch
*sw
= port
->sw
;
33 int start
, phys
, ret
, size
;
36 ret
= read_lc_desc(sw
, &desc
);
40 /* Start of port LC registers */
41 start
= (desc
& TB_LC_DESC_SIZE_MASK
) >> TB_LC_DESC_SIZE_SHIFT
;
42 size
= (desc
& TB_LC_DESC_PORT_SIZE_MASK
) >> TB_LC_DESC_PORT_SIZE_SHIFT
;
43 phys
= tb_phy_port_from_link(port
->port
);
45 return sw
->cap_lc
+ start
+ phys
* size
;
48 static int tb_lc_configure_lane(struct tb_port
*port
, bool configure
)
50 bool upstream
= tb_is_upstream_port(port
);
51 struct tb_switch
*sw
= port
->sw
;
55 if (sw
->generation
< 2)
58 cap
= find_port_lc_cap(port
);
62 ret
= tb_sw_read(sw
, &ctrl
, TB_CFG_SWITCH
, cap
+ TB_LC_SX_CTRL
, 1);
66 /* Resolve correct lane */
68 lane
= TB_LC_SX_CTRL_L1C
;
70 lane
= TB_LC_SX_CTRL_L2C
;
75 ctrl
|= TB_LC_SX_CTRL_UPSTREAM
;
79 ctrl
&= ~TB_LC_SX_CTRL_UPSTREAM
;
82 return tb_sw_write(sw
, &ctrl
, TB_CFG_SWITCH
, cap
+ TB_LC_SX_CTRL
, 1);
86 * tb_lc_configure_link() - Let LC know about configured link
87 * @sw: Switch that is being added
89 * Informs LC of both parent switch and @sw that there is established
90 * link between the two.
92 int tb_lc_configure_link(struct tb_switch
*sw
)
94 struct tb_port
*up
, *down
;
97 if (!tb_route(sw
) || tb_switch_is_icm(sw
))
100 up
= tb_upstream_port(sw
);
101 down
= tb_port_at(tb_route(sw
), tb_to_switch(sw
->dev
.parent
));
103 /* Configure parent link toward this switch */
104 ret
= tb_lc_configure_lane(down
, true);
108 /* Configure upstream link from this switch to the parent */
109 ret
= tb_lc_configure_lane(up
, true);
111 tb_lc_configure_lane(down
, false);
117 * tb_lc_unconfigure_link() - Let LC know about unconfigured link
118 * @sw: Switch to unconfigure
120 * Informs LC of both parent switch and @sw that the link between the
121 * two does not exist anymore.
123 void tb_lc_unconfigure_link(struct tb_switch
*sw
)
125 struct tb_port
*up
, *down
;
127 if (sw
->is_unplugged
|| !tb_route(sw
) || tb_switch_is_icm(sw
))
130 up
= tb_upstream_port(sw
);
131 down
= tb_port_at(tb_route(sw
), tb_to_switch(sw
->dev
.parent
));
133 tb_lc_configure_lane(up
, false);
134 tb_lc_configure_lane(down
, false);
138 * tb_lc_set_sleep() - Inform LC that the switch is going to sleep
139 * @sw: Switch to set sleep
141 * Let the switch link controllers know that the switch is going to
144 int tb_lc_set_sleep(struct tb_switch
*sw
)
146 int start
, size
, nlc
, ret
, i
;
149 if (sw
->generation
< 2)
152 ret
= read_lc_desc(sw
, &desc
);
156 /* Figure out number of link controllers */
157 nlc
= desc
& TB_LC_DESC_NLC_MASK
;
158 start
= (desc
& TB_LC_DESC_SIZE_MASK
) >> TB_LC_DESC_SIZE_SHIFT
;
159 size
= (desc
& TB_LC_DESC_PORT_SIZE_MASK
) >> TB_LC_DESC_PORT_SIZE_SHIFT
;
161 /* For each link controller set sleep bit */
162 for (i
= 0; i
< nlc
; i
++) {
163 unsigned int offset
= sw
->cap_lc
+ start
+ i
* size
;
166 ret
= tb_sw_read(sw
, &ctrl
, TB_CFG_SWITCH
,
167 offset
+ TB_LC_SX_CTRL
, 1);
171 ctrl
|= TB_LC_SX_CTRL_SLP
;
172 ret
= tb_sw_write(sw
, &ctrl
, TB_CFG_SWITCH
,
173 offset
+ TB_LC_SX_CTRL
, 1);
182 * tb_lc_lane_bonding_possible() - Is lane bonding possible towards switch
183 * @sw: Switch to check
185 * Checks whether conditions for lane bonding from parent to @sw are
188 bool tb_lc_lane_bonding_possible(struct tb_switch
*sw
)
194 if (sw
->generation
< 2)
197 up
= tb_upstream_port(sw
);
198 cap
= find_port_lc_cap(up
);
202 ret
= tb_sw_read(sw
, &val
, TB_CFG_SWITCH
, cap
+ TB_LC_PORT_ATTR
, 1);
206 return !!(val
& TB_LC_PORT_ATTR_BE
);
209 static int tb_lc_dp_sink_from_port(const struct tb_switch
*sw
,
212 struct tb_port
*port
;
214 /* The first DP IN port is sink 0 and second is sink 1 */
215 tb_switch_for_each_port(sw
, port
) {
216 if (tb_port_is_dpin(port
))
223 static int tb_lc_dp_sink_available(struct tb_switch
*sw
, int sink
)
228 ret
= tb_sw_read(sw
, &val
, TB_CFG_SWITCH
,
229 sw
->cap_lc
+ TB_LC_SNK_ALLOCATION
, 1);
234 * Sink is available for CM/SW to use if the allocation valie is
238 alloc
= val
& TB_LC_SNK_ALLOCATION_SNK0_MASK
;
239 if (!alloc
|| alloc
== TB_LC_SNK_ALLOCATION_SNK0_CM
)
242 alloc
= (val
& TB_LC_SNK_ALLOCATION_SNK1_MASK
) >>
243 TB_LC_SNK_ALLOCATION_SNK1_SHIFT
;
244 if (!alloc
|| alloc
== TB_LC_SNK_ALLOCATION_SNK1_CM
)
252 * tb_lc_dp_sink_query() - Is DP sink available for DP IN port
253 * @sw: Switch whose DP sink is queried
254 * @in: DP IN port to check
256 * Queries through LC SNK_ALLOCATION registers whether DP sink is available
257 * for the given DP IN port or not.
259 bool tb_lc_dp_sink_query(struct tb_switch
*sw
, struct tb_port
*in
)
264 * For older generations sink is always available as there is no
265 * allocation mechanism.
267 if (sw
->generation
< 3)
270 sink
= tb_lc_dp_sink_from_port(sw
, in
);
274 return !tb_lc_dp_sink_available(sw
, sink
);
278 * tb_lc_dp_sink_alloc() - Allocate DP sink
279 * @sw: Switch whose DP sink is allocated
280 * @in: DP IN port the DP sink is allocated for
282 * Allocate DP sink for @in via LC SNK_ALLOCATION registers. If the
283 * resource is available and allocation is successful returns %0. In all
284 * other cases returs negative errno. In particular %-EBUSY is returned if
285 * the resource was not available.
287 int tb_lc_dp_sink_alloc(struct tb_switch
*sw
, struct tb_port
*in
)
292 if (sw
->generation
< 3)
295 sink
= tb_lc_dp_sink_from_port(sw
, in
);
299 ret
= tb_lc_dp_sink_available(sw
, sink
);
303 ret
= tb_sw_read(sw
, &val
, TB_CFG_SWITCH
,
304 sw
->cap_lc
+ TB_LC_SNK_ALLOCATION
, 1);
309 val
&= ~TB_LC_SNK_ALLOCATION_SNK0_MASK
;
310 val
|= TB_LC_SNK_ALLOCATION_SNK0_CM
;
312 val
&= ~TB_LC_SNK_ALLOCATION_SNK1_MASK
;
313 val
|= TB_LC_SNK_ALLOCATION_SNK1_CM
<<
314 TB_LC_SNK_ALLOCATION_SNK1_SHIFT
;
317 ret
= tb_sw_write(sw
, &val
, TB_CFG_SWITCH
,
318 sw
->cap_lc
+ TB_LC_SNK_ALLOCATION
, 1);
323 tb_port_dbg(in
, "sink %d allocated\n", sink
);
328 * tb_lc_dp_sink_dealloc() - De-allocate DP sink
329 * @sw: Switch whose DP sink is de-allocated
330 * @in: DP IN port whose DP sink is de-allocated
332 * De-allocate DP sink from @in using LC SNK_ALLOCATION registers.
334 int tb_lc_dp_sink_dealloc(struct tb_switch
*sw
, struct tb_port
*in
)
339 if (sw
->generation
< 3)
342 sink
= tb_lc_dp_sink_from_port(sw
, in
);
346 /* Needs to be owned by CM/SW */
347 ret
= tb_lc_dp_sink_available(sw
, sink
);
351 ret
= tb_sw_read(sw
, &val
, TB_CFG_SWITCH
,
352 sw
->cap_lc
+ TB_LC_SNK_ALLOCATION
, 1);
357 val
&= ~TB_LC_SNK_ALLOCATION_SNK0_MASK
;
359 val
&= ~TB_LC_SNK_ALLOCATION_SNK1_MASK
;
361 ret
= tb_sw_write(sw
, &val
, TB_CFG_SWITCH
,
362 sw
->cap_lc
+ TB_LC_SNK_ALLOCATION
, 1);
366 tb_port_dbg(in
, "sink %d de-allocated\n", sink
);