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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / video / fbdev / amba-clcd.c
blobc3d55fc6c4e0354559ab6dab0bb128e541d4251d
1 /*
2 * linux/drivers/video/amba-clcd.c
3 *
4 * Copyright (C) 2001 ARM Limited, by David A Rusling
5 * Updated to 2.5, Deep Blue Solutions Ltd.
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive
9 * for more details.
10 *
11 * ARM PrimeCell PL110 Color LCD Controller
12 */
13 #include <linux/amba/bus.h>
14 #include <linux/amba/clcd.h>
15 #include <linux/backlight.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/fb.h>
20 #include <linux/init.h>
21 #include <linux/ioport.h>
22 #include <linux/list.h>
23 #include <linux/mm.h>
24 #include <linux/module.h>
25 #include <linux/of_address.h>
26 #include <linux/of_graph.h>
27 #include <linux/slab.h>
28 #include <linux/string.h>
29 #include <video/display_timing.h>
30 #include <video/of_display_timing.h>
31 #include <video/videomode.h>
32
33 #define to_clcd(info) container_of(info, struct clcd_fb, fb)
34
35 /* This is limited to 16 characters when displayed by X startup */
36 static const char *clcd_name = "CLCD FB";
37
38 /*
39 * Unfortunately, the enable/disable functions may be called either from
40 * process or IRQ context, and we _need_ to delay. This is _not_ good.
41 */
42 static inline void clcdfb_sleep(unsigned int ms)
43 {
44 if (in_atomic()) {
45 mdelay(ms);
46 } else {
47 msleep(ms);
48 }
49 }
50
51 static inline void clcdfb_set_start(struct clcd_fb *fb)
52 {
53 unsigned long ustart = fb->fb.fix.smem_start;
54 unsigned long lstart;
55
56 ustart += fb->fb.var.yoffset * fb->fb.fix.line_length;
57 lstart = ustart + fb->fb.var.yres * fb->fb.fix.line_length / 2;
58
59 writel(ustart, fb->regs + CLCD_UBAS);
60 writel(lstart, fb->regs + CLCD_LBAS);
61 }
62
63 static void clcdfb_disable(struct clcd_fb *fb)
64 {
65 u32 val;
66
67 if (fb->board->disable)
68 fb->board->disable(fb);
69
70 if (fb->panel->backlight) {
71 fb->panel->backlight->props.power = FB_BLANK_POWERDOWN;
72 backlight_update_status(fb->panel->backlight);
73 }
74
75 val = readl(fb->regs + fb->off_cntl);
76 if (val & CNTL_LCDPWR) {
77 val &= ~CNTL_LCDPWR;
78 writel(val, fb->regs + fb->off_cntl);
79
80 clcdfb_sleep(20);
81 }
82 if (val & CNTL_LCDEN) {
83 val &= ~CNTL_LCDEN;
84 writel(val, fb->regs + fb->off_cntl);
85 }
86
87 /*
88 * Disable CLCD clock source.
89 */
90 if (fb->clk_enabled) {
91 fb->clk_enabled = false;
92 clk_disable(fb->clk);
93 }
94 }
95
96 static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
97 {
98 /*
99 * Enable the CLCD clock source.
100 */
101 if (!fb->clk_enabled) {
102 fb->clk_enabled = true;
103 clk_enable(fb->clk);
104 }
105
106 /*
107 * Bring up by first enabling..
108 */
109 cntl |= CNTL_LCDEN;
110 writel(cntl, fb->regs + fb->off_cntl);
111
112 clcdfb_sleep(20);
113
114 /*
115 * and now apply power.
116 */
117 cntl |= CNTL_LCDPWR;
118 writel(cntl, fb->regs + fb->off_cntl);
119
120 /*
121 * Turn on backlight
122 */
123 if (fb->panel->backlight) {
124 fb->panel->backlight->props.power = FB_BLANK_UNBLANK;
125 backlight_update_status(fb->panel->backlight);
126 }
127
128 /*
129 * finally, enable the interface.
130 */
131 if (fb->board->enable)
132 fb->board->enable(fb);
133 }
134
135 static int
136 clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var)
137 {
138 u32 caps;
139 int ret = 0;
140
141 if (fb->panel->caps && fb->board->caps)
142 caps = fb->panel->caps & fb->board->caps;
143 else {
144 /* Old way of specifying what can be used */
145 caps = fb->panel->cntl & CNTL_BGR ?
146 CLCD_CAP_BGR : CLCD_CAP_RGB;
147 /* But mask out 444 modes as they weren't supported */
148 caps &= ~CLCD_CAP_444;
149 }
150
151 /* Only TFT panels can do RGB888/BGR888 */
152 if (!(fb->panel->cntl & CNTL_LCDTFT))
153 caps &= ~CLCD_CAP_888;
154
155 memset(&var->transp, 0, sizeof(var->transp));
156
157 var->red.msb_right = 0;
158 var->green.msb_right = 0;
159 var->blue.msb_right = 0;
160
161 switch (var->bits_per_pixel) {
162 case 1:
163 case 2:
164 case 4:
165 case 8:
166 /* If we can't do 5551, reject */
167 caps &= CLCD_CAP_5551;
168 if (!caps) {
169 ret = -EINVAL;
170 break;
171 }
172
173 var->red.length = var->bits_per_pixel;
174 var->red.offset = 0;
175 var->green.length = var->bits_per_pixel;
176 var->green.offset = 0;
177 var->blue.length = var->bits_per_pixel;
178 var->blue.offset = 0;
179 break;
180
181 case 16:
182 /* If we can't do 444, 5551 or 565, reject */
183 if (!(caps & (CLCD_CAP_444 | CLCD_CAP_5551 | CLCD_CAP_565))) {
184 ret = -EINVAL;
185 break;
186 }
187
188 /*
189 * Green length can be 4, 5 or 6 depending whether
190 * we're operating in 444, 5551 or 565 mode.
191 */
192 if (var->green.length == 4 && caps & CLCD_CAP_444)
193 caps &= CLCD_CAP_444;
194 if (var->green.length == 5 && caps & CLCD_CAP_5551)
195 caps &= CLCD_CAP_5551;
196 else if (var->green.length == 6 && caps & CLCD_CAP_565)
197 caps &= CLCD_CAP_565;
198 else {
199 /*
200 * PL110 officially only supports RGB555,
201 * but may be wired up to allow RGB565.
202 */
203 if (caps & CLCD_CAP_565) {
204 var->green.length = 6;
205 caps &= CLCD_CAP_565;
206 } else if (caps & CLCD_CAP_5551) {
207 var->green.length = 5;
208 caps &= CLCD_CAP_5551;
209 } else {
210 var->green.length = 4;
211 caps &= CLCD_CAP_444;
212 }
213 }
214
215 if (var->green.length >= 5) {
216 var->red.length = 5;
217 var->blue.length = 5;
218 } else {
219 var->red.length = 4;
220 var->blue.length = 4;
221 }
222 break;
223 case 32:
224 /* If we can't do 888, reject */
225 caps &= CLCD_CAP_888;
226 if (!caps) {
227 ret = -EINVAL;
228 break;
229 }
230
231 var->red.length = 8;
232 var->green.length = 8;
233 var->blue.length = 8;
234 break;
235 default:
236 ret = -EINVAL;
237 break;
238 }
239
240 /*
241 * >= 16bpp displays have separate colour component bitfields
242 * encoded in the pixel data. Calculate their position from
243 * the bitfield length defined above.
244 */
245 if (ret == 0 && var->bits_per_pixel >= 16) {
246 bool bgr, rgb;
247
248 bgr = caps & CLCD_CAP_BGR && var->blue.offset == 0;
249 rgb = caps & CLCD_CAP_RGB && var->red.offset == 0;
250
251 if (!bgr && !rgb)
252 /*
253 * The requested format was not possible, try just
254 * our capabilities. One of BGR or RGB must be
255 * supported.
256 */
257 bgr = caps & CLCD_CAP_BGR;
258
259 if (bgr) {
260 var->blue.offset = 0;
261 var->green.offset = var->blue.offset + var->blue.length;
262 var->red.offset = var->green.offset + var->green.length;
263 } else {
264 var->red.offset = 0;
265 var->green.offset = var->red.offset + var->red.length;
266 var->blue.offset = var->green.offset + var->green.length;
267 }
268 }
269
270 return ret;
271 }
272
273 static int clcdfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
274 {
275 struct clcd_fb *fb = to_clcd(info);
276 int ret = -EINVAL;
277
278 if (fb->board->check)
279 ret = fb->board->check(fb, var);
280
281 if (ret == 0 &&
282 var->xres_virtual * var->bits_per_pixel / 8 *
283 var->yres_virtual > fb->fb.fix.smem_len)
284 ret = -EINVAL;
285
286 if (ret == 0)
287 ret = clcdfb_set_bitfields(fb, var);
288
289 return ret;
290 }
291
292 static int clcdfb_set_par(struct fb_info *info)
293 {
294 struct clcd_fb *fb = to_clcd(info);
295 struct clcd_regs regs;
296
297 fb->fb.fix.line_length = fb->fb.var.xres_virtual *
298 fb->fb.var.bits_per_pixel / 8;
299
300 if (fb->fb.var.bits_per_pixel <= 8)
301 fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
302 else
303 fb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
304
305 fb->board->decode(fb, &regs);
306
307 clcdfb_disable(fb);
308
309 writel(regs.tim0, fb->regs + CLCD_TIM0);
310 writel(regs.tim1, fb->regs + CLCD_TIM1);
311 writel(regs.tim2, fb->regs + CLCD_TIM2);
312 writel(regs.tim3, fb->regs + CLCD_TIM3);
313
314 clcdfb_set_start(fb);
315
316 clk_set_rate(fb->clk, (1000000000 / regs.pixclock) * 1000);
317
318 fb->clcd_cntl = regs.cntl;
319
320 clcdfb_enable(fb, regs.cntl);
321
322 #ifdef DEBUG
323 printk(KERN_INFO
324 "CLCD: Registers set to\n"
325 " %08x %08x %08x %08x\n"
326 " %08x %08x %08x %08x\n",
327 readl(fb->regs + CLCD_TIM0), readl(fb->regs + CLCD_TIM1),
328 readl(fb->regs + CLCD_TIM2), readl(fb->regs + CLCD_TIM3),
329 readl(fb->regs + CLCD_UBAS), readl(fb->regs + CLCD_LBAS),
330 readl(fb->regs + fb->off_ienb), readl(fb->regs + fb->off_cntl));
331 #endif
332
333 return 0;
334 }
335
336 static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)
337 {
338 unsigned int mask = (1 << bf->length) - 1;
339
340 return (val >> (16 - bf->length) & mask) << bf->offset;
341 }
342
343 /*
344 * Set a single color register. The values supplied have a 16 bit
345 * magnitude. Return != 0 for invalid regno.
346 */
347 static int
348 clcdfb_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
349 unsigned int blue, unsigned int transp, struct fb_info *info)
350 {
351 struct clcd_fb *fb = to_clcd(info);
352
353 if (regno < 16)
354 fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |
355 convert_bitfield(blue, &fb->fb.var.blue) |
356 convert_bitfield(green, &fb->fb.var.green) |
357 convert_bitfield(red, &fb->fb.var.red);
358
359 if (fb->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) {
360 int hw_reg = CLCD_PALETTE + ((regno * 2) & ~3);
361 u32 val, mask, newval;
362
363 newval = (red >> 11) & 0x001f;
364 newval |= (green >> 6) & 0x03e0;
365 newval |= (blue >> 1) & 0x7c00;
366
367 /*
368 * 3.2.11: if we're configured for big endian
369 * byte order, the palette entries are swapped.
370 */
371 if (fb->clcd_cntl & CNTL_BEBO)
372 regno ^= 1;
373
374 if (regno & 1) {
375 newval <<= 16;
376 mask = 0x0000ffff;
377 } else {
378 mask = 0xffff0000;
379 }
380
381 val = readl(fb->regs + hw_reg) & mask;
382 writel(val | newval, fb->regs + hw_reg);
383 }
384
385 return regno > 255;
386 }
387
388 /*
389 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
390 * then the caller blanks by setting the CLUT (Color Look Up Table) to all
391 * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
392 * to e.g. a video mode which doesn't support it. Implements VESA suspend
393 * and powerdown modes on hardware that supports disabling hsync/vsync:
394 * blank_mode == 2: suspend vsync
395 * blank_mode == 3: suspend hsync
396 * blank_mode == 4: powerdown
397 */
398 static int clcdfb_blank(int blank_mode, struct fb_info *info)
399 {
400 struct clcd_fb *fb = to_clcd(info);
401
402 if (blank_mode != 0) {
403 clcdfb_disable(fb);
404 } else {
405 clcdfb_enable(fb, fb->clcd_cntl);
406 }
407 return 0;
408 }
409
410 static int clcdfb_mmap(struct fb_info *info,
411 struct vm_area_struct *vma)
412 {
413 struct clcd_fb *fb = to_clcd(info);
414 unsigned long len, off = vma->vm_pgoff << PAGE_SHIFT;
415 int ret = -EINVAL;
416
417 len = info->fix.smem_len;
418
419 if (off <= len && vma->vm_end - vma->vm_start <= len - off &&
420 fb->board->mmap)
421 ret = fb->board->mmap(fb, vma);
422
423 return ret;
424 }
425
426 static const struct fb_ops clcdfb_ops = {
427 .owner = THIS_MODULE,
428 .fb_check_var = clcdfb_check_var,
429 .fb_set_par = clcdfb_set_par,
430 .fb_setcolreg = clcdfb_setcolreg,
431 .fb_blank = clcdfb_blank,
432 .fb_fillrect = cfb_fillrect,
433 .fb_copyarea = cfb_copyarea,
434 .fb_imageblit = cfb_imageblit,
435 .fb_mmap = clcdfb_mmap,
436 };
437
438 static int clcdfb_register(struct clcd_fb *fb)
439 {
440 int ret;
441
442 /*
443 * ARM PL111 always has IENB at 0x1c; it's only PL110
444 * which is reversed on some platforms.
445 */
446 if (amba_manf(fb->dev) == 0x41 && amba_part(fb->dev) == 0x111) {
447 fb->off_ienb = CLCD_PL111_IENB;
448 fb->off_cntl = CLCD_PL111_CNTL;
449 } else {
450 fb->off_ienb = CLCD_PL110_IENB;
451 fb->off_cntl = CLCD_PL110_CNTL;
452 }
453
454 fb->clk = clk_get(&fb->dev->dev, NULL);
455 if (IS_ERR(fb->clk)) {
456 ret = PTR_ERR(fb->clk);
457 goto out;
458 }
459
460 ret = clk_prepare(fb->clk);
461 if (ret)
462 goto free_clk;
463
464 fb->fb.device = &fb->dev->dev;
465
466 fb->fb.fix.mmio_start = fb->dev->res.start;
467 fb->fb.fix.mmio_len = resource_size(&fb->dev->res);
468
469 fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len);
470 if (!fb->regs) {
471 printk(KERN_ERR "CLCD: unable to remap registers\n");
472 ret = -ENOMEM;
473 goto clk_unprep;
474 }
475
476 fb->fb.fbops = &clcdfb_ops;
477 fb->fb.flags = FBINFO_FLAG_DEFAULT;
478 fb->fb.pseudo_palette = fb->cmap;
479
480 strncpy(fb->fb.fix.id, clcd_name, sizeof(fb->fb.fix.id));
481 fb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
482 fb->fb.fix.type_aux = 0;
483 fb->fb.fix.xpanstep = 0;
484 fb->fb.fix.ypanstep = 0;
485 fb->fb.fix.ywrapstep = 0;
486 fb->fb.fix.accel = FB_ACCEL_NONE;
487
488 fb->fb.var.xres = fb->panel->mode.xres;
489 fb->fb.var.yres = fb->panel->mode.yres;
490 fb->fb.var.xres_virtual = fb->panel->mode.xres;
491 fb->fb.var.yres_virtual = fb->panel->mode.yres;
492 fb->fb.var.bits_per_pixel = fb->panel->bpp;
493 fb->fb.var.grayscale = fb->panel->grayscale;
494 fb->fb.var.pixclock = fb->panel->mode.pixclock;
495 fb->fb.var.left_margin = fb->panel->mode.left_margin;
496 fb->fb.var.right_margin = fb->panel->mode.right_margin;
497 fb->fb.var.upper_margin = fb->panel->mode.upper_margin;
498 fb->fb.var.lower_margin = fb->panel->mode.lower_margin;
499 fb->fb.var.hsync_len = fb->panel->mode.hsync_len;
500 fb->fb.var.vsync_len = fb->panel->mode.vsync_len;
501 fb->fb.var.sync = fb->panel->mode.sync;
502 fb->fb.var.vmode = fb->panel->mode.vmode;
503 fb->fb.var.activate = FB_ACTIVATE_NOW;
504 fb->fb.var.nonstd = 0;
505 fb->fb.var.height = fb->panel->height;
506 fb->fb.var.width = fb->panel->width;
507 fb->fb.var.accel_flags = 0;
508
509 fb->fb.monspecs.hfmin = 0;
510 fb->fb.monspecs.hfmax = 100000;
511 fb->fb.monspecs.vfmin = 0;
512 fb->fb.monspecs.vfmax = 400;
513 fb->fb.monspecs.dclkmin = 1000000;
514 fb->fb.monspecs.dclkmax = 100000000;
515
516 /*
517 * Make sure that the bitfields are set appropriately.
518 */
519 clcdfb_set_bitfields(fb, &fb->fb.var);
520
521 /*
522 * Allocate colourmap.
523 */
524 ret = fb_alloc_cmap(&fb->fb.cmap, 256, 0);
525 if (ret)
526 goto unmap;
527
528 /*
529 * Ensure interrupts are disabled.
530 */
531 writel(0, fb->regs + fb->off_ienb);
532
533 fb_set_var(&fb->fb, &fb->fb.var);
534
535 dev_info(&fb->dev->dev, "%s hardware, %s display\n",
536 fb->board->name, fb->panel->mode.name);
537
538 ret = register_framebuffer(&fb->fb);
539 if (ret == 0)
540 goto out;
541
542 printk(KERN_ERR "CLCD: cannot register framebuffer (%d)\n", ret);
543
544 fb_dealloc_cmap(&fb->fb.cmap);
545 unmap:
546 iounmap(fb->regs);
547 clk_unprep:
548 clk_unprepare(fb->clk);
549 free_clk:
550 clk_put(fb->clk);
551 out:
552 return ret;
553 }
554
555 #ifdef CONFIG_OF
556 static int clcdfb_of_get_dpi_panel_mode(struct device_node *node,
557 struct clcd_panel *clcd_panel)
558 {
559 int err;
560 struct display_timing timing;
561 struct videomode video;
562
563 err = of_get_display_timing(node, "panel-timing", &timing);
564 if (err) {
565 pr_err("%pOF: problems parsing panel-timing (%d)\n", node, err);
566 return err;
567 }
568
569 videomode_from_timing(&timing, &video);
570
571 err = fb_videomode_from_videomode(&video, &clcd_panel->mode);
572 if (err)
573 return err;
574
575 /* Set up some inversion flags */
576 if (timing.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
577 clcd_panel->tim2 |= TIM2_IPC;
578 else if (!(timing.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE))
579 /*
580 * To preserve backwards compatibility, the IPC (inverted
581 * pixel clock) flag needs to be set on any display that
582 * doesn't explicitly specify that the pixel clock is
583 * active on the negative or positive edge.
584 */
585 clcd_panel->tim2 |= TIM2_IPC;
586
587 if (timing.flags & DISPLAY_FLAGS_HSYNC_LOW)
588 clcd_panel->tim2 |= TIM2_IHS;
589
590 if (timing.flags & DISPLAY_FLAGS_VSYNC_LOW)
591 clcd_panel->tim2 |= TIM2_IVS;
592
593 if (timing.flags & DISPLAY_FLAGS_DE_LOW)
594 clcd_panel->tim2 |= TIM2_IOE;
595
596 return 0;
597 }
598
599 static int clcdfb_snprintf_mode(char *buf, int size, struct fb_videomode *mode)
600 {
601 return snprintf(buf, size, "%ux%u@%u", mode->xres, mode->yres,
602 mode->refresh);
603 }
604
605 static int clcdfb_of_get_backlight(struct device_node *panel,
606 struct clcd_panel *clcd_panel)
607 {
608 struct device_node *backlight;
609
610 /* Look up the optional backlight phandle */
611 backlight = of_parse_phandle(panel, "backlight", 0);
612 if (backlight) {
613 clcd_panel->backlight = of_find_backlight_by_node(backlight);
614 of_node_put(backlight);
615
616 if (!clcd_panel->backlight)
617 return -EPROBE_DEFER;
618 }
619 return 0;
620 }
621
622 static int clcdfb_of_get_mode(struct device *dev, struct device_node *panel,
623 struct clcd_panel *clcd_panel)
624 {
625 int err;
626 struct fb_videomode *mode;
627 char *name;
628 int len;
629
630 /* Only directly connected DPI panels supported for now */
631 if (of_device_is_compatible(panel, "panel-dpi"))
632 err = clcdfb_of_get_dpi_panel_mode(panel, clcd_panel);
633 else
634 err = -ENOENT;
635 if (err)
636 return err;
637 mode = &clcd_panel->mode;
638
639 len = clcdfb_snprintf_mode(NULL, 0, mode);
640 name = devm_kzalloc(dev, len + 1, GFP_KERNEL);
641 if (!name)
642 return -ENOMEM;
643
644 clcdfb_snprintf_mode(name, len + 1, mode);
645 mode->name = name;
646
647 return 0;
648 }
649
650 static int clcdfb_of_init_tft_panel(struct clcd_fb *fb, u32 r0, u32 g0, u32 b0)
651 {
652 static struct {
653 unsigned int part;
654 u32 r0, g0, b0;
655 u32 caps;
656 } panels[] = {
657 { 0x110, 1, 7, 13, CLCD_CAP_5551 },
658 { 0x110, 0, 8, 16, CLCD_CAP_888 },
659 { 0x110, 16, 8, 0, CLCD_CAP_888 },
660 { 0x111, 4, 14, 20, CLCD_CAP_444 },
661 { 0x111, 3, 11, 19, CLCD_CAP_444 | CLCD_CAP_5551 },
662 { 0x111, 3, 10, 19, CLCD_CAP_444 | CLCD_CAP_5551 |
663 CLCD_CAP_565 },
664 { 0x111, 0, 8, 16, CLCD_CAP_444 | CLCD_CAP_5551 |
665 CLCD_CAP_565 | CLCD_CAP_888 },
666 };
667 int i;
668
669 /* Bypass pixel clock divider */
670 fb->panel->tim2 |= TIM2_BCD;
671
672 /* TFT display, vert. comp. interrupt at the start of the back porch */
673 fb->panel->cntl |= CNTL_LCDTFT | CNTL_LCDVCOMP(1);
674
675 fb->panel->caps = 0;
676
677 /* Match the setup with known variants */
678 for (i = 0; i < ARRAY_SIZE(panels) && !fb->panel->caps; i++) {
679 if (amba_part(fb->dev) != panels[i].part)
680 continue;
681 if (g0 != panels[i].g0)
682 continue;
683 if (r0 == panels[i].r0 && b0 == panels[i].b0)
684 fb->panel->caps = panels[i].caps;
685 }
686
687 /*
688 * If we actually physically connected the R lines to B and
689 * vice versa
690 */
691 if (r0 != 0 && b0 == 0)
692 fb->panel->bgr_connection = true;
693
694 return fb->panel->caps ? 0 : -EINVAL;
695 }
696
697 static int clcdfb_of_init_display(struct clcd_fb *fb)
698 {
699 struct device_node *endpoint, *panel;
700 int err;
701 unsigned int bpp;
702 u32 max_bandwidth;
703 u32 tft_r0b0g0[3];
704
705 fb->panel = devm_kzalloc(&fb->dev->dev, sizeof(*fb->panel), GFP_KERNEL);
706 if (!fb->panel)
707 return -ENOMEM;
708
709 /*
710 * Fetch the panel endpoint.
711 */
712 endpoint = of_graph_get_next_endpoint(fb->dev->dev.of_node, NULL);
713 if (!endpoint)
714 return -ENODEV;
715
716 panel = of_graph_get_remote_port_parent(endpoint);
717 if (!panel)
718 return -ENODEV;
719
720 err = clcdfb_of_get_backlight(panel, fb->panel);
721 if (err)
722 return err;
723
724 err = clcdfb_of_get_mode(&fb->dev->dev, panel, fb->panel);
725 if (err)
726 return err;
727
728 err = of_property_read_u32(fb->dev->dev.of_node, "max-memory-bandwidth",
729 &max_bandwidth);
730 if (!err) {
731 /*
732 * max_bandwidth is in bytes per second and pixclock in
733 * pico-seconds, so the maximum allowed bits per pixel is
734 * 8 * max_bandwidth / (PICOS2KHZ(pixclock) * 1000)
735 * Rearrange this calculation to avoid overflow and then ensure
736 * result is a valid format.
737 */
738 bpp = max_bandwidth / (1000 / 8)
739 / PICOS2KHZ(fb->panel->mode.pixclock);
740 bpp = rounddown_pow_of_two(bpp);
741 if (bpp > 32)
742 bpp = 32;
743 } else
744 bpp = 32;
745 fb->panel->bpp = bpp;
746
747 #ifdef CONFIG_CPU_BIG_ENDIAN
748 fb->panel->cntl |= CNTL_BEBO;
749 #endif
750 fb->panel->width = -1;
751 fb->panel->height = -1;
752
753 if (of_property_read_u32_array(endpoint,
754 "arm,pl11x,tft-r0g0b0-pads",
755 tft_r0b0g0, ARRAY_SIZE(tft_r0b0g0)) != 0)
756 return -ENOENT;
757
758 return clcdfb_of_init_tft_panel(fb, tft_r0b0g0[0],
759 tft_r0b0g0[1], tft_r0b0g0[2]);
760 }
761
762 static int clcdfb_of_vram_setup(struct clcd_fb *fb)
763 {
764 int err;
765 struct device_node *memory;
766 u64 size;
767
768 err = clcdfb_of_init_display(fb);
769 if (err)
770 return err;
771
772 memory = of_parse_phandle(fb->dev->dev.of_node, "memory-region", 0);
773 if (!memory)
774 return -ENODEV;
775
776 fb->fb.screen_base = of_iomap(memory, 0);
777 if (!fb->fb.screen_base)
778 return -ENOMEM;
779
780 fb->fb.fix.smem_start = of_translate_address(memory,
781 of_get_address(memory, 0, &size, NULL));
782 fb->fb.fix.smem_len = size;
783
784 return 0;
785 }
786
787 static int clcdfb_of_vram_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
788 {
789 unsigned long off, user_size, kernel_size;
790
791
792 off = vma->vm_pgoff << PAGE_SHIFT;
793 user_size = vma->vm_end - vma->vm_start;
794 kernel_size = fb->fb.fix.smem_len;
795
796 if (off >= kernel_size || user_size > (kernel_size - off))
797 return -ENXIO;
798
799 return remap_pfn_range(vma, vma->vm_start,
800 __phys_to_pfn(fb->fb.fix.smem_start) + vma->vm_pgoff,
801 user_size,
802 pgprot_writecombine(vma->vm_page_prot));
803 }
804
805 static void clcdfb_of_vram_remove(struct clcd_fb *fb)
806 {
807 iounmap(fb->fb.screen_base);
808 }
809
810 static int clcdfb_of_dma_setup(struct clcd_fb *fb)
811 {
812 unsigned long framesize;
813 dma_addr_t dma;
814 int err;
815
816 err = clcdfb_of_init_display(fb);
817 if (err)
818 return err;
819
820 framesize = PAGE_ALIGN(fb->panel->mode.xres * fb->panel->mode.yres *
821 fb->panel->bpp / 8);
822 fb->fb.screen_base = dma_alloc_coherent(&fb->dev->dev, framesize,
823 &dma, GFP_KERNEL);
824 if (!fb->fb.screen_base)
825 return -ENOMEM;
826
827 fb->fb.fix.smem_start = dma;
828 fb->fb.fix.smem_len = framesize;
829
830 return 0;
831 }
832
833 static int clcdfb_of_dma_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
834 {
835 return dma_mmap_wc(&fb->dev->dev, vma, fb->fb.screen_base,
836 fb->fb.fix.smem_start, fb->fb.fix.smem_len);
837 }
838
839 static void clcdfb_of_dma_remove(struct clcd_fb *fb)
840 {
841 dma_free_coherent(&fb->dev->dev, fb->fb.fix.smem_len,
842 fb->fb.screen_base, fb->fb.fix.smem_start);
843 }
844
845 static struct clcd_board *clcdfb_of_get_board(struct amba_device *dev)
846 {
847 struct clcd_board *board = devm_kzalloc(&dev->dev, sizeof(*board),
848 GFP_KERNEL);
849 struct device_node *node = dev->dev.of_node;
850
851 if (!board)
852 return NULL;
853
854 board->name = of_node_full_name(node);
855 board->caps = CLCD_CAP_ALL;
856 board->check = clcdfb_check;
857 board->decode = clcdfb_decode;
858 if (of_find_property(node, "memory-region", NULL)) {
859 board->setup = clcdfb_of_vram_setup;
860 board->mmap = clcdfb_of_vram_mmap;
861 board->remove = clcdfb_of_vram_remove;
862 } else {
863 board->setup = clcdfb_of_dma_setup;
864 board->mmap = clcdfb_of_dma_mmap;
865 board->remove = clcdfb_of_dma_remove;
866 }
867
868 return board;
869 }
870 #else
871 static struct clcd_board *clcdfb_of_get_board(struct amba_device *dev)
872 {
873 return NULL;
874 }
875 #endif
876
877 static int clcdfb_probe(struct amba_device *dev, const struct amba_id *id)
878 {
879 struct clcd_board *board = dev_get_platdata(&dev->dev);
880 struct clcd_fb *fb;
881 int ret;
882
883 if (!board)
884 board = clcdfb_of_get_board(dev);
885
886 if (!board)
887 return -EINVAL;
888
889 ret = dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32));
890 if (ret)
891 goto out;
892
893 ret = amba_request_regions(dev, NULL);
894 if (ret) {
895 printk(KERN_ERR "CLCD: unable to reserve regs region\n");
896 goto out;
897 }
898
899 fb = kzalloc(sizeof(*fb), GFP_KERNEL);
900 if (!fb) {
901 ret = -ENOMEM;
902 goto free_region;
903 }
904
905 fb->dev = dev;
906 fb->board = board;
907
908 dev_info(&fb->dev->dev, "PL%03x designer %02x rev%u at 0x%08llx\n",
909 amba_part(dev), amba_manf(dev), amba_rev(dev),
910 (unsigned long long)dev->res.start);
911
912 ret = fb->board->setup(fb);
913 if (ret)
914 goto free_fb;
915
916 ret = clcdfb_register(fb);
917 if (ret == 0) {
918 amba_set_drvdata(dev, fb);
919 goto out;
920 }
921
922 fb->board->remove(fb);
923 free_fb:
924 kfree(fb);
925 free_region:
926 amba_release_regions(dev);
927 out:
928 return ret;
929 }
930
931 static int clcdfb_remove(struct amba_device *dev)
932 {
933 struct clcd_fb *fb = amba_get_drvdata(dev);
934
935 clcdfb_disable(fb);
936 unregister_framebuffer(&fb->fb);
937 if (fb->fb.cmap.len)
938 fb_dealloc_cmap(&fb->fb.cmap);
939 iounmap(fb->regs);
940 clk_unprepare(fb->clk);
941 clk_put(fb->clk);
942
943 fb->board->remove(fb);
944
945 kfree(fb);
946
947 amba_release_regions(dev);
948
949 return 0;
950 }
951
952 static const struct amba_id clcdfb_id_table[] = {
953 {
954 .id = 0x00041110,
955 .mask = 0x000ffffe,
956 },
957 { 0, 0 },
958 };
959
960 MODULE_DEVICE_TABLE(amba, clcdfb_id_table);
961
962 static struct amba_driver clcd_driver = {
963 .drv = {
964 .name = "clcd-pl11x",
965 },
966 .probe = clcdfb_probe,
967 .remove = clcdfb_remove,
968 .id_table = clcdfb_id_table,
969 };
970
971 static int __init amba_clcdfb_init(void)
972 {
973 if (fb_get_options("ambafb", NULL))
974 return -ENODEV;
975
976 return amba_driver_register(&clcd_driver);
977 }
978
979 module_init(amba_clcdfb_init);
980
981 static void __exit amba_clcdfb_exit(void)
982 {
983 amba_driver_unregister(&clcd_driver);
984 }
985
986 module_exit(amba_clcdfb_exit);
987
988 MODULE_DESCRIPTION("ARM PrimeCell PL110 CLCD core driver");
989 MODULE_LICENSE("GPL");
Linux with added FPC-III support