drivers/xen/xen-pciback/conf_space_header.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * PCI Backend - Handles the virtual fields in the configuration space headers.
   4  *
   5  * Author: Ryan Wilson <hap9@epoch.ncsc.mil>
   6  */
   7
   8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   9
  10 #include <linux/kernel.h>
  11 #include <linux/pci.h>
  12 #include "pciback.h"
  13 #include "conf_space.h"
  14
  15 struct pci_cmd_info {
  16         u16 val;
  17 };
  18
  19 struct pci_bar_info {
  20         u32 val;
  21         u32 len_val;
  22         int which;
  23 };
  24
  25 #define is_enable_cmd(value) ((value)&(PCI_COMMAND_MEMORY|PCI_COMMAND_IO))
  26 #define is_master_cmd(value) ((value)&PCI_COMMAND_MASTER)
  27
  28 /* Bits guests are allowed to control in permissive mode. */
  29 #define PCI_COMMAND_GUEST (PCI_COMMAND_MASTER|PCI_COMMAND_SPECIAL| \
  30                            PCI_COMMAND_INVALIDATE|PCI_COMMAND_VGA_PALETTE| \
  31                            PCI_COMMAND_WAIT|PCI_COMMAND_FAST_BACK)
  32
  33 static void *command_init(struct pci_dev *dev, int offset)
  34 {
  35         struct pci_cmd_info *cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  36         int err;
  37
  38         if (!cmd)
  39                 return ERR_PTR(-ENOMEM);
  40
  41         err = pci_read_config_word(dev, PCI_COMMAND, &cmd->val);
  42         if (err) {
  43                 kfree(cmd);
  44                 return ERR_PTR(err);
  45         }
  46
  47         return cmd;
  48 }
  49
  50 static int command_read(struct pci_dev *dev, int offset, u16 *value, void *data)
  51 {
  52         int ret = pci_read_config_word(dev, offset, value);
  53         const struct pci_cmd_info *cmd = data;
  54
  55         *value &= PCI_COMMAND_GUEST;
  56         *value |= cmd->val & ~PCI_COMMAND_GUEST;
  57
  58         return ret;
  59 }
  60
  61 static int command_write(struct pci_dev *dev, int offset, u16 value, void *data)
  62 {
  63         struct xen_pcibk_dev_data *dev_data;
  64         int err;
  65         u16 val;
  66         struct pci_cmd_info *cmd = data;
  67
  68         dev_data = pci_get_drvdata(dev);
  69         if (!pci_is_enabled(dev) && is_enable_cmd(value)) {
  70                 if (unlikely(verbose_request))
  71                         printk(KERN_DEBUG DRV_NAME ": %s: enable\n",
  72                                pci_name(dev));
  73                 err = pci_enable_device(dev);
  74                 if (err)
  75                         return err;
  76                 if (dev_data)
  77                         dev_data->enable_intx = 1;
  78         } else if (pci_is_enabled(dev) && !is_enable_cmd(value)) {
  79                 if (unlikely(verbose_request))
  80                         printk(KERN_DEBUG DRV_NAME ": %s: disable\n",
  81                                pci_name(dev));
  82                 pci_disable_device(dev);
  83                 if (dev_data)
  84                         dev_data->enable_intx = 0;
  85         }
  86
  87         if (!dev->is_busmaster && is_master_cmd(value)) {
  88                 if (unlikely(verbose_request))
  89                         printk(KERN_DEBUG DRV_NAME ": %s: set bus master\n",
  90                                pci_name(dev));
  91                 pci_set_master(dev);
  92         } else if (dev->is_busmaster && !is_master_cmd(value)) {
  93                 if (unlikely(verbose_request))
  94                         printk(KERN_DEBUG DRV_NAME ": %s: clear bus master\n",
  95                                pci_name(dev));
  96                 pci_clear_master(dev);
  97         }
  98
  99         if (!(cmd->val & PCI_COMMAND_INVALIDATE) &&
 100             (value & PCI_COMMAND_INVALIDATE)) {
 101                 if (unlikely(verbose_request))
 102                         printk(KERN_DEBUG
 103                                DRV_NAME ": %s: enable memory-write-invalidate\n",
 104                                pci_name(dev));
 105                 err = pci_set_mwi(dev);
 106                 if (err) {
 107                         pr_warn("%s: cannot enable memory-write-invalidate (%d)\n",
 108                                 pci_name(dev), err);
 109                         value &= ~PCI_COMMAND_INVALIDATE;
 110                 }
 111         } else if ((cmd->val & PCI_COMMAND_INVALIDATE) &&
 112                    !(value & PCI_COMMAND_INVALIDATE)) {
 113                 if (unlikely(verbose_request))
 114                         printk(KERN_DEBUG
 115                                DRV_NAME ": %s: disable memory-write-invalidate\n",
 116                                pci_name(dev));
 117                 pci_clear_mwi(dev);
 118         }
 119
 120         if (dev_data && dev_data->allow_interrupt_control) {
 121                 if ((cmd->val ^ value) & PCI_COMMAND_INTX_DISABLE) {
 122                         if (value & PCI_COMMAND_INTX_DISABLE) {
 123                                 pci_intx(dev, 0);
 124                         } else {
 125                                 /* Do not allow enabling INTx together with MSI or MSI-X. */
 126                                 switch (xen_pcibk_get_interrupt_type(dev)) {
 127                                 case INTERRUPT_TYPE_NONE:
 128                                         pci_intx(dev, 1);
 129                                         break;
 130                                 case INTERRUPT_TYPE_INTX:
 131                                         break;
 132                                 default:
 133                                         return PCIBIOS_SET_FAILED;
 134                                 }
 135                         }
 136                 }
 137         }
 138
 139         cmd->val = value;
 140
 141         if (!xen_pcibk_permissive && (!dev_data || !dev_data->permissive))
 142                 return 0;
 143
 144         /* Only allow the guest to control certain bits. */
 145         err = pci_read_config_word(dev, offset, &val);
 146         if (err || val == value)
 147                 return err;
 148
 149         value &= PCI_COMMAND_GUEST;
 150         value |= val & ~PCI_COMMAND_GUEST;
 151
 152         return pci_write_config_word(dev, offset, value);
 153 }
 154
 155 static int rom_write(struct pci_dev *dev, int offset, u32 value, void *data)
 156 {
 157         struct pci_bar_info *bar = data;
 158
 159         if (unlikely(!bar)) {
 160                 pr_warn(DRV_NAME ": driver data not found for %s\n",
 161                        pci_name(dev));
 162                 return XEN_PCI_ERR_op_failed;
 163         }
 164
 165         /* A write to obtain the length must happen as a 32-bit write.
 166          * This does not (yet) support writing individual bytes
 167          */
 168         if ((value | ~PCI_ROM_ADDRESS_MASK) == ~0U)
 169                 bar->which = 1;
 170         else {
 171                 u32 tmpval;
 172                 pci_read_config_dword(dev, offset, &tmpval);
 173                 if (tmpval != bar->val && value == bar->val) {
 174                         /* Allow restoration of bar value. */
 175                         pci_write_config_dword(dev, offset, bar->val);
 176                 }
 177                 bar->which = 0;
 178         }
 179
 180         /* Do we need to support enabling/disabling the rom address here? */
 181
 182         return 0;
 183 }
 184
 185 /* For the BARs, only allow writes which write ~0 or
 186  * the correct resource information
 187  * (Needed for when the driver probes the resource usage)
 188  */
 189 static int bar_write(struct pci_dev *dev, int offset, u32 value, void *data)
 190 {
 191         struct pci_bar_info *bar = data;
 192         unsigned int pos = (offset - PCI_BASE_ADDRESS_0) / 4;
 193         const struct resource *res = dev->resource;
 194         u32 mask;
 195
 196         if (unlikely(!bar)) {
 197                 pr_warn(DRV_NAME ": driver data not found for %s\n",
 198                        pci_name(dev));
 199                 return XEN_PCI_ERR_op_failed;
 200         }
 201
 202         /* A write to obtain the length must happen as a 32-bit write.
 203          * This does not (yet) support writing individual bytes
 204          */
 205         if (res[pos].flags & IORESOURCE_IO)
 206                 mask = ~PCI_BASE_ADDRESS_IO_MASK;
 207         else if (pos && (res[pos - 1].flags & IORESOURCE_MEM_64))
 208                 mask = 0;
 209         else
 210                 mask = ~PCI_BASE_ADDRESS_MEM_MASK;
 211         if ((value | mask) == ~0U)
 212                 bar->which = 1;
 213         else {
 214                 u32 tmpval;
 215                 pci_read_config_dword(dev, offset, &tmpval);
 216                 if (tmpval != bar->val && value == bar->val) {
 217                         /* Allow restoration of bar value. */
 218                         pci_write_config_dword(dev, offset, bar->val);
 219                 }
 220                 bar->which = 0;
 221         }
 222
 223         return 0;
 224 }
 225
 226 static int bar_read(struct pci_dev *dev, int offset, u32 * value, void *data)
 227 {
 228         struct pci_bar_info *bar = data;
 229
 230         if (unlikely(!bar)) {
 231                 pr_warn(DRV_NAME ": driver data not found for %s\n",
 232                        pci_name(dev));
 233                 return XEN_PCI_ERR_op_failed;
 234         }
 235
 236         *value = bar->which ? bar->len_val : bar->val;
 237
 238         return 0;
 239 }
 240
 241 static void *bar_init(struct pci_dev *dev, int offset)
 242 {
 243         unsigned int pos;
 244         const struct resource *res = dev->resource;
 245         struct pci_bar_info *bar = kzalloc(sizeof(*bar), GFP_KERNEL);
 246
 247         if (!bar)
 248                 return ERR_PTR(-ENOMEM);
 249
 250         if (offset == PCI_ROM_ADDRESS || offset == PCI_ROM_ADDRESS1)
 251                 pos = PCI_ROM_RESOURCE;
 252         else {
 253                 pos = (offset - PCI_BASE_ADDRESS_0) / 4;
 254                 if (pos && (res[pos - 1].flags & IORESOURCE_MEM_64)) {
 255                         bar->val = res[pos - 1].start >> 32;
 256                         bar->len_val = -resource_size(&res[pos - 1]) >> 32;
 257                         return bar;
 258                 }
 259         }
 260
 261         if (!res[pos].flags ||
 262             (res[pos].flags & (IORESOURCE_DISABLED | IORESOURCE_UNSET |
 263                                IORESOURCE_BUSY)))
 264                 return bar;
 265
 266         bar->val = res[pos].start |
 267                    (res[pos].flags & PCI_REGION_FLAG_MASK);
 268         bar->len_val = -resource_size(&res[pos]) |
 269                        (res[pos].flags & PCI_REGION_FLAG_MASK);
 270
 271         return bar;
 272 }
 273
 274 static void bar_reset(struct pci_dev *dev, int offset, void *data)
 275 {
 276         struct pci_bar_info *bar = data;
 277
 278         bar->which = 0;
 279 }
 280
 281 static void bar_release(struct pci_dev *dev, int offset, void *data)
 282 {
 283         kfree(data);
 284 }
 285
 286 static int xen_pcibk_read_vendor(struct pci_dev *dev, int offset,
 287                                u16 *value, void *data)
 288 {
 289         *value = dev->vendor;
 290
 291         return 0;
 292 }
 293
 294 static int xen_pcibk_read_device(struct pci_dev *dev, int offset,
 295                                u16 *value, void *data)
 296 {
 297         *value = dev->device;
 298
 299         return 0;
 300 }
 301
 302 static int interrupt_read(struct pci_dev *dev, int offset, u8 * value,
 303                           void *data)
 304 {
 305         *value = (u8) dev->irq;
 306
 307         return 0;
 308 }
 309
 310 static int bist_write(struct pci_dev *dev, int offset, u8 value, void *data)
 311 {
 312         u8 cur_value;
 313         int err;
 314
 315         err = pci_read_config_byte(dev, offset, &cur_value);
 316         if (err)
 317                 goto out;
 318
 319         if ((cur_value & ~PCI_BIST_START) == (value & ~PCI_BIST_START)
 320             || value == PCI_BIST_START)
 321                 err = pci_write_config_byte(dev, offset, value);
 322
 323 out:
 324         return err;
 325 }
 326
 327 static const struct config_field header_common[] = {
 328         {
 329          .offset    = PCI_VENDOR_ID,
 330          .size      = 2,
 331          .u.w.read  = xen_pcibk_read_vendor,
 332         },
 333         {
 334          .offset    = PCI_DEVICE_ID,
 335          .size      = 2,
 336          .u.w.read  = xen_pcibk_read_device,
 337         },
 338         {
 339          .offset    = PCI_COMMAND,
 340          .size      = 2,
 341          .init      = command_init,
 342          .release   = bar_release,
 343          .u.w.read  = command_read,
 344          .u.w.write = command_write,
 345         },
 346         {
 347          .offset    = PCI_INTERRUPT_LINE,
 348          .size      = 1,
 349          .u.b.read  = interrupt_read,
 350         },
 351         {
 352          .offset    = PCI_INTERRUPT_PIN,
 353          .size      = 1,
 354          .u.b.read  = xen_pcibk_read_config_byte,
 355         },
 356         {
 357          /* Any side effects of letting driver domain control cache line? */
 358          .offset    = PCI_CACHE_LINE_SIZE,
 359          .size      = 1,
 360          .u.b.read  = xen_pcibk_read_config_byte,
 361          .u.b.write = xen_pcibk_write_config_byte,
 362         },
 363         {
 364          .offset    = PCI_LATENCY_TIMER,
 365          .size      = 1,
 366          .u.b.read  = xen_pcibk_read_config_byte,
 367         },
 368         {
 369          .offset    = PCI_BIST,
 370          .size      = 1,
 371          .u.b.read  = xen_pcibk_read_config_byte,
 372          .u.b.write = bist_write,
 373         },
 374         {}
 375 };
 376
 377 #define CFG_FIELD_BAR(reg_offset)                       \
 378         {                                               \
 379         .offset     = reg_offset,                       \
 380         .size       = 4,                                \
 381         .init       = bar_init,                         \
 382         .reset      = bar_reset,                        \
 383         .release    = bar_release,                      \
 384         .u.dw.read  = bar_read,                         \
 385         .u.dw.write = bar_write,                        \
 386         }
 387
 388 #define CFG_FIELD_ROM(reg_offset)                       \
 389         {                                               \
 390         .offset     = reg_offset,                       \
 391         .size       = 4,                                \
 392         .init       = bar_init,                         \
 393         .reset      = bar_reset,                        \
 394         .release    = bar_release,                      \
 395         .u.dw.read  = bar_read,                         \
 396         .u.dw.write = rom_write,                        \
 397         }
 398
 399 static const struct config_field header_0[] = {
 400         CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
 401         CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
 402         CFG_FIELD_BAR(PCI_BASE_ADDRESS_2),
 403         CFG_FIELD_BAR(PCI_BASE_ADDRESS_3),
 404         CFG_FIELD_BAR(PCI_BASE_ADDRESS_4),
 405         CFG_FIELD_BAR(PCI_BASE_ADDRESS_5),
 406         CFG_FIELD_ROM(PCI_ROM_ADDRESS),
 407         {}
 408 };
 409
 410 static const struct config_field header_1[] = {
 411         CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
 412         CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
 413         CFG_FIELD_ROM(PCI_ROM_ADDRESS1),
 414         {}
 415 };
 416
 417 int xen_pcibk_config_header_add_fields(struct pci_dev *dev)
 418 {
 419         int err;
 420
 421         err = xen_pcibk_config_add_fields(dev, header_common);
 422         if (err)
 423                 goto out;
 424
 425         switch (dev->hdr_type) {
 426         case PCI_HEADER_TYPE_NORMAL:
 427                 err = xen_pcibk_config_add_fields(dev, header_0);
 428                 break;
 429
 430         case PCI_HEADER_TYPE_BRIDGE:
 431                 err = xen_pcibk_config_add_fields(dev, header_1);
 432                 break;
 433
 434         default:
 435                 err = -EINVAL;
 436                 pr_err("%s: Unsupported header type %d!\n",
 437                        pci_name(dev), dev->hdr_type);
 438                 break;
 439         }
 440
 441 out:
 442         return err;
 443 }