sound/soc/codecs/rt5682-sdw.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 //
   3 // rt5682-sdw.c  --  RT5682 ALSA SoC audio component driver
   4 //
   5 // Copyright 2019 Realtek Semiconductor Corp.
   6 // Author: Oder Chiou <oder_chiou@realtek.com>
   7 //
   8
   9 #include <linux/module.h>
  10 #include <linux/moduleparam.h>
  11 #include <linux/init.h>
  12 #include <linux/delay.h>
  13 #include <linux/pm.h>
  14 #include <linux/acpi.h>
  15 #include <linux/gpio.h>
  16 #include <linux/of_gpio.h>
  17 #include <linux/regulator/consumer.h>
  18 #include <linux/mutex.h>
  19 #include <linux/soundwire/sdw.h>
  20 #include <linux/soundwire/sdw_type.h>
  21 #include <sound/core.h>
  22 #include <sound/pcm.h>
  23 #include <sound/pcm_params.h>
  24 #include <sound/jack.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/initval.h>
  28 #include <sound/tlv.h>
  29
  30 #include "rt5682.h"
  31 #include "rt5682-sdw.h"
  32
  33 static bool rt5682_sdw_readable_register(struct device *dev, unsigned int reg)
  34 {
  35         switch (reg) {
  36         case 0x00e0:
  37         case 0x00f0:
  38         case 0x3000:
  39         case 0x3001:
  40         case 0x3004:
  41         case 0x3005:
  42         case 0x3008:
  43                 return true;
  44         default:
  45                 return false;
  46         }
  47 }
  48
  49 const struct regmap_config rt5682_sdw_regmap = {
  50         .name = "sdw",
  51         .reg_bits = 32,
  52         .val_bits = 8,
  53         .max_register = RT5682_I2C_MODE,
  54         .readable_reg = rt5682_sdw_readable_register,
  55         .cache_type = REGCACHE_NONE,
  56         .use_single_read = true,
  57         .use_single_write = true,
  58 };
  59
  60 static int rt5682_update_status(struct sdw_slave *slave,
  61                                         enum sdw_slave_status status)
  62 {
  63         struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
  64
  65         /* Update the status */
  66         rt5682->status = status;
  67
  68         if (status == SDW_SLAVE_UNATTACHED)
  69                 rt5682->hw_init = false;
  70
  71         /*
  72          * Perform initialization only if slave status is present and
  73          * hw_init flag is false
  74          */
  75         if (rt5682->hw_init || rt5682->status != SDW_SLAVE_ATTACHED)
  76                 return 0;
  77
  78         /* perform I/O transfers required for Slave initialization */
  79         return rt5682_io_init(&slave->dev, slave);
  80 }
  81
  82 static int rt5682_read_prop(struct sdw_slave *slave)
  83 {
  84         struct sdw_slave_prop *prop = &slave->prop;
  85         int nval, i, num_of_ports = 1;
  86         u32 bit;
  87         unsigned long addr;
  88         struct sdw_dpn_prop *dpn;
  89
  90         prop->paging_support = false;
  91
  92         /* first we need to allocate memory for set bits in port lists */
  93         prop->source_ports = 0x4;       /* BITMAP: 00000100 */
  94         prop->sink_ports = 0x2;         /* BITMAP: 00000010 */
  95
  96         nval = hweight32(prop->source_ports);
  97         num_of_ports += nval;
  98         prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
  99                                           sizeof(*prop->src_dpn_prop),
 100                                           GFP_KERNEL);
 101         if (!prop->src_dpn_prop)
 102                 return -ENOMEM;
 103
 104         i = 0;
 105         dpn = prop->src_dpn_prop;
 106         addr = prop->source_ports;
 107         for_each_set_bit(bit, &addr, 32) {
 108                 dpn[i].num = bit;
 109                 dpn[i].type = SDW_DPN_FULL;
 110                 dpn[i].simple_ch_prep_sm = true;
 111                 dpn[i].ch_prep_timeout = 10;
 112                 i++;
 113         }
 114
 115         /* do this again for sink now */
 116         nval = hweight32(prop->sink_ports);
 117         num_of_ports += nval;
 118         prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
 119                                            sizeof(*prop->sink_dpn_prop),
 120                                            GFP_KERNEL);
 121         if (!prop->sink_dpn_prop)
 122                 return -ENOMEM;
 123
 124         i = 0;
 125         dpn = prop->sink_dpn_prop;
 126         addr = prop->sink_ports;
 127         for_each_set_bit(bit, &addr, 32) {
 128                 dpn[i].num = bit;
 129                 dpn[i].type = SDW_DPN_FULL;
 130                 dpn[i].simple_ch_prep_sm = true;
 131                 dpn[i].ch_prep_timeout = 10;
 132                 i++;
 133         }
 134
 135         /* Allocate port_ready based on num_of_ports */
 136         slave->port_ready = devm_kcalloc(&slave->dev, num_of_ports,
 137                                          sizeof(*slave->port_ready),
 138                                          GFP_KERNEL);
 139         if (!slave->port_ready)
 140                 return -ENOMEM;
 141
 142         /* Initialize completion */
 143         for (i = 0; i < num_of_ports; i++)
 144                 init_completion(&slave->port_ready[i]);
 145
 146         /* set the timeout values */
 147         prop->clk_stop_timeout = 20;
 148
 149         /* wake-up event */
 150         prop->wake_capable = 1;
 151
 152         return 0;
 153 }
 154
 155 /* Bus clock frequency */
 156 #define RT5682_CLK_FREQ_9600000HZ 9600000
 157 #define RT5682_CLK_FREQ_12000000HZ 12000000
 158 #define RT5682_CLK_FREQ_6000000HZ 6000000
 159 #define RT5682_CLK_FREQ_4800000HZ 4800000
 160 #define RT5682_CLK_FREQ_2400000HZ 2400000
 161 #define RT5682_CLK_FREQ_12288000HZ 12288000
 162
 163 static int rt5682_clock_config(struct device *dev)
 164 {
 165         struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
 166         unsigned int clk_freq, value;
 167
 168         clk_freq = (rt5682->params.curr_dr_freq >> 1);
 169
 170         switch (clk_freq) {
 171         case RT5682_CLK_FREQ_12000000HZ:
 172                 value = 0x0;
 173                 break;
 174         case RT5682_CLK_FREQ_6000000HZ:
 175                 value = 0x1;
 176                 break;
 177         case RT5682_CLK_FREQ_9600000HZ:
 178                 value = 0x2;
 179                 break;
 180         case RT5682_CLK_FREQ_4800000HZ:
 181                 value = 0x3;
 182                 break;
 183         case RT5682_CLK_FREQ_2400000HZ:
 184                 value = 0x4;
 185                 break;
 186         case RT5682_CLK_FREQ_12288000HZ:
 187                 value = 0x5;
 188                 break;
 189         default:
 190                 return -EINVAL;
 191         }
 192
 193         regmap_write(rt5682->sdw_regmap, 0xe0, value);
 194         regmap_write(rt5682->sdw_regmap, 0xf0, value);
 195
 196         dev_dbg(dev, "%s complete, clk_freq=%d\n", __func__, clk_freq);
 197
 198         return 0;
 199 }
 200
 201 static int rt5682_bus_config(struct sdw_slave *slave,
 202                                         struct sdw_bus_params *params)
 203 {
 204         struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
 205         int ret;
 206
 207         memcpy(&rt5682->params, params, sizeof(*params));
 208
 209         ret = rt5682_clock_config(&slave->dev);
 210         if (ret < 0)
 211                 dev_err(&slave->dev, "Invalid clk config");
 212
 213         return ret;
 214 }
 215
 216 static int rt5682_interrupt_callback(struct sdw_slave *slave,
 217                                         struct sdw_slave_intr_status *status)
 218 {
 219         struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
 220
 221         dev_dbg(&slave->dev,
 222                 "%s control_port_stat=%x", __func__, status->control_port);
 223
 224         if (status->control_port & 0x4) {
 225                 mod_delayed_work(system_power_efficient_wq,
 226                         &rt5682->jack_detect_work, msecs_to_jiffies(250));
 227         }
 228
 229         return 0;
 230 }
 231
 232 static struct sdw_slave_ops rt5682_slave_ops = {
 233         .read_prop = rt5682_read_prop,
 234         .interrupt_callback = rt5682_interrupt_callback,
 235         .update_status = rt5682_update_status,
 236         .bus_config = rt5682_bus_config,
 237 };
 238
 239 static int rt5682_sdw_probe(struct sdw_slave *slave,
 240                            const struct sdw_device_id *id)
 241 {
 242         struct regmap *regmap;
 243
 244         /* Assign ops */
 245         slave->ops = &rt5682_slave_ops;
 246
 247         /* Regmap Initialization */
 248         regmap = devm_regmap_init_sdw(slave, &rt5682_sdw_regmap);
 249         if (IS_ERR(regmap))
 250                 return -EINVAL;
 251
 252         rt5682_sdw_init(&slave->dev, regmap, slave);
 253
 254         return 0;
 255 }
 256
 257 static int rt5682_sdw_remove(struct sdw_slave *slave)
 258 {
 259         struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
 260
 261         if (rt5682 && rt5682->hw_init)
 262                 cancel_delayed_work(&rt5682->jack_detect_work);
 263
 264         return 0;
 265 }
 266
 267 static const struct sdw_device_id rt5682_id[] = {
 268         SDW_SLAVE_ENTRY(0x025d, 0x5682, 0),
 269         {},
 270 };
 271 MODULE_DEVICE_TABLE(sdw, rt5682_id);
 272
 273 static int __maybe_unused rt5682_dev_suspend(struct device *dev)
 274 {
 275         struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
 276
 277         if (!rt5682->hw_init)
 278                 return 0;
 279
 280         regcache_cache_only(rt5682->regmap, true);
 281         regcache_mark_dirty(rt5682->regmap);
 282
 283         return 0;
 284 }
 285
 286 static int __maybe_unused rt5682_dev_resume(struct device *dev)
 287 {
 288         struct sdw_slave *slave = dev_to_sdw_dev(dev);
 289         struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
 290         unsigned long time;
 291
 292         if (!rt5682->hw_init)
 293                 return 0;
 294
 295         if (!slave->unattach_request)
 296                 goto regmap_sync;
 297
 298         time = wait_for_completion_timeout(&slave->initialization_complete,
 299                                 msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
 300         if (!time) {
 301                 dev_err(&slave->dev, "Initialization not complete, timed out\n");
 302                 return -ETIMEDOUT;
 303         }
 304
 305 regmap_sync:
 306         slave->unattach_request = 0;
 307         regcache_cache_only(rt5682->regmap, false);
 308         regcache_sync(rt5682->regmap);
 309
 310         return 0;
 311 }
 312
 313 static const struct dev_pm_ops rt5682_pm = {
 314         SET_SYSTEM_SLEEP_PM_OPS(rt5682_dev_suspend, rt5682_dev_resume)
 315         SET_RUNTIME_PM_OPS(rt5682_dev_suspend, rt5682_dev_resume, NULL)
 316 };
 317
 318 static struct sdw_driver rt5682_sdw_driver = {
 319         .driver = {
 320                 .name = "rt5682",
 321                 .owner = THIS_MODULE,
 322                 .pm = &rt5682_pm,
 323         },
 324         .probe = rt5682_sdw_probe,
 325         .remove = rt5682_sdw_remove,
 326         .ops = &rt5682_slave_ops,
 327         .id_table = rt5682_id,
 328 };
 329 module_sdw_driver(rt5682_sdw_driver);
 330
 331 MODULE_DESCRIPTION("ASoC RT5682 driver SDW");
 332 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
 333 MODULE_LICENSE("GPL v2");