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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / sound / soc / sof / intel / hda-dsp.c
blob99087b6afb6710185de18882f81f718d93a866db
1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
7 //
8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10 // Rander Wang <rander.wang@intel.com>
11 // Keyon Jie <yang.jie@linux.intel.com>
12 //
13
14 /*
15 * Hardware interface for generic Intel audio DSP HDA IP
16 */
17
18 #include <linux/module.h>
19 #include <sound/hdaudio_ext.h>
20 #include <sound/hda_register.h>
21 #include "../sof-audio.h"
22 #include "../ops.h"
23 #include "hda.h"
24 #include "hda-ipc.h"
25
26 static bool hda_enable_trace_D0I3_S0;
27 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG)
28 module_param_named(enable_trace_D0I3_S0, hda_enable_trace_D0I3_S0, bool, 0444);
29 MODULE_PARM_DESC(enable_trace_D0I3_S0,
30 "SOF HDA enable trace when the DSP is in D0I3 in S0");
31 #endif
32
33 /*
34 * DSP Core control.
35 */
36
37 int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask)
38 {
39 u32 adspcs;
40 u32 reset;
41 int ret;
42
43 /* set reset bits for cores */
44 reset = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
45 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
46 HDA_DSP_REG_ADSPCS,
47 reset, reset),
48
49 /* poll with timeout to check if operation successful */
50 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
51 HDA_DSP_REG_ADSPCS, adspcs,
52 ((adspcs & reset) == reset),
53 HDA_DSP_REG_POLL_INTERVAL_US,
54 HDA_DSP_RESET_TIMEOUT_US);
55 if (ret < 0) {
56 dev_err(sdev->dev,
57 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
58 __func__);
59 return ret;
60 }
61
62 /* has core entered reset ? */
63 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
64 HDA_DSP_REG_ADSPCS);
65 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) !=
66 HDA_DSP_ADSPCS_CRST_MASK(core_mask)) {
67 dev_err(sdev->dev,
68 "error: reset enter failed: core_mask %x adspcs 0x%x\n",
69 core_mask, adspcs);
70 ret = -EIO;
71 }
72
73 return ret;
74 }
75
76 int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask)
77 {
78 unsigned int crst;
79 u32 adspcs;
80 int ret;
81
82 /* clear reset bits for cores */
83 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
84 HDA_DSP_REG_ADSPCS,
85 HDA_DSP_ADSPCS_CRST_MASK(core_mask),
86 0);
87
88 /* poll with timeout to check if operation successful */
89 crst = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
90 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
91 HDA_DSP_REG_ADSPCS, adspcs,
92 !(adspcs & crst),
93 HDA_DSP_REG_POLL_INTERVAL_US,
94 HDA_DSP_RESET_TIMEOUT_US);
95
96 if (ret < 0) {
97 dev_err(sdev->dev,
98 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
99 __func__);
100 return ret;
101 }
102
103 /* has core left reset ? */
104 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
105 HDA_DSP_REG_ADSPCS);
106 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 0) {
107 dev_err(sdev->dev,
108 "error: reset leave failed: core_mask %x adspcs 0x%x\n",
109 core_mask, adspcs);
110 ret = -EIO;
111 }
112
113 return ret;
114 }
115
116 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask)
117 {
118 /* stall core */
119 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
120 HDA_DSP_REG_ADSPCS,
121 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
122 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
123
124 /* set reset state */
125 return hda_dsp_core_reset_enter(sdev, core_mask);
126 }
127
128 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask)
129 {
130 int ret;
131
132 /* leave reset state */
133 ret = hda_dsp_core_reset_leave(sdev, core_mask);
134 if (ret < 0)
135 return ret;
136
137 /* run core */
138 dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask);
139 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
140 HDA_DSP_REG_ADSPCS,
141 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
142 0);
143
144 /* is core now running ? */
145 if (!hda_dsp_core_is_enabled(sdev, core_mask)) {
146 hda_dsp_core_stall_reset(sdev, core_mask);
147 dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n",
148 core_mask);
149 ret = -EIO;
150 }
151
152 return ret;
153 }
154
155 /*
156 * Power Management.
157 */
158
159 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask)
160 {
161 unsigned int cpa;
162 u32 adspcs;
163 int ret;
164
165 /* update bits */
166 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
167 HDA_DSP_ADSPCS_SPA_MASK(core_mask),
168 HDA_DSP_ADSPCS_SPA_MASK(core_mask));
169
170 /* poll with timeout to check if operation successful */
171 cpa = HDA_DSP_ADSPCS_CPA_MASK(core_mask);
172 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
173 HDA_DSP_REG_ADSPCS, adspcs,
174 (adspcs & cpa) == cpa,
175 HDA_DSP_REG_POLL_INTERVAL_US,
176 HDA_DSP_RESET_TIMEOUT_US);
177 if (ret < 0) {
178 dev_err(sdev->dev,
179 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
180 __func__);
181 return ret;
182 }
183
184 /* did core power up ? */
185 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
186 HDA_DSP_REG_ADSPCS);
187 if ((adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) !=
188 HDA_DSP_ADSPCS_CPA_MASK(core_mask)) {
189 dev_err(sdev->dev,
190 "error: power up core failed core_mask %xadspcs 0x%x\n",
191 core_mask, adspcs);
192 ret = -EIO;
193 }
194
195 return ret;
196 }
197
198 int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask)
199 {
200 u32 adspcs;
201 int ret;
202
203 /* update bits */
204 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
205 HDA_DSP_REG_ADSPCS,
206 HDA_DSP_ADSPCS_SPA_MASK(core_mask), 0);
207
208 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
209 HDA_DSP_REG_ADSPCS, adspcs,
210 !(adspcs & HDA_DSP_ADSPCS_SPA_MASK(core_mask)),
211 HDA_DSP_REG_POLL_INTERVAL_US,
212 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC);
213 if (ret < 0)
214 dev_err(sdev->dev,
215 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
216 __func__);
217
218 return ret;
219 }
220
221 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
222 unsigned int core_mask)
223 {
224 int val;
225 bool is_enable;
226
227 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS);
228
229 is_enable = ((val & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) &&
230 (val & HDA_DSP_ADSPCS_SPA_MASK(core_mask)) &&
231 !(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) &&
232 !(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask)));
233
234 dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n",
235 is_enable, core_mask);
236
237 return is_enable;
238 }
239
240 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
241 {
242 int ret;
243
244 /* return if core is already enabled */
245 if (hda_dsp_core_is_enabled(sdev, core_mask))
246 return 0;
247
248 /* power up */
249 ret = hda_dsp_core_power_up(sdev, core_mask);
250 if (ret < 0) {
251 dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n",
252 core_mask);
253 return ret;
254 }
255
256 return hda_dsp_core_run(sdev, core_mask);
257 }
258
259 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
260 unsigned int core_mask)
261 {
262 int ret;
263
264 /* place core in reset prior to power down */
265 ret = hda_dsp_core_stall_reset(sdev, core_mask);
266 if (ret < 0) {
267 dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n",
268 core_mask);
269 return ret;
270 }
271
272 /* power down core */
273 ret = hda_dsp_core_power_down(sdev, core_mask);
274 if (ret < 0) {
275 dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n",
276 core_mask, ret);
277 return ret;
278 }
279
280 /* make sure we are in OFF state */
281 if (hda_dsp_core_is_enabled(sdev, core_mask)) {
282 dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n",
283 core_mask, ret);
284 ret = -EIO;
285 }
286
287 return ret;
288 }
289
290 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev)
291 {
292 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
293 const struct sof_intel_dsp_desc *chip = hda->desc;
294
295 /* enable IPC DONE and BUSY interrupts */
296 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
297 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY,
298 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY);
299
300 /* enable IPC interrupt */
301 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
302 HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
303 }
304
305 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev)
306 {
307 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
308 const struct sof_intel_dsp_desc *chip = hda->desc;
309
310 /* disable IPC interrupt */
311 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
312 HDA_DSP_ADSPIC_IPC, 0);
313
314 /* disable IPC BUSY and DONE interrupt */
315 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
316 HDA_DSP_REG_HIPCCTL_BUSY | HDA_DSP_REG_HIPCCTL_DONE, 0);
317 }
318
319 static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev)
320 {
321 struct hdac_bus *bus = sof_to_bus(sdev);
322 int retry = HDA_DSP_REG_POLL_RETRY_COUNT;
323
324 while (snd_hdac_chip_readb(bus, VS_D0I3C) & SOF_HDA_VS_D0I3C_CIP) {
325 if (!retry--)
326 return -ETIMEDOUT;
327 usleep_range(10, 15);
328 }
329
330 return 0;
331 }
332
333 static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags)
334 {
335 struct sof_ipc_pm_gate pm_gate;
336 struct sof_ipc_reply reply;
337
338 memset(&pm_gate, 0, sizeof(pm_gate));
339
340 /* configure pm_gate ipc message */
341 pm_gate.hdr.size = sizeof(pm_gate);
342 pm_gate.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE;
343 pm_gate.flags = flags;
344
345 /* send pm_gate ipc to dsp */
346 return sof_ipc_tx_message_no_pm(sdev->ipc, pm_gate.hdr.cmd,
347 &pm_gate, sizeof(pm_gate), &reply,
348 sizeof(reply));
349 }
350
351 static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value)
352 {
353 struct hdac_bus *bus = sof_to_bus(sdev);
354 int ret;
355
356 /* Write to D0I3C after Command-In-Progress bit is cleared */
357 ret = hda_dsp_wait_d0i3c_done(sdev);
358 if (ret < 0) {
359 dev_err(bus->dev, "CIP timeout before D0I3C update!\n");
360 return ret;
361 }
362
363 /* Update D0I3C register */
364 snd_hdac_chip_updateb(bus, VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value);
365
366 /* Wait for cmd in progress to be cleared before exiting the function */
367 ret = hda_dsp_wait_d0i3c_done(sdev);
368 if (ret < 0) {
369 dev_err(bus->dev, "CIP timeout after D0I3C update!\n");
370 return ret;
371 }
372
373 dev_vdbg(bus->dev, "D0I3C updated, register = 0x%x\n",
374 snd_hdac_chip_readb(bus, VS_D0I3C));
375
376 return 0;
377 }
378
379 static int hda_dsp_set_D0_state(struct snd_sof_dev *sdev,
380 const struct sof_dsp_power_state *target_state)
381 {
382 u32 flags = 0;
383 int ret;
384 u8 value = 0;
385
386 /*
387 * Sanity check for illegal state transitions
388 * The only allowed transitions are:
389 * 1. D3 -> D0I0
390 * 2. D0I0 -> D0I3
391 * 3. D0I3 -> D0I0
392 */
393 switch (sdev->dsp_power_state.state) {
394 case SOF_DSP_PM_D0:
395 /* Follow the sequence below for D0 substate transitions */
396 break;
397 case SOF_DSP_PM_D3:
398 /* Follow regular flow for D3 -> D0 transition */
399 return 0;
400 default:
401 dev_err(sdev->dev, "error: transition from %d to %d not allowed\n",
402 sdev->dsp_power_state.state, target_state->state);
403 return -EINVAL;
404 }
405
406 /* Set flags and register value for D0 target substate */
407 if (target_state->substate == SOF_HDA_DSP_PM_D0I3) {
408 value = SOF_HDA_VS_D0I3C_I3;
409
410 /*
411 * Trace DMA is disabled by default when the DSP enters D0I3.
412 * But it can be kept enabled when the DSP enters D0I3 while the
413 * system is in S0 for debug.
414 */
415 if (hda_enable_trace_D0I3_S0 &&
416 sdev->system_suspend_target != SOF_SUSPEND_NONE)
417 flags = HDA_PM_NO_DMA_TRACE;
418 } else {
419 /* prevent power gating in D0I0 */
420 flags = HDA_PM_PPG;
421 }
422
423 /* update D0I3C register */
424 ret = hda_dsp_update_d0i3c_register(sdev, value);
425 if (ret < 0)
426 return ret;
427
428 /*
429 * Notify the DSP of the state change.
430 * If this IPC fails, revert the D0I3C register update in order
431 * to prevent partial state change.
432 */
433 ret = hda_dsp_send_pm_gate_ipc(sdev, flags);
434 if (ret < 0) {
435 dev_err(sdev->dev,
436 "error: PM_GATE ipc error %d\n", ret);
437 goto revert;
438 }
439
440 return ret;
441
442 revert:
443 /* fallback to the previous register value */
444 value = value ? 0 : SOF_HDA_VS_D0I3C_I3;
445
446 /*
447 * This can fail but return the IPC error to signal that
448 * the state change failed.
449 */
450 hda_dsp_update_d0i3c_register(sdev, value);
451
452 return ret;
453 }
454
455 /* helper to log DSP state */
456 static void hda_dsp_state_log(struct snd_sof_dev *sdev)
457 {
458 switch (sdev->dsp_power_state.state) {
459 case SOF_DSP_PM_D0:
460 switch (sdev->dsp_power_state.substate) {
461 case SOF_HDA_DSP_PM_D0I0:
462 dev_dbg(sdev->dev, "Current DSP power state: D0I0\n");
463 break;
464 case SOF_HDA_DSP_PM_D0I3:
465 dev_dbg(sdev->dev, "Current DSP power state: D0I3\n");
466 break;
467 default:
468 dev_dbg(sdev->dev, "Unknown DSP D0 substate: %d\n",
469 sdev->dsp_power_state.substate);
470 break;
471 }
472 break;
473 case SOF_DSP_PM_D1:
474 dev_dbg(sdev->dev, "Current DSP power state: D1\n");
475 break;
476 case SOF_DSP_PM_D2:
477 dev_dbg(sdev->dev, "Current DSP power state: D2\n");
478 break;
479 case SOF_DSP_PM_D3_HOT:
480 dev_dbg(sdev->dev, "Current DSP power state: D3_HOT\n");
481 break;
482 case SOF_DSP_PM_D3:
483 dev_dbg(sdev->dev, "Current DSP power state: D3\n");
484 break;
485 case SOF_DSP_PM_D3_COLD:
486 dev_dbg(sdev->dev, "Current DSP power state: D3_COLD\n");
487 break;
488 default:
489 dev_dbg(sdev->dev, "Unknown DSP power state: %d\n",
490 sdev->dsp_power_state.state);
491 break;
492 }
493 }
494
495 /*
496 * All DSP power state transitions are initiated by the driver.
497 * If the requested state change fails, the error is simply returned.
498 * Further state transitions are attempted only when the set_power_save() op
499 * is called again either because of a new IPC sent to the DSP or
500 * during system suspend/resume.
501 */
502 int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
503 const struct sof_dsp_power_state *target_state)
504 {
505 int ret = 0;
506
507 /*
508 * When the DSP is already in D0I3 and the target state is D0I3,
509 * it could be the case that the DSP is in D0I3 during S0
510 * and the system is suspending to S0Ix. Therefore,
511 * hda_dsp_set_D0_state() must be called to disable trace DMA
512 * by sending the PM_GATE IPC to the FW.
513 */
514 if (target_state->substate == SOF_HDA_DSP_PM_D0I3 &&
515 sdev->system_suspend_target == SOF_SUSPEND_S0IX)
516 goto set_state;
517
518 /*
519 * For all other cases, return without doing anything if
520 * the DSP is already in the target state.
521 */
522 if (target_state->state == sdev->dsp_power_state.state &&
523 target_state->substate == sdev->dsp_power_state.substate)
524 return 0;
525
526 set_state:
527 switch (target_state->state) {
528 case SOF_DSP_PM_D0:
529 ret = hda_dsp_set_D0_state(sdev, target_state);
530 break;
531 case SOF_DSP_PM_D3:
532 /* The only allowed transition is: D0I0 -> D3 */
533 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0 &&
534 sdev->dsp_power_state.substate == SOF_HDA_DSP_PM_D0I0)
535 break;
536
537 dev_err(sdev->dev,
538 "error: transition from %d to %d not allowed\n",
539 sdev->dsp_power_state.state, target_state->state);
540 return -EINVAL;
541 default:
542 dev_err(sdev->dev, "error: target state unsupported %d\n",
543 target_state->state);
544 return -EINVAL;
545 }
546 if (ret < 0) {
547 dev_err(sdev->dev,
548 "failed to set requested target DSP state %d substate %d\n",
549 target_state->state, target_state->substate);
550 return ret;
551 }
552
553 sdev->dsp_power_state = *target_state;
554 hda_dsp_state_log(sdev);
555 return ret;
556 }
557
558 /*
559 * Audio DSP states may transform as below:-
560 *
561 * Opportunistic D0I3 in S0
562 * Runtime +---------------------+ Delayed D0i3 work timeout
563 * suspend | +--------------------+
564 * +------------+ D0I0(active) | |
565 * | | <---------------+ |
566 * | +--------> | New IPC | |
567 * | |Runtime +--^--+---------^--+--+ (via mailbox) | |
568 * | |resume | | | | | |
569 * | | | | | | | |
570 * | | System| | | | | |
571 * | | resume| | S3/S0IX | | | |
572 * | | | | suspend | | S0IX | |
573 * | | | | | |suspend | |
574 * | | | | | | | |
575 * | | | | | | | |
576 * +-v---+-----------+--v-------+ | | +------+----v----+
577 * | | | +-----------> |
578 * | D3 (suspended) | | | D0I3 |
579 * | | +--------------+ |
580 * | | System resume | |
581 * +----------------------------+ +----------------+
582 *
583 * S0IX suspend: The DSP is in D0I3 if any D0I3-compatible streams
584 * ignored the suspend trigger. Otherwise the DSP
585 * is in D3.
586 */
587
588 static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
589 {
590 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
591 const struct sof_intel_dsp_desc *chip = hda->desc;
592 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
593 struct hdac_bus *bus = sof_to_bus(sdev);
594 #endif
595 int ret;
596
597 hda_sdw_int_enable(sdev, false);
598
599 /* disable IPC interrupts */
600 hda_dsp_ipc_int_disable(sdev);
601
602 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
603 if (runtime_suspend)
604 hda_codec_jack_wake_enable(sdev);
605
606 /* power down all hda link */
607 snd_hdac_ext_bus_link_power_down_all(bus);
608 #endif
609
610 /* power down DSP */
611 ret = hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
612 if (ret < 0) {
613 dev_err(sdev->dev,
614 "error: failed to power down core during suspend\n");
615 return ret;
616 }
617
618 /* disable ppcap interrupt */
619 hda_dsp_ctrl_ppcap_enable(sdev, false);
620 hda_dsp_ctrl_ppcap_int_enable(sdev, false);
621
622 /* disable hda bus irq and streams */
623 hda_dsp_ctrl_stop_chip(sdev);
624
625 /* disable LP retention mode */
626 snd_sof_pci_update_bits(sdev, PCI_PGCTL,
627 PCI_PGCTL_LSRMD_MASK, PCI_PGCTL_LSRMD_MASK);
628
629 /* reset controller */
630 ret = hda_dsp_ctrl_link_reset(sdev, true);
631 if (ret < 0) {
632 dev_err(sdev->dev,
633 "error: failed to reset controller during suspend\n");
634 return ret;
635 }
636
637 /* display codec can powered off after link reset */
638 hda_codec_i915_display_power(sdev, false);
639
640 return 0;
641 }
642
643 static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume)
644 {
645 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
646 struct hdac_bus *bus = sof_to_bus(sdev);
647 struct hdac_ext_link *hlink = NULL;
648 #endif
649 int ret;
650
651 /* display codec must be powered before link reset */
652 hda_codec_i915_display_power(sdev, true);
653
654 /*
655 * clear TCSEL to clear playback on some HD Audio
656 * codecs. PCI TCSEL is defined in the Intel manuals.
657 */
658 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
659
660 /* reset and start hda controller */
661 ret = hda_dsp_ctrl_init_chip(sdev, true);
662 if (ret < 0) {
663 dev_err(sdev->dev,
664 "error: failed to start controller after resume\n");
665 return ret;
666 }
667
668 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
669 /* check jack status */
670 if (runtime_resume)
671 hda_codec_jack_check(sdev);
672
673 /* turn off the links that were off before suspend */
674 list_for_each_entry(hlink, &bus->hlink_list, list) {
675 if (!hlink->ref_count)
676 snd_hdac_ext_bus_link_power_down(hlink);
677 }
678
679 /* check dma status and clean up CORB/RIRB buffers */
680 if (!bus->cmd_dma_state)
681 snd_hdac_bus_stop_cmd_io(bus);
682 #endif
683
684 /* enable ppcap interrupt */
685 hda_dsp_ctrl_ppcap_enable(sdev, true);
686 hda_dsp_ctrl_ppcap_int_enable(sdev, true);
687
688 return 0;
689 }
690
691 int hda_dsp_resume(struct snd_sof_dev *sdev)
692 {
693 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
694 struct pci_dev *pci = to_pci_dev(sdev->dev);
695 const struct sof_dsp_power_state target_state = {
696 .state = SOF_DSP_PM_D0,
697 .substate = SOF_HDA_DSP_PM_D0I0,
698 };
699 int ret;
700
701 /* resume from D0I3 */
702 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0) {
703 hda_codec_i915_display_power(sdev, true);
704
705 /* Set DSP power state */
706 ret = snd_sof_dsp_set_power_state(sdev, &target_state);
707 if (ret < 0) {
708 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
709 target_state.state, target_state.substate);
710 return ret;
711 }
712
713 /* restore L1SEN bit */
714 if (hda->l1_support_changed)
715 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
716 HDA_VS_INTEL_EM2,
717 HDA_VS_INTEL_EM2_L1SEN, 0);
718
719 /* restore and disable the system wakeup */
720 pci_restore_state(pci);
721 disable_irq_wake(pci->irq);
722 return 0;
723 }
724
725 /* init hda controller. DSP cores will be powered up during fw boot */
726 ret = hda_resume(sdev, false);
727 if (ret < 0)
728 return ret;
729
730 return snd_sof_dsp_set_power_state(sdev, &target_state);
731 }
732
733 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
734 {
735 const struct sof_dsp_power_state target_state = {
736 .state = SOF_DSP_PM_D0,
737 };
738 int ret;
739
740 /* init hda controller. DSP cores will be powered up during fw boot */
741 ret = hda_resume(sdev, true);
742 if (ret < 0)
743 return ret;
744
745 return snd_sof_dsp_set_power_state(sdev, &target_state);
746 }
747
748 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev)
749 {
750 struct hdac_bus *hbus = sof_to_bus(sdev);
751
752 if (hbus->codec_powered) {
753 dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n",
754 (unsigned int)hbus->codec_powered);
755 return -EBUSY;
756 }
757
758 return 0;
759 }
760
761 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev)
762 {
763 const struct sof_dsp_power_state target_state = {
764 .state = SOF_DSP_PM_D3,
765 };
766 int ret;
767
768 /* stop hda controller and power dsp off */
769 ret = hda_suspend(sdev, true);
770 if (ret < 0)
771 return ret;
772
773 return snd_sof_dsp_set_power_state(sdev, &target_state);
774 }
775
776 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
777 {
778 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
779 struct hdac_bus *bus = sof_to_bus(sdev);
780 struct pci_dev *pci = to_pci_dev(sdev->dev);
781 const struct sof_dsp_power_state target_dsp_state = {
782 .state = target_state,
783 .substate = target_state == SOF_DSP_PM_D0 ?
784 SOF_HDA_DSP_PM_D0I3 : 0,
785 };
786 int ret;
787
788 /* cancel any attempt for DSP D0I3 */
789 cancel_delayed_work_sync(&hda->d0i3_work);
790
791 if (target_state == SOF_DSP_PM_D0) {
792 /* we can't keep a wakeref to display driver at suspend */
793 hda_codec_i915_display_power(sdev, false);
794
795 /* Set DSP power state */
796 ret = snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
797 if (ret < 0) {
798 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
799 target_dsp_state.state,
800 target_dsp_state.substate);
801 return ret;
802 }
803
804 /* enable L1SEN to make sure the system can enter S0Ix */
805 hda->l1_support_changed =
806 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
807 HDA_VS_INTEL_EM2,
808 HDA_VS_INTEL_EM2_L1SEN,
809 HDA_VS_INTEL_EM2_L1SEN);
810
811 /* enable the system waking up via IPC IRQ */
812 enable_irq_wake(pci->irq);
813 pci_save_state(pci);
814 return 0;
815 }
816
817 /* stop hda controller and power dsp off */
818 ret = hda_suspend(sdev, false);
819 if (ret < 0) {
820 dev_err(bus->dev, "error: suspending dsp\n");
821 return ret;
822 }
823
824 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
825 }
826
827 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev)
828 {
829 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
830 struct hdac_bus *bus = sof_to_bus(sdev);
831 struct snd_soc_pcm_runtime *rtd;
832 struct hdac_ext_stream *stream;
833 struct hdac_ext_link *link;
834 struct hdac_stream *s;
835 const char *name;
836 int stream_tag;
837
838 /* set internal flag for BE */
839 list_for_each_entry(s, &bus->stream_list, list) {
840 stream = stream_to_hdac_ext_stream(s);
841
842 /*
843 * clear stream. This should already be taken care for running
844 * streams when the SUSPEND trigger is called. But paused
845 * streams do not get suspended, so this needs to be done
846 * explicitly during suspend.
847 */
848 if (stream->link_substream) {
849 rtd = snd_pcm_substream_chip(stream->link_substream);
850 name = asoc_rtd_to_codec(rtd, 0)->component->name;
851 link = snd_hdac_ext_bus_get_link(bus, name);
852 if (!link)
853 return -EINVAL;
854
855 stream->link_prepared = 0;
856
857 if (hdac_stream(stream)->direction ==
858 SNDRV_PCM_STREAM_CAPTURE)
859 continue;
860
861 stream_tag = hdac_stream(stream)->stream_tag;
862 snd_hdac_ext_link_clear_stream_id(link, stream_tag);
863 }
864 }
865 #endif
866 return 0;
867 }
868
869 void hda_dsp_d0i3_work(struct work_struct *work)
870 {
871 struct sof_intel_hda_dev *hdev = container_of(work,
872 struct sof_intel_hda_dev,
873 d0i3_work.work);
874 struct hdac_bus *bus = &hdev->hbus.core;
875 struct snd_sof_dev *sdev = dev_get_drvdata(bus->dev);
876 struct sof_dsp_power_state target_state;
877 int ret;
878
879 target_state.state = SOF_DSP_PM_D0;
880
881 /* DSP can enter D0I3 iff only D0I3-compatible streams are active */
882 if (snd_sof_dsp_only_d0i3_compatible_stream_active(sdev))
883 target_state.substate = SOF_HDA_DSP_PM_D0I3;
884 else
885 target_state.substate = SOF_HDA_DSP_PM_D0I0;
886
887 /* remain in D0I0 */
888 if (target_state.substate == SOF_HDA_DSP_PM_D0I0)
889 return;
890
891 /* This can fail but error cannot be propagated */
892 ret = snd_sof_dsp_set_power_state(sdev, &target_state);
893 if (ret < 0)
894 dev_err_ratelimited(sdev->dev,
895 "error: failed to set DSP state %d substate %d\n",
896 target_state.state, target_state.substate);
897 }
Linux with added FPC-III support