sound/soc/sof/intel/hda.h

   1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
   2 /*
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * Copyright(c) 2017 Intel Corporation. All rights reserved.
   7  *
   8  * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
   9  */
  10
  11 #ifndef __SOF_INTEL_HDA_H
  12 #define __SOF_INTEL_HDA_H
  13
  14 #include <linux/soundwire/sdw.h>
  15 #include <linux/soundwire/sdw_intel.h>
  16 #include <sound/compress_driver.h>
  17 #include <sound/hda_codec.h>
  18 #include <sound/hdaudio_ext.h>
  19 #include "shim.h"
  20
  21 /* PCI registers */
  22 #define PCI_TCSEL                       0x44
  23 #define PCI_PGCTL                       PCI_TCSEL
  24 #define PCI_CGCTL                       0x48
  25
  26 /* PCI_PGCTL bits */
  27 #define PCI_PGCTL_ADSPPGD               BIT(2)
  28 #define PCI_PGCTL_LSRMD_MASK            BIT(4)
  29
  30 /* PCI_CGCTL bits */
  31 #define PCI_CGCTL_MISCBDCGE_MASK        BIT(6)
  32 #define PCI_CGCTL_ADSPDCGE              BIT(1)
  33
  34 /* Legacy HDA registers and bits used - widths are variable */
  35 #define SOF_HDA_GCAP                    0x0
  36 #define SOF_HDA_GCTL                    0x8
  37 /* accept unsol. response enable */
  38 #define SOF_HDA_GCTL_UNSOL              BIT(8)
  39 #define SOF_HDA_LLCH                    0x14
  40 #define SOF_HDA_INTCTL                  0x20
  41 #define SOF_HDA_INTSTS                  0x24
  42 #define SOF_HDA_WAKESTS                 0x0E
  43 #define SOF_HDA_WAKESTS_INT_MASK        ((1 << 8) - 1)
  44 #define SOF_HDA_RIRBSTS                 0x5d
  45
  46 /* SOF_HDA_GCTL register bist */
  47 #define SOF_HDA_GCTL_RESET              BIT(0)
  48
  49 /* SOF_HDA_INCTL regs */
  50 #define SOF_HDA_INT_GLOBAL_EN           BIT(31)
  51 #define SOF_HDA_INT_CTRL_EN             BIT(30)
  52 #define SOF_HDA_INT_ALL_STREAM          0xff
  53
  54 /* SOF_HDA_INTSTS regs */
  55 #define SOF_HDA_INTSTS_GIS              BIT(31)
  56
  57 #define SOF_HDA_MAX_CAPS                10
  58 #define SOF_HDA_CAP_ID_OFF              16
  59 #define SOF_HDA_CAP_ID_MASK             GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
  60                                                 SOF_HDA_CAP_ID_OFF)
  61 #define SOF_HDA_CAP_NEXT_MASK           0xFFFF
  62
  63 #define SOF_HDA_GTS_CAP_ID                      0x1
  64 #define SOF_HDA_ML_CAP_ID                       0x2
  65
  66 #define SOF_HDA_PP_CAP_ID               0x3
  67 #define SOF_HDA_REG_PP_PPCH             0x10
  68 #define SOF_HDA_REG_PP_PPCTL            0x04
  69 #define SOF_HDA_REG_PP_PPSTS            0x08
  70 #define SOF_HDA_PPCTL_PIE               BIT(31)
  71 #define SOF_HDA_PPCTL_GPROCEN           BIT(30)
  72
  73 /*Vendor Specific Registers*/
  74 #define SOF_HDA_VS_D0I3C                0x104A
  75
  76 /* D0I3C Register fields */
  77 #define SOF_HDA_VS_D0I3C_CIP            BIT(0) /* Command-In-Progress */
  78 #define SOF_HDA_VS_D0I3C_I3             BIT(2) /* D0i3 enable bit */
  79
  80 /* DPIB entry size: 8 Bytes = 2 DWords */
  81 #define SOF_HDA_DPIB_ENTRY_SIZE 0x8
  82
  83 #define SOF_HDA_SPIB_CAP_ID             0x4
  84 #define SOF_HDA_DRSM_CAP_ID             0x5
  85
  86 #define SOF_HDA_SPIB_BASE               0x08
  87 #define SOF_HDA_SPIB_INTERVAL           0x08
  88 #define SOF_HDA_SPIB_SPIB               0x00
  89 #define SOF_HDA_SPIB_MAXFIFO            0x04
  90
  91 #define SOF_HDA_PPHC_BASE               0x10
  92 #define SOF_HDA_PPHC_INTERVAL           0x10
  93
  94 #define SOF_HDA_PPLC_BASE               0x10
  95 #define SOF_HDA_PPLC_MULTI              0x10
  96 #define SOF_HDA_PPLC_INTERVAL           0x10
  97
  98 #define SOF_HDA_DRSM_BASE               0x08
  99 #define SOF_HDA_DRSM_INTERVAL           0x08
 100
 101 /* Descriptor error interrupt */
 102 #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR          0x10
 103
 104 /* FIFO error interrupt */
 105 #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR          0x08
 106
 107 /* Buffer completion interrupt */
 108 #define SOF_HDA_CL_DMA_SD_INT_COMPLETE          0x04
 109
 110 #define SOF_HDA_CL_DMA_SD_INT_MASK \
 111         (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \
 112         SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \
 113         SOF_HDA_CL_DMA_SD_INT_COMPLETE)
 114 #define SOF_HDA_SD_CTL_DMA_START                0x02 /* Stream DMA start bit */
 115
 116 /* Intel HD Audio Code Loader DMA Registers */
 117 #define SOF_HDA_ADSP_LOADER_BASE                0x80
 118 #define SOF_HDA_ADSP_DPLBASE                    0x70
 119 #define SOF_HDA_ADSP_DPUBASE                    0x74
 120 #define SOF_HDA_ADSP_DPLBASE_ENABLE             0x01
 121
 122 /* Stream Registers */
 123 #define SOF_HDA_ADSP_REG_CL_SD_CTL              0x00
 124 #define SOF_HDA_ADSP_REG_CL_SD_STS              0x03
 125 #define SOF_HDA_ADSP_REG_CL_SD_LPIB             0x04
 126 #define SOF_HDA_ADSP_REG_CL_SD_CBL              0x08
 127 #define SOF_HDA_ADSP_REG_CL_SD_LVI              0x0C
 128 #define SOF_HDA_ADSP_REG_CL_SD_FIFOW            0x0E
 129 #define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE         0x10
 130 #define SOF_HDA_ADSP_REG_CL_SD_FORMAT           0x12
 131 #define SOF_HDA_ADSP_REG_CL_SD_FIFOL            0x14
 132 #define SOF_HDA_ADSP_REG_CL_SD_BDLPL            0x18
 133 #define SOF_HDA_ADSP_REG_CL_SD_BDLPU            0x1C
 134 #define SOF_HDA_ADSP_SD_ENTRY_SIZE              0x20
 135
 136 /* CL: Software Position Based FIFO Capability Registers */
 137 #define SOF_DSP_REG_CL_SPBFIFO \
 138         (SOF_HDA_ADSP_LOADER_BASE + 0x20)
 139 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH      0x0
 140 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL    0x4
 141 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB        0x8
 142 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS    0xc
 143
 144 /* Stream Number */
 145 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT      20
 146 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
 147         GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
 148                 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
 149
 150 #define HDA_DSP_HDA_BAR                         0
 151 #define HDA_DSP_PP_BAR                          1
 152 #define HDA_DSP_SPIB_BAR                        2
 153 #define HDA_DSP_DRSM_BAR                        3
 154 #define HDA_DSP_BAR                             4
 155
 156 #define SRAM_WINDOW_OFFSET(x)                   (0x80000 + (x) * 0x20000)
 157
 158 #define HDA_DSP_MBOX_OFFSET                     SRAM_WINDOW_OFFSET(0)
 159
 160 #define HDA_DSP_PANIC_OFFSET(x) \
 161         (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
 162
 163 /* SRAM window 0 FW "registers" */
 164 #define HDA_DSP_SRAM_REG_ROM_STATUS             (HDA_DSP_MBOX_OFFSET + 0x0)
 165 #define HDA_DSP_SRAM_REG_ROM_ERROR              (HDA_DSP_MBOX_OFFSET + 0x4)
 166 /* FW and ROM share offset 4 */
 167 #define HDA_DSP_SRAM_REG_FW_STATUS              (HDA_DSP_MBOX_OFFSET + 0x4)
 168 #define HDA_DSP_SRAM_REG_FW_TRACEP              (HDA_DSP_MBOX_OFFSET + 0x8)
 169 #define HDA_DSP_SRAM_REG_FW_END                 (HDA_DSP_MBOX_OFFSET + 0xc)
 170
 171 #define HDA_DSP_MBOX_UPLINK_OFFSET              0x81000
 172
 173 #define HDA_DSP_STREAM_RESET_TIMEOUT            300
 174 /*
 175  * Timeout in us, for setting the stream RUN bit, during
 176  * start/stop the stream. The timeout expires if new RUN bit
 177  * value cannot be read back within the specified time.
 178  */
 179 #define HDA_DSP_STREAM_RUN_TIMEOUT              300
 180
 181 #define HDA_DSP_SPIB_ENABLE                     1
 182 #define HDA_DSP_SPIB_DISABLE                    0
 183
 184 #define SOF_HDA_MAX_BUFFER_SIZE                 (32 * PAGE_SIZE)
 185
 186 #define HDA_DSP_STACK_DUMP_SIZE                 32
 187
 188 /* ROM  status/error values */
 189 #define HDA_DSP_ROM_STS_MASK                    GENMASK(23, 0)
 190 #define HDA_DSP_ROM_INIT                        0x1
 191 #define HDA_DSP_ROM_FW_MANIFEST_LOADED          0x3
 192 #define HDA_DSP_ROM_FW_FW_LOADED                0x4
 193 #define HDA_DSP_ROM_FW_ENTERED                  0x5
 194 #define HDA_DSP_ROM_RFW_START                   0xf
 195 #define HDA_DSP_ROM_CSE_ERROR                   40
 196 #define HDA_DSP_ROM_CSE_WRONG_RESPONSE          41
 197 #define HDA_DSP_ROM_IMR_TO_SMALL                42
 198 #define HDA_DSP_ROM_BASE_FW_NOT_FOUND           43
 199 #define HDA_DSP_ROM_CSE_VALIDATION_FAILED       44
 200 #define HDA_DSP_ROM_IPC_FATAL_ERROR             45
 201 #define HDA_DSP_ROM_L2_CACHE_ERROR              46
 202 #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL        47
 203 #define HDA_DSP_ROM_API_PTR_INVALID             50
 204 #define HDA_DSP_ROM_BASEFW_INCOMPAT             51
 205 #define HDA_DSP_ROM_UNHANDLED_INTERRUPT         0xBEE00000
 206 #define HDA_DSP_ROM_MEMORY_HOLE_ECC             0xECC00000
 207 #define HDA_DSP_ROM_KERNEL_EXCEPTION            0xCAFE0000
 208 #define HDA_DSP_ROM_USER_EXCEPTION              0xBEEF0000
 209 #define HDA_DSP_ROM_UNEXPECTED_RESET            0xDECAF000
 210 #define HDA_DSP_ROM_NULL_FW_ENTRY               0x4c4c4e55
 211 #define HDA_DSP_IPC_PURGE_FW                    0x01004000
 212
 213 /* various timeout values */
 214 #define HDA_DSP_PU_TIMEOUT              50
 215 #define HDA_DSP_PD_TIMEOUT              50
 216 #define HDA_DSP_RESET_TIMEOUT_US        50000
 217 #define HDA_DSP_BASEFW_TIMEOUT_US       3000000
 218 #define HDA_DSP_INIT_TIMEOUT_US 500000
 219 #define HDA_DSP_CTRL_RESET_TIMEOUT              100
 220 #define HDA_DSP_WAIT_TIMEOUT            500     /* 500 msec */
 221 #define HDA_DSP_REG_POLL_INTERVAL_US            500     /* 0.5 msec */
 222 #define HDA_DSP_REG_POLL_RETRY_COUNT            50
 223
 224 #define HDA_DSP_ADSPIC_IPC                      1
 225 #define HDA_DSP_ADSPIS_IPC                      1
 226
 227 /* Intel HD Audio General DSP Registers */
 228 #define HDA_DSP_GEN_BASE                0x0
 229 #define HDA_DSP_REG_ADSPCS              (HDA_DSP_GEN_BASE + 0x04)
 230 #define HDA_DSP_REG_ADSPIC              (HDA_DSP_GEN_BASE + 0x08)
 231 #define HDA_DSP_REG_ADSPIS              (HDA_DSP_GEN_BASE + 0x0C)
 232 #define HDA_DSP_REG_ADSPIC2             (HDA_DSP_GEN_BASE + 0x10)
 233 #define HDA_DSP_REG_ADSPIS2             (HDA_DSP_GEN_BASE + 0x14)
 234
 235 #define HDA_DSP_REG_ADSPIS2_SNDW        BIT(5)
 236 #define HDA_DSP_REG_SNDW_WAKE_STS      0x2C192
 237
 238 /* Intel HD Audio Inter-Processor Communication Registers */
 239 #define HDA_DSP_IPC_BASE                0x40
 240 #define HDA_DSP_REG_HIPCT               (HDA_DSP_IPC_BASE + 0x00)
 241 #define HDA_DSP_REG_HIPCTE              (HDA_DSP_IPC_BASE + 0x04)
 242 #define HDA_DSP_REG_HIPCI               (HDA_DSP_IPC_BASE + 0x08)
 243 #define HDA_DSP_REG_HIPCIE              (HDA_DSP_IPC_BASE + 0x0C)
 244 #define HDA_DSP_REG_HIPCCTL             (HDA_DSP_IPC_BASE + 0x10)
 245
 246 /* Intel Vendor Specific Registers */
 247 #define HDA_VS_INTEL_EM2                0x1030
 248 #define HDA_VS_INTEL_EM2_L1SEN          BIT(13)
 249
 250 /*  HIPCI */
 251 #define HDA_DSP_REG_HIPCI_BUSY          BIT(31)
 252 #define HDA_DSP_REG_HIPCI_MSG_MASK      0x7FFFFFFF
 253
 254 /* HIPCIE */
 255 #define HDA_DSP_REG_HIPCIE_DONE BIT(30)
 256 #define HDA_DSP_REG_HIPCIE_MSG_MASK     0x3FFFFFFF
 257
 258 /* HIPCCTL */
 259 #define HDA_DSP_REG_HIPCCTL_DONE        BIT(1)
 260 #define HDA_DSP_REG_HIPCCTL_BUSY        BIT(0)
 261
 262 /* HIPCT */
 263 #define HDA_DSP_REG_HIPCT_BUSY          BIT(31)
 264 #define HDA_DSP_REG_HIPCT_MSG_MASK      0x7FFFFFFF
 265
 266 /* HIPCTE */
 267 #define HDA_DSP_REG_HIPCTE_MSG_MASK     0x3FFFFFFF
 268
 269 #define HDA_DSP_ADSPIC_CL_DMA           0x2
 270 #define HDA_DSP_ADSPIS_CL_DMA           0x2
 271
 272 /* Delay before scheduling D0i3 entry */
 273 #define BXT_D0I3_DELAY 5000
 274
 275 #define FW_CL_STREAM_NUMBER             0x1
 276
 277 /* ADSPCS - Audio DSP Control & Status */
 278
 279 /*
 280  * Core Reset - asserted high
 281  * CRST Mask for a given core mask pattern, cm
 282  */
 283 #define HDA_DSP_ADSPCS_CRST_SHIFT       0
 284 #define HDA_DSP_ADSPCS_CRST_MASK(cm)    ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT)
 285
 286 /*
 287  * Core run/stall - when set to '1' core is stalled
 288  * CSTALL Mask for a given core mask pattern, cm
 289  */
 290 #define HDA_DSP_ADSPCS_CSTALL_SHIFT     8
 291 #define HDA_DSP_ADSPCS_CSTALL_MASK(cm)  ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT)
 292
 293 /*
 294  * Set Power Active - when set to '1' turn cores on
 295  * SPA Mask for a given core mask pattern, cm
 296  */
 297 #define HDA_DSP_ADSPCS_SPA_SHIFT        16
 298 #define HDA_DSP_ADSPCS_SPA_MASK(cm)     ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT)
 299
 300 /*
 301  * Current Power Active - power status of cores, set by hardware
 302  * CPA Mask for a given core mask pattern, cm
 303  */
 304 #define HDA_DSP_ADSPCS_CPA_SHIFT        24
 305 #define HDA_DSP_ADSPCS_CPA_MASK(cm)     ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
 306
 307 /* Mask for a given core index, c = 0.. number of supported cores - 1 */
 308 #define HDA_DSP_CORE_MASK(c)            BIT(c)
 309
 310 /*
 311  * Mask for a given number of cores
 312  * nc = number of supported cores
 313  */
 314 #define SOF_DSP_CORES_MASK(nc)  GENMASK(((nc) - 1), 0)
 315
 316 /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
 317 #define CNL_DSP_IPC_BASE                0xc0
 318 #define CNL_DSP_REG_HIPCTDR             (CNL_DSP_IPC_BASE + 0x00)
 319 #define CNL_DSP_REG_HIPCTDA             (CNL_DSP_IPC_BASE + 0x04)
 320 #define CNL_DSP_REG_HIPCTDD             (CNL_DSP_IPC_BASE + 0x08)
 321 #define CNL_DSP_REG_HIPCIDR             (CNL_DSP_IPC_BASE + 0x10)
 322 #define CNL_DSP_REG_HIPCIDA             (CNL_DSP_IPC_BASE + 0x14)
 323 #define CNL_DSP_REG_HIPCIDD             (CNL_DSP_IPC_BASE + 0x18)
 324 #define CNL_DSP_REG_HIPCCTL             (CNL_DSP_IPC_BASE + 0x28)
 325
 326 /*  HIPCI */
 327 #define CNL_DSP_REG_HIPCIDR_BUSY                BIT(31)
 328 #define CNL_DSP_REG_HIPCIDR_MSG_MASK    0x7FFFFFFF
 329
 330 /* HIPCIE */
 331 #define CNL_DSP_REG_HIPCIDA_DONE        BIT(31)
 332 #define CNL_DSP_REG_HIPCIDA_MSG_MASK    0x7FFFFFFF
 333
 334 /* HIPCCTL */
 335 #define CNL_DSP_REG_HIPCCTL_DONE        BIT(1)
 336 #define CNL_DSP_REG_HIPCCTL_BUSY        BIT(0)
 337
 338 /* HIPCT */
 339 #define CNL_DSP_REG_HIPCTDR_BUSY                BIT(31)
 340 #define CNL_DSP_REG_HIPCTDR_MSG_MASK    0x7FFFFFFF
 341
 342 /* HIPCTDA */
 343 #define CNL_DSP_REG_HIPCTDA_DONE        BIT(31)
 344 #define CNL_DSP_REG_HIPCTDA_MSG_MASK    0x7FFFFFFF
 345
 346 /* HIPCTDD */
 347 #define CNL_DSP_REG_HIPCTDD_MSG_MASK    0x7FFFFFFF
 348
 349 /* BDL */
 350 #define HDA_DSP_BDL_SIZE                        4096
 351 #define HDA_DSP_MAX_BDL_ENTRIES                 \
 352         (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl))
 353
 354 /* Number of DAIs */
 355 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
 356
 357 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
 358 #define SOF_SKL_NUM_DAIS                16
 359 #else
 360 #define SOF_SKL_NUM_DAIS                15
 361 #endif
 362
 363 #else
 364 #define SOF_SKL_NUM_DAIS                8
 365 #endif
 366
 367 /* Intel HD Audio SRAM Window 0*/
 368 #define HDA_ADSP_SRAM0_BASE_SKL         0x8000
 369
 370 /* Firmware status window */
 371 #define HDA_ADSP_FW_STATUS_SKL          HDA_ADSP_SRAM0_BASE_SKL
 372 #define HDA_ADSP_ERROR_CODE_SKL         (HDA_ADSP_FW_STATUS_SKL + 0x4)
 373
 374 /* Host Device Memory Space */
 375 #define APL_SSP_BASE_OFFSET     0x2000
 376 #define CNL_SSP_BASE_OFFSET     0x10000
 377
 378 /* Host Device Memory Size of a Single SSP */
 379 #define SSP_DEV_MEM_SIZE        0x1000
 380
 381 /* SSP Count of the Platform */
 382 #define APL_SSP_COUNT           6
 383 #define CNL_SSP_COUNT           3
 384 #define ICL_SSP_COUNT           6
 385
 386 /* SSP Registers */
 387 #define SSP_SSC1_OFFSET         0x4
 388 #define SSP_SET_SCLK_SLAVE      BIT(25)
 389 #define SSP_SET_SFRM_SLAVE      BIT(24)
 390 #define SSP_SET_SLAVE           (SSP_SET_SCLK_SLAVE | SSP_SET_SFRM_SLAVE)
 391
 392 #define HDA_IDISP_CODEC(x) ((x) & BIT(2))
 393
 394 struct sof_intel_dsp_bdl {
 395         __le32 addr_l;
 396         __le32 addr_h;
 397         __le32 size;
 398         __le32 ioc;
 399 } __attribute((packed));
 400
 401 #define SOF_HDA_PLAYBACK_STREAMS        16
 402 #define SOF_HDA_CAPTURE_STREAMS         16
 403 #define SOF_HDA_PLAYBACK                0
 404 #define SOF_HDA_CAPTURE                 1
 405
 406 /*
 407  * Time in ms for opportunistic D0I3 entry delay.
 408  * This has been deliberately chosen to be long to avoid race conditions.
 409  * Could be optimized in future.
 410  */
 411 #define SOF_HDA_D0I3_WORK_DELAY_MS      5000
 412
 413 /* HDA DSP D0 substate */
 414 enum sof_hda_D0_substate {
 415         SOF_HDA_DSP_PM_D0I0,    /* default D0 substate */
 416         SOF_HDA_DSP_PM_D0I3,    /* low power D0 substate */
 417 };
 418
 419 /* represents DSP HDA controller frontend - i.e. host facing control */
 420 struct sof_intel_hda_dev {
 421
 422         struct hda_bus hbus;
 423
 424         /* hw config */
 425         const struct sof_intel_dsp_desc *desc;
 426
 427         /* trace */
 428         struct hdac_ext_stream *dtrace_stream;
 429
 430         /* if position update IPC needed */
 431         u32 no_ipc_position;
 432
 433         /* the maximum number of streams (playback + capture) supported */
 434         u32 stream_max;
 435
 436         /* PM related */
 437         bool l1_support_changed;/* during suspend, is L1SEN changed or not */
 438
 439         /* DMIC device */
 440         struct platform_device *dmic_dev;
 441
 442         /* delayed work to enter D0I3 opportunistically */
 443         struct delayed_work d0i3_work;
 444
 445         /* ACPI information stored between scan and probe steps */
 446         struct sdw_intel_acpi_info info;
 447
 448         /* sdw context allocated by SoundWire driver */
 449         struct sdw_intel_ctx *sdw;
 450 };
 451
 452 static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s)
 453 {
 454         struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
 455
 456         return &hda->hbus.core;
 457 }
 458
 459 static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s)
 460 {
 461         struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
 462
 463         return &hda->hbus;
 464 }
 465
 466 struct sof_intel_hda_stream {
 467         struct snd_sof_dev *sdev;
 468         struct hdac_ext_stream hda_stream;
 469         struct sof_intel_stream stream;
 470         int host_reserved; /* reserve host DMA channel */
 471 };
 472
 473 #define hstream_to_sof_hda_stream(hstream) \
 474         container_of(hstream, struct sof_intel_hda_stream, hda_stream)
 475
 476 #define bus_to_sof_hda(bus) \
 477         container_of(bus, struct sof_intel_hda_dev, hbus.core)
 478
 479 #define SOF_STREAM_SD_OFFSET(s) \
 480         (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \
 481          + SOF_HDA_ADSP_LOADER_BASE)
 482
 483 /*
 484  * DSP Core services.
 485  */
 486 int hda_dsp_probe(struct snd_sof_dev *sdev);
 487 int hda_dsp_remove(struct snd_sof_dev *sdev);
 488 int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev,
 489                              unsigned int core_mask);
 490 int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev,
 491                              unsigned int core_mask);
 492 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask);
 493 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
 494 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
 495 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
 496 int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask);
 497 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
 498                              unsigned int core_mask);
 499 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
 500                                   unsigned int core_mask);
 501 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev);
 502 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev);
 503
 504 int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
 505                             const struct sof_dsp_power_state *target_state);
 506
 507 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state);
 508 int hda_dsp_resume(struct snd_sof_dev *sdev);
 509 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev);
 510 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
 511 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev);
 512 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev);
 513 void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags);
 514 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
 515 void hda_ipc_dump(struct snd_sof_dev *sdev);
 516 void hda_ipc_irq_dump(struct snd_sof_dev *sdev);
 517 void hda_dsp_d0i3_work(struct work_struct *work);
 518
 519 /*
 520  * DSP PCM Operations.
 521  */
 522 u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate);
 523 u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits);
 524 int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
 525                      struct snd_pcm_substream *substream);
 526 int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
 527                       struct snd_pcm_substream *substream);
 528 int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
 529                           struct snd_pcm_substream *substream,
 530                           struct snd_pcm_hw_params *params,
 531                           struct sof_ipc_stream_params *ipc_params);
 532 int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
 533                            struct snd_pcm_substream *substream);
 534 int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
 535                         struct snd_pcm_substream *substream, int cmd);
 536 snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
 537                                       struct snd_pcm_substream *substream);
 538
 539 /*
 540  * DSP Stream Operations.
 541  */
 542
 543 int hda_dsp_stream_init(struct snd_sof_dev *sdev);
 544 void hda_dsp_stream_free(struct snd_sof_dev *sdev);
 545 int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
 546                              struct hdac_ext_stream *stream,
 547                              struct snd_dma_buffer *dmab,
 548                              struct snd_pcm_hw_params *params);
 549 int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
 550                            struct hdac_ext_stream *stream, int cmd);
 551 irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
 552 int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
 553                              struct snd_dma_buffer *dmab,
 554                              struct hdac_stream *stream);
 555 bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev);
 556 bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev);
 557
 558 struct hdac_ext_stream *
 559         hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction);
 560 int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
 561 int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
 562                                struct hdac_ext_stream *stream,
 563                                int enable, u32 size);
 564
 565 void hda_ipc_msg_data(struct snd_sof_dev *sdev,
 566                       struct snd_pcm_substream *substream,
 567                       void *p, size_t sz);
 568 int hda_ipc_pcm_params(struct snd_sof_dev *sdev,
 569                        struct snd_pcm_substream *substream,
 570                        const struct sof_ipc_pcm_params_reply *reply);
 571
 572 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
 573 /*
 574  * Probe Compress Operations.
 575  */
 576 int hda_probe_compr_assign(struct snd_sof_dev *sdev,
 577                            struct snd_compr_stream *cstream,
 578                            struct snd_soc_dai *dai);
 579 int hda_probe_compr_free(struct snd_sof_dev *sdev,
 580                          struct snd_compr_stream *cstream,
 581                          struct snd_soc_dai *dai);
 582 int hda_probe_compr_set_params(struct snd_sof_dev *sdev,
 583                                struct snd_compr_stream *cstream,
 584                                struct snd_compr_params *params,
 585                                struct snd_soc_dai *dai);
 586 int hda_probe_compr_trigger(struct snd_sof_dev *sdev,
 587                             struct snd_compr_stream *cstream, int cmd,
 588                             struct snd_soc_dai *dai);
 589 int hda_probe_compr_pointer(struct snd_sof_dev *sdev,
 590                             struct snd_compr_stream *cstream,
 591                             struct snd_compr_tstamp *tstamp,
 592                             struct snd_soc_dai *dai);
 593 #endif
 594
 595 /*
 596  * DSP IPC Operations.
 597  */
 598 int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev,
 599                          struct snd_sof_ipc_msg *msg);
 600 void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev);
 601 int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
 602 int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
 603
 604 irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
 605 int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
 606
 607 /*
 608  * DSP Code loader.
 609  */
 610 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev);
 611 int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev);
 612
 613 /* pre and post fw run ops */
 614 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev);
 615 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev);
 616
 617 /*
 618  * HDA Controller Operations.
 619  */
 620 int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
 621 void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable);
 622 void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable);
 623 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset);
 624 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
 625 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
 626 int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset);
 627 void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev);
 628 /*
 629  * HDA bus operations.
 630  */
 631 void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev);
 632
 633 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
 634 /*
 635  * HDA Codec operations.
 636  */
 637 void hda_codec_probe_bus(struct snd_sof_dev *sdev,
 638                          bool hda_codec_use_common_hdmi);
 639 void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev);
 640 void hda_codec_jack_check(struct snd_sof_dev *sdev);
 641
 642 #endif /* CONFIG_SND_SOC_SOF_HDA */
 643
 644 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && \
 645         (IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) || \
 646          IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
 647
 648 void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable);
 649 int hda_codec_i915_init(struct snd_sof_dev *sdev);
 650 int hda_codec_i915_exit(struct snd_sof_dev *sdev);
 651
 652 #else
 653
 654 static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev,
 655                                                 bool enable) { }
 656 static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; }
 657 static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; }
 658
 659 #endif
 660
 661 /*
 662  * Trace Control.
 663  */
 664 int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag);
 665 int hda_dsp_trace_release(struct snd_sof_dev *sdev);
 666 int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
 667
 668 /*
 669  * SoundWire support
 670  */
 671 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
 672
 673 int hda_sdw_startup(struct snd_sof_dev *sdev);
 674 void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable);
 675 void hda_sdw_process_wakeen(struct snd_sof_dev *sdev);
 676
 677 #else
 678
 679 static inline int hda_sdw_acpi_scan(struct snd_sof_dev *sdev)
 680 {
 681         return 0;
 682 }
 683
 684 static inline int hda_sdw_probe(struct snd_sof_dev *sdev)
 685 {
 686         return 0;
 687 }
 688
 689 static inline int hda_sdw_startup(struct snd_sof_dev *sdev)
 690 {
 691         return 0;
 692 }
 693
 694 static inline int hda_sdw_exit(struct snd_sof_dev *sdev)
 695 {
 696         return 0;
 697 }
 698
 699 static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable)
 700 {
 701 }
 702
 703 static inline bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
 704 {
 705         return false;
 706 }
 707
 708 static inline irqreturn_t hda_dsp_sdw_thread(int irq, void *context)
 709 {
 710         return IRQ_HANDLED;
 711 }
 712
 713 static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
 714 {
 715         return false;
 716 }
 717
 718 static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
 719 {
 720 }
 721 #endif
 722
 723 /* common dai driver */
 724 extern struct snd_soc_dai_driver skl_dai[];
 725
 726 /*
 727  * Platform Specific HW abstraction Ops.
 728  */
 729 extern const struct snd_sof_dsp_ops sof_apl_ops;
 730 extern const struct snd_sof_dsp_ops sof_cnl_ops;
 731
 732 extern const struct sof_intel_dsp_desc apl_chip_info;
 733 extern const struct sof_intel_dsp_desc cnl_chip_info;
 734 extern const struct sof_intel_dsp_desc skl_chip_info;
 735 extern const struct sof_intel_dsp_desc icl_chip_info;
 736 extern const struct sof_intel_dsp_desc tgl_chip_info;
 737 extern const struct sof_intel_dsp_desc ehl_chip_info;
 738 extern const struct sof_intel_dsp_desc jsl_chip_info;
 739
 740 /* machine driver select */
 741 void hda_machine_select(struct snd_sof_dev *sdev);
 742 void hda_set_mach_params(const struct snd_soc_acpi_mach *mach,
 743                          struct device *dev);
 744
 745 #endif