2 * Copyright (c) 2009-2010 Intel Corporation
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 * The full GNU General Public License is included in this distribution in
18 * the file called "COPYING".
21 * Jesse Barnes <jbarnes@virtuousgeek.org>
25 * Some Intel Ibex Peak based platforms support so-called "intelligent
26 * power sharing", which allows the CPU and GPU to cooperate to maximize
27 * performance within a given TDP (thermal design point). This driver
28 * performs the coordination between the CPU and GPU, monitors thermal and
29 * power statistics in the platform, and initializes power monitoring
30 * hardware. It also provides a few tunables to control behavior. Its
31 * primary purpose is to safely allow CPU and GPU turbo modes to be enabled
32 * by tracking power and thermal budget; secondarily it can boost turbo
33 * performance by allocating more power or thermal budget to the CPU or GPU
34 * based on available headroom and activity.
36 * The basic algorithm is driven by a 5s moving average of tempurature. If
37 * thermal headroom is available, the CPU and/or GPU power clamps may be
38 * adjusted upwards. If we hit the thermal ceiling or a thermal trigger,
39 * we scale back the clamp. Aside from trigger events (when we're critically
40 * close or over our TDP) we don't adjust the clamps more than once every
43 * The thermal device (device 31, function 6) has a set of registers that
44 * are updated by the ME firmware. The ME should also take the clamp values
45 * written to those registers and write them to the CPU, but we currently
46 * bypass that functionality and write the CPU MSR directly.
52 * - handle CPU hotplug
53 * - provide turbo enable/disable api
56 * - CDI 403777, 403778 - Auburndale EDS vol 1 & 2
57 * - CDI 401376 - Ibex Peak EDS
58 * - ref 26037, 26641 - IPS BIOS spec
59 * - ref 26489 - Nehalem BIOS writer's guide
60 * - ref 26921 - Ibex Peak BIOS Specification
63 #include <linux/debugfs.h>
64 #include <linux/delay.h>
65 #include <linux/interrupt.h>
66 #include <linux/kernel.h>
67 #include <linux/kthread.h>
68 #include <linux/module.h>
69 #include <linux/pci.h>
70 #include <linux/sched.h>
71 #include <linux/seq_file.h>
72 #include <linux/string.h>
73 #include <linux/tick.h>
74 #include <linux/timer.h>
75 #include <drm/i915_drm.h>
77 #include <asm/processor.h>
78 #include "intel_ips.h"
80 #include <asm-generic/io-64-nonatomic-lo-hi.h>
82 #define PCI_DEVICE_ID_INTEL_THERMAL_SENSOR 0x3b32
85 * Package level MSRs for monitor/control
87 #define PLATFORM_INFO 0xce
88 #define PLATFORM_TDP (1<<29)
89 #define PLATFORM_RATIO (1<<28)
91 #define IA32_MISC_ENABLE 0x1a0
92 #define IA32_MISC_TURBO_EN (1ULL<<38)
94 #define TURBO_POWER_CURRENT_LIMIT 0x1ac
95 #define TURBO_TDC_OVR_EN (1UL<<31)
96 #define TURBO_TDC_MASK (0x000000007fff0000UL)
97 #define TURBO_TDC_SHIFT (16)
98 #define TURBO_TDP_OVR_EN (1UL<<15)
99 #define TURBO_TDP_MASK (0x0000000000003fffUL)
102 * Core/thread MSRs for monitoring
104 #define IA32_PERF_CTL 0x199
105 #define IA32_PERF_TURBO_DIS (1ULL<<32)
108 * Thermal PCI device regs
110 #define THM_CFG_TBAR 0x10
111 #define THM_CFG_TBAR_HI 0x14
113 #define THM_TSIU 0x00
117 #define THM_TSTR 0x03
118 #define THM_TSTTP 0x04
119 #define THM_TSCO 0x08
120 #define THM_TSES 0x0c
121 #define THM_TSGPEN 0x0d
122 #define TSGPEN_HOT_LOHI (1<<1)
123 #define TSGPEN_CRIT_LOHI (1<<2)
124 #define THM_TSPC 0x0e
125 #define THM_PPEC 0x10
128 #define PTA_SLOPE_MASK (0xff00)
129 #define PTA_SLOPE_SHIFT 8
130 #define PTA_OFFSET_MASK (0x00ff)
131 #define THM_MGTA 0x16
132 #define MGTA_SLOPE_MASK (0xff00)
133 #define MGTA_SLOPE_SHIFT 8
134 #define MGTA_OFFSET_MASK (0x00ff)
136 #define TRC_CORE2_EN (1<<15)
137 #define TRC_THM_EN (1<<12)
138 #define TRC_C6_WAR (1<<8)
139 #define TRC_CORE1_EN (1<<7)
140 #define TRC_CORE_PWR (1<<6)
141 #define TRC_PCH_EN (1<<5)
142 #define TRC_MCH_EN (1<<4)
143 #define TRC_DIMM4 (1<<3)
144 #define TRC_DIMM3 (1<<2)
145 #define TRC_DIMM2 (1<<1)
146 #define TRC_DIMM1 (1<<0)
149 #define TEN_UPDATE_EN 1
151 #define PSC_NTG (1<<0) /* No GFX turbo support */
152 #define PSC_NTPC (1<<1) /* No CPU turbo support */
153 #define PSC_PP_DEF (0<<2) /* Perf policy up to driver */
154 #define PSP_PP_PC (1<<2) /* BIOS prefers CPU perf */
155 #define PSP_PP_BAL (2<<2) /* BIOS wants balanced perf */
156 #define PSP_PP_GFX (3<<2) /* BIOS prefers GFX perf */
157 #define PSP_PBRT (1<<4) /* BIOS run time support */
158 #define THM_CTV1 0x30
159 #define CTV_TEMP_ERROR (1<<15)
160 #define CTV_TEMP_MASK 0x3f
162 #define THM_CTV2 0x32
163 #define THM_CEC 0x34 /* undocumented power accumulator in joules */
165 #define THM_HTS 0x50 /* 32 bits */
166 #define HTS_PCPL_MASK (0x7fe00000)
167 #define HTS_PCPL_SHIFT 21
168 #define HTS_GPL_MASK (0x001ff000)
169 #define HTS_GPL_SHIFT 12
170 #define HTS_PP_MASK (0x00000c00)
171 #define HTS_PP_SHIFT 10
173 #define HTS_PP_PROC 1
176 #define HTS_PCTD_DIS (1<<9)
177 #define HTS_GTD_DIS (1<<8)
178 #define HTS_PTL_MASK (0x000000fe)
179 #define HTS_PTL_SHIFT 1
180 #define HTS_NVV (1<<0)
181 #define THM_HTSHI 0x54 /* 16 bits */
182 #define HTS2_PPL_MASK (0x03ff)
183 #define HTS2_PRST_MASK (0x3c00)
184 #define HTS2_PRST_SHIFT 10
185 #define HTS2_PRST_UNLOADED 0
186 #define HTS2_PRST_RUNNING 1
187 #define HTS2_PRST_TDISOP 2 /* turbo disabled due to power */
188 #define HTS2_PRST_TDISHT 3 /* turbo disabled due to high temp */
189 #define HTS2_PRST_TDISUSR 4 /* user disabled turbo */
190 #define HTS2_PRST_TDISPLAT 5 /* platform disabled turbo */
191 #define HTS2_PRST_TDISPM 6 /* power management disabled turbo */
192 #define HTS2_PRST_TDISERR 7 /* some kind of error disabled turbo */
194 #define THM_MGTV 0x58
195 #define TV_MASK 0x000000000000ff00
198 #define PTV_MASK 0x00ff
199 #define THM_MMGPC 0x64
200 #define THM_MPPC 0x66
201 #define THM_MPCPC 0x68
202 #define THM_TSPIEN 0x82
203 #define TSPIEN_AUX_LOHI (1<<0)
204 #define TSPIEN_HOT_LOHI (1<<1)
205 #define TSPIEN_CRIT_LOHI (1<<2)
206 #define TSPIEN_AUX2_LOHI (1<<3)
207 #define THM_TSLOCK 0x83
211 #define STS_PCPL_MASK (0x7fe00000)
212 #define STS_PCPL_SHIFT 21
213 #define STS_GPL_MASK (0x001ff000)
214 #define STS_GPL_SHIFT 12
215 #define STS_PP_MASK (0x00000c00)
216 #define STS_PP_SHIFT 10
218 #define STS_PP_PROC 1
221 #define STS_PCTD_DIS (1<<9)
222 #define STS_GTD_DIS (1<<8)
223 #define STS_PTL_MASK (0x000000fe)
224 #define STS_PTL_SHIFT 1
225 #define STS_NVV (1<<0)
227 #define SEC_ACK (1<<0)
230 #define STS_PPL_MASK (0x0003ff00)
231 #define STS_PPL_SHIFT 16
235 #define ITV_ME_SEQNO_MASK 0x00ff0000 /* ME should update every ~200ms */
236 #define ITV_ME_SEQNO_SHIFT (16)
237 #define ITV_MCH_TEMP_MASK 0x0000ff00
238 #define ITV_MCH_TEMP_SHIFT (8)
239 #define ITV_PCH_TEMP_MASK 0x000000ff
241 #define thm_readb(off) readb(ips->regmap + (off))
242 #define thm_readw(off) readw(ips->regmap + (off))
243 #define thm_readl(off) readl(ips->regmap + (off))
244 #define thm_readq(off) readq(ips->regmap + (off))
246 #define thm_writeb(off, val) writeb((val), ips->regmap + (off))
247 #define thm_writew(off, val) writew((val), ips->regmap + (off))
248 #define thm_writel(off, val) writel((val), ips->regmap + (off))
250 static const int IPS_ADJUST_PERIOD
= 5000; /* ms */
251 static bool late_i915_load
= false;
253 /* For initial average collection */
254 static const int IPS_SAMPLE_PERIOD
= 200; /* ms */
255 static const int IPS_SAMPLE_WINDOW
= 5000; /* 5s moving window of samples */
256 #define IPS_SAMPLE_COUNT (IPS_SAMPLE_WINDOW / IPS_SAMPLE_PERIOD)
259 struct ips_mcp_limits
{
261 int cpu_model
; /* includes extended model... */
262 int mcp_power_limit
; /* mW units */
263 int core_power_limit
;
265 int core_temp_limit
; /* degrees C */
269 /* Max temps are -10 degrees C to avoid PROCHOT# */
271 struct ips_mcp_limits ips_sv_limits
= {
272 .mcp_power_limit
= 35000,
273 .core_power_limit
= 29000,
274 .mch_power_limit
= 20000,
275 .core_temp_limit
= 95,
279 struct ips_mcp_limits ips_lv_limits
= {
280 .mcp_power_limit
= 25000,
281 .core_power_limit
= 21000,
282 .mch_power_limit
= 13000,
283 .core_temp_limit
= 95,
287 struct ips_mcp_limits ips_ulv_limits
= {
288 .mcp_power_limit
= 18000,
289 .core_power_limit
= 14000,
290 .mch_power_limit
= 11000,
291 .core_temp_limit
= 95,
298 struct task_struct
*monitor
;
299 struct task_struct
*adjust
;
300 struct dentry
*debug_root
;
302 /* Average CPU core temps (all averages in .01 degrees C for precision) */
307 /* Average for the CPU (both cores?) */
309 /* Average power consumption (in mW) */
318 /* Maximums & prefs, protected by turbo status lock */
319 spinlock_t turbo_status_lock
;
322 u16 core_power_limit
;
324 bool cpu_turbo_enabled
;
326 bool gpu_turbo_enabled
;
329 bool poll_turbo_status
;
331 bool turbo_toggle_allowed
;
332 struct ips_mcp_limits
*limits
;
334 /* Optional MCH interfaces for if i915 is in use */
335 unsigned long (*read_mch_val
)(void);
336 bool (*gpu_raise
)(void);
337 bool (*gpu_lower
)(void);
338 bool (*gpu_busy
)(void);
339 bool (*gpu_turbo_disable
)(void);
341 /* For restoration at unload */
342 u64 orig_turbo_limit
;
343 u64 orig_turbo_ratios
;
347 ips_gpu_turbo_enabled(struct ips_driver
*ips
);
350 * ips_cpu_busy - is CPU busy?
351 * @ips: IPS driver struct
353 * Check CPU for load to see whether we should increase its thermal budget.
356 * True if the CPU could use more power, false otherwise.
358 static bool ips_cpu_busy(struct ips_driver
*ips
)
360 if ((avenrun
[0] >> FSHIFT
) > 1)
367 * ips_cpu_raise - raise CPU power clamp
368 * @ips: IPS driver struct
370 * Raise the CPU power clamp by %IPS_CPU_STEP, in accordance with TDP for
373 * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR upwards (as
374 * long as we haven't hit the TDP limit for the SKU).
376 static void ips_cpu_raise(struct ips_driver
*ips
)
379 u16 cur_tdp_limit
, new_tdp_limit
;
381 if (!ips
->cpu_turbo_enabled
)
384 rdmsrl(TURBO_POWER_CURRENT_LIMIT
, turbo_override
);
386 cur_tdp_limit
= turbo_override
& TURBO_TDP_MASK
;
387 new_tdp_limit
= cur_tdp_limit
+ 8; /* 1W increase */
389 /* Clamp to SKU TDP limit */
390 if (((new_tdp_limit
* 10) / 8) > ips
->core_power_limit
)
391 new_tdp_limit
= cur_tdp_limit
;
393 thm_writew(THM_MPCPC
, (new_tdp_limit
* 10) / 8);
395 turbo_override
|= TURBO_TDC_OVR_EN
| TURBO_TDP_OVR_EN
;
396 wrmsrl(TURBO_POWER_CURRENT_LIMIT
, turbo_override
);
398 turbo_override
&= ~TURBO_TDP_MASK
;
399 turbo_override
|= new_tdp_limit
;
401 wrmsrl(TURBO_POWER_CURRENT_LIMIT
, turbo_override
);
405 * ips_cpu_lower - lower CPU power clamp
406 * @ips: IPS driver struct
408 * Lower CPU power clamp b %IPS_CPU_STEP if possible.
410 * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR down, going
411 * as low as the platform limits will allow (though we could go lower there
412 * wouldn't be much point).
414 static void ips_cpu_lower(struct ips_driver
*ips
)
417 u16 cur_limit
, new_limit
;
419 rdmsrl(TURBO_POWER_CURRENT_LIMIT
, turbo_override
);
421 cur_limit
= turbo_override
& TURBO_TDP_MASK
;
422 new_limit
= cur_limit
- 8; /* 1W decrease */
424 /* Clamp to SKU TDP limit */
425 if (new_limit
< (ips
->orig_turbo_limit
& TURBO_TDP_MASK
))
426 new_limit
= ips
->orig_turbo_limit
& TURBO_TDP_MASK
;
428 thm_writew(THM_MPCPC
, (new_limit
* 10) / 8);
430 turbo_override
|= TURBO_TDC_OVR_EN
| TURBO_TDP_OVR_EN
;
431 wrmsrl(TURBO_POWER_CURRENT_LIMIT
, turbo_override
);
433 turbo_override
&= ~TURBO_TDP_MASK
;
434 turbo_override
|= new_limit
;
436 wrmsrl(TURBO_POWER_CURRENT_LIMIT
, turbo_override
);
440 * do_enable_cpu_turbo - internal turbo enable function
443 * Internal function for actually updating MSRs. When we enable/disable
444 * turbo, we need to do it on each CPU; this function is the one called
445 * by on_each_cpu() when needed.
447 static void do_enable_cpu_turbo(void *data
)
451 rdmsrl(IA32_PERF_CTL
, perf_ctl
);
452 if (perf_ctl
& IA32_PERF_TURBO_DIS
) {
453 perf_ctl
&= ~IA32_PERF_TURBO_DIS
;
454 wrmsrl(IA32_PERF_CTL
, perf_ctl
);
459 * ips_enable_cpu_turbo - enable turbo mode on all CPUs
460 * @ips: IPS driver struct
462 * Enable turbo mode by clearing the disable bit in IA32_PERF_CTL on
463 * all logical threads.
465 static void ips_enable_cpu_turbo(struct ips_driver
*ips
)
467 /* Already on, no need to mess with MSRs */
468 if (ips
->__cpu_turbo_on
)
471 if (ips
->turbo_toggle_allowed
)
472 on_each_cpu(do_enable_cpu_turbo
, ips
, 1);
474 ips
->__cpu_turbo_on
= true;
478 * do_disable_cpu_turbo - internal turbo disable function
481 * Internal function for actually updating MSRs. When we enable/disable
482 * turbo, we need to do it on each CPU; this function is the one called
483 * by on_each_cpu() when needed.
485 static void do_disable_cpu_turbo(void *data
)
489 rdmsrl(IA32_PERF_CTL
, perf_ctl
);
490 if (!(perf_ctl
& IA32_PERF_TURBO_DIS
)) {
491 perf_ctl
|= IA32_PERF_TURBO_DIS
;
492 wrmsrl(IA32_PERF_CTL
, perf_ctl
);
497 * ips_disable_cpu_turbo - disable turbo mode on all CPUs
498 * @ips: IPS driver struct
500 * Disable turbo mode by setting the disable bit in IA32_PERF_CTL on
501 * all logical threads.
503 static void ips_disable_cpu_turbo(struct ips_driver
*ips
)
505 /* Already off, leave it */
506 if (!ips
->__cpu_turbo_on
)
509 if (ips
->turbo_toggle_allowed
)
510 on_each_cpu(do_disable_cpu_turbo
, ips
, 1);
512 ips
->__cpu_turbo_on
= false;
516 * ips_gpu_busy - is GPU busy?
517 * @ips: IPS driver struct
519 * Check GPU for load to see whether we should increase its thermal budget.
520 * We need to call into the i915 driver in this case.
523 * True if the GPU could use more power, false otherwise.
525 static bool ips_gpu_busy(struct ips_driver
*ips
)
527 if (!ips_gpu_turbo_enabled(ips
))
530 return ips
->gpu_busy();
534 * ips_gpu_raise - raise GPU power clamp
535 * @ips: IPS driver struct
537 * Raise the GPU frequency/power if possible. We need to call into the
538 * i915 driver in this case.
540 static void ips_gpu_raise(struct ips_driver
*ips
)
542 if (!ips_gpu_turbo_enabled(ips
))
545 if (!ips
->gpu_raise())
546 ips
->gpu_turbo_enabled
= false;
552 * ips_gpu_lower - lower GPU power clamp
553 * @ips: IPS driver struct
555 * Lower GPU frequency/power if possible. Need to call i915.
557 static void ips_gpu_lower(struct ips_driver
*ips
)
559 if (!ips_gpu_turbo_enabled(ips
))
562 if (!ips
->gpu_lower())
563 ips
->gpu_turbo_enabled
= false;
569 * ips_enable_gpu_turbo - notify the gfx driver turbo is available
570 * @ips: IPS driver struct
572 * Call into the graphics driver indicating that it can safely use
575 static void ips_enable_gpu_turbo(struct ips_driver
*ips
)
577 if (ips
->__gpu_turbo_on
)
579 ips
->__gpu_turbo_on
= true;
583 * ips_disable_gpu_turbo - notify the gfx driver to disable turbo mode
584 * @ips: IPS driver struct
586 * Request that the graphics driver disable turbo mode.
588 static void ips_disable_gpu_turbo(struct ips_driver
*ips
)
590 /* Avoid calling i915 if turbo is already disabled */
591 if (!ips
->__gpu_turbo_on
)
594 if (!ips
->gpu_turbo_disable())
595 dev_err(&ips
->dev
->dev
, "failed to disable graphis turbo\n");
597 ips
->__gpu_turbo_on
= false;
601 * mcp_exceeded - check whether we're outside our thermal & power limits
602 * @ips: IPS driver struct
604 * Check whether the MCP is over its thermal or power budget.
606 static bool mcp_exceeded(struct ips_driver
*ips
)
613 spin_lock_irqsave(&ips
->turbo_status_lock
, flags
);
615 temp_limit
= ips
->mcp_temp_limit
* 100;
616 if (ips
->mcp_avg_temp
> temp_limit
)
619 avg_power
= ips
->cpu_avg_power
+ ips
->mch_avg_power
;
620 if (avg_power
> ips
->mcp_power_limit
)
623 spin_unlock_irqrestore(&ips
->turbo_status_lock
, flags
);
629 * cpu_exceeded - check whether a CPU core is outside its limits
630 * @ips: IPS driver struct
631 * @cpu: CPU number to check
633 * Check a given CPU's average temp or power is over its limit.
635 static bool cpu_exceeded(struct ips_driver
*ips
, int cpu
)
641 spin_lock_irqsave(&ips
->turbo_status_lock
, flags
);
642 avg
= cpu
? ips
->ctv2_avg_temp
: ips
->ctv1_avg_temp
;
643 if (avg
> (ips
->limits
->core_temp_limit
* 100))
645 if (ips
->cpu_avg_power
> ips
->core_power_limit
* 100)
647 spin_unlock_irqrestore(&ips
->turbo_status_lock
, flags
);
650 dev_info(&ips
->dev
->dev
,
651 "CPU power or thermal limit exceeded\n");
657 * mch_exceeded - check whether the GPU is over budget
658 * @ips: IPS driver struct
660 * Check the MCH temp & power against their maximums.
662 static bool mch_exceeded(struct ips_driver
*ips
)
667 spin_lock_irqsave(&ips
->turbo_status_lock
, flags
);
668 if (ips
->mch_avg_temp
> (ips
->limits
->mch_temp_limit
* 100))
670 if (ips
->mch_avg_power
> ips
->mch_power_limit
)
672 spin_unlock_irqrestore(&ips
->turbo_status_lock
, flags
);
678 * verify_limits - verify BIOS provided limits
679 * @ips: IPS structure
681 * BIOS can optionally provide non-default limits for power and temp. Check
682 * them here and use the defaults if the BIOS values are not provided or
683 * are otherwise unusable.
685 static void verify_limits(struct ips_driver
*ips
)
687 if (ips
->mcp_power_limit
< ips
->limits
->mcp_power_limit
||
688 ips
->mcp_power_limit
> 35000)
689 ips
->mcp_power_limit
= ips
->limits
->mcp_power_limit
;
691 if (ips
->mcp_temp_limit
< ips
->limits
->core_temp_limit
||
692 ips
->mcp_temp_limit
< ips
->limits
->mch_temp_limit
||
693 ips
->mcp_temp_limit
> 150)
694 ips
->mcp_temp_limit
= min(ips
->limits
->core_temp_limit
,
695 ips
->limits
->mch_temp_limit
);
699 * update_turbo_limits - get various limits & settings from regs
700 * @ips: IPS driver struct
702 * Update the IPS power & temp limits, along with turbo enable flags,
703 * based on latest register contents.
705 * Used at init time and for runtime BIOS support, which requires polling
706 * the regs for updates (as a result of AC->DC transition for example).
709 * Caller must hold turbo_status_lock (outside of init)
711 static void update_turbo_limits(struct ips_driver
*ips
)
713 u32 hts
= thm_readl(THM_HTS
);
715 ips
->cpu_turbo_enabled
= !(hts
& HTS_PCTD_DIS
);
717 * Disable turbo for now, until we can figure out why the power figures
720 ips
->cpu_turbo_enabled
= false;
723 ips
->gpu_turbo_enabled
= !(hts
& HTS_GTD_DIS
);
725 ips
->core_power_limit
= thm_readw(THM_MPCPC
);
726 ips
->mch_power_limit
= thm_readw(THM_MMGPC
);
727 ips
->mcp_temp_limit
= thm_readw(THM_PTL
);
728 ips
->mcp_power_limit
= thm_readw(THM_MPPC
);
731 /* Ignore BIOS CPU vs GPU pref */
735 * ips_adjust - adjust power clamp based on thermal state
736 * @data: ips driver structure
738 * Wake up every 5s or so and check whether we should adjust the power clamp.
739 * Check CPU and GPU load to determine which needs adjustment. There are
740 * several things to consider here:
741 * - do we need to adjust up or down?
746 * - is CPU or GPU preferred? (CPU is default)
748 * So, given the above, we do the following:
749 * - up (TDP available)
750 * - CPU not busy, GPU not busy - nothing
751 * - CPU busy, GPU not busy - adjust CPU up
752 * - CPU not busy, GPU busy - adjust GPU up
753 * - CPU busy, GPU busy - adjust preferred unit up, taking headroom from
754 * non-preferred unit if necessary
755 * - down (at TDP limit)
756 * - adjust both CPU and GPU down if possible
758 cpu+ gpu+ cpu+gpu- cpu-gpu+ cpu-gpu-
759 cpu < gpu < cpu+gpu+ cpu+ gpu+ nothing
760 cpu < gpu >= cpu+gpu-(mcp<) cpu+gpu-(mcp<) gpu- gpu-
761 cpu >= gpu < cpu-gpu+(mcp<) cpu- cpu-gpu+(mcp<) cpu-
762 cpu >= gpu >= cpu-gpu- cpu-gpu- cpu-gpu- cpu-gpu-
765 static int ips_adjust(void *data
)
767 struct ips_driver
*ips
= data
;
770 dev_dbg(&ips
->dev
->dev
, "starting ips-adjust thread\n");
773 * Adjust CPU and GPU clamps every 5s if needed. Doing it more
774 * often isn't recommended due to ME interaction.
777 bool cpu_busy
= ips_cpu_busy(ips
);
778 bool gpu_busy
= ips_gpu_busy(ips
);
780 spin_lock_irqsave(&ips
->turbo_status_lock
, flags
);
781 if (ips
->poll_turbo_status
)
782 update_turbo_limits(ips
);
783 spin_unlock_irqrestore(&ips
->turbo_status_lock
, flags
);
785 /* Update turbo status if necessary */
786 if (ips
->cpu_turbo_enabled
)
787 ips_enable_cpu_turbo(ips
);
789 ips_disable_cpu_turbo(ips
);
791 if (ips
->gpu_turbo_enabled
)
792 ips_enable_gpu_turbo(ips
);
794 ips_disable_gpu_turbo(ips
);
796 /* We're outside our comfort zone, crank them down */
797 if (mcp_exceeded(ips
)) {
803 if (!cpu_exceeded(ips
, 0) && cpu_busy
)
808 if (!mch_exceeded(ips
) && gpu_busy
)
814 schedule_timeout_interruptible(msecs_to_jiffies(IPS_ADJUST_PERIOD
));
815 } while (!kthread_should_stop());
817 dev_dbg(&ips
->dev
->dev
, "ips-adjust thread stopped\n");
823 * Helpers for reading out temp/power values and calculating their
824 * averages for the decision making and monitoring functions.
827 static u16
calc_avg_temp(struct ips_driver
*ips
, u16
*array
)
833 for (i
= 0; i
< IPS_SAMPLE_COUNT
; i
++)
834 total
+= (u64
)(array
[i
] * 100);
836 do_div(total
, IPS_SAMPLE_COUNT
);
843 static u16
read_mgtv(struct ips_driver
*ips
)
849 val
= thm_readq(THM_MGTV
);
850 val
= (val
& TV_MASK
) >> TV_SHIFT
;
852 slope
= offset
= thm_readw(THM_MGTA
);
853 slope
= (slope
& MGTA_SLOPE_MASK
) >> MGTA_SLOPE_SHIFT
;
854 offset
= offset
& MGTA_OFFSET_MASK
;
856 ret
= ((val
* slope
+ 0x40) >> 7) + offset
;
858 return 0; /* MCH temp reporting buggy */
861 static u16
read_ptv(struct ips_driver
*ips
)
863 u16 val
, slope
, offset
;
865 slope
= (ips
->pta_val
& PTA_SLOPE_MASK
) >> PTA_SLOPE_SHIFT
;
866 offset
= ips
->pta_val
& PTA_OFFSET_MASK
;
868 val
= thm_readw(THM_PTV
) & PTV_MASK
;
873 static u16
read_ctv(struct ips_driver
*ips
, int cpu
)
875 int reg
= cpu
? THM_CTV2
: THM_CTV1
;
878 val
= thm_readw(reg
);
879 if (!(val
& CTV_TEMP_ERROR
))
880 val
= (val
) >> 6; /* discard fractional component */
887 static u32
get_cpu_power(struct ips_driver
*ips
, u32
*last
, int period
)
893 * CEC is in joules/65535. Take difference over time to
896 val
= thm_readl(THM_CEC
);
898 /* period is in ms and we want mW */
899 ret
= (((val
- *last
) * 1000) / period
);
900 ret
= (ret
* 1000) / 65535;
906 static const u16 temp_decay_factor
= 2;
907 static u16
update_average_temp(u16 avg
, u16 val
)
911 /* Multiply by 100 for extra precision */
912 ret
= (val
* 100 / temp_decay_factor
) +
913 (((temp_decay_factor
- 1) * avg
) / temp_decay_factor
);
917 static const u16 power_decay_factor
= 2;
918 static u16
update_average_power(u32 avg
, u32 val
)
922 ret
= (val
/ power_decay_factor
) +
923 (((power_decay_factor
- 1) * avg
) / power_decay_factor
);
928 static u32
calc_avg_power(struct ips_driver
*ips
, u32
*array
)
934 for (i
= 0; i
< IPS_SAMPLE_COUNT
; i
++)
937 do_div(total
, IPS_SAMPLE_COUNT
);
943 static void monitor_timeout(unsigned long arg
)
945 wake_up_process((struct task_struct
*)arg
);
949 * ips_monitor - temp/power monitoring thread
950 * @data: ips driver structure
952 * This is the main function for the IPS driver. It monitors power and
953 * tempurature in the MCP and adjusts CPU and GPU power clams accordingly.
955 * We keep a 5s moving average of power consumption and tempurature. Using
956 * that data, along with CPU vs GPU preference, we adjust the power clamps
959 static int ips_monitor(void *data
)
961 struct ips_driver
*ips
= data
;
962 struct timer_list timer
;
963 unsigned long seqno_timestamp
, expire
, last_msecs
, last_sample_period
;
965 u32
*cpu_samples
, *mchp_samples
, old_cpu_power
;
966 u16
*mcp_samples
, *ctv1_samples
, *ctv2_samples
, *mch_samples
;
967 u8 cur_seqno
, last_seqno
;
969 mcp_samples
= kzalloc(sizeof(u16
) * IPS_SAMPLE_COUNT
, GFP_KERNEL
);
970 ctv1_samples
= kzalloc(sizeof(u16
) * IPS_SAMPLE_COUNT
, GFP_KERNEL
);
971 ctv2_samples
= kzalloc(sizeof(u16
) * IPS_SAMPLE_COUNT
, GFP_KERNEL
);
972 mch_samples
= kzalloc(sizeof(u16
) * IPS_SAMPLE_COUNT
, GFP_KERNEL
);
973 cpu_samples
= kzalloc(sizeof(u32
) * IPS_SAMPLE_COUNT
, GFP_KERNEL
);
974 mchp_samples
= kzalloc(sizeof(u32
) * IPS_SAMPLE_COUNT
, GFP_KERNEL
);
975 if (!mcp_samples
|| !ctv1_samples
|| !ctv2_samples
|| !mch_samples
||
976 !cpu_samples
|| !mchp_samples
) {
977 dev_err(&ips
->dev
->dev
,
978 "failed to allocate sample array, ips disabled\n");
988 last_seqno
= (thm_readl(THM_ITV
) & ITV_ME_SEQNO_MASK
) >>
990 seqno_timestamp
= get_jiffies_64();
992 old_cpu_power
= thm_readl(THM_CEC
);
993 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD
));
995 /* Collect an initial average */
996 for (i
= 0; i
< IPS_SAMPLE_COUNT
; i
++) {
1000 mcp_samples
[i
] = read_ptv(ips
);
1002 val
= read_ctv(ips
, 0);
1003 ctv1_samples
[i
] = val
;
1005 val
= read_ctv(ips
, 1);
1006 ctv2_samples
[i
] = val
;
1008 val
= read_mgtv(ips
);
1009 mch_samples
[i
] = val
;
1011 cpu_power
= get_cpu_power(ips
, &old_cpu_power
,
1013 cpu_samples
[i
] = cpu_power
;
1015 if (ips
->read_mch_val
) {
1016 mchp
= ips
->read_mch_val();
1017 mchp_samples
[i
] = mchp
;
1020 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD
));
1021 if (kthread_should_stop())
1025 ips
->mcp_avg_temp
= calc_avg_temp(ips
, mcp_samples
);
1026 ips
->ctv1_avg_temp
= calc_avg_temp(ips
, ctv1_samples
);
1027 ips
->ctv2_avg_temp
= calc_avg_temp(ips
, ctv2_samples
);
1028 ips
->mch_avg_temp
= calc_avg_temp(ips
, mch_samples
);
1029 ips
->cpu_avg_power
= calc_avg_power(ips
, cpu_samples
);
1030 ips
->mch_avg_power
= calc_avg_power(ips
, mchp_samples
);
1032 kfree(ctv1_samples
);
1033 kfree(ctv2_samples
);
1036 kfree(mchp_samples
);
1038 /* Start the adjustment thread now that we have data */
1039 wake_up_process(ips
->adjust
);
1042 * Ok, now we have an initial avg. From here on out, we track the
1043 * running avg using a decaying average calculation. This allows
1044 * us to reduce the sample frequency if the CPU and GPU are idle.
1046 old_cpu_power
= thm_readl(THM_CEC
);
1047 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD
));
1048 last_sample_period
= IPS_SAMPLE_PERIOD
;
1050 setup_deferrable_timer_on_stack(&timer
, monitor_timeout
,
1051 (unsigned long)current
);
1053 u32 cpu_val
, mch_val
;
1057 val
= read_ptv(ips
);
1058 ips
->mcp_avg_temp
= update_average_temp(ips
->mcp_avg_temp
, val
);
1061 val
= read_ctv(ips
, 0);
1062 ips
->ctv1_avg_temp
=
1063 update_average_temp(ips
->ctv1_avg_temp
, val
);
1065 cpu_val
= get_cpu_power(ips
, &old_cpu_power
,
1066 last_sample_period
);
1067 ips
->cpu_avg_power
=
1068 update_average_power(ips
->cpu_avg_power
, cpu_val
);
1070 if (ips
->second_cpu
) {
1072 val
= read_ctv(ips
, 1);
1073 ips
->ctv2_avg_temp
=
1074 update_average_temp(ips
->ctv2_avg_temp
, val
);
1078 val
= read_mgtv(ips
);
1079 ips
->mch_avg_temp
= update_average_temp(ips
->mch_avg_temp
, val
);
1081 if (ips
->read_mch_val
) {
1082 mch_val
= ips
->read_mch_val();
1083 ips
->mch_avg_power
=
1084 update_average_power(ips
->mch_avg_power
,
1089 * Make sure ME is updating thermal regs.
1091 * If it's been more than a second since the last update,
1092 * the ME is probably hung.
1094 cur_seqno
= (thm_readl(THM_ITV
) & ITV_ME_SEQNO_MASK
) >>
1096 if (cur_seqno
== last_seqno
&&
1097 time_after(jiffies
, seqno_timestamp
+ HZ
)) {
1098 dev_warn(&ips
->dev
->dev
, "ME failed to update for more than 1s, likely hung\n");
1100 seqno_timestamp
= get_jiffies_64();
1101 last_seqno
= cur_seqno
;
1104 last_msecs
= jiffies_to_msecs(jiffies
);
1105 expire
= jiffies
+ msecs_to_jiffies(IPS_SAMPLE_PERIOD
);
1107 __set_current_state(TASK_INTERRUPTIBLE
);
1108 mod_timer(&timer
, expire
);
1111 /* Calculate actual sample period for power averaging */
1112 last_sample_period
= jiffies_to_msecs(jiffies
) - last_msecs
;
1113 if (!last_sample_period
)
1114 last_sample_period
= 1;
1115 } while (!kthread_should_stop());
1117 del_timer_sync(&timer
);
1118 destroy_timer_on_stack(&timer
);
1120 dev_dbg(&ips
->dev
->dev
, "ips-monitor thread stopped\n");
1126 #define THM_DUMPW(reg) \
1128 u16 val = thm_readw(reg); \
1129 dev_dbg(&ips->dev->dev, #reg ": 0x%04x\n", val); \
1131 #define THM_DUMPL(reg) \
1133 u32 val = thm_readl(reg); \
1134 dev_dbg(&ips->dev->dev, #reg ": 0x%08x\n", val); \
1136 #define THM_DUMPQ(reg) \
1138 u64 val = thm_readq(reg); \
1139 dev_dbg(&ips->dev->dev, #reg ": 0x%016x\n", val); \
1142 static void dump_thermal_info(struct ips_driver
*ips
)
1146 ptl
= thm_readw(THM_PTL
);
1147 dev_dbg(&ips
->dev
->dev
, "Processor temp limit: %d\n", ptl
);
1151 THM_DUMPW(THM_CTV1
);
1154 THM_DUMPQ(THM_MGTV
);
1159 * ips_irq_handler - handle temperature triggers and other IPS events
1163 * Handle temperature limit trigger events, generally by lowering the clamps.
1164 * If we're at a critical limit, we clamp back to the lowest possible value
1165 * to prevent emergency shutdown.
1167 static irqreturn_t
ips_irq_handler(int irq
, void *arg
)
1169 struct ips_driver
*ips
= arg
;
1170 u8 tses
= thm_readb(THM_TSES
);
1171 u8 tes
= thm_readb(THM_TES
);
1176 dev_info(&ips
->dev
->dev
, "TSES: 0x%02x\n", tses
);
1177 dev_info(&ips
->dev
->dev
, "TES: 0x%02x\n", tes
);
1179 /* STS update from EC? */
1183 sts
= thm_readl(THM_STS
);
1184 tc1
= thm_readl(THM_TC1
);
1186 if (sts
& STS_NVV
) {
1187 spin_lock(&ips
->turbo_status_lock
);
1188 ips
->core_power_limit
= (sts
& STS_PCPL_MASK
) >>
1190 ips
->mch_power_limit
= (sts
& STS_GPL_MASK
) >>
1192 /* ignore EC CPU vs GPU pref */
1193 ips
->cpu_turbo_enabled
= !(sts
& STS_PCTD_DIS
);
1195 * Disable turbo for now, until we can figure
1196 * out why the power figures are wrong
1198 ips
->cpu_turbo_enabled
= false;
1200 ips
->gpu_turbo_enabled
= !(sts
& STS_GTD_DIS
);
1201 ips
->mcp_temp_limit
= (sts
& STS_PTL_MASK
) >>
1203 ips
->mcp_power_limit
= (tc1
& STS_PPL_MASK
) >>
1206 spin_unlock(&ips
->turbo_status_lock
);
1208 thm_writeb(THM_SEC
, SEC_ACK
);
1210 thm_writeb(THM_TES
, tes
);
1215 dev_warn(&ips
->dev
->dev
,
1216 "thermal trip occurred, tses: 0x%04x\n", tses
);
1217 thm_writeb(THM_TSES
, tses
);
1223 #ifndef CONFIG_DEBUG_FS
1224 static void ips_debugfs_init(struct ips_driver
*ips
) { return; }
1225 static void ips_debugfs_cleanup(struct ips_driver
*ips
) { return; }
1228 /* Expose current state and limits in debugfs if possible */
1230 struct ips_debugfs_node
{
1231 struct ips_driver
*ips
;
1233 int (*show
)(struct seq_file
*m
, void *data
);
1236 static int show_cpu_temp(struct seq_file
*m
, void *data
)
1238 struct ips_driver
*ips
= m
->private;
1240 seq_printf(m
, "%d.%02d\n", ips
->ctv1_avg_temp
/ 100,
1241 ips
->ctv1_avg_temp
% 100);
1246 static int show_cpu_power(struct seq_file
*m
, void *data
)
1248 struct ips_driver
*ips
= m
->private;
1250 seq_printf(m
, "%dmW\n", ips
->cpu_avg_power
);
1255 static int show_cpu_clamp(struct seq_file
*m
, void *data
)
1260 rdmsrl(TURBO_POWER_CURRENT_LIMIT
, turbo_override
);
1262 tdp
= (int)(turbo_override
& TURBO_TDP_MASK
);
1263 tdc
= (int)((turbo_override
& TURBO_TDC_MASK
) >> TURBO_TDC_SHIFT
);
1265 /* Convert to .1W/A units */
1270 seq_printf(m
, "%d.%dW %d.%dA\n", tdp
/ 10, tdp
% 10,
1271 tdc
/ 10, tdc
% 10);
1276 static int show_mch_temp(struct seq_file
*m
, void *data
)
1278 struct ips_driver
*ips
= m
->private;
1280 seq_printf(m
, "%d.%02d\n", ips
->mch_avg_temp
/ 100,
1281 ips
->mch_avg_temp
% 100);
1286 static int show_mch_power(struct seq_file
*m
, void *data
)
1288 struct ips_driver
*ips
= m
->private;
1290 seq_printf(m
, "%dmW\n", ips
->mch_avg_power
);
1295 static struct ips_debugfs_node ips_debug_files
[] = {
1296 { NULL
, "cpu_temp", show_cpu_temp
},
1297 { NULL
, "cpu_power", show_cpu_power
},
1298 { NULL
, "cpu_clamp", show_cpu_clamp
},
1299 { NULL
, "mch_temp", show_mch_temp
},
1300 { NULL
, "mch_power", show_mch_power
},
1303 static int ips_debugfs_open(struct inode
*inode
, struct file
*file
)
1305 struct ips_debugfs_node
*node
= inode
->i_private
;
1307 return single_open(file
, node
->show
, node
->ips
);
1310 static const struct file_operations ips_debugfs_ops
= {
1311 .owner
= THIS_MODULE
,
1312 .open
= ips_debugfs_open
,
1314 .llseek
= seq_lseek
,
1315 .release
= single_release
,
1318 static void ips_debugfs_cleanup(struct ips_driver
*ips
)
1320 if (ips
->debug_root
)
1321 debugfs_remove_recursive(ips
->debug_root
);
1325 static void ips_debugfs_init(struct ips_driver
*ips
)
1329 ips
->debug_root
= debugfs_create_dir("ips", NULL
);
1330 if (!ips
->debug_root
) {
1331 dev_err(&ips
->dev
->dev
,
1332 "failed to create debugfs entries: %ld\n",
1333 PTR_ERR(ips
->debug_root
));
1337 for (i
= 0; i
< ARRAY_SIZE(ips_debug_files
); i
++) {
1339 struct ips_debugfs_node
*node
= &ips_debug_files
[i
];
1342 ent
= debugfs_create_file(node
->name
, S_IFREG
| S_IRUGO
,
1343 ips
->debug_root
, node
,
1346 dev_err(&ips
->dev
->dev
,
1347 "failed to create debug file: %ld\n",
1356 ips_debugfs_cleanup(ips
);
1359 #endif /* CONFIG_DEBUG_FS */
1362 * ips_detect_cpu - detect whether CPU supports IPS
1364 * Walk our list and see if we're on a supported CPU. If we find one,
1365 * return the limits for it.
1367 static struct ips_mcp_limits
*ips_detect_cpu(struct ips_driver
*ips
)
1369 u64 turbo_power
, misc_en
;
1370 struct ips_mcp_limits
*limits
= NULL
;
1373 if (!(boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
== 37)) {
1374 dev_info(&ips
->dev
->dev
, "Non-IPS CPU detected.\n");
1378 rdmsrl(IA32_MISC_ENABLE
, misc_en
);
1380 * If the turbo enable bit isn't set, we shouldn't try to enable/disable
1381 * turbo manually or we'll get an illegal MSR access, even though
1382 * turbo will still be available.
1384 if (misc_en
& IA32_MISC_TURBO_EN
)
1385 ips
->turbo_toggle_allowed
= true;
1387 ips
->turbo_toggle_allowed
= false;
1389 if (strstr(boot_cpu_data
.x86_model_id
, "CPU M"))
1390 limits
= &ips_sv_limits
;
1391 else if (strstr(boot_cpu_data
.x86_model_id
, "CPU L"))
1392 limits
= &ips_lv_limits
;
1393 else if (strstr(boot_cpu_data
.x86_model_id
, "CPU U"))
1394 limits
= &ips_ulv_limits
;
1396 dev_info(&ips
->dev
->dev
, "No CPUID match found.\n");
1400 rdmsrl(TURBO_POWER_CURRENT_LIMIT
, turbo_power
);
1401 tdp
= turbo_power
& TURBO_TDP_MASK
;
1403 /* Sanity check TDP against CPU */
1404 if (limits
->core_power_limit
!= (tdp
/ 8) * 1000) {
1405 dev_info(&ips
->dev
->dev
, "CPU TDP doesn't match expected value (found %d, expected %d)\n",
1406 tdp
/ 8, limits
->core_power_limit
/ 1000);
1407 limits
->core_power_limit
= (tdp
/ 8) * 1000;
1415 * ips_get_i915_syms - try to get GPU control methods from i915 driver
1418 * The i915 driver exports several interfaces to allow the IPS driver to
1419 * monitor and control graphics turbo mode. If we can find them, we can
1420 * enable graphics turbo, otherwise we must disable it to avoid exceeding
1421 * thermal and power limits in the MCP.
1423 static bool ips_get_i915_syms(struct ips_driver
*ips
)
1425 ips
->read_mch_val
= symbol_get(i915_read_mch_val
);
1426 if (!ips
->read_mch_val
)
1428 ips
->gpu_raise
= symbol_get(i915_gpu_raise
);
1429 if (!ips
->gpu_raise
)
1431 ips
->gpu_lower
= symbol_get(i915_gpu_lower
);
1432 if (!ips
->gpu_lower
)
1434 ips
->gpu_busy
= symbol_get(i915_gpu_busy
);
1437 ips
->gpu_turbo_disable
= symbol_get(i915_gpu_turbo_disable
);
1438 if (!ips
->gpu_turbo_disable
)
1444 symbol_put(i915_gpu_busy
);
1446 symbol_put(i915_gpu_lower
);
1448 symbol_put(i915_gpu_raise
);
1450 symbol_put(i915_read_mch_val
);
1456 ips_gpu_turbo_enabled(struct ips_driver
*ips
)
1458 if (!ips
->gpu_busy
&& late_i915_load
) {
1459 if (ips_get_i915_syms(ips
)) {
1460 dev_info(&ips
->dev
->dev
,
1461 "i915 driver attached, reenabling gpu turbo\n");
1462 ips
->gpu_turbo_enabled
= !(thm_readl(THM_HTS
) & HTS_GTD_DIS
);
1466 return ips
->gpu_turbo_enabled
;
1470 ips_link_to_i915_driver(void)
1472 /* We can't cleanly get at the various ips_driver structs from
1473 * this caller (the i915 driver), so just set a flag saying
1474 * that it's time to try getting the symbols again.
1476 late_i915_load
= true;
1478 EXPORT_SYMBOL_GPL(ips_link_to_i915_driver
);
1480 static DEFINE_PCI_DEVICE_TABLE(ips_id_table
) = {
1481 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
,
1482 PCI_DEVICE_ID_INTEL_THERMAL_SENSOR
), },
1486 MODULE_DEVICE_TABLE(pci
, ips_id_table
);
1488 static int ips_probe(struct pci_dev
*dev
, const struct pci_device_id
*id
)
1491 struct ips_driver
*ips
;
1494 u16 htshi
, trc
, trc_required_mask
;
1497 ips
= kzalloc(sizeof(struct ips_driver
), GFP_KERNEL
);
1501 pci_set_drvdata(dev
, ips
);
1504 ips
->limits
= ips_detect_cpu(ips
);
1506 dev_info(&dev
->dev
, "IPS not supported on this CPU\n");
1511 spin_lock_init(&ips
->turbo_status_lock
);
1513 ret
= pci_enable_device(dev
);
1515 dev_err(&dev
->dev
, "can't enable PCI device, aborting\n");
1519 if (!pci_resource_start(dev
, 0)) {
1520 dev_err(&dev
->dev
, "TBAR not assigned, aborting\n");
1525 ret
= pci_request_regions(dev
, "ips thermal sensor");
1527 dev_err(&dev
->dev
, "thermal resource busy, aborting\n");
1532 ips
->regmap
= ioremap(pci_resource_start(dev
, 0),
1533 pci_resource_len(dev
, 0));
1535 dev_err(&dev
->dev
, "failed to map thermal regs, aborting\n");
1540 tse
= thm_readb(THM_TSE
);
1541 if (tse
!= TSE_EN
) {
1542 dev_err(&dev
->dev
, "thermal device not enabled (0x%02x), aborting\n", tse
);
1547 trc
= thm_readw(THM_TRC
);
1548 trc_required_mask
= TRC_CORE1_EN
| TRC_CORE_PWR
| TRC_MCH_EN
;
1549 if ((trc
& trc_required_mask
) != trc_required_mask
) {
1550 dev_err(&dev
->dev
, "thermal reporting for required devices not enabled, aborting\n");
1555 if (trc
& TRC_CORE2_EN
)
1556 ips
->second_cpu
= true;
1558 update_turbo_limits(ips
);
1559 dev_dbg(&dev
->dev
, "max cpu power clamp: %dW\n",
1560 ips
->mcp_power_limit
/ 10);
1561 dev_dbg(&dev
->dev
, "max core power clamp: %dW\n",
1562 ips
->core_power_limit
/ 10);
1563 /* BIOS may update limits at runtime */
1564 if (thm_readl(THM_PSC
) & PSP_PBRT
)
1565 ips
->poll_turbo_status
= true;
1567 if (!ips_get_i915_syms(ips
)) {
1568 dev_info(&dev
->dev
, "failed to get i915 symbols, graphics turbo disabled until i915 loads\n");
1569 ips
->gpu_turbo_enabled
= false;
1571 dev_dbg(&dev
->dev
, "graphics turbo enabled\n");
1572 ips
->gpu_turbo_enabled
= true;
1576 * Check PLATFORM_INFO MSR to make sure this chip is
1579 rdmsrl(PLATFORM_INFO
, platform_info
);
1580 if (!(platform_info
& PLATFORM_TDP
)) {
1581 dev_err(&dev
->dev
, "platform indicates TDP override unavailable, aborting\n");
1587 * IRQ handler for ME interaction
1588 * Note: don't use MSI here as the PCH has bugs.
1590 pci_disable_msi(dev
);
1591 ret
= request_irq(dev
->irq
, ips_irq_handler
, IRQF_SHARED
, "ips",
1594 dev_err(&dev
->dev
, "request irq failed, aborting\n");
1598 /* Enable aux, hot & critical interrupts */
1599 thm_writeb(THM_TSPIEN
, TSPIEN_AUX2_LOHI
| TSPIEN_CRIT_LOHI
|
1600 TSPIEN_HOT_LOHI
| TSPIEN_AUX_LOHI
);
1601 thm_writeb(THM_TEN
, TEN_UPDATE_EN
);
1603 /* Collect adjustment values */
1604 ips
->cta_val
= thm_readw(THM_CTA
);
1605 ips
->pta_val
= thm_readw(THM_PTA
);
1606 ips
->mgta_val
= thm_readw(THM_MGTA
);
1608 /* Save turbo limits & ratios */
1609 rdmsrl(TURBO_POWER_CURRENT_LIMIT
, ips
->orig_turbo_limit
);
1611 ips_disable_cpu_turbo(ips
);
1612 ips
->cpu_turbo_enabled
= false;
1614 /* Create thermal adjust thread */
1615 ips
->adjust
= kthread_create(ips_adjust
, ips
, "ips-adjust");
1616 if (IS_ERR(ips
->adjust
)) {
1618 "failed to create thermal adjust thread, aborting\n");
1620 goto error_free_irq
;
1625 * Set up the work queue and monitor thread. The monitor thread
1626 * will wake up ips_adjust thread.
1628 ips
->monitor
= kthread_run(ips_monitor
, ips
, "ips-monitor");
1629 if (IS_ERR(ips
->monitor
)) {
1631 "failed to create thermal monitor thread, aborting\n");
1633 goto error_thread_cleanup
;
1636 hts
= (ips
->core_power_limit
<< HTS_PCPL_SHIFT
) |
1637 (ips
->mcp_temp_limit
<< HTS_PTL_SHIFT
) | HTS_NVV
;
1638 htshi
= HTS2_PRST_RUNNING
<< HTS2_PRST_SHIFT
;
1640 thm_writew(THM_HTSHI
, htshi
);
1641 thm_writel(THM_HTS
, hts
);
1643 ips_debugfs_init(ips
);
1645 dev_info(&dev
->dev
, "IPS driver initialized, MCP temp limit %d\n",
1646 ips
->mcp_temp_limit
);
1649 error_thread_cleanup
:
1650 kthread_stop(ips
->adjust
);
1652 free_irq(ips
->dev
->irq
, ips
);
1654 iounmap(ips
->regmap
);
1656 pci_release_regions(dev
);
1662 static void ips_remove(struct pci_dev
*dev
)
1664 struct ips_driver
*ips
= pci_get_drvdata(dev
);
1670 ips_debugfs_cleanup(ips
);
1672 /* Release i915 driver */
1673 if (ips
->read_mch_val
)
1674 symbol_put(i915_read_mch_val
);
1676 symbol_put(i915_gpu_raise
);
1678 symbol_put(i915_gpu_lower
);
1680 symbol_put(i915_gpu_busy
);
1681 if (ips
->gpu_turbo_disable
)
1682 symbol_put(i915_gpu_turbo_disable
);
1684 rdmsrl(TURBO_POWER_CURRENT_LIMIT
, turbo_override
);
1685 turbo_override
&= ~(TURBO_TDC_OVR_EN
| TURBO_TDP_OVR_EN
);
1686 wrmsrl(TURBO_POWER_CURRENT_LIMIT
, turbo_override
);
1687 wrmsrl(TURBO_POWER_CURRENT_LIMIT
, ips
->orig_turbo_limit
);
1689 free_irq(ips
->dev
->irq
, ips
);
1691 kthread_stop(ips
->adjust
);
1693 kthread_stop(ips
->monitor
);
1694 iounmap(ips
->regmap
);
1695 pci_release_regions(dev
);
1697 dev_dbg(&dev
->dev
, "IPS driver removed\n");
1701 static int ips_suspend(struct pci_dev
*dev
, pm_message_t state
)
1706 static int ips_resume(struct pci_dev
*dev
)
1711 #define ips_suspend NULL
1712 #define ips_resume NULL
1713 #endif /* CONFIG_PM */
1715 static void ips_shutdown(struct pci_dev
*dev
)
1719 static struct pci_driver ips_pci_driver
= {
1720 .name
= "intel ips",
1721 .id_table
= ips_id_table
,
1723 .remove
= ips_remove
,
1724 .suspend
= ips_suspend
,
1725 .resume
= ips_resume
,
1726 .shutdown
= ips_shutdown
,
1729 static int __init
ips_init(void)
1731 return pci_register_driver(&ips_pci_driver
);
1733 module_init(ips_init
);
1735 static void ips_exit(void)
1737 pci_unregister_driver(&ips_pci_driver
);
1740 module_exit(ips_exit
);
1742 MODULE_LICENSE("GPL");
1743 MODULE_AUTHOR("Jesse Barnes <jbarnes@virtuousgeek.org>");
1744 MODULE_DESCRIPTION("Intelligent Power Sharing Driver");