drivers/spi/spi-fsl-dspi.c

   1 /*
   2  * drivers/spi/spi-fsl-dspi.c
   3  *
   4  * Copyright 2013 Freescale Semiconductor, Inc.
   5  *
   6  * Freescale DSPI driver
   7  * This file contains a driver for the Freescale DSPI
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/errno.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/regmap.h>
  22 #include <linux/sched.h>
  23 #include <linux/delay.h>
  24 #include <linux/io.h>
  25 #include <linux/clk.h>
  26 #include <linux/err.h>
  27 #include <linux/spi/spi.h>
  28 #include <linux/spi/spi_bitbang.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32
  33 #define DRIVER_NAME "fsl-dspi"
  34
  35 #define TRAN_STATE_RX_VOID              0x01
  36 #define TRAN_STATE_TX_VOID              0x02
  37 #define TRAN_STATE_WORD_ODD_NUM 0x04
  38
  39 #define DSPI_FIFO_SIZE                  4
  40
  41 #define SPI_MCR         0x00
  42 #define SPI_MCR_MASTER          (1 << 31)
  43 #define SPI_MCR_PCSIS           (0x3F << 16)
  44 #define SPI_MCR_CLR_TXF (1 << 11)
  45 #define SPI_MCR_CLR_RXF (1 << 10)
  46
  47 #define SPI_TCR                 0x08
  48
  49 #define SPI_CTAR(x)             (0x0c + (((x) & 0x3) * 4))
  50 #define SPI_CTAR_FMSZ(x)        (((x) & 0x0000000f) << 27)
  51 #define SPI_CTAR_CPOL(x)        ((x) << 26)
  52 #define SPI_CTAR_CPHA(x)        ((x) << 25)
  53 #define SPI_CTAR_LSBFE(x)       ((x) << 24)
  54 #define SPI_CTAR_PCSSCR(x)      (((x) & 0x00000003) << 22)
  55 #define SPI_CTAR_PASC(x)        (((x) & 0x00000003) << 20)
  56 #define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
  57 #define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
  58 #define SPI_CTAR_CSSCK(x)       (((x) & 0x0000000f) << 12)
  59 #define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
  60 #define SPI_CTAR_DT(x)          (((x) & 0x0000000f) << 4)
  61 #define SPI_CTAR_BR(x)          ((x) & 0x0000000f)
  62
  63 #define SPI_CTAR0_SLAVE 0x0c
  64
  65 #define SPI_SR                  0x2c
  66 #define SPI_SR_EOQF             0x10000000
  67
  68 #define SPI_RSER                0x30
  69 #define SPI_RSER_EOQFE          0x10000000
  70
  71 #define SPI_PUSHR               0x34
  72 #define SPI_PUSHR_CONT          (1 << 31)
  73 #define SPI_PUSHR_CTAS(x)       (((x) & 0x00000003) << 28)
  74 #define SPI_PUSHR_EOQ           (1 << 27)
  75 #define SPI_PUSHR_CTCNT (1 << 26)
  76 #define SPI_PUSHR_PCS(x)        (((1 << x) & 0x0000003f) << 16)
  77 #define SPI_PUSHR_TXDATA(x)     ((x) & 0x0000ffff)
  78
  79 #define SPI_PUSHR_SLAVE 0x34
  80
  81 #define SPI_POPR                0x38
  82 #define SPI_POPR_RXDATA(x)      ((x) & 0x0000ffff)
  83
  84 #define SPI_TXFR0               0x3c
  85 #define SPI_TXFR1               0x40
  86 #define SPI_TXFR2               0x44
  87 #define SPI_TXFR3               0x48
  88 #define SPI_RXFR0               0x7c
  89 #define SPI_RXFR1               0x80
  90 #define SPI_RXFR2               0x84
  91 #define SPI_RXFR3               0x88
  92
  93 #define SPI_FRAME_BITS(bits)    SPI_CTAR_FMSZ((bits) - 1)
  94 #define SPI_FRAME_BITS_MASK     SPI_CTAR_FMSZ(0xf)
  95 #define SPI_FRAME_BITS_16       SPI_CTAR_FMSZ(0xf)
  96 #define SPI_FRAME_BITS_8        SPI_CTAR_FMSZ(0x7)
  97
  98 #define SPI_CS_INIT             0x01
  99 #define SPI_CS_ASSERT           0x02
 100 #define SPI_CS_DROP             0x04
 101
 102 struct chip_data {
 103         u32 mcr_val;
 104         u32 ctar_val;
 105         u16 void_write_data;
 106 };
 107
 108 struct fsl_dspi {
 109         struct spi_bitbang      bitbang;
 110         struct platform_device  *pdev;
 111
 112         struct regmap           *regmap;
 113         int                     irq;
 114         struct clk              *clk;
 115
 116         struct spi_transfer     *cur_transfer;
 117         struct chip_data        *cur_chip;
 118         size_t                  len;
 119         void                    *tx;
 120         void                    *tx_end;
 121         void                    *rx;
 122         void                    *rx_end;
 123         char                    dataflags;
 124         u8                      cs;
 125         u16                     void_write_data;
 126
 127         wait_queue_head_t       waitq;
 128         u32                     waitflags;
 129 };
 130
 131 static inline int is_double_byte_mode(struct fsl_dspi *dspi)
 132 {
 133         unsigned int val;
 134
 135         regmap_read(dspi->regmap, SPI_CTAR(dspi->cs), &val);
 136
 137         return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
 138 }
 139
 140 static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
 141                 unsigned long clkrate)
 142 {
 143         /* Valid baud rate pre-scaler values */
 144         int pbr_tbl[4] = {2, 3, 5, 7};
 145         int brs[16] = { 2,      4,      6,      8,
 146                 16,     32,     64,     128,
 147                 256,    512,    1024,   2048,
 148                 4096,   8192,   16384,  32768 };
 149         int temp, i = 0, j = 0;
 150
 151         temp = clkrate / 2 / speed_hz;
 152
 153         for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
 154                 for (j = 0; j < ARRAY_SIZE(brs); j++) {
 155                         if (pbr_tbl[i] * brs[j] >= temp) {
 156                                 *pbr = i;
 157                                 *br = j;
 158                                 return;
 159                         }
 160                 }
 161
 162         pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld\
 163                 ,we use the max prescaler value.\n", speed_hz, clkrate);
 164         *pbr = ARRAY_SIZE(pbr_tbl) - 1;
 165         *br =  ARRAY_SIZE(brs) - 1;
 166 }
 167
 168 static int dspi_transfer_write(struct fsl_dspi *dspi)
 169 {
 170         int tx_count = 0;
 171         int tx_word;
 172         u16 d16;
 173         u8  d8;
 174         u32 dspi_pushr = 0;
 175         int first = 1;
 176
 177         tx_word = is_double_byte_mode(dspi);
 178
 179         /* If we are in word mode, but only have a single byte to transfer
 180          * then switch to byte mode temporarily.  Will switch back at the
 181          * end of the transfer.
 182          */
 183         if (tx_word && (dspi->len == 1)) {
 184                 dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
 185                 regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
 186                                 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
 187                 tx_word = 0;
 188         }
 189
 190         while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) {
 191                 if (tx_word) {
 192                         if (dspi->len == 1)
 193                                 break;
 194
 195                         if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
 196                                 d16 = *(u16 *)dspi->tx;
 197                                 dspi->tx += 2;
 198                         } else {
 199                                 d16 = dspi->void_write_data;
 200                         }
 201
 202                         dspi_pushr = SPI_PUSHR_TXDATA(d16) |
 203                                 SPI_PUSHR_PCS(dspi->cs) |
 204                                 SPI_PUSHR_CTAS(dspi->cs) |
 205                                 SPI_PUSHR_CONT;
 206
 207                         dspi->len -= 2;
 208                 } else {
 209                         if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
 210
 211                                 d8 = *(u8 *)dspi->tx;
 212                                 dspi->tx++;
 213                         } else {
 214                                 d8 = (u8)dspi->void_write_data;
 215                         }
 216
 217                         dspi_pushr = SPI_PUSHR_TXDATA(d8) |
 218                                 SPI_PUSHR_PCS(dspi->cs) |
 219                                 SPI_PUSHR_CTAS(dspi->cs) |
 220                                 SPI_PUSHR_CONT;
 221
 222                         dspi->len--;
 223                 }
 224
 225                 if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) {
 226                         /* last transfer in the transfer */
 227                         dspi_pushr |= SPI_PUSHR_EOQ;
 228                 } else if (tx_word && (dspi->len == 1))
 229                         dspi_pushr |= SPI_PUSHR_EOQ;
 230
 231                 if (first) {
 232                         first = 0;
 233                         dspi_pushr |= SPI_PUSHR_CTCNT; /* clear counter */
 234                 }
 235
 236                 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
 237
 238                 tx_count++;
 239         }
 240
 241         return tx_count * (tx_word + 1);
 242 }
 243
 244 static int dspi_transfer_read(struct fsl_dspi *dspi)
 245 {
 246         int rx_count = 0;
 247         int rx_word = is_double_byte_mode(dspi);
 248         u16 d;
 249         while ((dspi->rx < dspi->rx_end)
 250                         && (rx_count < DSPI_FIFO_SIZE)) {
 251                 if (rx_word) {
 252                         unsigned int val;
 253
 254                         if ((dspi->rx_end - dspi->rx) == 1)
 255                                 break;
 256
 257                         regmap_read(dspi->regmap, SPI_POPR, &val);
 258                         d = SPI_POPR_RXDATA(val);
 259
 260                         if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
 261                                 *(u16 *)dspi->rx = d;
 262                         dspi->rx += 2;
 263
 264                 } else {
 265                         unsigned int val;
 266
 267                         regmap_read(dspi->regmap, SPI_POPR, &val);
 268                         d = SPI_POPR_RXDATA(val);
 269                         if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
 270                                 *(u8 *)dspi->rx = d;
 271                         dspi->rx++;
 272                 }
 273                 rx_count++;
 274         }
 275
 276         return rx_count;
 277 }
 278
 279 static int dspi_txrx_transfer(struct spi_device *spi, struct spi_transfer *t)
 280 {
 281         struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
 282         dspi->cur_transfer = t;
 283         dspi->cur_chip = spi_get_ctldata(spi);
 284         dspi->cs = spi->chip_select;
 285         dspi->void_write_data = dspi->cur_chip->void_write_data;
 286
 287         dspi->dataflags = 0;
 288         dspi->tx = (void *)t->tx_buf;
 289         dspi->tx_end = dspi->tx + t->len;
 290         dspi->rx = t->rx_buf;
 291         dspi->rx_end = dspi->rx + t->len;
 292         dspi->len = t->len;
 293
 294         if (!dspi->rx)
 295                 dspi->dataflags |= TRAN_STATE_RX_VOID;
 296
 297         if (!dspi->tx)
 298                 dspi->dataflags |= TRAN_STATE_TX_VOID;
 299
 300         regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
 301         regmap_write(dspi->regmap, SPI_CTAR(dspi->cs), dspi->cur_chip->ctar_val);
 302         regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
 303
 304         if (t->speed_hz)
 305                 regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
 306                                 dspi->cur_chip->ctar_val);
 307
 308         dspi_transfer_write(dspi);
 309
 310         if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
 311                 dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
 312         dspi->waitflags = 0;
 313
 314         return t->len - dspi->len;
 315 }
 316
 317 static void dspi_chipselect(struct spi_device *spi, int value)
 318 {
 319         struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
 320         unsigned int pushr;
 321
 322         regmap_read(dspi->regmap, SPI_PUSHR, &pushr);
 323
 324         switch (value) {
 325         case BITBANG_CS_ACTIVE:
 326                 pushr |= SPI_PUSHR_CONT;
 327                 break;
 328         case BITBANG_CS_INACTIVE:
 329                 pushr &= ~SPI_PUSHR_CONT;
 330                 break;
 331         }
 332
 333         regmap_write(dspi->regmap, SPI_PUSHR, pushr);
 334 }
 335
 336 static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 337 {
 338         struct chip_data *chip;
 339         struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
 340         unsigned char br = 0, pbr = 0, fmsz = 0;
 341
 342         /* Only alloc on first setup */
 343         chip = spi_get_ctldata(spi);
 344         if (chip == NULL) {
 345                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 346                 if (!chip)
 347                         return -ENOMEM;
 348         }
 349
 350         chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS |
 351                 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;
 352         if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
 353                 fmsz = spi->bits_per_word - 1;
 354         } else {
 355                 pr_err("Invalid wordsize\n");
 356                 return -ENODEV;
 357         }
 358
 359         chip->void_write_data = 0;
 360
 361         hz_to_spi_baud(&pbr, &br,
 362                         spi->max_speed_hz, clk_get_rate(dspi->clk));
 363
 364         chip->ctar_val =  SPI_CTAR_FMSZ(fmsz)
 365                 | SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
 366                 | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
 367                 | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
 368                 | SPI_CTAR_PBR(pbr)
 369                 | SPI_CTAR_BR(br);
 370
 371         spi_set_ctldata(spi, chip);
 372
 373         return 0;
 374 }
 375
 376 static int dspi_setup(struct spi_device *spi)
 377 {
 378         if (!spi->max_speed_hz)
 379                 return -EINVAL;
 380
 381         return dspi_setup_transfer(spi, NULL);
 382 }
 383
 384 static void dspi_cleanup(struct spi_device *spi)
 385 {
 386         struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
 387
 388         dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
 389                         spi->master->bus_num, spi->chip_select);
 390
 391         kfree(chip);
 392 }
 393
 394 static irqreturn_t dspi_interrupt(int irq, void *dev_id)
 395 {
 396         struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
 397
 398         regmap_write(dspi->regmap, SPI_SR, SPI_SR_EOQF);
 399
 400         dspi_transfer_read(dspi);
 401
 402         if (!dspi->len) {
 403                 if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
 404                         regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
 405                                 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(16));
 406
 407                 dspi->waitflags = 1;
 408                 wake_up_interruptible(&dspi->waitq);
 409         } else {
 410                 dspi_transfer_write(dspi);
 411
 412                 return IRQ_HANDLED;
 413         }
 414
 415         return IRQ_HANDLED;
 416 }
 417
 418 static const struct of_device_id fsl_dspi_dt_ids[] = {
 419         { .compatible = "fsl,vf610-dspi", .data = NULL, },
 420         { /* sentinel */ }
 421 };
 422 MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
 423
 424 #ifdef CONFIG_PM_SLEEP
 425 static int dspi_suspend(struct device *dev)
 426 {
 427         struct spi_master *master = dev_get_drvdata(dev);
 428         struct fsl_dspi *dspi = spi_master_get_devdata(master);
 429
 430         spi_master_suspend(master);
 431         clk_disable_unprepare(dspi->clk);
 432
 433         return 0;
 434 }
 435
 436 static int dspi_resume(struct device *dev)
 437 {
 438         struct spi_master *master = dev_get_drvdata(dev);
 439         struct fsl_dspi *dspi = spi_master_get_devdata(master);
 440
 441         clk_prepare_enable(dspi->clk);
 442         spi_master_resume(master);
 443
 444         return 0;
 445 }
 446 #endif /* CONFIG_PM_SLEEP */
 447
 448 static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
 449
 450 static struct regmap_config dspi_regmap_config = {
 451         .reg_bits = 32,
 452         .val_bits = 32,
 453         .reg_stride = 4,
 454         .max_register = 0x88,
 455 };
 456
 457 static int dspi_probe(struct platform_device *pdev)
 458 {
 459         struct device_node *np = pdev->dev.of_node;
 460         struct spi_master *master;
 461         struct fsl_dspi *dspi;
 462         struct resource *res;
 463         void __iomem *base;
 464         int ret = 0, cs_num, bus_num;
 465
 466         master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
 467         if (!master)
 468                 return -ENOMEM;
 469
 470         dspi = spi_master_get_devdata(master);
 471         dspi->pdev = pdev;
 472         dspi->bitbang.master = master;
 473         dspi->bitbang.chipselect = dspi_chipselect;
 474         dspi->bitbang.setup_transfer = dspi_setup_transfer;
 475         dspi->bitbang.txrx_bufs = dspi_txrx_transfer;
 476         dspi->bitbang.master->setup = dspi_setup;
 477         dspi->bitbang.master->dev.of_node = pdev->dev.of_node;
 478
 479         master->cleanup = dspi_cleanup;
 480         master->mode_bits = SPI_CPOL | SPI_CPHA;
 481         master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) |
 482                                         SPI_BPW_MASK(16);
 483
 484         ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
 485         if (ret < 0) {
 486                 dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
 487                 goto out_master_put;
 488         }
 489         master->num_chipselect = cs_num;
 490
 491         ret = of_property_read_u32(np, "bus-num", &bus_num);
 492         if (ret < 0) {
 493                 dev_err(&pdev->dev, "can't get bus-num\n");
 494                 goto out_master_put;
 495         }
 496         master->bus_num = bus_num;
 497
 498         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 499         base = devm_ioremap_resource(&pdev->dev, res);
 500         if (IS_ERR(base)) {
 501                 ret = PTR_ERR(base);
 502                 goto out_master_put;
 503         }
 504
 505         dspi_regmap_config.lock_arg = dspi;
 506         dspi_regmap_config.val_format_endian =
 507                 of_property_read_bool(np, "big-endian")
 508                         ? REGMAP_ENDIAN_BIG : REGMAP_ENDIAN_DEFAULT;
 509         dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dspi", base,
 510                                                 &dspi_regmap_config);
 511         if (IS_ERR(dspi->regmap)) {
 512                 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
 513                                 PTR_ERR(dspi->regmap));
 514                 return PTR_ERR(dspi->regmap);
 515         }
 516
 517         dspi->irq = platform_get_irq(pdev, 0);
 518         if (dspi->irq < 0) {
 519                 dev_err(&pdev->dev, "can't get platform irq\n");
 520                 ret = dspi->irq;
 521                 goto out_master_put;
 522         }
 523
 524         ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
 525                         pdev->name, dspi);
 526         if (ret < 0) {
 527                 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
 528                 goto out_master_put;
 529         }
 530
 531         dspi->clk = devm_clk_get(&pdev->dev, "dspi");
 532         if (IS_ERR(dspi->clk)) {
 533                 ret = PTR_ERR(dspi->clk);
 534                 dev_err(&pdev->dev, "unable to get clock\n");
 535                 goto out_master_put;
 536         }
 537         clk_prepare_enable(dspi->clk);
 538
 539         init_waitqueue_head(&dspi->waitq);
 540         platform_set_drvdata(pdev, master);
 541
 542         ret = spi_bitbang_start(&dspi->bitbang);
 543         if (ret != 0) {
 544                 dev_err(&pdev->dev, "Problem registering DSPI master\n");
 545                 goto out_clk_put;
 546         }
 547
 548         pr_info(KERN_INFO "Freescale DSPI master initialized\n");
 549         return ret;
 550
 551 out_clk_put:
 552         clk_disable_unprepare(dspi->clk);
 553 out_master_put:
 554         spi_master_put(master);
 555
 556         return ret;
 557 }
 558
 559 static int dspi_remove(struct platform_device *pdev)
 560 {
 561         struct spi_master *master = platform_get_drvdata(pdev);
 562         struct fsl_dspi *dspi = spi_master_get_devdata(master);
 563
 564         /* Disconnect from the SPI framework */
 565         spi_bitbang_stop(&dspi->bitbang);
 566         clk_disable_unprepare(dspi->clk);
 567         spi_master_put(dspi->bitbang.master);
 568
 569         return 0;
 570 }
 571
 572 static struct platform_driver fsl_dspi_driver = {
 573         .driver.name    = DRIVER_NAME,
 574         .driver.of_match_table = fsl_dspi_dt_ids,
 575         .driver.owner   = THIS_MODULE,
 576         .driver.pm = &dspi_pm,
 577         .probe          = dspi_probe,
 578         .remove         = dspi_remove,
 579 };
 580 module_platform_driver(fsl_dspi_driver);
 581
 582 MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
 583 MODULE_LICENSE("GPL");
 584 MODULE_ALIAS("platform:" DRIVER_NAME);