drivers/spi/spi-sirf.c

   1 /*
   2  * SPI bus driver for CSR SiRFprimaII
   3  *
   4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/kernel.h>
  11 #include <linux/slab.h>
  12 #include <linux/clk.h>
  13 #include <linux/completion.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/of.h>
  17 #include <linux/bitops.h>
  18 #include <linux/err.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/of_gpio.h>
  21 #include <linux/spi/spi.h>
  22 #include <linux/spi/spi_bitbang.h>
  23 #include <linux/dmaengine.h>
  24 #include <linux/dma-direction.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #define DRIVER_NAME "sirfsoc_spi"
  28
  29 #define SIRFSOC_SPI_CTRL                0x0000
  30 #define SIRFSOC_SPI_CMD                 0x0004
  31 #define SIRFSOC_SPI_TX_RX_EN            0x0008
  32 #define SIRFSOC_SPI_INT_EN              0x000C
  33 #define SIRFSOC_SPI_INT_STATUS          0x0010
  34 #define SIRFSOC_SPI_TX_DMA_IO_CTRL      0x0100
  35 #define SIRFSOC_SPI_TX_DMA_IO_LEN       0x0104
  36 #define SIRFSOC_SPI_TXFIFO_CTRL         0x0108
  37 #define SIRFSOC_SPI_TXFIFO_LEVEL_CHK    0x010C
  38 #define SIRFSOC_SPI_TXFIFO_OP           0x0110
  39 #define SIRFSOC_SPI_TXFIFO_STATUS       0x0114
  40 #define SIRFSOC_SPI_TXFIFO_DATA         0x0118
  41 #define SIRFSOC_SPI_RX_DMA_IO_CTRL      0x0120
  42 #define SIRFSOC_SPI_RX_DMA_IO_LEN       0x0124
  43 #define SIRFSOC_SPI_RXFIFO_CTRL         0x0128
  44 #define SIRFSOC_SPI_RXFIFO_LEVEL_CHK    0x012C
  45 #define SIRFSOC_SPI_RXFIFO_OP           0x0130
  46 #define SIRFSOC_SPI_RXFIFO_STATUS       0x0134
  47 #define SIRFSOC_SPI_RXFIFO_DATA         0x0138
  48 #define SIRFSOC_SPI_DUMMY_DELAY_CTL     0x0144
  49
  50 /* SPI CTRL register defines */
  51 #define SIRFSOC_SPI_SLV_MODE            BIT(16)
  52 #define SIRFSOC_SPI_CMD_MODE            BIT(17)
  53 #define SIRFSOC_SPI_CS_IO_OUT           BIT(18)
  54 #define SIRFSOC_SPI_CS_IO_MODE          BIT(19)
  55 #define SIRFSOC_SPI_CLK_IDLE_STAT       BIT(20)
  56 #define SIRFSOC_SPI_CS_IDLE_STAT        BIT(21)
  57 #define SIRFSOC_SPI_TRAN_MSB            BIT(22)
  58 #define SIRFSOC_SPI_DRV_POS_EDGE        BIT(23)
  59 #define SIRFSOC_SPI_CS_HOLD_TIME        BIT(24)
  60 #define SIRFSOC_SPI_CLK_SAMPLE_MODE     BIT(25)
  61 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_8   (0 << 26)
  62 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_12  (1 << 26)
  63 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_16  (2 << 26)
  64 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_32  (3 << 26)
  65 #define SIRFSOC_SPI_CMD_BYTE_NUM(x)             ((x & 3) << 28)
  66 #define SIRFSOC_SPI_ENA_AUTO_CLR                BIT(30)
  67 #define SIRFSOC_SPI_MUL_DAT_MODE                BIT(31)
  68
  69 /* Interrupt Enable */
  70 #define SIRFSOC_SPI_RX_DONE_INT_EN              BIT(0)
  71 #define SIRFSOC_SPI_TX_DONE_INT_EN              BIT(1)
  72 #define SIRFSOC_SPI_RX_OFLOW_INT_EN             BIT(2)
  73 #define SIRFSOC_SPI_TX_UFLOW_INT_EN             BIT(3)
  74 #define SIRFSOC_SPI_RX_IO_DMA_INT_EN    BIT(4)
  75 #define SIRFSOC_SPI_TX_IO_DMA_INT_EN    BIT(5)
  76 #define SIRFSOC_SPI_RXFIFO_FULL_INT_EN  BIT(6)
  77 #define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7)
  78 #define SIRFSOC_SPI_RXFIFO_THD_INT_EN   BIT(8)
  79 #define SIRFSOC_SPI_TXFIFO_THD_INT_EN   BIT(9)
  80 #define SIRFSOC_SPI_FRM_END_INT_EN      BIT(10)
  81
  82 #define SIRFSOC_SPI_INT_MASK_ALL                0x1FFF
  83
  84 /* Interrupt status */
  85 #define SIRFSOC_SPI_RX_DONE             BIT(0)
  86 #define SIRFSOC_SPI_TX_DONE             BIT(1)
  87 #define SIRFSOC_SPI_RX_OFLOW            BIT(2)
  88 #define SIRFSOC_SPI_TX_UFLOW            BIT(3)
  89 #define SIRFSOC_SPI_RX_IO_DMA           BIT(4)
  90 #define SIRFSOC_SPI_RX_FIFO_FULL        BIT(6)
  91 #define SIRFSOC_SPI_TXFIFO_EMPTY        BIT(7)
  92 #define SIRFSOC_SPI_RXFIFO_THD_REACH    BIT(8)
  93 #define SIRFSOC_SPI_TXFIFO_THD_REACH    BIT(9)
  94 #define SIRFSOC_SPI_FRM_END             BIT(10)
  95
  96 /* TX RX enable */
  97 #define SIRFSOC_SPI_RX_EN               BIT(0)
  98 #define SIRFSOC_SPI_TX_EN               BIT(1)
  99 #define SIRFSOC_SPI_CMD_TX_EN           BIT(2)
 100
 101 #define SIRFSOC_SPI_IO_MODE_SEL         BIT(0)
 102 #define SIRFSOC_SPI_RX_DMA_FLUSH        BIT(2)
 103
 104 /* FIFO OPs */
 105 #define SIRFSOC_SPI_FIFO_RESET          BIT(0)
 106 #define SIRFSOC_SPI_FIFO_START          BIT(1)
 107
 108 /* FIFO CTRL */
 109 #define SIRFSOC_SPI_FIFO_WIDTH_BYTE     (0 << 0)
 110 #define SIRFSOC_SPI_FIFO_WIDTH_WORD     (1 << 0)
 111 #define SIRFSOC_SPI_FIFO_WIDTH_DWORD    (2 << 0)
 112
 113 /* FIFO Status */
 114 #define SIRFSOC_SPI_FIFO_LEVEL_MASK     0xFF
 115 #define SIRFSOC_SPI_FIFO_FULL           BIT(8)
 116 #define SIRFSOC_SPI_FIFO_EMPTY          BIT(9)
 117
 118 /* 256 bytes rx/tx FIFO */
 119 #define SIRFSOC_SPI_FIFO_SIZE           256
 120 #define SIRFSOC_SPI_DAT_FRM_LEN_MAX     (64 * 1024)
 121
 122 #define SIRFSOC_SPI_FIFO_SC(x)          ((x) & 0x3F)
 123 #define SIRFSOC_SPI_FIFO_LC(x)          (((x) & 0x3F) << 10)
 124 #define SIRFSOC_SPI_FIFO_HC(x)          (((x) & 0x3F) << 20)
 125 #define SIRFSOC_SPI_FIFO_THD(x)         (((x) & 0xFF) << 2)
 126
 127 /*
 128  * only if the rx/tx buffer and transfer size are 4-bytes aligned, we use dma
 129  * due to the limitation of dma controller
 130  */
 131
 132 #define ALIGNED(x) (!((u32)x & 0x3))
 133 #define IS_DMA_VALID(x) (x && ALIGNED(x->tx_buf) && ALIGNED(x->rx_buf) && \
 134         ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE))
 135
 136 #define SIRFSOC_MAX_CMD_BYTES   4
 137
 138 struct sirfsoc_spi {
 139         struct spi_bitbang bitbang;
 140         struct completion rx_done;
 141         struct completion tx_done;
 142
 143         void __iomem *base;
 144         u32 ctrl_freq;  /* SPI controller clock speed */
 145         struct clk *clk;
 146
 147         /* rx & tx bufs from the spi_transfer */
 148         const void *tx;
 149         void *rx;
 150
 151         /* place received word into rx buffer */
 152         void (*rx_word) (struct sirfsoc_spi *);
 153         /* get word from tx buffer for sending */
 154         void (*tx_word) (struct sirfsoc_spi *);
 155
 156         /* number of words left to be tranmitted/received */
 157         unsigned int left_tx_word;
 158         unsigned int left_rx_word;
 159
 160         /* rx & tx DMA channels */
 161         struct dma_chan *rx_chan;
 162         struct dma_chan *tx_chan;
 163         dma_addr_t src_start;
 164         dma_addr_t dst_start;
 165         void *dummypage;
 166         int word_width; /* in bytes */
 167
 168         /*
 169          * if tx size is not more than 4 and rx size is NULL, use
 170          * command model
 171          */
 172         bool    tx_by_cmd;
 173
 174         int chipselect[0];
 175 };
 176
 177 static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi)
 178 {
 179         u32 data;
 180         u8 *rx = sspi->rx;
 181
 182         data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
 183
 184         if (rx) {
 185                 *rx++ = (u8) data;
 186                 sspi->rx = rx;
 187         }
 188
 189         sspi->left_rx_word--;
 190 }
 191
 192 static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi)
 193 {
 194         u32 data = 0;
 195         const u8 *tx = sspi->tx;
 196
 197         if (tx) {
 198                 data = *tx++;
 199                 sspi->tx = tx;
 200         }
 201
 202         writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
 203         sspi->left_tx_word--;
 204 }
 205
 206 static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi)
 207 {
 208         u32 data;
 209         u16 *rx = sspi->rx;
 210
 211         data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
 212
 213         if (rx) {
 214                 *rx++ = (u16) data;
 215                 sspi->rx = rx;
 216         }
 217
 218         sspi->left_rx_word--;
 219 }
 220
 221 static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi)
 222 {
 223         u32 data = 0;
 224         const u16 *tx = sspi->tx;
 225
 226         if (tx) {
 227                 data = *tx++;
 228                 sspi->tx = tx;
 229         }
 230
 231         writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
 232         sspi->left_tx_word--;
 233 }
 234
 235 static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi)
 236 {
 237         u32 data;
 238         u32 *rx = sspi->rx;
 239
 240         data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
 241
 242         if (rx) {
 243                 *rx++ = (u32) data;
 244                 sspi->rx = rx;
 245         }
 246
 247         sspi->left_rx_word--;
 248
 249 }
 250
 251 static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi)
 252 {
 253         u32 data = 0;
 254         const u32 *tx = sspi->tx;
 255
 256         if (tx) {
 257                 data = *tx++;
 258                 sspi->tx = tx;
 259         }
 260
 261         writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
 262         sspi->left_tx_word--;
 263 }
 264
 265 static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
 266 {
 267         struct sirfsoc_spi *sspi = dev_id;
 268         u32 spi_stat = readl(sspi->base + SIRFSOC_SPI_INT_STATUS);
 269         if (sspi->tx_by_cmd && (spi_stat & SIRFSOC_SPI_FRM_END)) {
 270                 complete(&sspi->tx_done);
 271                 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
 272                 writel(SIRFSOC_SPI_INT_MASK_ALL,
 273                                 sspi->base + SIRFSOC_SPI_INT_STATUS);
 274                 return IRQ_HANDLED;
 275         }
 276
 277         /* Error Conditions */
 278         if (spi_stat & SIRFSOC_SPI_RX_OFLOW ||
 279                         spi_stat & SIRFSOC_SPI_TX_UFLOW) {
 280                 complete(&sspi->tx_done);
 281                 complete(&sspi->rx_done);
 282                 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
 283                 writel(SIRFSOC_SPI_INT_MASK_ALL,
 284                                 sspi->base + SIRFSOC_SPI_INT_STATUS);
 285                 return IRQ_HANDLED;
 286         }
 287         if (spi_stat & SIRFSOC_SPI_TXFIFO_EMPTY)
 288                 complete(&sspi->tx_done);
 289         while (!(readl(sspi->base + SIRFSOC_SPI_INT_STATUS) &
 290                 SIRFSOC_SPI_RX_IO_DMA))
 291                 cpu_relax();
 292         complete(&sspi->rx_done);
 293         writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
 294         writel(SIRFSOC_SPI_INT_MASK_ALL,
 295                         sspi->base + SIRFSOC_SPI_INT_STATUS);
 296
 297         return IRQ_HANDLED;
 298 }
 299
 300 static void spi_sirfsoc_dma_fini_callback(void *data)
 301 {
 302         struct completion *dma_complete = data;
 303
 304         complete(dma_complete);
 305 }
 306
 307 static int spi_sirfsoc_cmd_transfer(struct spi_device *spi,
 308         struct spi_transfer *t)
 309 {
 310         struct sirfsoc_spi *sspi;
 311         int timeout = t->len * 10;
 312         u32 cmd;
 313
 314         sspi = spi_master_get_devdata(spi->master);
 315         memcpy(&cmd, sspi->tx, t->len);
 316         if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST))
 317                 cmd = cpu_to_be32(cmd) >>
 318                         ((SIRFSOC_MAX_CMD_BYTES - t->len) * 8);
 319         if (sspi->word_width == 2 && t->len == 4 &&
 320                         (!(spi->mode & SPI_LSB_FIRST)))
 321                 cmd = ((cmd & 0xffff) << 16) | (cmd >> 16);
 322         writel(cmd, sspi->base + SIRFSOC_SPI_CMD);
 323         writel(SIRFSOC_SPI_FRM_END_INT_EN,
 324                 sspi->base + SIRFSOC_SPI_INT_EN);
 325         writel(SIRFSOC_SPI_CMD_TX_EN,
 326                 sspi->base + SIRFSOC_SPI_TX_RX_EN);
 327         if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
 328                 dev_err(&spi->dev, "cmd transfer timeout\n");
 329                 return 0;
 330         }
 331
 332         return t->len;
 333 }
 334
 335 static void spi_sirfsoc_dma_transfer(struct spi_device *spi,
 336         struct spi_transfer *t)
 337 {
 338         struct sirfsoc_spi *sspi;
 339         struct dma_async_tx_descriptor *rx_desc, *tx_desc;
 340         int timeout = t->len * 10;
 341
 342         sspi = spi_master_get_devdata(spi->master);
 343         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 344         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 345         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 346         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 347         writel(0, sspi->base + SIRFSOC_SPI_INT_EN);
 348         writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS);
 349         if (sspi->left_tx_word < SIRFSOC_SPI_DAT_FRM_LEN_MAX) {
 350                 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
 351                         SIRFSOC_SPI_ENA_AUTO_CLR | SIRFSOC_SPI_MUL_DAT_MODE,
 352                         sspi->base + SIRFSOC_SPI_CTRL);
 353                 writel(sspi->left_tx_word - 1,
 354                                 sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
 355                 writel(sspi->left_tx_word - 1,
 356                                 sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
 357         } else {
 358                 writel(readl(sspi->base + SIRFSOC_SPI_CTRL),
 359                         sspi->base + SIRFSOC_SPI_CTRL);
 360                 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
 361                 writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
 362         }
 363         sspi->dst_start = dma_map_single(&spi->dev, sspi->rx, t->len,
 364                                         (t->tx_buf != t->rx_buf) ?
 365                                         DMA_FROM_DEVICE : DMA_BIDIRECTIONAL);
 366         rx_desc = dmaengine_prep_slave_single(sspi->rx_chan,
 367                 sspi->dst_start, t->len, DMA_DEV_TO_MEM,
 368                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 369         rx_desc->callback = spi_sirfsoc_dma_fini_callback;
 370         rx_desc->callback_param = &sspi->rx_done;
 371
 372         sspi->src_start = dma_map_single(&spi->dev, (void *)sspi->tx, t->len,
 373                                         (t->tx_buf != t->rx_buf) ?
 374                                         DMA_TO_DEVICE : DMA_BIDIRECTIONAL);
 375         tx_desc = dmaengine_prep_slave_single(sspi->tx_chan,
 376                 sspi->src_start, t->len, DMA_MEM_TO_DEV,
 377                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 378         tx_desc->callback = spi_sirfsoc_dma_fini_callback;
 379         tx_desc->callback_param = &sspi->tx_done;
 380
 381         dmaengine_submit(tx_desc);
 382         dmaengine_submit(rx_desc);
 383         dma_async_issue_pending(sspi->tx_chan);
 384         dma_async_issue_pending(sspi->rx_chan);
 385         writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN,
 386                         sspi->base + SIRFSOC_SPI_TX_RX_EN);
 387         if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) {
 388                 dev_err(&spi->dev, "transfer timeout\n");
 389                 dmaengine_terminate_all(sspi->rx_chan);
 390         } else
 391                 sspi->left_rx_word = 0;
 392         /*
 393          * we only wait tx-done event if transferring by DMA. for PIO,
 394          * we get rx data by writing tx data, so if rx is done, tx has
 395          * done earlier
 396          */
 397         if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
 398                 dev_err(&spi->dev, "transfer timeout\n");
 399                 dmaengine_terminate_all(sspi->tx_chan);
 400         }
 401         dma_unmap_single(&spi->dev, sspi->src_start, t->len, DMA_TO_DEVICE);
 402         dma_unmap_single(&spi->dev, sspi->dst_start, t->len, DMA_FROM_DEVICE);
 403         /* TX, RX FIFO stop */
 404         writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 405         writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 406         if (sspi->left_tx_word >= SIRFSOC_SPI_DAT_FRM_LEN_MAX)
 407                 writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN);
 408 }
 409
 410 static void spi_sirfsoc_pio_transfer(struct spi_device *spi,
 411                 struct spi_transfer *t)
 412 {
 413         struct sirfsoc_spi *sspi;
 414         int timeout = t->len * 10;
 415
 416         sspi = spi_master_get_devdata(spi->master);
 417         do {
 418                 writel(SIRFSOC_SPI_FIFO_RESET,
 419                         sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 420                 writel(SIRFSOC_SPI_FIFO_RESET,
 421                         sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 422                 writel(SIRFSOC_SPI_FIFO_START,
 423                         sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 424                 writel(SIRFSOC_SPI_FIFO_START,
 425                         sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 426                 writel(0, sspi->base + SIRFSOC_SPI_INT_EN);
 427                 writel(SIRFSOC_SPI_INT_MASK_ALL,
 428                         sspi->base + SIRFSOC_SPI_INT_STATUS);
 429                 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
 430                         SIRFSOC_SPI_MUL_DAT_MODE | SIRFSOC_SPI_ENA_AUTO_CLR,
 431                         sspi->base + SIRFSOC_SPI_CTRL);
 432                 writel(min(sspi->left_tx_word, (u32)(256 / sspi->word_width))
 433                                 - 1, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
 434                 writel(min(sspi->left_rx_word, (u32)(256 / sspi->word_width))
 435                                 - 1, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
 436                 while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS)
 437                         & SIRFSOC_SPI_FIFO_FULL)) && sspi->left_tx_word)
 438                         sspi->tx_word(sspi);
 439                 writel(SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN |
 440                         SIRFSOC_SPI_TX_UFLOW_INT_EN |
 441                         SIRFSOC_SPI_RX_OFLOW_INT_EN |
 442                         SIRFSOC_SPI_RX_IO_DMA_INT_EN,
 443                         sspi->base + SIRFSOC_SPI_INT_EN);
 444                 writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN,
 445                         sspi->base + SIRFSOC_SPI_TX_RX_EN);
 446                 if (!wait_for_completion_timeout(&sspi->tx_done, timeout) ||
 447                         !wait_for_completion_timeout(&sspi->rx_done, timeout)) {
 448                         dev_err(&spi->dev, "transfer timeout\n");
 449                         break;
 450                 }
 451                 while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS)
 452                         & SIRFSOC_SPI_FIFO_EMPTY)) && sspi->left_rx_word)
 453                         sspi->rx_word(sspi);
 454                 writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 455                 writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 456         } while (sspi->left_tx_word != 0 || sspi->left_rx_word != 0);
 457 }
 458
 459 static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
 460 {
 461         struct sirfsoc_spi *sspi;
 462         sspi = spi_master_get_devdata(spi->master);
 463
 464         sspi->tx = t->tx_buf ? t->tx_buf : sspi->dummypage;
 465         sspi->rx = t->rx_buf ? t->rx_buf : sspi->dummypage;
 466         sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width;
 467         reinit_completion(&sspi->rx_done);
 468         reinit_completion(&sspi->tx_done);
 469         /*
 470          * in the transfer, if transfer data using command register with rx_buf
 471          * null, just fill command data into command register and wait for its
 472          * completion.
 473          */
 474         if (sspi->tx_by_cmd)
 475                 spi_sirfsoc_cmd_transfer(spi, t);
 476         else if (IS_DMA_VALID(t))
 477                 spi_sirfsoc_dma_transfer(spi, t);
 478         else
 479                 spi_sirfsoc_pio_transfer(spi, t);
 480
 481         return t->len - sspi->left_rx_word * sspi->word_width;
 482 }
 483
 484 static void spi_sirfsoc_chipselect(struct spi_device *spi, int value)
 485 {
 486         struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master);
 487
 488         if (sspi->chipselect[spi->chip_select] == 0) {
 489                 u32 regval = readl(sspi->base + SIRFSOC_SPI_CTRL);
 490                 switch (value) {
 491                 case BITBANG_CS_ACTIVE:
 492                         if (spi->mode & SPI_CS_HIGH)
 493                                 regval |= SIRFSOC_SPI_CS_IO_OUT;
 494                         else
 495                                 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
 496                         break;
 497                 case BITBANG_CS_INACTIVE:
 498                         if (spi->mode & SPI_CS_HIGH)
 499                                 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
 500                         else
 501                                 regval |= SIRFSOC_SPI_CS_IO_OUT;
 502                         break;
 503                 }
 504                 writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
 505         } else {
 506                 int gpio = sspi->chipselect[spi->chip_select];
 507                 switch (value) {
 508                 case BITBANG_CS_ACTIVE:
 509                         gpio_direction_output(gpio,
 510                                         spi->mode & SPI_CS_HIGH ? 1 : 0);
 511                         break;
 512                 case BITBANG_CS_INACTIVE:
 513                         gpio_direction_output(gpio,
 514                                         spi->mode & SPI_CS_HIGH ? 0 : 1);
 515                         break;
 516                 }
 517         }
 518 }
 519
 520 static int
 521 spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 522 {
 523         struct sirfsoc_spi *sspi;
 524         u8 bits_per_word = 0;
 525         int hz = 0;
 526         u32 regval;
 527         u32 txfifo_ctrl, rxfifo_ctrl;
 528         u32 fifo_size = SIRFSOC_SPI_FIFO_SIZE / 4;
 529
 530         sspi = spi_master_get_devdata(spi->master);
 531
 532         bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
 533         hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz;
 534
 535         regval = (sspi->ctrl_freq / (2 * hz)) - 1;
 536         if (regval > 0xFFFF || regval < 0) {
 537                 dev_err(&spi->dev, "Speed %d not supported\n", hz);
 538                 return -EINVAL;
 539         }
 540
 541         switch (bits_per_word) {
 542         case 8:
 543                 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8;
 544                 sspi->rx_word = spi_sirfsoc_rx_word_u8;
 545                 sspi->tx_word = spi_sirfsoc_tx_word_u8;
 546                 break;
 547         case 12:
 548         case 16:
 549                 regval |= (bits_per_word ==  12) ?
 550                         SIRFSOC_SPI_TRAN_DAT_FORMAT_12 :
 551                         SIRFSOC_SPI_TRAN_DAT_FORMAT_16;
 552                 sspi->rx_word = spi_sirfsoc_rx_word_u16;
 553                 sspi->tx_word = spi_sirfsoc_tx_word_u16;
 554                 break;
 555         case 32:
 556                 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32;
 557                 sspi->rx_word = spi_sirfsoc_rx_word_u32;
 558                 sspi->tx_word = spi_sirfsoc_tx_word_u32;
 559                 break;
 560         default:
 561                 BUG();
 562         }
 563
 564         sspi->word_width = DIV_ROUND_UP(bits_per_word, 8);
 565         txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 566                                            (sspi->word_width >> 1);
 567         rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 568                                            (sspi->word_width >> 1);
 569
 570         if (!(spi->mode & SPI_CS_HIGH))
 571                 regval |= SIRFSOC_SPI_CS_IDLE_STAT;
 572         if (!(spi->mode & SPI_LSB_FIRST))
 573                 regval |= SIRFSOC_SPI_TRAN_MSB;
 574         if (spi->mode & SPI_CPOL)
 575                 regval |= SIRFSOC_SPI_CLK_IDLE_STAT;
 576
 577         /*
 578          * Data should be driven at least 1/2 cycle before the fetch edge
 579          * to make sure that data gets stable at the fetch edge.
 580          */
 581         if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) ||
 582             (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA)))
 583                 regval &= ~SIRFSOC_SPI_DRV_POS_EDGE;
 584         else
 585                 regval |= SIRFSOC_SPI_DRV_POS_EDGE;
 586
 587         writel(SIRFSOC_SPI_FIFO_SC(fifo_size - 2) |
 588                         SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
 589                         SIRFSOC_SPI_FIFO_HC(2),
 590                 sspi->base + SIRFSOC_SPI_TXFIFO_LEVEL_CHK);
 591         writel(SIRFSOC_SPI_FIFO_SC(2) |
 592                         SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
 593                         SIRFSOC_SPI_FIFO_HC(fifo_size - 2),
 594                 sspi->base + SIRFSOC_SPI_RXFIFO_LEVEL_CHK);
 595         writel(txfifo_ctrl, sspi->base + SIRFSOC_SPI_TXFIFO_CTRL);
 596         writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL);
 597
 598         if (t && t->tx_buf && !t->rx_buf && (t->len <= SIRFSOC_MAX_CMD_BYTES)) {
 599                 regval |= (SIRFSOC_SPI_CMD_BYTE_NUM((t->len - 1)) |
 600                                 SIRFSOC_SPI_CMD_MODE);
 601                 sspi->tx_by_cmd = true;
 602         } else {
 603                 regval &= ~SIRFSOC_SPI_CMD_MODE;
 604                 sspi->tx_by_cmd = false;
 605         }
 606         /*
 607          * set spi controller in RISC chipselect mode, we are controlling CS by
 608          * software BITBANG_CS_ACTIVE and BITBANG_CS_INACTIVE.
 609          */
 610         regval |= SIRFSOC_SPI_CS_IO_MODE;
 611         writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
 612
 613         if (IS_DMA_VALID(t)) {
 614                 /* Enable DMA mode for RX, TX */
 615                 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
 616                 writel(SIRFSOC_SPI_RX_DMA_FLUSH,
 617                         sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
 618         } else {
 619                 /* Enable IO mode for RX, TX */
 620                 writel(SIRFSOC_SPI_IO_MODE_SEL,
 621                         sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
 622                 writel(SIRFSOC_SPI_IO_MODE_SEL,
 623                         sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
 624         }
 625
 626         return 0;
 627 }
 628
 629 static int spi_sirfsoc_setup(struct spi_device *spi)
 630 {
 631         if (!spi->max_speed_hz)
 632                 return -EINVAL;
 633
 634         return spi_sirfsoc_setup_transfer(spi, NULL);
 635 }
 636
 637 static int spi_sirfsoc_probe(struct platform_device *pdev)
 638 {
 639         struct sirfsoc_spi *sspi;
 640         struct spi_master *master;
 641         struct resource *mem_res;
 642         int num_cs, cs_gpio, irq;
 643         int i;
 644         int ret;
 645
 646         ret = of_property_read_u32(pdev->dev.of_node,
 647                         "sirf,spi-num-chipselects", &num_cs);
 648         if (ret < 0) {
 649                 dev_err(&pdev->dev, "Unable to get chip select number\n");
 650                 goto err_cs;
 651         }
 652
 653         master = spi_alloc_master(&pdev->dev,
 654                         sizeof(*sspi) + sizeof(int) * num_cs);
 655         if (!master) {
 656                 dev_err(&pdev->dev, "Unable to allocate SPI master\n");
 657                 return -ENOMEM;
 658         }
 659         platform_set_drvdata(pdev, master);
 660         sspi = spi_master_get_devdata(master);
 661
 662         master->num_chipselect = num_cs;
 663
 664         for (i = 0; i < master->num_chipselect; i++) {
 665                 cs_gpio = of_get_named_gpio(pdev->dev.of_node, "cs-gpios", i);
 666                 if (cs_gpio < 0) {
 667                         dev_err(&pdev->dev, "can't get cs gpio from DT\n");
 668                         ret = -ENODEV;
 669                         goto free_master;
 670                 }
 671
 672                 sspi->chipselect[i] = cs_gpio;
 673                 if (cs_gpio == 0)
 674                         continue; /* use cs from spi controller */
 675
 676                 ret = gpio_request(cs_gpio, DRIVER_NAME);
 677                 if (ret) {
 678                         while (i > 0) {
 679                                 i--;
 680                                 if (sspi->chipselect[i] > 0)
 681                                         gpio_free(sspi->chipselect[i]);
 682                         }
 683                         dev_err(&pdev->dev, "fail to request cs gpios\n");
 684                         goto free_master;
 685                 }
 686         }
 687
 688         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 689         sspi->base = devm_ioremap_resource(&pdev->dev, mem_res);
 690         if (IS_ERR(sspi->base)) {
 691                 ret = PTR_ERR(sspi->base);
 692                 goto free_master;
 693         }
 694
 695         irq = platform_get_irq(pdev, 0);
 696         if (irq < 0) {
 697                 ret = -ENXIO;
 698                 goto free_master;
 699         }
 700         ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0,
 701                                 DRIVER_NAME, sspi);
 702         if (ret)
 703                 goto free_master;
 704
 705         sspi->bitbang.master = master;
 706         sspi->bitbang.chipselect = spi_sirfsoc_chipselect;
 707         sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer;
 708         sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer;
 709         sspi->bitbang.master->setup = spi_sirfsoc_setup;
 710         master->bus_num = pdev->id;
 711         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH;
 712         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(12) |
 713                                         SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
 714         sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
 715
 716         /* request DMA channels */
 717         sspi->rx_chan = dma_request_slave_channel(&pdev->dev, "rx");
 718         if (!sspi->rx_chan) {
 719                 dev_err(&pdev->dev, "can not allocate rx dma channel\n");
 720                 ret = -ENODEV;
 721                 goto free_master;
 722         }
 723         sspi->tx_chan = dma_request_slave_channel(&pdev->dev, "tx");
 724         if (!sspi->tx_chan) {
 725                 dev_err(&pdev->dev, "can not allocate tx dma channel\n");
 726                 ret = -ENODEV;
 727                 goto free_rx_dma;
 728         }
 729
 730         sspi->clk = clk_get(&pdev->dev, NULL);
 731         if (IS_ERR(sspi->clk)) {
 732                 ret = PTR_ERR(sspi->clk);
 733                 goto free_tx_dma;
 734         }
 735         clk_prepare_enable(sspi->clk);
 736         sspi->ctrl_freq = clk_get_rate(sspi->clk);
 737
 738         init_completion(&sspi->rx_done);
 739         init_completion(&sspi->tx_done);
 740
 741         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 742         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 743         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 744         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 745         /* We are not using dummy delay between command and data */
 746         writel(0, sspi->base + SIRFSOC_SPI_DUMMY_DELAY_CTL);
 747
 748         sspi->dummypage = kmalloc(2 * PAGE_SIZE, GFP_KERNEL);
 749         if (!sspi->dummypage) {
 750                 ret = -ENOMEM;
 751                 goto free_clk;
 752         }
 753
 754         ret = spi_bitbang_start(&sspi->bitbang);
 755         if (ret)
 756                 goto free_dummypage;
 757
 758         dev_info(&pdev->dev, "registerred, bus number = %d\n", master->bus_num);
 759
 760         return 0;
 761 free_dummypage:
 762         kfree(sspi->dummypage);
 763 free_clk:
 764         clk_disable_unprepare(sspi->clk);
 765         clk_put(sspi->clk);
 766 free_tx_dma:
 767         dma_release_channel(sspi->tx_chan);
 768 free_rx_dma:
 769         dma_release_channel(sspi->rx_chan);
 770 free_master:
 771         spi_master_put(master);
 772 err_cs:
 773         return ret;
 774 }
 775
 776 static int  spi_sirfsoc_remove(struct platform_device *pdev)
 777 {
 778         struct spi_master *master;
 779         struct sirfsoc_spi *sspi;
 780         int i;
 781
 782         master = platform_get_drvdata(pdev);
 783         sspi = spi_master_get_devdata(master);
 784
 785         spi_bitbang_stop(&sspi->bitbang);
 786         for (i = 0; i < master->num_chipselect; i++) {
 787                 if (sspi->chipselect[i] > 0)
 788                         gpio_free(sspi->chipselect[i]);
 789         }
 790         kfree(sspi->dummypage);
 791         clk_disable_unprepare(sspi->clk);
 792         clk_put(sspi->clk);
 793         dma_release_channel(sspi->rx_chan);
 794         dma_release_channel(sspi->tx_chan);
 795         spi_master_put(master);
 796         return 0;
 797 }
 798
 799 #ifdef CONFIG_PM_SLEEP
 800 static int spi_sirfsoc_suspend(struct device *dev)
 801 {
 802         struct spi_master *master = dev_get_drvdata(dev);
 803         struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
 804         int ret;
 805
 806         ret = spi_master_suspend(master);
 807         if (ret)
 808                 return ret;
 809
 810         clk_disable(sspi->clk);
 811         return 0;
 812 }
 813
 814 static int spi_sirfsoc_resume(struct device *dev)
 815 {
 816         struct spi_master *master = dev_get_drvdata(dev);
 817         struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
 818
 819         clk_enable(sspi->clk);
 820         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 821         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 822         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 823         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 824
 825         return spi_master_resume(master);
 826 }
 827 #endif
 828
 829 static SIMPLE_DEV_PM_OPS(spi_sirfsoc_pm_ops, spi_sirfsoc_suspend,
 830                          spi_sirfsoc_resume);
 831
 832 static const struct of_device_id spi_sirfsoc_of_match[] = {
 833         { .compatible = "sirf,prima2-spi", },
 834         { .compatible = "sirf,marco-spi", },
 835         {}
 836 };
 837 MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match);
 838
 839 static struct platform_driver spi_sirfsoc_driver = {
 840         .driver = {
 841                 .name = DRIVER_NAME,
 842                 .owner = THIS_MODULE,
 843                 .pm     = &spi_sirfsoc_pm_ops,
 844                 .of_match_table = spi_sirfsoc_of_match,
 845         },
 846         .probe = spi_sirfsoc_probe,
 847         .remove = spi_sirfsoc_remove,
 848 };
 849 module_platform_driver(spi_sirfsoc_driver);
 850 MODULE_DESCRIPTION("SiRF SoC SPI master driver");
 851 MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>");
 852 MODULE_AUTHOR("Barry Song <Baohua.Song@csr.com>");
 853 MODULE_LICENSE("GPL v2");