drivers/staging/cxt1e1/functions.c

   1 /* Copyright (C) 2003-2005  SBE, Inc.
   2  *
   3  *   This program is free software; you can redistribute it and/or modify
   4  *   it under the terms of the GNU General Public License as published by
   5  *   the Free Software Foundation; either version 2 of the License, or
   6  *   (at your option) any later version.
   7  *
   8  *   This program is distributed in the hope that it will be useful,
   9  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *   GNU General Public License for more details.
  12  */
  13
  14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  15
  16 #include <linux/slab.h>
  17 #include <linux/io.h>
  18 #include <asm/byteorder.h>
  19 #include <linux/netdevice.h>
  20 #include <linux/delay.h>
  21 #include <linux/hdlc.h>
  22 #include "pmcc4_sysdep.h"
  23 #include "sbecom_inline_linux.h"
  24 #include "libsbew.h"
  25 #include "pmcc4.h"
  26
  27
  28 #ifndef USE_MAX_INT_DELAY
  29 static int  dummy = 0;
  30
  31 #endif
  32
  33 extern int  drvr_state;
  34
  35
  36 #if 1
  37 u_int32_t
  38 pci_read_32(u_int32_t *p)
  39 {
  40 #ifdef FLOW_DEBUG
  41         u_int32_t   v;
  42
  43         FLUSH_PCI_READ();
  44         v = le32_to_cpu(*p);
  45         if (cxt1e1_log_level >= LOG_DEBUG)
  46                 pr_info("pci_read : %x = %x\n", (u_int32_t) p, v);
  47         return v;
  48 #else
  49         FLUSH_PCI_READ();              /* */
  50         return le32_to_cpu(*p);
  51 #endif
  52 }
  53
  54 void
  55 pci_write_32(u_int32_t *p, u_int32_t v)
  56 {
  57 #ifdef FLOW_DEBUG
  58         if (cxt1e1_log_level >= LOG_DEBUG)
  59                 pr_info("pci_write: %x = %x\n", (u_int32_t) p, v);
  60 #endif
  61         *p = cpu_to_le32 (v);
  62         FLUSH_PCI_WRITE();             /* This routine is called from routines
  63                                         * which do multiple register writes
  64                                         * which themselves need flushing between
  65                                         * writes in order to guarantee write
  66                                         * ordering.  It is less code-cumbersome
  67                                         * to flush here-in then to investigate
  68                                         * and code the many other register
  69                                         * writing routines. */
  70 }
  71 #endif
  72
  73
  74 void
  75 pci_flush_write(ci_t *ci)
  76 {
  77         volatile u_int32_t v;
  78
  79     /* issue a PCI read to flush PCI write thru bridge */
  80         v = *(u_int32_t *) &ci->reg->glcd;  /* any address would do */
  81
  82     /*
  83      * return nothing, this just reads PCI bridge interface to flush
  84      * previously written data
  85      */
  86 }
  87
  88
  89 static void
  90 watchdog_func(unsigned long arg)
  91 {
  92         struct watchdog *wd = (void *) arg;
  93
  94         if (drvr_state != SBE_DRVR_AVAILABLE) {
  95                 if (cxt1e1_log_level >= LOG_MONITOR)
  96                         pr_warning("%s: drvr not available (%x)\n",
  97                                    __func__, drvr_state);
  98                 return;
  99         }
 100         schedule_work(&wd->work);
 101         mod_timer(&wd->h, jiffies + wd->ticks);
 102 }
 103
 104 int OS_init_watchdog(struct watchdog *wdp, void (*f) (void *),
 105                      void *c, int usec)
 106 {
 107         wdp->func = f;
 108         wdp->softc = c;
 109         wdp->ticks = (HZ) * (usec / 1000) / 1000;
 110         INIT_WORK(&wdp->work, (void *)f);
 111         init_timer(&wdp->h);
 112         {
 113                 ci_t       *ci = (ci_t *) c;
 114
 115                 wdp->h.data = (unsigned long) &ci->wd;
 116         }
 117         wdp->h.function = watchdog_func;
 118         return 0;
 119 }
 120
 121 void
 122 OS_uwait(int usec, char *description)
 123 {
 124         int         tmp;
 125
 126         if (usec >= 1000) {
 127                 mdelay(usec / 1000);
 128                 /* now delay residual */
 129                 tmp = (usec / 1000) * 1000; /* round */
 130                 tmp = usec - tmp;           /* residual */
 131                 if (tmp) {                           /* wait on residual */
 132                         udelay(tmp);
 133                 }
 134         } else {
 135                 udelay(usec);
 136         }
 137 }
 138
 139 /* dummy short delay routine called as a subroutine so that compiler
 140  * does not optimize/remove its intent (a short delay)
 141  */
 142
 143 void
 144 OS_uwait_dummy(void)
 145 {
 146 #ifndef USE_MAX_INT_DELAY
 147         dummy++;
 148 #else
 149         udelay(1);
 150 #endif
 151 }
 152
 153
 154 void
 155 OS_sem_init(void *sem, int state)
 156 {
 157         switch (state) {
 158         case SEM_TAKEN:
 159             sema_init((struct semaphore *) sem, 0);
 160             break;
 161         case SEM_AVAILABLE:
 162             sema_init((struct semaphore *) sem, 1);
 163             break;
 164         default:                        /* otherwise, set sem.count to state's
 165                                         * value */
 166             sema_init(sem, state);
 167             break;
 168         }
 169 }
 170
 171
 172 int
 173 sd_line_is_ok(void *user)
 174 {
 175         struct net_device *ndev = (struct net_device *) user;
 176
 177         return netif_carrier_ok(ndev);
 178 }
 179
 180 void
 181 sd_line_is_up(void *user)
 182 {
 183         struct net_device *ndev = (struct net_device *) user;
 184
 185         netif_carrier_on(ndev);
 186         return;
 187 }
 188
 189 void
 190 sd_line_is_down(void *user)
 191 {
 192         struct net_device *ndev = (struct net_device *) user;
 193
 194         netif_carrier_off(ndev);
 195         return;
 196 }
 197
 198 void
 199 sd_disable_xmit(void *user)
 200 {
 201         struct net_device *dev = (struct net_device *) user;
 202
 203         netif_stop_queue(dev);
 204         return;
 205 }
 206
 207 void
 208 sd_enable_xmit(void *user)
 209 {
 210         struct net_device *dev = (struct net_device *) user;
 211
 212         netif_wake_queue(dev);
 213         return;
 214 }
 215
 216 int
 217 sd_queue_stopped(void *user)
 218 {
 219         struct net_device *ndev = (struct net_device *) user;
 220
 221         return netif_queue_stopped(ndev);
 222 }
 223
 224 void sd_recv_consume(void *token, size_t len, void *user)
 225 {
 226         struct net_device *ndev = user;
 227         struct sk_buff *skb = token;
 228
 229         skb->dev = ndev;
 230         skb_put(skb, len);
 231         skb->protocol = hdlc_type_trans(skb, ndev);
 232         netif_rx(skb);
 233 }
 234
 235
 236 /**
 237  ** Read some reserved location w/in the COMET chip as a usable
 238  ** VMETRO trigger point or other trace marking event.
 239  **/
 240
 241 #include "comet.h"
 242
 243 extern ci_t *CI;                /* dummy pointer to board ZERO's data */
 244 void
 245 VMETRO_TRIGGER(ci_t *ci, int x)
 246 {
 247         struct s_comet_reg    *comet;
 248         volatile u_int32_t data;
 249
 250         comet = ci->port[0].cometbase;  /* default to COMET # 0 */
 251
 252         switch (x) {
 253         default:
 254         case 0:
 255             data = pci_read_32((u_int32_t *) &comet->__res24);     /* 0x90 */
 256             break;
 257         case 1:
 258             data = pci_read_32((u_int32_t *) &comet->__res25);     /* 0x94 */
 259             break;
 260         case 2:
 261             data = pci_read_32((u_int32_t *) &comet->__res26);     /* 0x98 */
 262             break;
 263         case 3:
 264             data = pci_read_32((u_int32_t *) &comet->__res27);     /* 0x9C */
 265             break;
 266         case 4:
 267             data = pci_read_32((u_int32_t *) &comet->__res88);     /* 0x220 */
 268             break;
 269         case 5:
 270             data = pci_read_32((u_int32_t *) &comet->__res89);     /* 0x224 */
 271             break;
 272         case 6:
 273             data = pci_read_32((u_int32_t *) &comet->__res8A);     /* 0x228 */
 274             break;
 275         case 7:
 276             data = pci_read_32((u_int32_t *) &comet->__res8B);     /* 0x22C */
 277             break;
 278         case 8:
 279             data = pci_read_32((u_int32_t *) &comet->__resA0);     /* 0x280 */
 280             break;
 281         case 9:
 282             data = pci_read_32((u_int32_t *) &comet->__resA1);     /* 0x284 */
 283             break;
 284         case 10:
 285             data = pci_read_32((u_int32_t *) &comet->__resA2);     /* 0x288 */
 286             break;
 287         case 11:
 288             data = pci_read_32((u_int32_t *) &comet->__resA3);     /* 0x28C */
 289             break;
 290         case 12:
 291             data = pci_read_32((u_int32_t *) &comet->__resA4);     /* 0x290 */
 292             break;
 293         case 13:
 294             data = pci_read_32((u_int32_t *) &comet->__resA5);     /* 0x294 */
 295             break;
 296         case 14:
 297             data = pci_read_32((u_int32_t *) &comet->__resA6);     /* 0x298 */
 298             break;
 299         case 15:
 300             data = pci_read_32((u_int32_t *) &comet->__resA7);     /* 0x29C */
 301             break;
 302         case 16:
 303             data = pci_read_32((u_int32_t *) &comet->__res74);     /* 0x1D0 */
 304             break;
 305         case 17:
 306             data = pci_read_32((u_int32_t *) &comet->__res75);     /* 0x1D4 */
 307             break;
 308         case 18:
 309             data = pci_read_32((u_int32_t *) &comet->__res76);     /* 0x1D8 */
 310             break;
 311         case 19:
 312             data = pci_read_32((u_int32_t *) &comet->__res77);     /* 0x1DC */
 313             break;
 314         }
 315 }
 316
 317
 318 /***  End-of-File  ***/