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usb: dwc3: keystone: drop dma_mask configuration
[linux/fpc-iii.git] / drivers / staging / cxt1e1 / musycc.c
blob0bcbd8a3fc840285978d20bb1a7aae7158826ca4
1 static unsigned int max_intcnt;
2 static unsigned int max_bh;
3
4 /*-----------------------------------------------------------------------------
5 * musycc.c -
6 *
7 * Copyright (C) 2007 One Stop Systems, Inc.
8 * Copyright (C) 2003-2006 SBE, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * For further information, contact via email: support@onestopsystems.com
21 * One Stop Systems, Inc. Escondido, California U.S.A.
22 *-----------------------------------------------------------------------------
23 */
24
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27 #include <linux/types.h>
28 #include "pmcc4_sysdep.h"
29 #include <linux/kernel.h>
30 #include <linux/errno.h>
31 #include <linux/init.h>
32 #include "sbecom_inline_linux.h"
33 #include "libsbew.h"
34 #include "pmcc4_private.h"
35 #include "pmcc4.h"
36 #include "musycc.h"
37
38 #define sd_find_chan(ci,ch) c4_find_chan(ch)
39
40
41 /*******************************************************************/
42 /* global driver variables */
43 extern ci_t *c4_list;
44 extern int drvr_state;
45
46 extern int cxt1e1_max_mru;
47 extern int cxt1e1_max_mtu;
48 extern int max_rxdesc_used;
49 extern int max_txdesc_used;
50 extern ci_t *CI; /* dummy pointr to board ZEROE's data - DEBUG
51 * USAGE */
52
53
54 /*******************************************************************/
55 /* forward references */
56 void c4_fifo_free(mpi_t *, int);
57 void c4_wk_chan_restart(mch_t *);
58 void musycc_bh_tx_eom(mpi_t *, int);
59 int musycc_chan_up(ci_t *, int);
60 status_t __init musycc_init(ci_t *);
61 void musycc_intr_bh_tasklet(ci_t *);
62 void musycc_serv_req(mpi_t *, u_int32_t);
63 void musycc_update_timeslots(mpi_t *);
64
65 /*******************************************************************/
66
67 static int
68 musycc_dump_rxbuffer_ring(mch_t *ch, int lockit)
69 {
70 struct mdesc *m;
71 unsigned long flags = 0;
72
73 u_int32_t status;
74 int n;
75
76 #ifdef RLD_DUMP_BUFDATA
77 u_int32_t *dp;
78 int len = 0;
79 #endif
80 if (lockit)
81 spin_lock_irqsave(&ch->ch_rxlock, flags);
82 if (ch->rxd_num == 0)
83 pr_info(" ZERO receive buffers allocated for this channel.");
84 else {
85 FLUSH_MEM_READ();
86 m = &ch->mdr[ch->rxix_irq_srv];
87 for (n = ch->rxd_num; n; n--) {
88 status = le32_to_cpu(m->status);
89 pr_info("%c %08lx[%2d]: sts %08x (%c%c%c%c:%d.) Data [%08x] Next [%08x]\n",
90 (m == &ch->mdr[ch->rxix_irq_srv]) ? 'F' : ' ',
91 (unsigned long) m, n,
92 status,
93 m->data ? (status & HOST_RX_OWNED ? 'H' : 'M') : '-',
94 status & POLL_DISABLED ? 'P' : '-',
95 status & EOBIRQ_ENABLE ? 'b' : '-',
96 status & EOMIRQ_ENABLE ? 'm' : '-',
97 status & LENGTH_MASK,
98 le32_to_cpu(m->data), le32_to_cpu(m->next));
99 #ifdef RLD_DUMP_BUFDATA
100 len = status & LENGTH_MASK;
101
102 #if 1
103 if (m->data && (status & HOST_RX_OWNED))
104 #else
105 /* always dump regardless of valid RX data */
106 if (m->data)
107 #endif
108 {
109 dp = (u_int32_t *)OS_phystov((void *)(le32_to_cpu(m->data)));
110 if (len >= 0x10)
111 pr_info(" %x[%x]: %08X %08X %08X %08x\n",
112 (u_int32_t)dp, len,
113 *dp, *(dp + 1),
114 *(dp + 2), *(dp + 3));
115 else if (len >= 0x08)
116 pr_info(" %x[%x]: %08X %08X\n",
117 (u_int32_t)dp, len,
118 *dp, *(dp + 1));
119 else
120 pr_info(" %x[%x]: %08X\n",
121 (u_int32_t)dp,
122 len, *dp);
123 }
124 #endif
125 m = m->snext;
126 }
127 }
128 pr_info("\n");
129
130 if (lockit)
131 spin_unlock_irqrestore(&ch->ch_rxlock, flags);
132 return 0;
133 }
134
135 static int
136 musycc_dump_txbuffer_ring(mch_t *ch, int lockit)
137 {
138 struct mdesc *m;
139 unsigned long flags = 0;
140 u_int32_t status;
141 int n;
142 #ifdef RLD_DUMP_BUFDATA
143 u_int32_t *dp;
144 int len = 0;
145 #endif
146
147 if (lockit)
148 spin_lock_irqsave(&ch->ch_txlock, flags);
149 if (ch->txd_num == 0)
150 pr_info(" ZERO transmit buffers allocated for this channel.");
151 else {
152 FLUSH_MEM_READ();
153 m = ch->txd_irq_srv;
154 for (n = ch->txd_num; n; n--) {
155 status = le32_to_cpu(m->status);
156 pr_info("%c%c %08lx[%2d]: sts %08x (%c%c%c%c:%d.) Data [%08x] Next [%08x]\n",
157 (m == ch->txd_usr_add) ? 'F' : ' ',
158 (m == ch->txd_irq_srv) ? 'L' : ' ',
159 (unsigned long) m, n,
160 status,
161 m->data ? (status & MUSYCC_TX_OWNED ? 'M' : 'H') : '-',
162 status & POLL_DISABLED ? 'P' : '-',
163 status & EOBIRQ_ENABLE ? 'b' : '-',
164 status & EOMIRQ_ENABLE ? 'm' : '-',
165 status & LENGTH_MASK,
166 le32_to_cpu(m->data), le32_to_cpu(m->next));
167 #ifdef RLD_DUMP_BUFDATA
168 len = status & LENGTH_MASK;
169
170 if (m->data) {
171 dp = (u_int32_t *)OS_phystov((void *)(le32_to_cpu(m->data)));
172 if (len >= 0x10)
173 pr_info(" %x[%x]: %08X %08X %08X %08x\n",
174 (u_int32_t) dp, len,
175 *dp, *(dp + 1),
176 *(dp + 2), *(dp + 3));
177 else if (len >= 0x08)
178 pr_info(" %x[%x]: %08X %08X\n",
179 (u_int32_t)dp, len,
180 *dp, *(dp + 1));
181 else
182 pr_info(" %x[%x]: %08X\n",
183 (u_int32_t)dp, len, *dp);
184 }
185 #endif
186 m = m->snext;
187 }
188 } /* -for- */
189 pr_info("\n");
190
191 if (lockit)
192 spin_unlock_irqrestore(&ch->ch_txlock, flags);
193 return 0;
194 }
195
196 /*
197 * The following supports a backdoor debug facility which can be used to
198 * display the state of a board's channel.
199 */
200
201 status_t
202 musycc_dump_ring(ci_t *ci, unsigned int chan)
203 {
204 mch_t *ch;
205 int bh;
206
207 if (chan >= MAX_CHANS_USED)
208 return SBE_DRVR_FAIL; /* E2BIG */
209
210 bh = atomic_read(&ci->bh_pending);
211 pr_info(">> bh_pend %d [%d] ihead %d itail %d [%d] th_cnt %d bh_cnt %d wdcnt %d note %d\n",
212 bh, max_bh, ci->iqp_headx, ci->iqp_tailx, max_intcnt,
213 ci->intlog.drvr_intr_thcount,
214 ci->intlog.drvr_intr_bhcount,
215 ci->wdcount, ci->wd_notify);
216 max_bh = 0; /* reset counter */
217 max_intcnt = 0; /* reset counter */
218
219 ch = sd_find_chan(dummy, chan);
220 if (!ch) {
221 pr_info(">> musycc_dump_ring: channel %d not up.\n", chan);
222 return ENOENT;
223 }
224 pr_info(">> CI %p CHANNEL %3d @ %p: state %x status/p %x/%x\n",
225 ci, chan, ch, ch->state,
226 ch->status, ch->p.status);
227 pr_info("--------------------------------\n");
228 pr_info("TX Buffer Ring - Channel %d, txd_num %d. (bd/ch pend %d %d), TXD required %d, txpkt %lu\n",
229 chan, ch->txd_num,
230 (u_int32_t)atomic_read(&ci->tx_pending),
231 (u_int32_t)atomic_read(&ch->tx_pending),
232 ch->txd_required, ch->s.tx_packets);
233 pr_info("++ User 0x%p IRQ_SRV 0x%p USR_ADD 0x%p QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
234 ch->user, ch->txd_irq_srv, ch->txd_usr_add,
235 sd_queue_stopped(ch->user),
236 ch->ch_start_tx, ch->tx_full, ch->txd_free, ch->p.chan_mode);
237 musycc_dump_txbuffer_ring(ch, 1);
238 pr_info("RX Buffer Ring - Channel %d, rxd_num %d. IRQ_SRV[%d] 0x%p, start_rx %x rxpkt %lu\n",
239 chan, ch->rxd_num, ch->rxix_irq_srv,
240 &ch->mdr[ch->rxix_irq_srv], ch->ch_start_rx, ch->s.rx_packets);
241 musycc_dump_rxbuffer_ring(ch, 1);
242
243 return SBE_DRVR_SUCCESS;
244 }
245
246
247 status_t
248 musycc_dump_rings(ci_t *ci, unsigned int start_chan)
249 {
250 unsigned int chan;
251
252 for (chan = start_chan; chan < (start_chan + 5); chan++)
253 musycc_dump_ring(ci, chan);
254 return SBE_DRVR_SUCCESS;
255 }
256
257
258 /*
259 * NOTE on musycc_init_mdt(): These MUSYCC writes are only operational after
260 * a MUSYCC GROUP_INIT command has been issued.
261 */
262
263 void
264 musycc_init_mdt(mpi_t *pi)
265 {
266 u_int32_t *addr, cfg;
267 int i;
268
269 /*
270 * This Idle Code insertion takes effect prior to channel's first
271 * transmitted message. After that, each message contains its own Idle
272 * Code information which is to be issued after the message is
273 * transmitted (Ref.MUSYCC 5.2.2.3: MCENBL bit in Group Configuration
274 * Descriptor).
275 */
276
277 addr = (u_int32_t *) ((u_long) pi->reg + MUSYCC_MDT_BASE03_ADDR);
278 cfg = CFG_CH_FLAG_7E << IDLE_CODE;
279
280 for (i = 0; i < 32; addr++, i++)
281 pci_write_32(addr, cfg);
282 }
283
284
285 /* Set TX thp to the next unprocessed md */
286
287 void
288 musycc_update_tx_thp(mch_t *ch)
289 {
290 struct mdesc *md;
291 unsigned long flags;
292
293 spin_lock_irqsave(&ch->ch_txlock, flags);
294 while (1) {
295 md = ch->txd_irq_srv;
296 FLUSH_MEM_READ();
297 if (!md->data) {
298 /* No MDs with buffers to process */
299 spin_unlock_irqrestore(&ch->ch_txlock, flags);
300 return;
301 }
302 if ((le32_to_cpu(md->status)) & MUSYCC_TX_OWNED) {
303 /* this is the MD to restart TX with */
304 break;
305 }
306 /*
307 * Otherwise, we have a valid, host-owned message descriptor which
308 * has been successfully transmitted and whose buffer can be freed,
309 * so... process this MD, it's owned by the host. (This might give
310 * as a new, updated txd_irq_srv.)
311 */
312 musycc_bh_tx_eom(ch->up, ch->gchan);
313 }
314 md = ch->txd_irq_srv;
315 ch->up->regram->thp[ch->gchan] = cpu_to_le32(OS_vtophys(md));
316 FLUSH_MEM_WRITE();
317
318 if (ch->tx_full) {
319 ch->tx_full = 0;
320 ch->txd_required = 0;
321 sd_enable_xmit(ch->user); /* re-enable to catch flow controlled
322 * channel */
323 }
324 spin_unlock_irqrestore(&ch->ch_txlock, flags);
325
326 #ifdef RLD_TRANS_DEBUG
327 pr_info("++ musycc_update_tx_thp[%d]: setting thp = %p, sts %x\n",
328 ch->channum, md, md->status);
329 #endif
330 }
331
332
333 /*
334 * This is the workq task executed by the OS when our queue_work() is
335 * scheduled and run. It can fire off either RX or TX ACTIVATION depending
336 * upon the channel's ch_start_tx and ch_start_rx variables. This routine
337 * is implemented as a work queue so that the call to the service request is
338 * able to sleep, awaiting an interrupt acknowledgment response (SACK) from
339 * the hardware.
340 */
341
342 void
343 musycc_wq_chan_restart(void *arg) /* channel private structure */
344 {
345 mch_t *ch;
346 mpi_t *pi;
347 struct mdesc *md;
348
349 #if defined(RLD_TRANS_DEBUG) || defined(RLD_RXACT_DEBUG)
350 static int hereb4 = 7;
351 #endif
352
353 ch = container_of(arg, struct c4_chan_info, ch_work);
354 pi = ch->up;
355
356 #ifdef RLD_TRANS_DEBUG
357 pr_info("wq_chan_restart[%d]: start_RT[%d/%d] status %x\n",
358 ch->channum, ch->ch_start_rx, ch->ch_start_tx, ch->status);
359
360 #endif
361
362 /**********************************/
363 /** check for RX restart request **/
364 /**********************************/
365
366 if ((ch->ch_start_rx) && (ch->status & RX_ENABLED)) {
367
368 ch->ch_start_rx = 0;
369 #if defined(RLD_TRANS_DEBUG) || defined(RLD_RXACT_DEBUG)
370 if (hereb4) { /* RLD DEBUG */
371 hereb4--;
372 #ifdef RLD_TRANS_DEBUG
373 md = &ch->mdr[ch->rxix_irq_srv];
374 pr_info("++ musycc_wq_chan_restart[%d] CHAN RX ACTIVATE: rxix_irq_srv %d, md %p sts %x, rxpkt %lu\n",
375 ch->channum, ch->rxix_irq_srv, md,
376 le32_to_cpu(md->status), ch->s.rx_packets);
377 #elif defined(RLD_RXACT_DEBUG)
378 md = &ch->mdr[ch->rxix_irq_srv];
379 pr_info("++ musycc_wq_chan_restart[%d] CHAN RX ACTIVATE: rxix_irq_srv %d, md %p sts %x, rxpkt %lu\n",
380 ch->channum, ch->rxix_irq_srv,
381 md, le32_to_cpu(md->status),
382 ch->s.rx_packets);
383 musycc_dump_rxbuffer_ring(ch, 1); /* RLD DEBUG */
384 #endif
385 }
386 #endif
387 musycc_serv_req(pi, SR_CHANNEL_ACTIVATE |
388 SR_RX_DIRECTION | ch->gchan);
389 }
390 /**********************************/
391 /** check for TX restart request **/
392 /**********************************/
393
394 if ((ch->ch_start_tx) && (ch->status & TX_ENABLED)) {
395 /* find next unprocessed message, then set TX thp to it */
396 musycc_update_tx_thp(ch);
397
398 md = ch->txd_irq_srv;
399 if (!md) {
400 #ifdef RLD_TRANS_DEBUG
401 pr_info("-- musycc_wq_chan_restart[%d]: WARNING, starting NULL md\n",
402 ch->channum);
403 #endif
404 } else if (md->data && ((le32_to_cpu(md->status)) &
405 MUSYCC_TX_OWNED)) {
406 ch->ch_start_tx = 0;
407
408 #ifdef RLD_TRANS_DEBUG
409 pr_info("++ musycc_wq_chan_restart() CHAN TX ACTIVATE: chan %d txd_irq_srv %p = sts %x, txpkt %lu\n",
410 ch->channum, ch->txd_irq_srv,
411 ch->txd_irq_srv->status, ch->s.tx_packets);
412 #endif
413 musycc_serv_req(pi, SR_CHANNEL_ACTIVATE |
414 SR_TX_DIRECTION | ch->gchan);
415 }
416 #ifdef RLD_RESTART_DEBUG
417 else {
418 /* retain request to start until retried and we have data to xmit */
419 pr_info("-- musycc_wq_chan_restart[%d]: DELAYED due to md %p sts %x data %x, start_tx %x\n",
420 ch->channum, md,
421 le32_to_cpu(md->status),
422 le32_to_cpu(md->data), ch->ch_start_tx);
423 musycc_dump_txbuffer_ring(ch, 0);
424 }
425 #endif
426 }
427 }
428
429
430 /*
431 * Channel restart either fires of a workqueue request (2.6) or lodges a
432 * watchdog activation sequence (2.4).
433 */
434
435 void
436 musycc_chan_restart(mch_t *ch)
437 {
438 #ifdef RLD_RESTART_DEBUG
439 pr_info("++ musycc_chan_restart[%d]: txd_irq_srv @ %p = sts %x\n",
440 ch->channum, ch->txd_irq_srv, ch->txd_irq_srv->status);
441 #endif
442
443 /* 2.6 - find next unprocessed message, then set TX thp to it */
444 #ifdef RLD_RESTART_DEBUG
445 pr_info(">> musycc_chan_restart: scheduling Chan %x workQ @ %p\n",
446 ch->channum, &ch->ch_work);
447 #endif
448 c4_wk_chan_restart(ch); /* work queue mechanism fires off: Ref:
449 * musycc_wq_chan_restart () */
450 }
451
452
453 void
454 rld_put_led(mpi_t *pi, u_int32_t ledval)
455 {
456 static u_int32_t led;
457
458 if (ledval == 0)
459 led = 0;
460 else
461 led |= ledval;
462
463 /* RLD DEBUG TRANHANG */
464 pci_write_32((u_int32_t *) &pi->up->cpldbase->leds, led);
465 }
466
467
468 #define MUSYCC_SR_RETRY_CNT 9
469
470 void
471 musycc_serv_req(mpi_t *pi, u_int32_t req)
472 {
473 volatile u_int32_t r;
474 int rcnt;
475
476 /*
477 * PORT NOTE: Semaphore protect service loop guarantees only a single
478 * operation at a time. Per MUSYCC Manual - "Issuing service requests to
479 * the same channel group without first receiving ACK from each request
480 * may cause the host to lose track of which service request has been
481 * acknowledged."
482 */
483
484 SD_SEM_TAKE(&pi->sr_sem_busy, "serv"); /* only 1 thru here, per
485 * group */
486
487 if (pi->sr_last == req) {
488 #ifdef RLD_TRANS_DEBUG
489 pr_info(">> same SR, Port %d Req %x\n", pi->portnum, req);
490 #endif
491
492 /*
493 * The most likely repeated request is the channel activation command
494 * which follows the occurrence of a Transparent mode TX ONR or a
495 * BUFF error. If the previous command was a CHANNEL ACTIVATE,
496 * precede it with a NOOP command in order maintain coherent control
497 * of this current (re)ACTIVATE.
498 */
499
500 r = (pi->sr_last & ~SR_GCHANNEL_MASK);
501 if ((r == (SR_CHANNEL_ACTIVATE | SR_TX_DIRECTION)) ||
502 (r == (SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION))) {
503 #ifdef RLD_TRANS_DEBUG
504 pr_info(">> same CHAN ACT SR, Port %d Req %x => issue SR_NOOP CMD\n", pi->portnum, req);
505 #endif
506 /* allow this next request */
507 SD_SEM_GIVE(&pi->sr_sem_busy);
508 musycc_serv_req(pi, SR_NOOP);
509 /* relock & continue w/ original req */
510 SD_SEM_TAKE(&pi->sr_sem_busy, "serv");
511 } else if (req == SR_NOOP) {
512 /* no need to issue back-to-back
513 * SR_NOOP commands at this time
514 */
515 #ifdef RLD_TRANS_DEBUG
516 pr_info(">> same Port SR_NOOP skipped, Port %d\n",
517 pi->portnum);
518 #endif
519 /* allow this next request */
520 SD_SEM_GIVE(&pi->sr_sem_busy);
521 return;
522 }
523 }
524 rcnt = 0;
525 pi->sr_last = req;
526 rewrite:
527 pci_write_32((u_int32_t *) &pi->reg->srd, req);
528 FLUSH_MEM_WRITE();
529
530 /*
531 * Per MUSYCC Manual, Section 6.1,2 - "When writing an SCR service
532 * request, the host must ensure at least one PCI bus clock cycle has
533 * elapsed before writing another service request. To meet this minimum
534 * elapsed service request write timing interval, it is recommended that
535 * the host follow any SCR write with another operation which reads from
536 * the same address."
537 */
538
539 /* adhere to write timing imposition */
540 r = pci_read_32((u_int32_t *) &pi->reg->srd);
541
542
543 if ((r != req) && (req != SR_CHIP_RESET) &&
544 (++rcnt <= MUSYCC_SR_RETRY_CNT)) {
545 if (cxt1e1_log_level >= LOG_MONITOR)
546 pr_info("%s: %d - reissue srv req/last %x/%x (hdw reads %x), Chan %d.\n",
547 pi->up->devname, rcnt, req, pi->sr_last, r,
548 (pi->portnum * MUSYCC_NCHANS) + (req & 0x1f));
549 /* this delay helps reduce reissue counts
550 * (reason not yet researched)
551 */
552 OS_uwait_dummy();
553 goto rewrite;
554 }
555 if (rcnt > MUSYCC_SR_RETRY_CNT) {
556 pr_warning("%s: failed service request (#%d)= %x, group %d.\n",
557 pi->up->devname, MUSYCC_SR_RETRY_CNT,
558 req, pi->portnum);
559 SD_SEM_GIVE(&pi->sr_sem_busy); /* allow any next request */
560 return;
561 }
562 if (req == SR_CHIP_RESET) {
563 /*
564 * PORT NOTE: the CHIP_RESET command is NOT ack'd by the MUSYCC, thus
565 * the upcoming delay is used. Though the MUSYCC documentation
566 * suggests a read-after-write would supply the required delay, it's
567 * unclear what CPU/BUS clock speeds might have been assumed when
568 * suggesting this 'lack of ACK' workaround. Thus the use of uwait.
569 */
570 OS_uwait(100000, "icard"); /* 100ms */
571 } else {
572 FLUSH_MEM_READ();
573 /* sleep until SACK interrupt occurs */
574 SD_SEM_TAKE(&pi->sr_sem_wait, "sakack");
575 }
576 SD_SEM_GIVE(&pi->sr_sem_busy); /* allow any next request */
577 }
578
579
580 #ifdef SBE_PMCC4_ENABLE
581 void
582 musycc_update_timeslots(mpi_t *pi)
583 {
584 int i, ch;
585 char e1mode = IS_FRAME_ANY_E1(pi->p.port_mode);
586
587 for (i = 0; i < 32; i++) {
588 int usedby = 0, last = 0, ts, j, bits[8];
589
590 u_int8_t lastval = 0;
591
592 if (((i == 0) && e1mode) || /* disable if E1 mode */
593 ((i == 16) && ((pi->p.port_mode == CFG_FRAME_E1CRC_CAS) ||
594 (pi->p.port_mode == CFG_FRAME_E1CRC_CAS_AMI))) ||
595 ((i > 23) && (!e1mode))) /* disable if T1 mode */
596 /* make tslot unavailable for this mode */
597 pi->tsm[i] = 0xff;
598 else
599 /* make tslot available for assignment */
600 pi->tsm[i] = 0x00;
601 for (j = 0; j < 8; j++)
602 bits[j] = -1;
603 for (ch = 0; ch < MUSYCC_NCHANS; ch++) {
604 if ((pi->chan[ch]->state == UP) &&
605 (pi->chan[ch]->p.bitmask[i])) {
606 usedby++;
607 last = ch;
608 lastval = pi->chan[ch]->p.bitmask[i];
609 for (j = 0; j < 8; j++)
610 if (lastval & (1 << j))
611 bits[j] = ch;
612 pi->tsm[i] |= lastval;
613 }
614 }
615 if (!usedby)
616 ts = 0;
617 else if ((usedby == 1) && (lastval == 0xff))
618 ts = (4 << 5) | last;
619 else if ((usedby == 1) && (lastval == 0x7f))
620 ts = (5 << 5) | last;
621 else {
622 int idx;
623
624 if (bits[0] < 0)
625 ts = (6 << 5) | (idx = last);
626 else
627 ts = (7 << 5) | (idx = bits[0]);
628 for (j = 1; j < 8; j++) {
629 pi->regram->rscm[idx * 8 + j] =
630 (bits[j] < 0) ? 0 : (0x80 | bits[j]);
631 pi->regram->tscm[idx * 8 + j] =
632 (bits[j] < 0) ? 0 : (0x80 | bits[j]);
633 }
634 }
635 pi->regram->rtsm[i] = ts;
636 pi->regram->ttsm[i] = ts;
637 }
638 FLUSH_MEM_WRITE();
639
640 musycc_serv_req(pi, SR_TIMESLOT_MAP | SR_RX_DIRECTION);
641 musycc_serv_req(pi, SR_TIMESLOT_MAP | SR_TX_DIRECTION);
642 musycc_serv_req(pi, SR_SUBCHANNEL_MAP | SR_RX_DIRECTION);
643 musycc_serv_req(pi, SR_SUBCHANNEL_MAP | SR_TX_DIRECTION);
644 }
645 #endif
646
647
648 #ifdef SBE_WAN256T3_ENABLE
649 void
650 musycc_update_timeslots(mpi_t *pi)
651 {
652 mch_t *ch;
653
654 u_int8_t ts, hmask, tsen;
655 int gchan;
656 int i;
657
658 #ifdef SBE_PMCC4_ENABLE
659 hmask = (0x1f << pi->up->p.hypersize) & 0x1f;
660 #endif
661 #ifdef SBE_WAN256T3_ENABLE
662 hmask = (0x1f << hyperdummy) & 0x1f;
663 #endif
664 for (i = 0; i < 128; i++) {
665 gchan = ((pi->portnum * MUSYCC_NCHANS) +
666 (i & hmask)) % MUSYCC_NCHANS;
667 ch = pi->chan[gchan];
668 if (ch->p.mode_56k)
669 tsen = MODE_56KBPS;
670 else
671 tsen = MODE_64KBPS; /* also the default */
672 ts = ((pi->portnum % 4) == (i / 32)) ? (tsen << 5) | (i & hmask) : 0;
673 pi->regram->rtsm[i] = ts;
674 pi->regram->ttsm[i] = ts;
675 }
676 FLUSH_MEM_WRITE();
677 musycc_serv_req(pi, SR_TIMESLOT_MAP | SR_RX_DIRECTION);
678 musycc_serv_req(pi, SR_TIMESLOT_MAP | SR_TX_DIRECTION);
679 }
680 #endif
681
682
683 /*
684 * This routine converts a generic library channel configuration parameter
685 * into a hardware specific register value (IE. MUSYCC CCD Register).
686 */
687 u_int32_t
688 musycc_chan_proto(int proto)
689 {
690 int reg;
691
692 switch (proto) {
693 case CFG_CH_PROTO_TRANS: /* 0 */
694 reg = MUSYCC_CCD_TRANS;
695 break;
696 case CFG_CH_PROTO_SS7: /* 1 */
697 reg = MUSYCC_CCD_SS7;
698 break;
699 default:
700 case CFG_CH_PROTO_ISLP_MODE: /* 4 */
701 case CFG_CH_PROTO_HDLC_FCS16: /* 2 */
702 reg = MUSYCC_CCD_HDLC_FCS16;
703 break;
704 case CFG_CH_PROTO_HDLC_FCS32: /* 3 */
705 reg = MUSYCC_CCD_HDLC_FCS32;
706 break;
707 }
708
709 return reg;
710 }
711
712 #ifdef SBE_WAN256T3_ENABLE
713 static void __init
714 musycc_init_port(mpi_t *pi)
715 {
716 pci_write_32((u_int32_t *) &pi->reg->gbp, OS_vtophys(pi->regram));
717
718 pi->regram->grcd =
719 __constant_cpu_to_le32(MUSYCC_GRCD_RX_ENABLE |
720 MUSYCC_GRCD_TX_ENABLE |
721 MUSYCC_GRCD_SF_ALIGN |
722 MUSYCC_GRCD_SUBCHAN_DISABLE |
723 MUSYCC_GRCD_OOFMP_DISABLE |
724 MUSYCC_GRCD_COFAIRQ_DISABLE |
725 MUSYCC_GRCD_MC_ENABLE |
726 (MUSYCC_GRCD_POLLTH_32 << MUSYCC_GRCD_POLLTH_SHIFT));
727
728 pi->regram->pcd =
729 __constant_cpu_to_le32(MUSYCC_PCD_E1X4_MODE |
730 MUSYCC_PCD_TXDATA_RISING |
731 MUSYCC_PCD_TX_DRIVEN);
732
733 /* Message length descriptor */
734 pi->regram->mld = __constant_cpu_to_le32(cxt1e1_max_mru | (cxt1e1_max_mru << 16));
735 FLUSH_MEM_WRITE();
736
737 musycc_serv_req(pi, SR_GROUP_INIT | SR_RX_DIRECTION);
738 musycc_serv_req(pi, SR_GROUP_INIT | SR_TX_DIRECTION);
739
740 musycc_init_mdt(pi);
741
742 musycc_update_timeslots(pi);
743 }
744 #endif
745
746
747 status_t __init
748 musycc_init(ci_t *ci)
749 {
750 char *regaddr; /* temp for address boundary calculations */
751 int i, gchan;
752
753 OS_sem_init(&ci->sem_wdbusy, SEM_AVAILABLE); /* watchdog exclusion */
754
755 /*
756 * Per MUSYCC manual, Section 6.3.4 - "The host must allocate a dword
757 * aligned memory segment for interrupt queue pointers."
758 */
759
760 #define INT_QUEUE_BOUNDARY 4
761
762 regaddr = kzalloc((INT_QUEUE_SIZE + 1) * sizeof(u_int32_t),
763 GFP_KERNEL | GFP_DMA);
764 if (!regaddr)
765 return -ENOMEM;
766 ci->iqd_p_saved = regaddr; /* save orig value for free's usage */
767 /* this calculates closest boundary */
768 ci->iqd_p = (u_int32_t *) ((unsigned long)(regaddr + INT_QUEUE_BOUNDARY - 1) &
769 (~(INT_QUEUE_BOUNDARY - 1)));
770
771 for (i = 0; i < INT_QUEUE_SIZE; i++)
772 ci->iqd_p[i] = __constant_cpu_to_le32(INT_EMPTY_ENTRY);
773
774 for (i = 0; i < ci->max_port; i++) {
775 mpi_t *pi = &ci->port[i];
776
777 /*
778 * Per MUSYCC manual, Section 6.3.2 - "The host must allocate a 2KB
779 * bound memory segment for Channel Group 0."
780 */
781
782 #define GROUP_BOUNDARY 0x800
783
784 regaddr = kzalloc(sizeof(struct musycc_groupr) + GROUP_BOUNDARY,
785 GFP_KERNEL | GFP_DMA);
786 if (!regaddr) {
787 for (gchan = 0; gchan < i; gchan++) {
788 pi = &ci->port[gchan];
789 kfree(pi->reg);
790 pi->reg = NULL;
791 }
792 return -ENOMEM;
793 }
794 pi->regram_saved = regaddr; /* save orig value for free's usage */
795 /* this calculates closest boundary */
796 pi->regram = (struct musycc_groupr *) ((unsigned long)(regaddr + GROUP_BOUNDARY - 1) &
797 (~(GROUP_BOUNDARY - 1)));
798 }
799
800 /* any board centric MUSYCC commands will use group ZERO as its "home" */
801 ci->regram = ci->port[0].regram;
802 musycc_serv_req(&ci->port[0], SR_CHIP_RESET);
803
804 pci_write_32((u_int32_t *) &ci->reg->gbp, OS_vtophys(ci->regram));
805 pci_flush_write(ci);
806 #ifdef CONFIG_SBE_PMCC4_NCOMM
807 ci->regram->__glcd = __constant_cpu_to_le32(GCD_MAGIC);
808 #else
809 /* standard driver POLLS for INTB via CPLD register */
810 ci->regram->__glcd = __constant_cpu_to_le32(GCD_MAGIC |
811 MUSYCC_GCD_INTB_DISABLE);
812 #endif
813
814 ci->regram->__iqp = cpu_to_le32(OS_vtophys(&ci->iqd_p[0]));
815 ci->regram->__iql = __constant_cpu_to_le32(INT_QUEUE_SIZE - 1);
816 pci_write_32((u_int32_t *) &ci->reg->dacbp, 0);
817 FLUSH_MEM_WRITE();
818
819 ci->state = C_RUNNING; /* mark as full interrupt processing
820 * available */
821
822 musycc_serv_req(&ci->port[0], SR_GLOBAL_INIT); /* FIRST INTERRUPT ! */
823
824 /* sanity check settable parameters */
825
826 if (cxt1e1_max_mru > 0xffe) {
827 pr_warning("Maximum allowed MRU exceeded, resetting %d to %d.\n",
828 cxt1e1_max_mru, 0xffe);
829 cxt1e1_max_mru = 0xffe;
830 }
831 if (cxt1e1_max_mtu > 0xffe) {
832 pr_warning("Maximum allowed MTU exceeded, resetting %d to %d.\n",
833 cxt1e1_max_mtu, 0xffe);
834 cxt1e1_max_mtu = 0xffe;
835 }
836 #ifdef SBE_WAN256T3_ENABLE
837 for (i = 0; i < MUSYCC_NPORTS; i++)
838 musycc_init_port(&ci->port[i]);
839 #endif
840
841 return SBE_DRVR_SUCCESS; /* no error */
842 }
843
844
845 void
846 musycc_bh_tx_eom(mpi_t *pi, int gchan)
847 {
848 mch_t *ch;
849 struct mdesc *md;
850
851 volatile u_int32_t status;
852
853 ch = pi->chan[gchan];
854 if (!ch || ch->state != UP) {
855 if (cxt1e1_log_level >= LOG_ERROR)
856 pr_info("%s: intr: xmit EOM on uninitialized channel %d\n",
857 pi->up->devname, gchan);
858 }
859 if (!ch || !ch->mdt)
860 return; /* note: mdt==0 implies a malloc()
861 * failure w/in chan_up() routine */
862
863 do {
864 FLUSH_MEM_READ();
865 md = ch->txd_irq_srv;
866 status = le32_to_cpu(md->status);
867
868 /*
869 * Note: Per MUSYCC Ref 6.4.9, the host does not poll a host-owned
870 * Transmit Buffer Descriptor during Transparent Mode.
871 */
872 if (status & MUSYCC_TX_OWNED) {
873 int readCount, loopCount;
874
875 /***********************************************************/
876 /* HW Bug Fix */
877 /* ---------- */
878 /* Under certain PCI Bus loading conditions, the data */
879 /* associated with an update of Shared Memory is delayed */
880 /* relative to its PCI Interrupt. This is caught when */
881 /* the host determines it does not yet OWN the descriptor. */
882 /***********************************************************/
883
884 readCount = 0;
885 while (status & MUSYCC_TX_OWNED) {
886 for (loopCount = 0; loopCount < 0x30; loopCount++)
887 /* use call to avoid optimization
888 * removal of dummy delay */
889 OS_uwait_dummy();
890 FLUSH_MEM_READ();
891 status = le32_to_cpu(md->status);
892 if (readCount++ > 40)
893 break; /* don't wait any longer */
894 }
895 if (status & MUSYCC_TX_OWNED) {
896 if (cxt1e1_log_level >= LOG_MONITOR) {
897 pr_info("%s: Port %d Chan %2d - unexpected TX msg ownership intr (md %p sts %x)\n",
898 pi->up->devname, pi->portnum,
899 ch->channum, md, status);
900 pr_info("++ User 0x%p IRQ_SRV 0x%p USR_ADD 0x%p QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
901 ch->user, ch->txd_irq_srv,
902 ch->txd_usr_add,
903 sd_queue_stopped(ch->user),
904 ch->ch_start_tx, ch->tx_full,
905 ch->txd_free, ch->p.chan_mode);
906 musycc_dump_txbuffer_ring(ch, 0);
907 }
908 break; /* Not our mdesc, done */
909 } else {
910 if (cxt1e1_log_level >= LOG_MONITOR)
911 pr_info("%s: Port %d Chan %2d - recovered TX msg ownership [%d] (md %p sts %x)\n",
912 pi->up->devname, pi->portnum,
913 ch->channum, readCount,
914 md, status);
915 }
916 }
917 ch->txd_irq_srv = md->snext;
918
919 md->data = 0;
920 if (md->mem_token) {
921 /* upcount channel */
922 atomic_sub(OS_mem_token_tlen(md->mem_token),
923 &ch->tx_pending);
924 /* upcount card */
925 atomic_sub(OS_mem_token_tlen(md->mem_token),
926 &pi->up->tx_pending);
927 #ifdef SBE_WAN256T3_ENABLE
928 if (!atomic_read(&pi->up->tx_pending))
929 wan256t3_led(pi->up, LED_TX, 0);
930 #endif
931 OS_mem_token_free_irq(md->mem_token);
932 md->mem_token = NULL;
933 }
934 md->status = 0;
935 #ifdef RLD_TXFULL_DEBUG
936 if (cxt1e1_log_level >= LOG_MONITOR2)
937 pr_info("~~ tx_eom: tx_full %x txd_free %d -> %d\n",
938 ch->tx_full, ch->txd_free, ch->txd_free + 1);
939 #endif
940 ++ch->txd_free;
941 FLUSH_MEM_WRITE();
942
943 if ((ch->p.chan_mode != CFG_CH_PROTO_TRANS) &&
944 (status & EOBIRQ_ENABLE)) {
945 if (cxt1e1_log_level >= LOG_MONITOR)
946 pr_info("%s: Mode (%x) incorrect EOB status (%x)\n",
947 pi->up->devname, ch->p.chan_mode,
948 status);
949 if ((status & EOMIRQ_ENABLE) == 0)
950 break;
951 }
952 } while ((ch->p.chan_mode != CFG_CH_PROTO_TRANS) &&
953 ((status & EOMIRQ_ENABLE) == 0));
954 /*
955 * NOTE: (The above 'while' is coupled w/ previous 'do', way above.) Each
956 * Transparent data buffer has the EOB bit, and NOT the EOM bit, set and
957 * will furthermore have a separate IQD associated with each messages
958 * buffer.
959 */
960
961 FLUSH_MEM_READ();
962 /*
963 * Smooth flow control hysterisis by maintaining task stoppage until half
964 * the available write buffers are available.
965 */
966 if (ch->tx_full && (ch->txd_free >= (ch->txd_num / 2))) {
967 /*
968 * Then, only releave task stoppage if we actually have enough
969 * buffers to service the last requested packet. It may require MORE
970 * than half the available!
971 */
972 if (ch->txd_free >= ch->txd_required) {
973
974 #ifdef RLD_TXFULL_DEBUG
975 if (cxt1e1_log_level >= LOG_MONITOR2)
976 pr_info("tx_eom[%d]: enable xmit tx_full no more, txd_free %d txd_num/2 %d\n",
977 ch->channum,
978 ch->txd_free, ch->txd_num / 2);
979 #endif
980 ch->tx_full = 0;
981 ch->txd_required = 0;
982 /* re-enable to catch flow controlled channel */
983 sd_enable_xmit(ch->user);
984 }
985 }
986 #ifdef RLD_TXFULL_DEBUG
987 else if (ch->tx_full) {
988 if (cxt1e1_log_level >= LOG_MONITOR2)
989 pr_info("tx_eom[%d]: bypass TX enable though room available? (txd_free %d txd_num/2 %d)\n",
990 ch->channum,
991 ch->txd_free, ch->txd_num / 2);
992 }
993 #endif
994
995 FLUSH_MEM_WRITE();
996 }
997
998
999 static void
1000 musycc_bh_rx_eom(mpi_t *pi, int gchan)
1001 {
1002 mch_t *ch;
1003 void *m, *m2;
1004 struct mdesc *md;
1005 volatile u_int32_t status;
1006 u_int32_t error;
1007
1008 ch = pi->chan[gchan];
1009 if (!ch || ch->state != UP) {
1010 if (cxt1e1_log_level > LOG_ERROR)
1011 pr_info("%s: intr: receive EOM on uninitialized channel %d\n",
1012 pi->up->devname, gchan);
1013 return;
1014 }
1015 if (!ch->mdr)
1016 return; /* can this happen ? */
1017
1018 for (;;) {
1019 FLUSH_MEM_READ();
1020 md = &ch->mdr[ch->rxix_irq_srv];
1021 status = le32_to_cpu(md->status);
1022 if (!(status & HOST_RX_OWNED))
1023 break; /* Not our mdesc, done */
1024 m = md->mem_token;
1025 error = (status >> 16) & 0xf;
1026 if (error == 0) {
1027 {
1028 m2 = OS_mem_token_alloc(cxt1e1_max_mru);
1029 if (m2) {
1030 /* substitute the mbuf+cluster */
1031 md->mem_token = m2;
1032 md->data = cpu_to_le32(OS_vtophys(
1033 OS_mem_token_data(m2)));
1034
1035 /* pass the received mbuf upward */
1036 sd_recv_consume(m, status & LENGTH_MASK,
1037 ch->user);
1038 ch->s.rx_packets++;
1039 ch->s.rx_bytes += status & LENGTH_MASK;
1040 } else
1041 ch->s.rx_dropped++;
1042 }
1043 } else if (error == ERR_FCS)
1044 ch->s.rx_crc_errors++;
1045 else if (error == ERR_ALIGN)
1046 ch->s.rx_missed_errors++;
1047 else if (error == ERR_ABT)
1048 ch->s.rx_missed_errors++;
1049 else if (error == ERR_LNG)
1050 ch->s.rx_length_errors++;
1051 else if (error == ERR_SHT)
1052 ch->s.rx_length_errors++;
1053 FLUSH_MEM_WRITE();
1054 status = cxt1e1_max_mru;
1055 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1056 status |= EOBIRQ_ENABLE;
1057 md->status = cpu_to_le32(status);
1058
1059 /* Check next mdesc in the ring */
1060 if (++ch->rxix_irq_srv >= ch->rxd_num)
1061 ch->rxix_irq_srv = 0;
1062 FLUSH_MEM_WRITE();
1063 }
1064 }
1065
1066
1067 irqreturn_t
1068 musycc_intr_th_handler(void *devp)
1069 {
1070 ci_t *ci = (ci_t *) devp;
1071 volatile u_int32_t status, currInt = 0;
1072 u_int32_t nextInt, intCnt;
1073
1074 /*
1075 * Hardware not available, potential interrupt hang. But since interrupt
1076 * might be shared, just return.
1077 */
1078 if (ci->state == C_INIT)
1079 return IRQ_NONE;
1080 /*
1081 * Marked as hardware available. Don't service interrupts, just clear the
1082 * event.
1083 */
1084
1085 if (ci->state == C_IDLE) {
1086 status = pci_read_32((u_int32_t *) &ci->reg->isd);
1087
1088 /* clear the interrupt but process nothing else */
1089 pci_write_32((u_int32_t *) &ci->reg->isd, status);
1090 return IRQ_HANDLED;
1091 }
1092 FLUSH_PCI_READ();
1093 FLUSH_MEM_READ();
1094
1095 status = pci_read_32((u_int32_t *) &ci->reg->isd);
1096 nextInt = INTRPTS_NEXTINT(status);
1097 intCnt = INTRPTS_INTCNT(status);
1098 ci->intlog.drvr_intr_thcount++;
1099
1100 /*********************************************************/
1101 /* HW Bug Fix */
1102 /* ---------- */
1103 /* Under certain PCI Bus loading conditions, the */
1104 /* MUSYCC looses the data associated with an update */
1105 /* of its ISD and erroneously returns the immediately */
1106 /* preceding 'nextInt' value. However, the 'intCnt' */
1107 /* value appears to be correct. By not starting service */
1108 /* where the 'missing' 'nextInt' SHOULD point causes */
1109 /* the IQD not to be serviced - the 'not serviced' */
1110 /* entries then remain and continue to increase as more */
1111 /* incorrect ISD's are encountered. */
1112 /*********************************************************/
1113
1114 if (nextInt != INTRPTS_NEXTINT(ci->intlog.this_status_new)) {
1115 if (cxt1e1_log_level >= LOG_MONITOR) {
1116 pr_info("%s: note - updated ISD from %08x to %08x\n",
1117 ci->devname, status,
1118 (status & (~INTRPTS_NEXTINT_M)) |
1119 ci->intlog.this_status_new);
1120 }
1121 /*
1122 * Replace bogus status with software corrected value.
1123 *
1124 * It's not known whether, during this problem occurrence, if the
1125 * INTFULL bit is correctly reported or not.
1126 */
1127 status = (status & (~INTRPTS_NEXTINT_M)) |
1128 (ci->intlog.this_status_new);
1129 nextInt = INTRPTS_NEXTINT(status);
1130 }
1131 /**********************************************/
1132 /* Cn847x Bug Fix */
1133 /* -------------- */
1134 /* Fix for inability to write back same index */
1135 /* as read for a full interrupt queue. */
1136 /**********************************************/
1137
1138 if (intCnt == INT_QUEUE_SIZE)
1139 currInt = ((intCnt - 1) + nextInt) & (INT_QUEUE_SIZE - 1);
1140 else
1141 /************************************************/
1142 /* Interrupt Write Location Issues */
1143 /* ------------------------------- */
1144 /* When the interrupt status descriptor is */
1145 /* written, the interrupt line is de-asserted */
1146 /* by the Cn847x. In the case of MIPS */
1147 /* microprocessors, this must occur at the */
1148 /* beginning of the interrupt handler so that */
1149 /* the interrupt handle is not re-entered due */
1150 /* to interrupt dis-assertion latency. */
1151 /* In the case of all other processors, this */
1152 /* action should occur at the end of the */
1153 /* interrupt handler to avoid overwriting the */
1154 /* interrupt queue. */
1155 /************************************************/
1156
1157 if (intCnt)
1158 currInt = (intCnt + nextInt) & (INT_QUEUE_SIZE - 1);
1159 else {
1160 /*
1161 * NOTE: Servicing an interrupt whose ISD contains a count of ZERO
1162 * can be indicative of a Shared Interrupt chain. Our driver can be
1163 * called from the system's interrupt handler as a matter of the OS
1164 * walking the chain. As the chain is walked, the interrupt will
1165 * eventually be serviced by the correct driver/handler.
1166 */
1167 return IRQ_NONE;
1168 }
1169
1170 ci->iqp_tailx = currInt;
1171
1172 currInt <<= INTRPTS_NEXTINT_S;
1173 ci->intlog.last_status_new = ci->intlog.this_status_new;
1174 ci->intlog.this_status_new = currInt;
1175
1176 if ((cxt1e1_log_level >= LOG_WARN) && (status & INTRPTS_INTFULL_M))
1177 pr_info("%s: Interrupt queue full condition occurred\n",
1178 ci->devname);
1179 if (cxt1e1_log_level >= LOG_DEBUG)
1180 pr_info("%s: interrupts pending, isd @ 0x%p: %x curr %d cnt %d NEXT %d\n",
1181 ci->devname, &ci->reg->isd,
1182 status, nextInt, intCnt,
1183 (intCnt + nextInt) & (INT_QUEUE_SIZE - 1));
1184
1185 FLUSH_MEM_WRITE();
1186 #if defined(SBE_ISR_TASKLET)
1187 pci_write_32((u_int32_t *) &ci->reg->isd, currInt);
1188 atomic_inc(&ci->bh_pending);
1189 tasklet_schedule(&ci->ci_musycc_isr_tasklet);
1190 #elif defined(SBE_ISR_IMMEDIATE)
1191 pci_write_32((u_int32_t *) &ci->reg->isd, currInt);
1192 atomic_inc(&ci->bh_pending);
1193 queue_task(&ci->ci_musycc_isr_tq, &tq_immediate);
1194 mark_bh(IMMEDIATE_BH);
1195 #elif defined(SBE_ISR_INLINE)
1196 (void) musycc_intr_bh_tasklet(ci);
1197 pci_write_32((u_int32_t *) &ci->reg->isd, currInt);
1198 #endif
1199 return IRQ_HANDLED;
1200 }
1201
1202
1203 #if defined(SBE_ISR_IMMEDIATE)
1204 unsigned long
1205 #else
1206 void
1207 #endif
1208 musycc_intr_bh_tasklet(ci_t *ci)
1209 {
1210 mpi_t *pi;
1211 mch_t *ch;
1212 unsigned int intCnt;
1213 volatile u_int32_t currInt = 0;
1214 volatile unsigned int headx, tailx;
1215 int readCount, loopCount;
1216 int group, gchan, event, err, tx;
1217 u_int32_t badInt = INT_EMPTY_ENTRY;
1218 u_int32_t badInt2 = INT_EMPTY_ENTRY2;
1219
1220 /*
1221 * Hardware not available, potential interrupt hang. But since interrupt
1222 * might be shared, just return.
1223 */
1224 if ((drvr_state != SBE_DRVR_AVAILABLE) || (ci->state == C_INIT)) {
1225 #if defined(SBE_ISR_IMMEDIATE)
1226 return 0L;
1227 #else
1228 return;
1229 #endif
1230 }
1231 #if defined(SBE_ISR_TASKLET) || defined(SBE_ISR_IMMEDIATE)
1232 if (drvr_state != SBE_DRVR_AVAILABLE) {
1233 #if defined(SBE_ISR_TASKLET)
1234 return;
1235 #elif defined(SBE_ISR_IMMEDIATE)
1236 return 0L;
1237 #endif
1238 }
1239 #elif defined(SBE_ISR_INLINE)
1240 /* no semaphore taken, no double checks */
1241 #endif
1242
1243 ci->intlog.drvr_intr_bhcount++;
1244 FLUSH_MEM_READ();
1245 {
1246 unsigned int bh = atomic_read(&ci->bh_pending);
1247
1248 max_bh = max(bh, max_bh);
1249 }
1250 atomic_set(&ci->bh_pending, 0);/* if here, no longer pending */
1251 while ((headx = ci->iqp_headx) != (tailx = ci->iqp_tailx)) {
1252 intCnt = (tailx >= headx) ? (tailx - headx) : (tailx - headx + INT_QUEUE_SIZE);
1253 currInt = le32_to_cpu(ci->iqd_p[headx]);
1254
1255 max_intcnt = max(intCnt, max_intcnt); /* RLD DEBUG */
1256
1257 /**************************************************/
1258 /* HW Bug Fix */
1259 /* ---------- */
1260 /* The following code checks for the condition */
1261 /* of interrupt assertion before interrupt */
1262 /* queue update. This is a problem on several */
1263 /* PCI-Local bridge chips found on some products. */
1264 /**************************************************/
1265
1266 readCount = 0;
1267 if ((currInt == badInt) || (currInt == badInt2))
1268 ci->intlog.drvr_int_failure++;
1269
1270 while ((currInt == badInt) || (currInt == badInt2)) {
1271 for (loopCount = 0; loopCount < 0x30; loopCount++)
1272 /* use call to avoid optimization
1273 * removal of dummy delay
1274 */
1275 OS_uwait_dummy();
1276 FLUSH_MEM_READ();
1277 currInt = le32_to_cpu(ci->iqd_p[headx]);
1278 if (readCount++ > 20)
1279 break;
1280 }
1281
1282 /* catch failure of Bug Fix checking */
1283 if ((currInt == badInt) || (currInt == badInt2)) {
1284 if (cxt1e1_log_level >= LOG_WARN)
1285 pr_info("%s: Illegal Interrupt Detected @ 0x%p, mod %d.)\n",
1286 ci->devname, &ci->iqd_p[headx], headx);
1287
1288 /*
1289 * If the descriptor has not recovered, then leaving the EMPTY
1290 * entry set will not signal to the MUSYCC that this descriptor
1291 * has been serviced. The Interrupt Queue can then start losing
1292 * available descriptors and MUSYCC eventually encounters and
1293 * reports the INTFULL condition. Per manual, changing any bit
1294 * marks descriptor as available, thus the use of different
1295 * EMPTY_ENTRY values.
1296 */
1297
1298 if (currInt == badInt)
1299 ci->iqd_p[headx] = __constant_cpu_to_le32(INT_EMPTY_ENTRY2);
1300 else
1301 ci->iqd_p[headx] = __constant_cpu_to_le32(INT_EMPTY_ENTRY);
1302 /* insure wrapness */
1303 ci->iqp_headx = (headx + 1) & (INT_QUEUE_SIZE - 1);
1304 FLUSH_MEM_WRITE();
1305 FLUSH_MEM_READ();
1306 continue;
1307 }
1308 group = INTRPT_GRP(currInt);
1309 gchan = INTRPT_CH(currInt);
1310 event = INTRPT_EVENT(currInt);
1311 err = INTRPT_ERROR(currInt);
1312 tx = currInt & INTRPT_DIR_M;
1313
1314 ci->iqd_p[headx] = __constant_cpu_to_le32(INT_EMPTY_ENTRY);
1315 FLUSH_MEM_WRITE();
1316
1317 if (cxt1e1_log_level >= LOG_DEBUG) {
1318 if (err != 0)
1319 pr_info(" %08x -> err: %2d,", currInt, err);
1320
1321 pr_info("+ interrupt event: %d, grp: %d, chan: %2d, side: %cX\n",
1322 event, group, gchan, tx ? 'T' : 'R');
1323 }
1324 /* notice that here we assume 1-1 group - port mapping */
1325 pi = &ci->port[group];
1326 ch = pi->chan[gchan];
1327 switch (event) {
1328 case EVE_SACK: /* Service Request Acknowledge */
1329 if (cxt1e1_log_level >= LOG_DEBUG) {
1330 volatile u_int32_t r;
1331
1332 r = pci_read_32((u_int32_t *) &pi->reg->srd);
1333 pr_info("- SACK cmd: %08x (hdw= %08x)\n",
1334 pi->sr_last, r);
1335 }
1336 /* wake up waiting process */
1337 SD_SEM_GIVE(&pi->sr_sem_wait);
1338 break;
1339 case EVE_CHABT: /* Change To Abort Code (0x7e -> 0xff) */
1340 case EVE_CHIC: /* Change To Idle Code (0xff -> 0x7e) */
1341 break;
1342 case EVE_EOM: /* End Of Message */
1343 case EVE_EOB: /* End Of Buffer (Transparent mode) */
1344 if (tx)
1345 musycc_bh_tx_eom(pi, gchan);
1346 else
1347 musycc_bh_rx_eom(pi, gchan);
1348 /*
1349 * MUSYCC Interrupt Descriptor section states that EOB and EOM
1350 * can be combined with the NONE error (as well as others). So
1351 * drop thru to catch this...
1352 */
1353 case EVE_NONE:
1354 if (err == ERR_SHT)
1355 ch->s.rx_length_errors++;
1356 break;
1357 default:
1358 if (cxt1e1_log_level >= LOG_WARN)
1359 pr_info("%s: unexpected interrupt event: %d, iqd[%d]: %08x, port: %d\n", ci->devname,
1360 event, headx, currInt, group);
1361 break;
1362 } /* switch on event */
1363
1364
1365 /*
1366 * Per MUSYCC Manual, Section 6.4.8.3 [Transmit Errors], TX errors
1367 * are service-affecting and require action to resume normal
1368 * bit-level processing.
1369 */
1370
1371 switch (err) {
1372 case ERR_ONR:
1373 /*
1374 * Per MUSYCC manual, Section 6.4.8.3 [Transmit Errors], this
1375 * error requires Transmit channel reactivation.
1376 *
1377 * Per MUSYCC manual, Section 6.4.8.4 [Receive Errors], this error
1378 * requires Receive channel reactivation.
1379 */
1380 if (tx) {
1381
1382 /*
1383 * TX ONR Error only occurs when channel is configured for
1384 * Transparent Mode. However, this code will catch and
1385 * re-activate on ANY TX ONR error.
1386 */
1387
1388 /*
1389 * Set flag to re-enable on any next transmit attempt.
1390 */
1391 ch->ch_start_tx = CH_START_TX_ONR;
1392
1393 #ifdef RLD_TRANS_DEBUG
1394 if (1 || cxt1e1_log_level >= LOG_MONITOR)
1395 #else
1396 if (cxt1e1_log_level >= LOG_MONITOR)
1397 #endif
1398 {
1399 pr_info("%s: TX buffer underflow [ONR] on channel %d, mode %x QStopped %x free %d\n",
1400 ci->devname, ch->channum,
1401 ch->p.chan_mode,
1402 sd_queue_stopped(ch->user),
1403 ch->txd_free);
1404 #ifdef RLD_DEBUG
1405 /* problem = ONR on HDLC mode */
1406 if (ch->p.chan_mode == 2) {
1407 pr_info("++ Failed Last %x Next %x QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
1408 (u_int32_t)ch->txd_irq_srv,
1409 (u_int32_t)ch->txd_usr_add,
1410 sd_queue_stopped(ch->user),
1411 ch->ch_start_tx,
1412 ch->tx_full,
1413 ch->txd_free,
1414 ch->p.chan_mode);
1415 musycc_dump_txbuffer_ring(ch, 0);
1416 }
1417 #endif
1418 }
1419 } else { /* RX buffer overrun */
1420 /*
1421 * Per MUSYCC manual, Section 6.4.8.4 [Receive Errors],
1422 * channel recovery for this RX ONR error IS required. It is
1423 * also suggested to increase the number of receive buffers
1424 * for this channel. Receive channel reactivation IS
1425 * required, and data has been lost.
1426 */
1427 ch->s.rx_over_errors++;
1428 ch->ch_start_rx = CH_START_RX_ONR;
1429
1430 if (cxt1e1_log_level >= LOG_WARN) {
1431 pr_info("%s: RX buffer overflow [ONR] on channel %d, mode %x\n",
1432 ci->devname, ch->channum,
1433 ch->p.chan_mode);
1434 #ifdef RLD_DEBUG
1435 musycc_dump_rxbuffer_ring(ch, 0);
1436 #endif
1437 }
1438 }
1439 musycc_chan_restart(ch);
1440 break;
1441 case ERR_BUF:
1442 if (tx) {
1443 ch->s.tx_fifo_errors++;
1444 ch->ch_start_tx = CH_START_TX_BUF;
1445 /*
1446 * Per MUSYCC manual, Section 6.4.8.3 [Transmit Errors],
1447 * this BUFF error requires Transmit channel reactivation.
1448 */
1449 if (cxt1e1_log_level >= LOG_MONITOR)
1450 pr_info("%s: TX buffer underrun [BUFF] on channel %d, mode %x\n",
1451 ci->devname, ch->channum,
1452 ch->p.chan_mode);
1453 } else { /* RX buffer overrun */
1454 ch->s.rx_over_errors++;
1455 /*
1456 * Per MUSYCC manual, Section 6.4.8.4 [Receive Errors], HDLC
1457 * mode requires NO recovery for this RX BUFF error is
1458 * required. It is suggested to increase the FIFO buffer
1459 * space for this channel. Receive channel reactivation is
1460 * not required, but data has been lost.
1461 */
1462 if (cxt1e1_log_level >= LOG_WARN)
1463 pr_info("%s: RX buffer overrun [BUFF] on channel %d, mode %x\n",
1464 ci->devname, ch->channum,
1465 ch->p.chan_mode);
1466 /*
1467 * Per MUSYCC manual, Section 6.4.9.4 [Receive Errors],
1468 * Transparent mode DOES require recovery for the RX BUFF
1469 * error. It is suggested to increase the FIFO buffer space
1470 * for this channel. Receive channel reactivation IS
1471 * required and data has been lost.
1472 */
1473 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1474 ch->ch_start_rx = CH_START_RX_BUF;
1475 }
1476
1477 if (tx || (ch->p.chan_mode == CFG_CH_PROTO_TRANS))
1478 musycc_chan_restart(ch);
1479 break;
1480 default:
1481 break;
1482 } /* switch on err */
1483
1484 /* Check for interrupt lost condition */
1485 if ((currInt & INTRPT_ILOST_M) &&
1486 (cxt1e1_log_level >= LOG_ERROR))
1487 pr_info("%s: Interrupt queue overflow - ILOST asserted\n",
1488 ci->devname);
1489 /* insure wrapness */
1490 ci->iqp_headx = (headx + 1) & (INT_QUEUE_SIZE - 1);
1491 FLUSH_MEM_WRITE();
1492 FLUSH_MEM_READ();
1493 } /* while */
1494 if ((cxt1e1_log_level >= LOG_MONITOR2) &&
1495 (ci->iqp_headx != ci->iqp_tailx)) {
1496 int bh;
1497
1498 bh = atomic_read(&CI->bh_pending);
1499 pr_info("_bh_: late arrivals, head %d != tail %d, pending %d\n",
1500 ci->iqp_headx, ci->iqp_tailx, bh);
1501 }
1502 #if defined(SBE_ISR_IMMEDIATE)
1503 return 0L;
1504 #endif
1505 /* else, nothing returned */
1506 }
1507
1508 #ifdef SBE_PMCC4_ENABLE
1509 status_t
1510 musycc_chan_down(ci_t *dummy, int channum)
1511 {
1512 mpi_t *pi;
1513 mch_t *ch;
1514 int i, gchan;
1515
1516 ch = sd_find_chan(dummy, channum);
1517 if (!ch)
1518 return -EINVAL;
1519 pi = ch->up;
1520 gchan = ch->gchan;
1521
1522 /* Deactivate the channel */
1523 musycc_serv_req(pi, SR_CHANNEL_DEACTIVATE | SR_RX_DIRECTION | gchan);
1524 ch->ch_start_rx = 0;
1525 musycc_serv_req(pi, SR_CHANNEL_DEACTIVATE | SR_TX_DIRECTION | gchan);
1526 ch->ch_start_tx = 0;
1527
1528 if (ch->state == DOWN)
1529 return 0;
1530 ch->state = DOWN;
1531
1532 pi->regram->thp[gchan] = 0;
1533 pi->regram->tmp[gchan] = 0;
1534 pi->regram->rhp[gchan] = 0;
1535 pi->regram->rmp[gchan] = 0;
1536 FLUSH_MEM_WRITE();
1537 for (i = 0; i < ch->txd_num; i++)
1538 if (ch->mdt[i].mem_token)
1539 OS_mem_token_free(ch->mdt[i].mem_token);
1540
1541 for (i = 0; i < ch->rxd_num; i++)
1542 if (ch->mdr[i].mem_token)
1543 OS_mem_token_free(ch->mdr[i].mem_token);
1544
1545 kfree(ch->mdr);
1546 ch->mdr = NULL;
1547 ch->rxd_num = 0;
1548 kfree(ch->mdt);
1549 ch->mdt = NULL;
1550 ch->txd_num = 0;
1551
1552 musycc_update_timeslots(pi);
1553 c4_fifo_free(pi, ch->gchan);
1554
1555 pi->openchans--;
1556 return 0;
1557 }
1558 #endif
1559
1560 int
1561 musycc_start_xmit(ci_t *ci, int channum, void *mem_token)
1562 {
1563 mch_t *ch;
1564 struct mdesc *md;
1565 void *m2;
1566 int txd_need_cnt;
1567 u_int32_t len;
1568
1569 ch = sd_find_chan(ci, channum);
1570 if (!ch)
1571 return -ENOENT;
1572
1573 /* full interrupt processing available */
1574 if (ci->state != C_RUNNING)
1575 return -EINVAL;
1576 if (ch->state != UP)
1577 return -EINVAL;
1578
1579 /* how else to flag unwritable state ? */
1580 if (!(ch->status & TX_ENABLED))
1581 return -EROFS;
1582
1583 #ifdef RLD_TRANS_DEBUG
1584 if (1 || cxt1e1_log_level >= LOG_MONITOR2)
1585 #else
1586 if (cxt1e1_log_level >= LOG_MONITOR2)
1587 #endif
1588 {
1589 pr_info("++ start_xmt[%d]: state %x start %x full %d free %d required %d stopped %x\n",
1590 channum, ch->state, ch->ch_start_tx, ch->tx_full,
1591 ch->txd_free, ch->txd_required,
1592 sd_queue_stopped(ch->user));
1593 }
1594 /***********************************************/
1595 /** Determine total amount of data to be sent **/
1596 /***********************************************/
1597 m2 = mem_token;
1598 txd_need_cnt = 0;
1599 for (len = OS_mem_token_tlen(m2); len > 0;
1600 m2 = (void *) OS_mem_token_next(m2)) {
1601 if (!OS_mem_token_len(m2))
1602 continue;
1603 txd_need_cnt++;
1604 len -= OS_mem_token_len(m2);
1605 }
1606
1607 if (txd_need_cnt == 0) {
1608 if (cxt1e1_log_level >= LOG_MONITOR2)
1609 pr_info("%s channel %d: no TX data in User buffer\n",
1610 ci->devname, channum);
1611 OS_mem_token_free(mem_token);
1612 return 0; /* no data to send */
1613 }
1614 /*************************************************/
1615 /** Are there sufficient descriptors available? **/
1616 /*************************************************/
1617 if (txd_need_cnt > ch->txd_num) { /* never enough descriptors for this
1618 * large a buffer */
1619 if (cxt1e1_log_level >= LOG_DEBUG)
1620 pr_info("start_xmit: discarding buffer, insufficient descriptor cnt %d, need %d.\n",
1621 ch->txd_num, txd_need_cnt + 1);
1622 ch->s.tx_dropped++;
1623 OS_mem_token_free(mem_token);
1624 return 0;
1625 }
1626
1627 /************************************************************/
1628 /** flow control the line if not enough descriptors remain **/
1629 /************************************************************/
1630 if (txd_need_cnt > ch->txd_free) {
1631 if (cxt1e1_log_level >= LOG_MONITOR2)
1632 pr_info("start_xmit[%d]: EBUSY - need more descriptors, have %d of %d need %d\n",
1633 channum, ch->txd_free,
1634 ch->txd_num, txd_need_cnt);
1635 ch->tx_full = 1;
1636 ch->txd_required = txd_need_cnt;
1637 sd_disable_xmit(ch->user);
1638 return -EBUSY; /* tell user to try again later */
1639 }
1640 /**************************************************/
1641 /** Put the user data into MUSYCC data buffer(s) **/
1642 /**************************************************/
1643 m2 = mem_token;
1644 md = ch->txd_usr_add; /* get current available descriptor */
1645
1646 for (len = OS_mem_token_tlen(m2); len > 0; m2 = OS_mem_token_next(m2)) {
1647 int u = OS_mem_token_len(m2);
1648
1649 if (!u)
1650 continue;
1651 len -= u;
1652
1653 /*
1654 * Enable following chunks, yet wait to enable the FIRST chunk until
1655 * after ALL subsequent chunks are setup.
1656 */
1657 if (md != ch->txd_usr_add) /* not first chunk */
1658 /* transfer ownership from HOST to MUSYCC */
1659 u |= MUSYCC_TX_OWNED;
1660
1661 if (len) /* not last chunk */
1662 u |= EOBIRQ_ENABLE;
1663 else if (ch->p.chan_mode == CFG_CH_PROTO_TRANS) {
1664 /*
1665 * Per MUSYCC Ref 6.4.9 for Transparent Mode, the host must
1666 * always clear EOMIRQ_ENABLE in every Transmit Buffer Descriptor
1667 * (IE. don't set herein).
1668 */
1669 u |= EOBIRQ_ENABLE;
1670 } else
1671 u |= EOMIRQ_ENABLE; /* EOM, last HDLC chunk */
1672
1673
1674 /* last chunk in hdlc mode */
1675 u |= (ch->p.idlecode << IDLE_CODE);
1676 if (ch->p.pad_fill_count) {
1677 u |= (PADFILL_ENABLE | (ch->p.pad_fill_count << EXTRA_FLAGS));
1678 }
1679 /* Fill in mds on last segment, others set ZERO
1680 * so that entire token is removed ONLY when ALL
1681 * segments have been transmitted.
1682 */
1683 md->mem_token = len ? NULL : mem_token;
1684
1685 md->data = cpu_to_le32(OS_vtophys(OS_mem_token_data(m2)));
1686 FLUSH_MEM_WRITE();
1687 md->status = cpu_to_le32(u);
1688 --ch->txd_free;
1689 md = md->snext;
1690 }
1691 FLUSH_MEM_WRITE();
1692
1693
1694 /*
1695 * Now transfer ownership of first chunk from HOST to MUSYCC in order to
1696 * fire-off this XMIT.
1697 */
1698 ch->txd_usr_add->status |= __constant_cpu_to_le32(MUSYCC_TX_OWNED);
1699 FLUSH_MEM_WRITE();
1700 ch->txd_usr_add = md;
1701
1702 len = OS_mem_token_tlen(mem_token);
1703 atomic_add(len, &ch->tx_pending);
1704 atomic_add(len, &ci->tx_pending);
1705 ch->s.tx_packets++;
1706 ch->s.tx_bytes += len;
1707 /*
1708 * If an ONR was seen, then channel requires poking to restart
1709 * transmission.
1710 */
1711 if (ch->ch_start_tx)
1712 musycc_chan_restart(ch);
1713 #ifdef SBE_WAN256T3_ENABLE
1714 wan256t3_led(ci, LED_TX, LEDV_G);
1715 #endif
1716 return 0;
1717 }
1718
1719
1720 /*** End-of-File ***/
Linux with added FPC-III support