1 // SPDX-License-Identifier: GPL-2.0
3 * Implement the AER root port service driver. The driver registers an IRQ
4 * handler. When a root port triggers an AER interrupt, the IRQ handler
5 * collects root port status and schedules work.
7 * Copyright (C) 2006 Intel Corp.
8 * Tom Long Nguyen (tom.l.nguyen@intel.com)
9 * Zhang Yanmin (yanmin.zhang@intel.com)
11 * (C) Copyright 2009 Hewlett-Packard Development Company, L.P.
12 * Andrew Patterson <andrew.patterson@hp.com>
15 #include <linux/cper.h>
16 #include <linux/pci.h>
17 #include <linux/pci-acpi.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/kfifo.h>
26 #include <linux/slab.h>
27 #include <acpi/apei.h>
28 #include <ras/ras_event.h>
33 #define AER_ERROR_SOURCES_MAX 128
35 #define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */
36 #define AER_MAX_TYPEOF_UNCOR_ERRS 26 /* as per PCI_ERR_UNCOR_STATUS*/
38 struct aer_err_source
{
44 struct pci_dev
*rpd
; /* Root Port device */
45 DECLARE_KFIFO(aer_fifo
, struct aer_err_source
, AER_ERROR_SOURCES_MAX
);
48 /* AER stats for the device */
52 * Fields for all AER capable devices. They indicate the errors
53 * "as seen by this device". Note that this may mean that if an
54 * end point is causing problems, the AER counters may increment
55 * at its link partner (e.g. root port) because the errors will be
56 * "seen" by the link partner and not the the problematic end point
57 * itself (which may report all counters as 0 as it never saw any
60 /* Counters for different type of correctable errors */
61 u64 dev_cor_errs
[AER_MAX_TYPEOF_COR_ERRS
];
62 /* Counters for different type of fatal uncorrectable errors */
63 u64 dev_fatal_errs
[AER_MAX_TYPEOF_UNCOR_ERRS
];
64 /* Counters for different type of nonfatal uncorrectable errors */
65 u64 dev_nonfatal_errs
[AER_MAX_TYPEOF_UNCOR_ERRS
];
66 /* Total number of ERR_COR sent by this device */
67 u64 dev_total_cor_errs
;
68 /* Total number of ERR_FATAL sent by this device */
69 u64 dev_total_fatal_errs
;
70 /* Total number of ERR_NONFATAL sent by this device */
71 u64 dev_total_nonfatal_errs
;
74 * Fields for Root ports & root complex event collectors only, these
75 * indicate the total number of ERR_COR, ERR_FATAL, and ERR_NONFATAL
76 * messages received by the root port / event collector, INCLUDING the
77 * ones that are generated internally (by the rootport itself)
79 u64 rootport_total_cor_errs
;
80 u64 rootport_total_fatal_errs
;
81 u64 rootport_total_nonfatal_errs
;
84 #define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
87 PCI_ERR_UNC_COMP_ABORT| \
88 PCI_ERR_UNC_UNX_COMP| \
91 #define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
92 PCI_EXP_RTCTL_SENFEE| \
94 #define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \
95 PCI_ERR_ROOT_CMD_NONFATAL_EN| \
96 PCI_ERR_ROOT_CMD_FATAL_EN)
97 #define ERR_COR_ID(d) (d & 0xffff)
98 #define ERR_UNCOR_ID(d) (d >> 16)
100 static int pcie_aer_disable
;
102 void pci_no_aer(void)
104 pcie_aer_disable
= 1;
107 bool pci_aer_available(void)
109 return !pcie_aer_disable
&& pci_msi_enabled();
112 #ifdef CONFIG_PCIE_ECRC
114 #define ECRC_POLICY_DEFAULT 0 /* ECRC set by BIOS */
115 #define ECRC_POLICY_OFF 1 /* ECRC off for performance */
116 #define ECRC_POLICY_ON 2 /* ECRC on for data integrity */
118 static int ecrc_policy
= ECRC_POLICY_DEFAULT
;
120 static const char *ecrc_policy_str
[] = {
121 [ECRC_POLICY_DEFAULT
] = "bios",
122 [ECRC_POLICY_OFF
] = "off",
123 [ECRC_POLICY_ON
] = "on"
127 * enable_ercr_checking - enable PCIe ECRC checking for a device
128 * @dev: the PCI device
130 * Returns 0 on success, or negative on failure.
132 static int enable_ecrc_checking(struct pci_dev
*dev
)
137 if (!pci_is_pcie(dev
))
144 pci_read_config_dword(dev
, pos
+ PCI_ERR_CAP
, ®32
);
145 if (reg32
& PCI_ERR_CAP_ECRC_GENC
)
146 reg32
|= PCI_ERR_CAP_ECRC_GENE
;
147 if (reg32
& PCI_ERR_CAP_ECRC_CHKC
)
148 reg32
|= PCI_ERR_CAP_ECRC_CHKE
;
149 pci_write_config_dword(dev
, pos
+ PCI_ERR_CAP
, reg32
);
155 * disable_ercr_checking - disables PCIe ECRC checking for a device
156 * @dev: the PCI device
158 * Returns 0 on success, or negative on failure.
160 static int disable_ecrc_checking(struct pci_dev
*dev
)
165 if (!pci_is_pcie(dev
))
172 pci_read_config_dword(dev
, pos
+ PCI_ERR_CAP
, ®32
);
173 reg32
&= ~(PCI_ERR_CAP_ECRC_GENE
| PCI_ERR_CAP_ECRC_CHKE
);
174 pci_write_config_dword(dev
, pos
+ PCI_ERR_CAP
, reg32
);
180 * pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based on global policy
181 * @dev: the PCI device
183 void pcie_set_ecrc_checking(struct pci_dev
*dev
)
185 switch (ecrc_policy
) {
186 case ECRC_POLICY_DEFAULT
:
188 case ECRC_POLICY_OFF
:
189 disable_ecrc_checking(dev
);
192 enable_ecrc_checking(dev
);
200 * pcie_ecrc_get_policy - parse kernel command-line ecrc option
202 void pcie_ecrc_get_policy(char *str
)
206 for (i
= 0; i
< ARRAY_SIZE(ecrc_policy_str
); i
++)
207 if (!strncmp(str
, ecrc_policy_str
[i
],
208 strlen(ecrc_policy_str
[i
])))
210 if (i
>= ARRAY_SIZE(ecrc_policy_str
))
215 #endif /* CONFIG_PCIE_ECRC */
217 #ifdef CONFIG_ACPI_APEI
218 static inline int hest_match_pci(struct acpi_hest_aer_common
*p
,
221 return ACPI_HEST_SEGMENT(p
->bus
) == pci_domain_nr(pci
->bus
) &&
222 ACPI_HEST_BUS(p
->bus
) == pci
->bus
->number
&&
223 p
->device
== PCI_SLOT(pci
->devfn
) &&
224 p
->function
== PCI_FUNC(pci
->devfn
);
227 static inline bool hest_match_type(struct acpi_hest_header
*hest_hdr
,
230 u16 hest_type
= hest_hdr
->type
;
231 u8 pcie_type
= pci_pcie_type(dev
);
233 if ((hest_type
== ACPI_HEST_TYPE_AER_ROOT_PORT
&&
234 pcie_type
== PCI_EXP_TYPE_ROOT_PORT
) ||
235 (hest_type
== ACPI_HEST_TYPE_AER_ENDPOINT
&&
236 pcie_type
== PCI_EXP_TYPE_ENDPOINT
) ||
237 (hest_type
== ACPI_HEST_TYPE_AER_BRIDGE
&&
238 (dev
->class >> 16) == PCI_BASE_CLASS_BRIDGE
))
243 struct aer_hest_parse_info
{
244 struct pci_dev
*pci_dev
;
248 static int hest_source_is_pcie_aer(struct acpi_hest_header
*hest_hdr
)
250 if (hest_hdr
->type
== ACPI_HEST_TYPE_AER_ROOT_PORT
||
251 hest_hdr
->type
== ACPI_HEST_TYPE_AER_ENDPOINT
||
252 hest_hdr
->type
== ACPI_HEST_TYPE_AER_BRIDGE
)
257 static int aer_hest_parse(struct acpi_hest_header
*hest_hdr
, void *data
)
259 struct aer_hest_parse_info
*info
= data
;
260 struct acpi_hest_aer_common
*p
;
263 if (!hest_source_is_pcie_aer(hest_hdr
))
266 p
= (struct acpi_hest_aer_common
*)(hest_hdr
+ 1);
267 ff
= !!(p
->flags
& ACPI_HEST_FIRMWARE_FIRST
);
270 * If no specific device is supplied, determine whether
271 * FIRMWARE_FIRST is set for *any* PCIe device.
273 if (!info
->pci_dev
) {
274 info
->firmware_first
|= ff
;
278 /* Otherwise, check the specific device */
279 if (p
->flags
& ACPI_HEST_GLOBAL
) {
280 if (hest_match_type(hest_hdr
, info
->pci_dev
))
281 info
->firmware_first
= ff
;
283 if (hest_match_pci(p
, info
->pci_dev
))
284 info
->firmware_first
= ff
;
289 static void aer_set_firmware_first(struct pci_dev
*pci_dev
)
292 struct aer_hest_parse_info info
= {
297 rc
= apei_hest_parse(aer_hest_parse
, &info
);
300 pci_dev
->__aer_firmware_first
= 0;
302 pci_dev
->__aer_firmware_first
= info
.firmware_first
;
303 pci_dev
->__aer_firmware_first_valid
= 1;
306 int pcie_aer_get_firmware_first(struct pci_dev
*dev
)
308 if (!pci_is_pcie(dev
))
311 if (pcie_ports_native
)
314 if (!dev
->__aer_firmware_first_valid
)
315 aer_set_firmware_first(dev
);
316 return dev
->__aer_firmware_first
;
319 static bool aer_firmware_first
;
322 * aer_acpi_firmware_first - Check if APEI should control AER.
324 bool aer_acpi_firmware_first(void)
326 static bool parsed
= false;
327 struct aer_hest_parse_info info
= {
328 .pci_dev
= NULL
, /* Check all PCIe devices */
332 if (pcie_ports_native
)
336 apei_hest_parse(aer_hest_parse
, &info
);
337 aer_firmware_first
= info
.firmware_first
;
340 return aer_firmware_first
;
344 #define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
345 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE)
347 int pci_enable_pcie_error_reporting(struct pci_dev
*dev
)
349 if (pcie_aer_get_firmware_first(dev
))
355 return pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
, PCI_EXP_AER_FLAGS
);
357 EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting
);
359 int pci_disable_pcie_error_reporting(struct pci_dev
*dev
)
361 if (pcie_aer_get_firmware_first(dev
))
364 return pcie_capability_clear_word(dev
, PCI_EXP_DEVCTL
,
367 EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting
);
369 void pci_aer_clear_device_status(struct pci_dev
*dev
)
373 pcie_capability_read_word(dev
, PCI_EXP_DEVSTA
, &sta
);
374 pcie_capability_write_word(dev
, PCI_EXP_DEVSTA
, sta
);
377 int pci_cleanup_aer_uncorrect_error_status(struct pci_dev
*dev
)
386 if (pcie_aer_get_firmware_first(dev
))
389 /* Clear status bits for ERR_NONFATAL errors only */
390 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_STATUS
, &status
);
391 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_SEVER
, &sev
);
394 pci_write_config_dword(dev
, pos
+ PCI_ERR_UNCOR_STATUS
, status
);
398 EXPORT_SYMBOL_GPL(pci_cleanup_aer_uncorrect_error_status
);
400 void pci_aer_clear_fatal_status(struct pci_dev
*dev
)
409 if (pcie_aer_get_firmware_first(dev
))
412 /* Clear status bits for ERR_FATAL errors only */
413 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_STATUS
, &status
);
414 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_SEVER
, &sev
);
417 pci_write_config_dword(dev
, pos
+ PCI_ERR_UNCOR_STATUS
, status
);
420 int pci_cleanup_aer_error_status_regs(struct pci_dev
*dev
)
426 if (!pci_is_pcie(dev
))
433 if (pcie_aer_get_firmware_first(dev
))
436 port_type
= pci_pcie_type(dev
);
437 if (port_type
== PCI_EXP_TYPE_ROOT_PORT
) {
438 pci_read_config_dword(dev
, pos
+ PCI_ERR_ROOT_STATUS
, &status
);
439 pci_write_config_dword(dev
, pos
+ PCI_ERR_ROOT_STATUS
, status
);
442 pci_read_config_dword(dev
, pos
+ PCI_ERR_COR_STATUS
, &status
);
443 pci_write_config_dword(dev
, pos
+ PCI_ERR_COR_STATUS
, status
);
445 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_STATUS
, &status
);
446 pci_write_config_dword(dev
, pos
+ PCI_ERR_UNCOR_STATUS
, status
);
451 void pci_aer_init(struct pci_dev
*dev
)
453 dev
->aer_cap
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ERR
);
456 dev
->aer_stats
= kzalloc(sizeof(struct aer_stats
), GFP_KERNEL
);
458 pci_cleanup_aer_error_status_regs(dev
);
461 void pci_aer_exit(struct pci_dev
*dev
)
463 kfree(dev
->aer_stats
);
464 dev
->aer_stats
= NULL
;
467 #define AER_AGENT_RECEIVER 0
468 #define AER_AGENT_REQUESTER 1
469 #define AER_AGENT_COMPLETER 2
470 #define AER_AGENT_TRANSMITTER 3
472 #define AER_AGENT_REQUESTER_MASK(t) ((t == AER_CORRECTABLE) ? \
473 0 : (PCI_ERR_UNC_COMP_TIME|PCI_ERR_UNC_UNSUP))
474 #define AER_AGENT_COMPLETER_MASK(t) ((t == AER_CORRECTABLE) ? \
475 0 : PCI_ERR_UNC_COMP_ABORT)
476 #define AER_AGENT_TRANSMITTER_MASK(t) ((t == AER_CORRECTABLE) ? \
477 (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER) : 0)
479 #define AER_GET_AGENT(t, e) \
480 ((e & AER_AGENT_COMPLETER_MASK(t)) ? AER_AGENT_COMPLETER : \
481 (e & AER_AGENT_REQUESTER_MASK(t)) ? AER_AGENT_REQUESTER : \
482 (e & AER_AGENT_TRANSMITTER_MASK(t)) ? AER_AGENT_TRANSMITTER : \
485 #define AER_PHYSICAL_LAYER_ERROR 0
486 #define AER_DATA_LINK_LAYER_ERROR 1
487 #define AER_TRANSACTION_LAYER_ERROR 2
489 #define AER_PHYSICAL_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
490 PCI_ERR_COR_RCVR : 0)
491 #define AER_DATA_LINK_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
492 (PCI_ERR_COR_BAD_TLP| \
493 PCI_ERR_COR_BAD_DLLP| \
494 PCI_ERR_COR_REP_ROLL| \
495 PCI_ERR_COR_REP_TIMER) : PCI_ERR_UNC_DLP)
497 #define AER_GET_LAYER_ERROR(t, e) \
498 ((e & AER_PHYSICAL_LAYER_ERROR_MASK(t)) ? AER_PHYSICAL_LAYER_ERROR : \
499 (e & AER_DATA_LINK_LAYER_ERROR_MASK(t)) ? AER_DATA_LINK_LAYER_ERROR : \
500 AER_TRANSACTION_LAYER_ERROR)
505 static const char *aer_error_severity_string
[] = {
506 "Uncorrected (Non-Fatal)",
507 "Uncorrected (Fatal)",
511 static const char *aer_error_layer
[] = {
517 static const char *aer_correctable_error_string
[AER_MAX_TYPEOF_COR_ERRS
] = {
518 "RxErr", /* Bit Position 0 */
524 "BadTLP", /* Bit Position 6 */
525 "BadDLLP", /* Bit Position 7 */
526 "Rollover", /* Bit Position 8 */
530 "Timeout", /* Bit Position 12 */
531 "NonFatalErr", /* Bit Position 13 */
532 "CorrIntErr", /* Bit Position 14 */
533 "HeaderOF", /* Bit Position 15 */
536 static const char *aer_uncorrectable_error_string
[AER_MAX_TYPEOF_UNCOR_ERRS
] = {
537 "Undefined", /* Bit Position 0 */
541 "DLP", /* Bit Position 4 */
542 "SDES", /* Bit Position 5 */
549 "TLP", /* Bit Position 12 */
550 "FCP", /* Bit Position 13 */
551 "CmpltTO", /* Bit Position 14 */
552 "CmpltAbrt", /* Bit Position 15 */
553 "UnxCmplt", /* Bit Position 16 */
554 "RxOF", /* Bit Position 17 */
555 "MalfTLP", /* Bit Position 18 */
556 "ECRC", /* Bit Position 19 */
557 "UnsupReq", /* Bit Position 20 */
558 "ACSViol", /* Bit Position 21 */
559 "UncorrIntErr", /* Bit Position 22 */
560 "BlockedTLP", /* Bit Position 23 */
561 "AtomicOpBlocked", /* Bit Position 24 */
562 "TLPBlockedErr", /* Bit Position 25 */
565 static const char *aer_agent_string
[] = {
572 #define aer_stats_dev_attr(name, stats_array, strings_array, \
573 total_string, total_field) \
575 name##_show(struct device *dev, struct device_attribute *attr, \
580 struct pci_dev *pdev = to_pci_dev(dev); \
581 u64 *stats = pdev->aer_stats->stats_array; \
583 for (i = 0; i < ARRAY_SIZE(strings_array); i++) { \
584 if (strings_array[i]) \
585 str += sprintf(str, "%s %llu\n", \
586 strings_array[i], stats[i]); \
588 str += sprintf(str, #stats_array "_bit[%d] %llu\n",\
591 str += sprintf(str, "TOTAL_%s %llu\n", total_string, \
592 pdev->aer_stats->total_field); \
595 static DEVICE_ATTR_RO(name)
597 aer_stats_dev_attr(aer_dev_correctable
, dev_cor_errs
,
598 aer_correctable_error_string
, "ERR_COR",
600 aer_stats_dev_attr(aer_dev_fatal
, dev_fatal_errs
,
601 aer_uncorrectable_error_string
, "ERR_FATAL",
602 dev_total_fatal_errs
);
603 aer_stats_dev_attr(aer_dev_nonfatal
, dev_nonfatal_errs
,
604 aer_uncorrectable_error_string
, "ERR_NONFATAL",
605 dev_total_nonfatal_errs
);
607 #define aer_stats_rootport_attr(name, field) \
609 name##_show(struct device *dev, struct device_attribute *attr, \
612 struct pci_dev *pdev = to_pci_dev(dev); \
613 return sprintf(buf, "%llu\n", pdev->aer_stats->field); \
615 static DEVICE_ATTR_RO(name)
617 aer_stats_rootport_attr(aer_rootport_total_err_cor
,
618 rootport_total_cor_errs
);
619 aer_stats_rootport_attr(aer_rootport_total_err_fatal
,
620 rootport_total_fatal_errs
);
621 aer_stats_rootport_attr(aer_rootport_total_err_nonfatal
,
622 rootport_total_nonfatal_errs
);
624 static struct attribute
*aer_stats_attrs
[] __ro_after_init
= {
625 &dev_attr_aer_dev_correctable
.attr
,
626 &dev_attr_aer_dev_fatal
.attr
,
627 &dev_attr_aer_dev_nonfatal
.attr
,
628 &dev_attr_aer_rootport_total_err_cor
.attr
,
629 &dev_attr_aer_rootport_total_err_fatal
.attr
,
630 &dev_attr_aer_rootport_total_err_nonfatal
.attr
,
634 static umode_t
aer_stats_attrs_are_visible(struct kobject
*kobj
,
635 struct attribute
*a
, int n
)
637 struct device
*dev
= kobj_to_dev(kobj
);
638 struct pci_dev
*pdev
= to_pci_dev(dev
);
640 if (!pdev
->aer_stats
)
643 if ((a
== &dev_attr_aer_rootport_total_err_cor
.attr
||
644 a
== &dev_attr_aer_rootport_total_err_fatal
.attr
||
645 a
== &dev_attr_aer_rootport_total_err_nonfatal
.attr
) &&
646 pci_pcie_type(pdev
) != PCI_EXP_TYPE_ROOT_PORT
)
652 const struct attribute_group aer_stats_attr_group
= {
653 .attrs
= aer_stats_attrs
,
654 .is_visible
= aer_stats_attrs_are_visible
,
657 static void pci_dev_aer_stats_incr(struct pci_dev
*pdev
,
658 struct aer_err_info
*info
)
660 int status
, i
, max
= -1;
662 struct aer_stats
*aer_stats
= pdev
->aer_stats
;
667 switch (info
->severity
) {
668 case AER_CORRECTABLE
:
669 aer_stats
->dev_total_cor_errs
++;
670 counter
= &aer_stats
->dev_cor_errs
[0];
671 max
= AER_MAX_TYPEOF_COR_ERRS
;
674 aer_stats
->dev_total_nonfatal_errs
++;
675 counter
= &aer_stats
->dev_nonfatal_errs
[0];
676 max
= AER_MAX_TYPEOF_UNCOR_ERRS
;
679 aer_stats
->dev_total_fatal_errs
++;
680 counter
= &aer_stats
->dev_fatal_errs
[0];
681 max
= AER_MAX_TYPEOF_UNCOR_ERRS
;
685 status
= (info
->status
& ~info
->mask
);
686 for (i
= 0; i
< max
; i
++)
687 if (status
& (1 << i
))
691 static void pci_rootport_aer_stats_incr(struct pci_dev
*pdev
,
692 struct aer_err_source
*e_src
)
694 struct aer_stats
*aer_stats
= pdev
->aer_stats
;
699 if (e_src
->status
& PCI_ERR_ROOT_COR_RCV
)
700 aer_stats
->rootport_total_cor_errs
++;
702 if (e_src
->status
& PCI_ERR_ROOT_UNCOR_RCV
) {
703 if (e_src
->status
& PCI_ERR_ROOT_FATAL_RCV
)
704 aer_stats
->rootport_total_fatal_errs
++;
706 aer_stats
->rootport_total_nonfatal_errs
++;
710 static void __print_tlp_header(struct pci_dev
*dev
,
711 struct aer_header_log_regs
*t
)
713 pci_err(dev
, " TLP Header: %08x %08x %08x %08x\n",
714 t
->dw0
, t
->dw1
, t
->dw2
, t
->dw3
);
717 static void __aer_print_error(struct pci_dev
*dev
,
718 struct aer_err_info
*info
)
721 const char *errmsg
= NULL
;
722 status
= (info
->status
& ~info
->mask
);
724 for (i
= 0; i
< 32; i
++) {
725 if (!(status
& (1 << i
)))
728 if (info
->severity
== AER_CORRECTABLE
)
729 errmsg
= i
< ARRAY_SIZE(aer_correctable_error_string
) ?
730 aer_correctable_error_string
[i
] : NULL
;
732 errmsg
= i
< ARRAY_SIZE(aer_uncorrectable_error_string
) ?
733 aer_uncorrectable_error_string
[i
] : NULL
;
736 pci_err(dev
, " [%2d] %-22s%s\n", i
, errmsg
,
737 info
->first_error
== i
? " (First)" : "");
739 pci_err(dev
, " [%2d] Unknown Error Bit%s\n",
740 i
, info
->first_error
== i
? " (First)" : "");
742 pci_dev_aer_stats_incr(dev
, info
);
745 void aer_print_error(struct pci_dev
*dev
, struct aer_err_info
*info
)
748 int id
= ((dev
->bus
->number
<< 8) | dev
->devfn
);
751 pci_err(dev
, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n",
752 aer_error_severity_string
[info
->severity
]);
756 layer
= AER_GET_LAYER_ERROR(info
->severity
, info
->status
);
757 agent
= AER_GET_AGENT(info
->severity
, info
->status
);
759 pci_err(dev
, "PCIe Bus Error: severity=%s, type=%s, (%s)\n",
760 aer_error_severity_string
[info
->severity
],
761 aer_error_layer
[layer
], aer_agent_string
[agent
]);
763 pci_err(dev
, " device [%04x:%04x] error status/mask=%08x/%08x\n",
764 dev
->vendor
, dev
->device
,
765 info
->status
, info
->mask
);
767 __aer_print_error(dev
, info
);
769 if (info
->tlp_header_valid
)
770 __print_tlp_header(dev
, &info
->tlp
);
773 if (info
->id
&& info
->error_dev_num
> 1 && info
->id
== id
)
774 pci_err(dev
, " Error of this Agent is reported first\n");
776 trace_aer_event(dev_name(&dev
->dev
), (info
->status
& ~info
->mask
),
777 info
->severity
, info
->tlp_header_valid
, &info
->tlp
);
780 static void aer_print_port_info(struct pci_dev
*dev
, struct aer_err_info
*info
)
782 u8 bus
= info
->id
>> 8;
783 u8 devfn
= info
->id
& 0xff;
785 pci_info(dev
, "AER: %s%s error received: %04x:%02x:%02x.%d\n",
786 info
->multi_error_valid
? "Multiple " : "",
787 aer_error_severity_string
[info
->severity
],
788 pci_domain_nr(dev
->bus
), bus
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
791 #ifdef CONFIG_ACPI_APEI_PCIEAER
792 int cper_severity_to_aer(int cper_severity
)
794 switch (cper_severity
) {
795 case CPER_SEV_RECOVERABLE
:
800 return AER_CORRECTABLE
;
803 EXPORT_SYMBOL_GPL(cper_severity_to_aer
);
805 void cper_print_aer(struct pci_dev
*dev
, int aer_severity
,
806 struct aer_capability_regs
*aer
)
808 int layer
, agent
, tlp_header_valid
= 0;
810 struct aer_err_info info
;
812 if (aer_severity
== AER_CORRECTABLE
) {
813 status
= aer
->cor_status
;
814 mask
= aer
->cor_mask
;
816 status
= aer
->uncor_status
;
817 mask
= aer
->uncor_mask
;
818 tlp_header_valid
= status
& AER_LOG_TLP_MASKS
;
821 layer
= AER_GET_LAYER_ERROR(aer_severity
, status
);
822 agent
= AER_GET_AGENT(aer_severity
, status
);
824 memset(&info
, 0, sizeof(info
));
825 info
.severity
= aer_severity
;
826 info
.status
= status
;
828 info
.first_error
= PCI_ERR_CAP_FEP(aer
->cap_control
);
830 pci_err(dev
, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status
, mask
);
831 __aer_print_error(dev
, &info
);
832 pci_err(dev
, "aer_layer=%s, aer_agent=%s\n",
833 aer_error_layer
[layer
], aer_agent_string
[agent
]);
835 if (aer_severity
!= AER_CORRECTABLE
)
836 pci_err(dev
, "aer_uncor_severity: 0x%08x\n",
837 aer
->uncor_severity
);
839 if (tlp_header_valid
)
840 __print_tlp_header(dev
, &aer
->header_log
);
842 trace_aer_event(dev_name(&dev
->dev
), (status
& ~mask
),
843 aer_severity
, tlp_header_valid
, &aer
->header_log
);
848 * add_error_device - list device to be handled
849 * @e_info: pointer to error info
850 * @dev: pointer to pci_dev to be added
852 static int add_error_device(struct aer_err_info
*e_info
, struct pci_dev
*dev
)
854 if (e_info
->error_dev_num
< AER_MAX_MULTI_ERR_DEVICES
) {
855 e_info
->dev
[e_info
->error_dev_num
] = pci_dev_get(dev
);
856 e_info
->error_dev_num
++;
863 * is_error_source - check whether the device is source of reported error
864 * @dev: pointer to pci_dev to be checked
865 * @e_info: pointer to reported error info
867 static bool is_error_source(struct pci_dev
*dev
, struct aer_err_info
*e_info
)
874 * When bus id is equal to 0, it might be a bad id
875 * reported by root port.
877 if ((PCI_BUS_NUM(e_info
->id
) != 0) &&
878 !(dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_AERSID
)) {
879 /* Device ID match? */
880 if (e_info
->id
== ((dev
->bus
->number
<< 8) | dev
->devfn
))
883 /* Continue id comparing if there is no multiple error */
884 if (!e_info
->multi_error_valid
)
890 * 1) bus id is equal to 0. Some ports might lose the bus
891 * id of error source id;
892 * 2) bus flag PCI_BUS_FLAGS_NO_AERSID is set
893 * 3) There are multiple errors and prior ID comparing fails;
894 * We check AER status registers to find possible reporter.
896 if (atomic_read(&dev
->enable_cnt
) == 0)
899 /* Check if AER is enabled */
900 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, ®16
);
901 if (!(reg16
& PCI_EXP_AER_FLAGS
))
908 /* Check if error is recorded */
909 if (e_info
->severity
== AER_CORRECTABLE
) {
910 pci_read_config_dword(dev
, pos
+ PCI_ERR_COR_STATUS
, &status
);
911 pci_read_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
, &mask
);
913 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_STATUS
, &status
);
914 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_MASK
, &mask
);
922 static int find_device_iter(struct pci_dev
*dev
, void *data
)
924 struct aer_err_info
*e_info
= (struct aer_err_info
*)data
;
926 if (is_error_source(dev
, e_info
)) {
927 /* List this device */
928 if (add_error_device(e_info
, dev
)) {
929 /* We cannot handle more... Stop iteration */
930 /* TODO: Should print error message here? */
934 /* If there is only a single error, stop iteration */
935 if (!e_info
->multi_error_valid
)
942 * find_source_device - search through device hierarchy for source device
943 * @parent: pointer to Root Port pci_dev data structure
944 * @e_info: including detailed error information such like id
946 * Return true if found.
948 * Invoked by DPC when error is detected at the Root Port.
949 * Caller of this function must set id, severity, and multi_error_valid of
950 * struct aer_err_info pointed by @e_info properly. This function must fill
951 * e_info->error_dev_num and e_info->dev[], based on the given information.
953 static bool find_source_device(struct pci_dev
*parent
,
954 struct aer_err_info
*e_info
)
956 struct pci_dev
*dev
= parent
;
959 /* Must reset in this function */
960 e_info
->error_dev_num
= 0;
962 /* Is Root Port an agent that sends error message? */
963 result
= find_device_iter(dev
, e_info
);
967 pci_walk_bus(parent
->subordinate
, find_device_iter
, e_info
);
969 if (!e_info
->error_dev_num
) {
970 pci_printk(KERN_DEBUG
, parent
, "can't find device of ID%04x\n",
978 * handle_error_source - handle logging error into an event log
979 * @dev: pointer to pci_dev data structure of error source device
980 * @info: comprehensive error information
982 * Invoked when an error being detected by Root Port.
984 static void handle_error_source(struct pci_dev
*dev
, struct aer_err_info
*info
)
988 if (info
->severity
== AER_CORRECTABLE
) {
990 * Correctable error does not need software intervention.
991 * No need to go through error recovery process.
995 pci_write_config_dword(dev
, pos
+ PCI_ERR_COR_STATUS
,
997 pci_aer_clear_device_status(dev
);
998 } else if (info
->severity
== AER_NONFATAL
)
999 pcie_do_recovery(dev
, pci_channel_io_normal
,
1000 PCIE_PORT_SERVICE_AER
);
1001 else if (info
->severity
== AER_FATAL
)
1002 pcie_do_recovery(dev
, pci_channel_io_frozen
,
1003 PCIE_PORT_SERVICE_AER
);
1007 #ifdef CONFIG_ACPI_APEI_PCIEAER
1009 #define AER_RECOVER_RING_ORDER 4
1010 #define AER_RECOVER_RING_SIZE (1 << AER_RECOVER_RING_ORDER)
1012 struct aer_recover_entry
{
1017 struct aer_capability_regs
*regs
;
1020 static DEFINE_KFIFO(aer_recover_ring
, struct aer_recover_entry
,
1021 AER_RECOVER_RING_SIZE
);
1023 static void aer_recover_work_func(struct work_struct
*work
)
1025 struct aer_recover_entry entry
;
1026 struct pci_dev
*pdev
;
1028 while (kfifo_get(&aer_recover_ring
, &entry
)) {
1029 pdev
= pci_get_domain_bus_and_slot(entry
.domain
, entry
.bus
,
1032 pr_err("AER recover: Can not find pci_dev for %04x:%02x:%02x:%x\n",
1033 entry
.domain
, entry
.bus
,
1034 PCI_SLOT(entry
.devfn
), PCI_FUNC(entry
.devfn
));
1037 cper_print_aer(pdev
, entry
.severity
, entry
.regs
);
1038 if (entry
.severity
== AER_NONFATAL
)
1039 pcie_do_recovery(pdev
, pci_channel_io_normal
,
1040 PCIE_PORT_SERVICE_AER
);
1041 else if (entry
.severity
== AER_FATAL
)
1042 pcie_do_recovery(pdev
, pci_channel_io_frozen
,
1043 PCIE_PORT_SERVICE_AER
);
1049 * Mutual exclusion for writers of aer_recover_ring, reader side don't
1050 * need lock, because there is only one reader and lock is not needed
1051 * between reader and writer.
1053 static DEFINE_SPINLOCK(aer_recover_ring_lock
);
1054 static DECLARE_WORK(aer_recover_work
, aer_recover_work_func
);
1056 void aer_recover_queue(int domain
, unsigned int bus
, unsigned int devfn
,
1057 int severity
, struct aer_capability_regs
*aer_regs
)
1059 struct aer_recover_entry entry
= {
1063 .severity
= severity
,
1067 if (kfifo_in_spinlocked(&aer_recover_ring
, &entry
, 1,
1068 &aer_recover_ring_lock
))
1069 schedule_work(&aer_recover_work
);
1071 pr_err("AER recover: Buffer overflow when recovering AER for %04x:%02x:%02x:%x\n",
1072 domain
, bus
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
1074 EXPORT_SYMBOL_GPL(aer_recover_queue
);
1078 * aer_get_device_error_info - read error status from dev and store it to info
1079 * @dev: pointer to the device expected to have a error record
1080 * @info: pointer to structure to store the error record
1082 * Return 1 on success, 0 on error.
1084 * Note that @info is reused among all error devices. Clear fields properly.
1086 int aer_get_device_error_info(struct pci_dev
*dev
, struct aer_err_info
*info
)
1090 /* Must reset in this function */
1092 info
->tlp_header_valid
= 0;
1096 /* The device might not support AER */
1100 if (info
->severity
== AER_CORRECTABLE
) {
1101 pci_read_config_dword(dev
, pos
+ PCI_ERR_COR_STATUS
,
1103 pci_read_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
,
1105 if (!(info
->status
& ~info
->mask
))
1107 } else if (pci_pcie_type(dev
) == PCI_EXP_TYPE_ROOT_PORT
||
1108 pci_pcie_type(dev
) == PCI_EXP_TYPE_DOWNSTREAM
||
1109 info
->severity
== AER_NONFATAL
) {
1111 /* Link is still healthy for IO reads */
1112 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_STATUS
,
1114 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_MASK
,
1116 if (!(info
->status
& ~info
->mask
))
1119 /* Get First Error Pointer */
1120 pci_read_config_dword(dev
, pos
+ PCI_ERR_CAP
, &temp
);
1121 info
->first_error
= PCI_ERR_CAP_FEP(temp
);
1123 if (info
->status
& AER_LOG_TLP_MASKS
) {
1124 info
->tlp_header_valid
= 1;
1125 pci_read_config_dword(dev
,
1126 pos
+ PCI_ERR_HEADER_LOG
, &info
->tlp
.dw0
);
1127 pci_read_config_dword(dev
,
1128 pos
+ PCI_ERR_HEADER_LOG
+ 4, &info
->tlp
.dw1
);
1129 pci_read_config_dword(dev
,
1130 pos
+ PCI_ERR_HEADER_LOG
+ 8, &info
->tlp
.dw2
);
1131 pci_read_config_dword(dev
,
1132 pos
+ PCI_ERR_HEADER_LOG
+ 12, &info
->tlp
.dw3
);
1139 static inline void aer_process_err_devices(struct aer_err_info
*e_info
)
1143 /* Report all before handle them, not to lost records by reset etc. */
1144 for (i
= 0; i
< e_info
->error_dev_num
&& e_info
->dev
[i
]; i
++) {
1145 if (aer_get_device_error_info(e_info
->dev
[i
], e_info
))
1146 aer_print_error(e_info
->dev
[i
], e_info
);
1148 for (i
= 0; i
< e_info
->error_dev_num
&& e_info
->dev
[i
]; i
++) {
1149 if (aer_get_device_error_info(e_info
->dev
[i
], e_info
))
1150 handle_error_source(e_info
->dev
[i
], e_info
);
1155 * aer_isr_one_error - consume an error detected by root port
1156 * @rpc: pointer to the root port which holds an error
1157 * @e_src: pointer to an error source
1159 static void aer_isr_one_error(struct aer_rpc
*rpc
,
1160 struct aer_err_source
*e_src
)
1162 struct pci_dev
*pdev
= rpc
->rpd
;
1163 struct aer_err_info e_info
;
1165 pci_rootport_aer_stats_incr(pdev
, e_src
);
1168 * There is a possibility that both correctable error and
1169 * uncorrectable error being logged. Report correctable error first.
1171 if (e_src
->status
& PCI_ERR_ROOT_COR_RCV
) {
1172 e_info
.id
= ERR_COR_ID(e_src
->id
);
1173 e_info
.severity
= AER_CORRECTABLE
;
1175 if (e_src
->status
& PCI_ERR_ROOT_MULTI_COR_RCV
)
1176 e_info
.multi_error_valid
= 1;
1178 e_info
.multi_error_valid
= 0;
1179 aer_print_port_info(pdev
, &e_info
);
1181 if (find_source_device(pdev
, &e_info
))
1182 aer_process_err_devices(&e_info
);
1185 if (e_src
->status
& PCI_ERR_ROOT_UNCOR_RCV
) {
1186 e_info
.id
= ERR_UNCOR_ID(e_src
->id
);
1188 if (e_src
->status
& PCI_ERR_ROOT_FATAL_RCV
)
1189 e_info
.severity
= AER_FATAL
;
1191 e_info
.severity
= AER_NONFATAL
;
1193 if (e_src
->status
& PCI_ERR_ROOT_MULTI_UNCOR_RCV
)
1194 e_info
.multi_error_valid
= 1;
1196 e_info
.multi_error_valid
= 0;
1198 aer_print_port_info(pdev
, &e_info
);
1200 if (find_source_device(pdev
, &e_info
))
1201 aer_process_err_devices(&e_info
);
1206 * aer_isr - consume errors detected by root port
1207 * @work: definition of this work item
1209 * Invoked, as DPC, when root port records new detected error
1211 static irqreturn_t
aer_isr(int irq
, void *context
)
1213 struct pcie_device
*dev
= (struct pcie_device
*)context
;
1214 struct aer_rpc
*rpc
= get_service_data(dev
);
1215 struct aer_err_source
uninitialized_var(e_src
);
1217 if (kfifo_is_empty(&rpc
->aer_fifo
))
1220 while (kfifo_get(&rpc
->aer_fifo
, &e_src
))
1221 aer_isr_one_error(rpc
, &e_src
);
1226 * aer_irq - Root Port's ISR
1227 * @irq: IRQ assigned to Root Port
1228 * @context: pointer to Root Port data structure
1230 * Invoked when Root Port detects AER messages.
1232 static irqreturn_t
aer_irq(int irq
, void *context
)
1234 struct pcie_device
*pdev
= (struct pcie_device
*)context
;
1235 struct aer_rpc
*rpc
= get_service_data(pdev
);
1236 struct pci_dev
*rp
= rpc
->rpd
;
1237 struct aer_err_source e_src
= {};
1238 int pos
= rp
->aer_cap
;
1240 pci_read_config_dword(rp
, pos
+ PCI_ERR_ROOT_STATUS
, &e_src
.status
);
1241 if (!(e_src
.status
& (PCI_ERR_ROOT_UNCOR_RCV
|PCI_ERR_ROOT_COR_RCV
)))
1244 pci_read_config_dword(rp
, pos
+ PCI_ERR_ROOT_ERR_SRC
, &e_src
.id
);
1245 pci_write_config_dword(rp
, pos
+ PCI_ERR_ROOT_STATUS
, e_src
.status
);
1247 if (!kfifo_put(&rpc
->aer_fifo
, e_src
))
1250 return IRQ_WAKE_THREAD
;
1253 static int set_device_error_reporting(struct pci_dev
*dev
, void *data
)
1255 bool enable
= *((bool *)data
);
1256 int type
= pci_pcie_type(dev
);
1258 if ((type
== PCI_EXP_TYPE_ROOT_PORT
) ||
1259 (type
== PCI_EXP_TYPE_UPSTREAM
) ||
1260 (type
== PCI_EXP_TYPE_DOWNSTREAM
)) {
1262 pci_enable_pcie_error_reporting(dev
);
1264 pci_disable_pcie_error_reporting(dev
);
1268 pcie_set_ecrc_checking(dev
);
1274 * set_downstream_devices_error_reporting - enable/disable the error reporting bits on the root port and its downstream ports.
1275 * @dev: pointer to root port's pci_dev data structure
1276 * @enable: true = enable error reporting, false = disable error reporting.
1278 static void set_downstream_devices_error_reporting(struct pci_dev
*dev
,
1281 set_device_error_reporting(dev
, &enable
);
1283 if (!dev
->subordinate
)
1285 pci_walk_bus(dev
->subordinate
, set_device_error_reporting
, &enable
);
1289 * aer_enable_rootport - enable Root Port's interrupts when receiving messages
1290 * @rpc: pointer to a Root Port data structure
1292 * Invoked when PCIe bus loads AER service driver.
1294 static void aer_enable_rootport(struct aer_rpc
*rpc
)
1296 struct pci_dev
*pdev
= rpc
->rpd
;
1301 /* Clear PCIe Capability's Device Status */
1302 pcie_capability_read_word(pdev
, PCI_EXP_DEVSTA
, ®16
);
1303 pcie_capability_write_word(pdev
, PCI_EXP_DEVSTA
, reg16
);
1305 /* Disable system error generation in response to error messages */
1306 pcie_capability_clear_word(pdev
, PCI_EXP_RTCTL
,
1307 SYSTEM_ERROR_INTR_ON_MESG_MASK
);
1309 aer_pos
= pdev
->aer_cap
;
1310 /* Clear error status */
1311 pci_read_config_dword(pdev
, aer_pos
+ PCI_ERR_ROOT_STATUS
, ®32
);
1312 pci_write_config_dword(pdev
, aer_pos
+ PCI_ERR_ROOT_STATUS
, reg32
);
1313 pci_read_config_dword(pdev
, aer_pos
+ PCI_ERR_COR_STATUS
, ®32
);
1314 pci_write_config_dword(pdev
, aer_pos
+ PCI_ERR_COR_STATUS
, reg32
);
1315 pci_read_config_dword(pdev
, aer_pos
+ PCI_ERR_UNCOR_STATUS
, ®32
);
1316 pci_write_config_dword(pdev
, aer_pos
+ PCI_ERR_UNCOR_STATUS
, reg32
);
1319 * Enable error reporting for the root port device and downstream port
1322 set_downstream_devices_error_reporting(pdev
, true);
1324 /* Enable Root Port's interrupt in response to error messages */
1325 pci_read_config_dword(pdev
, aer_pos
+ PCI_ERR_ROOT_COMMAND
, ®32
);
1326 reg32
|= ROOT_PORT_INTR_ON_MESG_MASK
;
1327 pci_write_config_dword(pdev
, aer_pos
+ PCI_ERR_ROOT_COMMAND
, reg32
);
1331 * aer_disable_rootport - disable Root Port's interrupts when receiving messages
1332 * @rpc: pointer to a Root Port data structure
1334 * Invoked when PCIe bus unloads AER service driver.
1336 static void aer_disable_rootport(struct aer_rpc
*rpc
)
1338 struct pci_dev
*pdev
= rpc
->rpd
;
1343 * Disable error reporting for the root port device and downstream port
1346 set_downstream_devices_error_reporting(pdev
, false);
1348 pos
= pdev
->aer_cap
;
1349 /* Disable Root's interrupt in response to error messages */
1350 pci_read_config_dword(pdev
, pos
+ PCI_ERR_ROOT_COMMAND
, ®32
);
1351 reg32
&= ~ROOT_PORT_INTR_ON_MESG_MASK
;
1352 pci_write_config_dword(pdev
, pos
+ PCI_ERR_ROOT_COMMAND
, reg32
);
1354 /* Clear Root's error status reg */
1355 pci_read_config_dword(pdev
, pos
+ PCI_ERR_ROOT_STATUS
, ®32
);
1356 pci_write_config_dword(pdev
, pos
+ PCI_ERR_ROOT_STATUS
, reg32
);
1360 * aer_remove - clean up resources
1361 * @dev: pointer to the pcie_dev data structure
1363 * Invoked when PCI Express bus unloads or AER probe fails.
1365 static void aer_remove(struct pcie_device
*dev
)
1367 struct aer_rpc
*rpc
= get_service_data(dev
);
1369 aer_disable_rootport(rpc
);
1373 * aer_probe - initialize resources
1374 * @dev: pointer to the pcie_dev data structure
1376 * Invoked when PCI Express bus loads AER service driver.
1378 static int aer_probe(struct pcie_device
*dev
)
1381 struct aer_rpc
*rpc
;
1382 struct device
*device
= &dev
->device
;
1384 rpc
= devm_kzalloc(device
, sizeof(struct aer_rpc
), GFP_KERNEL
);
1386 dev_printk(KERN_DEBUG
, device
, "alloc AER rpc failed\n");
1389 rpc
->rpd
= dev
->port
;
1390 set_service_data(dev
, rpc
);
1392 status
= devm_request_threaded_irq(device
, dev
->irq
, aer_irq
, aer_isr
,
1393 IRQF_SHARED
, "aerdrv", dev
);
1395 dev_printk(KERN_DEBUG
, device
, "request AER IRQ %d failed\n",
1400 aer_enable_rootport(rpc
);
1401 dev_info(device
, "AER enabled with IRQ %d\n", dev
->irq
);
1406 * aer_root_reset - reset link on Root Port
1407 * @dev: pointer to Root Port's pci_dev data structure
1409 * Invoked by Port Bus driver when performing link reset at Root Port.
1411 static pci_ers_result_t
aer_root_reset(struct pci_dev
*dev
)
1419 /* Disable Root's interrupt in response to error messages */
1420 pci_read_config_dword(dev
, pos
+ PCI_ERR_ROOT_COMMAND
, ®32
);
1421 reg32
&= ~ROOT_PORT_INTR_ON_MESG_MASK
;
1422 pci_write_config_dword(dev
, pos
+ PCI_ERR_ROOT_COMMAND
, reg32
);
1424 rc
= pci_bus_error_reset(dev
);
1425 pci_printk(KERN_DEBUG
, dev
, "Root Port link has been reset\n");
1427 /* Clear Root Error Status */
1428 pci_read_config_dword(dev
, pos
+ PCI_ERR_ROOT_STATUS
, ®32
);
1429 pci_write_config_dword(dev
, pos
+ PCI_ERR_ROOT_STATUS
, reg32
);
1431 /* Enable Root Port's interrupt in response to error messages */
1432 pci_read_config_dword(dev
, pos
+ PCI_ERR_ROOT_COMMAND
, ®32
);
1433 reg32
|= ROOT_PORT_INTR_ON_MESG_MASK
;
1434 pci_write_config_dword(dev
, pos
+ PCI_ERR_ROOT_COMMAND
, reg32
);
1436 return rc
? PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_RECOVERED
;
1439 static struct pcie_port_service_driver aerdriver
= {
1441 .port_type
= PCI_EXP_TYPE_ROOT_PORT
,
1442 .service
= PCIE_PORT_SERVICE_AER
,
1445 .remove
= aer_remove
,
1446 .reset_link
= aer_root_reset
,
1450 * aer_service_init - register AER root service driver
1452 * Invoked when AER root service driver is loaded.
1454 int __init
pcie_aer_init(void)
1456 if (!pci_aer_available() || aer_acpi_firmware_first())
1458 return pcie_port_service_register(&aerdriver
);