drivers/pci/pcie/dpc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * PCI Express Downstream Port Containment services driver
   4  * Author: Keith Busch <keith.busch@intel.com>
   5  *
   6  * Copyright (C) 2016 Intel Corp.
   7  */
   8
   9 #include <linux/aer.h>
  10 #include <linux/delay.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/init.h>
  13 #include <linux/pci.h>
  14
  15 #include "portdrv.h"
  16 #include "../pci.h"
  17
  18 struct dpc_dev {
  19         struct pcie_device      *dev;
  20         u16                     cap_pos;
  21         bool                    rp_extensions;
  22         u8                      rp_log_size;
  23 };
  24
  25 static const char * const rp_pio_error_string[] = {
  26         "Configuration Request received UR Completion",  /* Bit Position 0  */
  27         "Configuration Request received CA Completion",  /* Bit Position 1  */
  28         "Configuration Request Completion Timeout",      /* Bit Position 2  */
  29         NULL,
  30         NULL,
  31         NULL,
  32         NULL,
  33         NULL,
  34         "I/O Request received UR Completion",            /* Bit Position 8  */
  35         "I/O Request received CA Completion",            /* Bit Position 9  */
  36         "I/O Request Completion Timeout",                /* Bit Position 10 */
  37         NULL,
  38         NULL,
  39         NULL,
  40         NULL,
  41         NULL,
  42         "Memory Request received UR Completion",         /* Bit Position 16 */
  43         "Memory Request received CA Completion",         /* Bit Position 17 */
  44         "Memory Request Completion Timeout",             /* Bit Position 18 */
  45 };
  46
  47 static struct dpc_dev *to_dpc_dev(struct pci_dev *dev)
  48 {
  49         struct device *device;
  50
  51         device = pcie_port_find_device(dev, PCIE_PORT_SERVICE_DPC);
  52         if (!device)
  53                 return NULL;
  54         return get_service_data(to_pcie_device(device));
  55 }
  56
  57 void pci_save_dpc_state(struct pci_dev *dev)
  58 {
  59         struct dpc_dev *dpc;
  60         struct pci_cap_saved_state *save_state;
  61         u16 *cap;
  62
  63         if (!pci_is_pcie(dev))
  64                 return;
  65
  66         dpc = to_dpc_dev(dev);
  67         if (!dpc)
  68                 return;
  69
  70         save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_DPC);
  71         if (!save_state)
  72                 return;
  73
  74         cap = (u16 *)&save_state->cap.data[0];
  75         pci_read_config_word(dev, dpc->cap_pos + PCI_EXP_DPC_CTL, cap);
  76 }
  77
  78 void pci_restore_dpc_state(struct pci_dev *dev)
  79 {
  80         struct dpc_dev *dpc;
  81         struct pci_cap_saved_state *save_state;
  82         u16 *cap;
  83
  84         if (!pci_is_pcie(dev))
  85                 return;
  86
  87         dpc = to_dpc_dev(dev);
  88         if (!dpc)
  89                 return;
  90
  91         save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_DPC);
  92         if (!save_state)
  93                 return;
  94
  95         cap = (u16 *)&save_state->cap.data[0];
  96         pci_write_config_word(dev, dpc->cap_pos + PCI_EXP_DPC_CTL, *cap);
  97 }
  98
  99 static int dpc_wait_rp_inactive(struct dpc_dev *dpc)
 100 {
 101         unsigned long timeout = jiffies + HZ;
 102         struct pci_dev *pdev = dpc->dev->port;
 103         struct device *dev = &dpc->dev->device;
 104         u16 cap = dpc->cap_pos, status;
 105
 106         pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
 107         while (status & PCI_EXP_DPC_RP_BUSY &&
 108                                         !time_after(jiffies, timeout)) {
 109                 msleep(10);
 110                 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
 111         }
 112         if (status & PCI_EXP_DPC_RP_BUSY) {
 113                 dev_warn(dev, "DPC root port still busy\n");
 114                 return -EBUSY;
 115         }
 116         return 0;
 117 }
 118
 119 static pci_ers_result_t dpc_reset_link(struct pci_dev *pdev)
 120 {
 121         struct dpc_dev *dpc;
 122         u16 cap;
 123
 124         /*
 125          * DPC disables the Link automatically in hardware, so it has
 126          * already been reset by the time we get here.
 127          */
 128         dpc = to_dpc_dev(pdev);
 129         cap = dpc->cap_pos;
 130
 131         /*
 132          * Wait until the Link is inactive, then clear DPC Trigger Status
 133          * to allow the Port to leave DPC.
 134          */
 135         pcie_wait_for_link(pdev, false);
 136
 137         if (dpc->rp_extensions && dpc_wait_rp_inactive(dpc))
 138                 return PCI_ERS_RESULT_DISCONNECT;
 139
 140         pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
 141                               PCI_EXP_DPC_STATUS_TRIGGER);
 142
 143         if (!pcie_wait_for_link(pdev, true))
 144                 return PCI_ERS_RESULT_DISCONNECT;
 145
 146         return PCI_ERS_RESULT_RECOVERED;
 147 }
 148
 149 static void dpc_process_rp_pio_error(struct dpc_dev *dpc)
 150 {
 151         struct device *dev = &dpc->dev->device;
 152         struct pci_dev *pdev = dpc->dev->port;
 153         u16 cap = dpc->cap_pos, dpc_status, first_error;
 154         u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix;
 155         int i;
 156
 157         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
 158         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask);
 159         dev_err(dev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
 160                 status, mask);
 161
 162         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev);
 163         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr);
 164         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc);
 165         dev_err(dev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
 166                 sev, syserr, exc);
 167
 168         /* Get First Error Pointer */
 169         pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status);
 170         first_error = (dpc_status & 0x1f00) >> 8;
 171
 172         for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) {
 173                 if ((status & ~mask) & (1 << i))
 174                         dev_err(dev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
 175                                 first_error == i ? " (First)" : "");
 176         }
 177
 178         if (dpc->rp_log_size < 4)
 179                 goto clear_status;
 180         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
 181                               &dw0);
 182         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
 183                               &dw1);
 184         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
 185                               &dw2);
 186         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
 187                               &dw3);
 188         dev_err(dev, "TLP Header: %#010x %#010x %#010x %#010x\n",
 189                 dw0, dw1, dw2, dw3);
 190
 191         if (dpc->rp_log_size < 5)
 192                 goto clear_status;
 193         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log);
 194         dev_err(dev, "RP PIO ImpSpec Log %#010x\n", log);
 195
 196         for (i = 0; i < dpc->rp_log_size - 5; i++) {
 197                 pci_read_config_dword(pdev,
 198                         cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, &prefix);
 199                 dev_err(dev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix);
 200         }
 201  clear_status:
 202         pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, status);
 203 }
 204
 205 static irqreturn_t dpc_handler(int irq, void *context)
 206 {
 207         struct aer_err_info info;
 208         struct dpc_dev *dpc = context;
 209         struct pci_dev *pdev = dpc->dev->port;
 210         struct device *dev = &dpc->dev->device;
 211         u16 cap = dpc->cap_pos, status, source, reason, ext_reason;
 212
 213         pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
 214         pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID, &source);
 215
 216         dev_info(dev, "DPC containment event, status:%#06x source:%#06x\n",
 217                  status, source);
 218
 219         reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN) >> 1;
 220         ext_reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT) >> 5;
 221         dev_warn(dev, "DPC %s detected\n",
 222                  (reason == 0) ? "unmasked uncorrectable error" :
 223                  (reason == 1) ? "ERR_NONFATAL" :
 224                  (reason == 2) ? "ERR_FATAL" :
 225                  (ext_reason == 0) ? "RP PIO error" :
 226                  (ext_reason == 1) ? "software trigger" :
 227                                      "reserved error");
 228
 229         /* show RP PIO error detail information */
 230         if (dpc->rp_extensions && reason == 3 && ext_reason == 0)
 231                 dpc_process_rp_pio_error(dpc);
 232         else if (reason == 0 && aer_get_device_error_info(pdev, &info)) {
 233                 aer_print_error(pdev, &info);
 234                 pci_cleanup_aer_uncorrect_error_status(pdev);
 235         }
 236
 237         /* We configure DPC so it only triggers on ERR_FATAL */
 238         pcie_do_recovery(pdev, pci_channel_io_frozen, PCIE_PORT_SERVICE_DPC);
 239
 240         return IRQ_HANDLED;
 241 }
 242
 243 static irqreturn_t dpc_irq(int irq, void *context)
 244 {
 245         struct dpc_dev *dpc = (struct dpc_dev *)context;
 246         struct pci_dev *pdev = dpc->dev->port;
 247         u16 cap = dpc->cap_pos, status;
 248
 249         pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
 250
 251         if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT) || status == (u16)(~0))
 252                 return IRQ_NONE;
 253
 254         pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
 255                               PCI_EXP_DPC_STATUS_INTERRUPT);
 256         if (status & PCI_EXP_DPC_STATUS_TRIGGER)
 257                 return IRQ_WAKE_THREAD;
 258         return IRQ_HANDLED;
 259 }
 260
 261 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
 262 static int dpc_probe(struct pcie_device *dev)
 263 {
 264         struct dpc_dev *dpc;
 265         struct pci_dev *pdev = dev->port;
 266         struct device *device = &dev->device;
 267         int status;
 268         u16 ctl, cap;
 269
 270         if (pcie_aer_get_firmware_first(pdev))
 271                 return -ENOTSUPP;
 272
 273         dpc = devm_kzalloc(device, sizeof(*dpc), GFP_KERNEL);
 274         if (!dpc)
 275                 return -ENOMEM;
 276
 277         dpc->cap_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
 278         dpc->dev = dev;
 279         set_service_data(dev, dpc);
 280
 281         status = devm_request_threaded_irq(device, dev->irq, dpc_irq,
 282                                            dpc_handler, IRQF_SHARED,
 283                                            "pcie-dpc", dpc);
 284         if (status) {
 285                 dev_warn(device, "request IRQ%d failed: %d\n", dev->irq,
 286                          status);
 287                 return status;
 288         }
 289
 290         pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CAP, &cap);
 291         pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl);
 292
 293         dpc->rp_extensions = (cap & PCI_EXP_DPC_CAP_RP_EXT);
 294         if (dpc->rp_extensions) {
 295                 dpc->rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
 296                 if (dpc->rp_log_size < 4 || dpc->rp_log_size > 9) {
 297                         dev_err(device, "RP PIO log size %u is invalid\n",
 298                                 dpc->rp_log_size);
 299                         dpc->rp_log_size = 0;
 300                 }
 301         }
 302
 303         ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN;
 304         pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);
 305
 306         dev_info(device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
 307                 cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
 308                 FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
 309                 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), dpc->rp_log_size,
 310                 FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE));
 311
 312         pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_DPC, sizeof(u16));
 313         return status;
 314 }
 315
 316 static void dpc_remove(struct pcie_device *dev)
 317 {
 318         struct dpc_dev *dpc = get_service_data(dev);
 319         struct pci_dev *pdev = dev->port;
 320         u16 ctl;
 321
 322         pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl);
 323         ctl &= ~(PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN);
 324         pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);
 325 }
 326
 327 static struct pcie_port_service_driver dpcdriver = {
 328         .name           = "dpc",
 329         .port_type      = PCIE_ANY_PORT,
 330         .service        = PCIE_PORT_SERVICE_DPC,
 331         .probe          = dpc_probe,
 332         .remove         = dpc_remove,
 333         .reset_link     = dpc_reset_link,
 334 };
 335
 336 int __init pcie_dpc_init(void)
 337 {
 338         return pcie_port_service_register(&dpcdriver);
 339 }