mic: vop: Fix use-after-free on remove
[linux/fpc-iii.git] / drivers / scsi / mpt3sas / mpi / mpi2_ioc.h
blob68ea408cd5c5cadb7d7dd73d6c5932ea6901b562
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
6 * Name: mpi2_ioc.h
7 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
8 * Creation Date: October 11, 2006
10 * mpi2_ioc.h Version: 02.00.37
12 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
13 * prefix are for use only on MPI v2.5 products, and must not be used
14 * with MPI v2.0 products. Unless otherwise noted, names beginning with
15 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
17 * Version History
18 * ---------------
20 * Date Version Description
21 * -------- -------- ------------------------------------------------------
22 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
23 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
24 * MaxTargets.
25 * Added TotalImageSize field to FWDownload Request.
26 * Added reserved words to FWUpload Request.
27 * 06-26-07 02.00.02 Added IR Configuration Change List Event.
28 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
29 * request and replaced it with
30 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
31 * Replaced the MinReplyQueueDepth field of the IOCFacts
32 * reply with MaxReplyDescriptorPostQueueDepth.
33 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
34 * depth for the Reply Descriptor Post Queue.
35 * Added SASAddress field to Initiator Device Table
36 * Overflow Event data.
37 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
38 * for SAS Initiator Device Status Change Event data.
39 * Modified Reason Code defines for SAS Topology Change
40 * List Event data, including adding a bit for PHY Vacant
41 * status, and adding a mask for the Reason Code.
42 * Added define for
43 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
44 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
45 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of
46 * the IOCFacts Reply.
47 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
48 * Moved MPI2_VERSION_UNION to mpi2.h.
49 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
50 * instead of enables, and added SASBroadcastPrimitiveMasks
51 * field.
52 * Added Log Entry Added Event and related structure.
53 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
54 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
55 * Added MaxVolumes and MaxPersistentEntries fields to
56 * IOCFacts reply.
57 * Added ProtocalFlags and IOCCapabilities fields to
58 * MPI2_FW_IMAGE_HEADER.
59 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
60 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
61 * a U16 (from a U32).
62 * Removed extra 's' from EventMasks name.
63 * 06-27-08 02.00.08 Fixed an offset in a comment.
64 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
65 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
66 * renamed MinReplyFrameSize to ReplyFrameSize.
67 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
68 * Added two new RAIDOperation values for Integrated RAID
69 * Operations Status Event data.
70 * Added four new IR Configuration Change List Event data
71 * ReasonCode values.
72 * Added two new ReasonCode defines for SAS Device Status
73 * Change Event data.
74 * Added three new DiscoveryStatus bits for the SAS
75 * Discovery event data.
76 * Added Multiplexing Status Change bit to the PhyStatus
77 * field of the SAS Topology Change List event data.
78 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
79 * BootFlags are now product-specific.
80 * Added defines for the indivdual signature bytes
81 * for MPI2_INIT_IMAGE_FOOTER.
82 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
83 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
84 * define.
85 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
86 * define.
87 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
88 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
89 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
90 * Added two new reason codes for SAS Device Status Change
91 * Event.
92 * Added new event: SAS PHY Counter.
93 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
94 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
95 * Added new product id family for 2208.
96 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
97 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
98 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
99 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
100 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
101 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
102 * Added Host Based Discovery Phy Event data.
103 * Added defines for ProductID Product field
104 * (MPI2_FW_HEADER_PID_).
105 * Modified values for SAS ProductID Family
106 * (MPI2_FW_HEADER_PID_FAMILY_).
107 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines.
108 * Added PowerManagementControl Request structures and
109 * defines.
110 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete.
111 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
112 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
113 * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added
114 * SASNotifyPrimitiveMasks field to
115 * MPI2_EVENT_NOTIFICATION_REQUEST.
116 * Added Temperature Threshold Event.
117 * Added Host Message Event.
118 * Added Send Host Message request and reply.
119 * 05-25-11 02.00.18 For Extended Image Header, added
120 * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
121 * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
122 * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
123 * 08-24-11 02.00.19 Added PhysicalPort field to
124 * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
125 * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
126 * 11-18-11 02.00.20 Incorporating additions for MPI v2.5.
127 * 03-29-12 02.00.21 Added a product specific range to event values.
128 * 07-26-12 02.00.22 Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE.
129 * Added ElapsedSeconds field to
130 * MPI2_EVENT_DATA_IR_OPERATION_STATUS.
131 * 08-19-13 02.00.23 For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE
132 * and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY.
133 * Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE.
134 * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY.
135 * Added Encrypted Hash Extended Image.
136 * 12-05-13 02.00.24 Added MPI25_HASH_IMAGE_TYPE_BIOS.
137 * 11-18-14 02.00.25 Updated copyright information.
138 * 03-16-15 02.00.26 Updated for MPI v2.6.
139 * Added MPI2_EVENT_ACTIVE_CABLE_EXCEPTION and
140 * MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT.
141 * Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS and
142 * MPI26_FW_HEADER_PID_FAMILY_3516_SAS.
143 * Added MPI26_CTRL_OP_SHUTDOWN.
144 * 08-25-15 02.00.27 Added IC ARCH Class based signature defines.
145 * Added MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED event.
146 * Added ConigurationFlags field to IOCInit message to
147 * support NVMe SGL format control.
148 * Added PCIe SRIOV support.
149 * 02-17-16 02.00.28 Added SAS 4 22.5 gbs speed support.
150 * Added PCIe 4 16.0 GT/sec speec support.
151 * Removed AHCI support.
152 * Removed SOP support.
153 * 07-01-16 02.00.29 Added Archclass for 4008 product.
154 * Added IOCException MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED
155 * 08-23-16 02.00.30 Added new defines for the ImageType field of FWDownload
156 * Request Message.
157 * Added new defines for the ImageType field of FWUpload
158 * Request Message.
159 * Added new values for the RegionType field in the Layout
160 * Data sections of the FLASH Layout Extended Image Data.
161 * Added new defines for the ReasonCode field of
162 * Active Cable Exception Event.
163 * Added MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE and
164 * MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE.
165 * 11-23-16 02.00.31 Added MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR and
166 * MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR.
167 * 02-02-17 02.00.32 Added MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP.
168 * Added MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT and related
169 * defines for the ReasonCode field.
170 * 06-13-17 02.00.33 Added MPI2_FW_DOWNLOAD_ITYPE_CPLD.
171 * 09-29-17 02.00.34 Added MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED
172 * to the ReasonCode field in PCIe Device Status Change
173 * Event Data.
174 * 07-22-18 02.00.35 Added FW_DOWNLOAD_ITYPE_CPLD and _PSOC.
175 * Moved FW image definitions ionto new mpi2_image,h
176 * 08-14-18 02.00.36 Fixed definition of MPI2_FW_DOWNLOAD_ITYPE_PSOC (0x16)
177 * 09-07-18 02.00.37 Added MPI26_EVENT_PCIE_TOPO_PI_16_LANES
178 * --------------------------------------------------------------------------
181 #ifndef MPI2_IOC_H
182 #define MPI2_IOC_H
184 /*****************************************************************************
186 * IOC Messages
188 *****************************************************************************/
190 /****************************************************************************
191 * IOCInit message
192 ****************************************************************************/
194 /*IOCInit Request message */
195 typedef struct _MPI2_IOC_INIT_REQUEST {
196 U8 WhoInit; /*0x00 */
197 U8 Reserved1; /*0x01 */
198 U8 ChainOffset; /*0x02 */
199 U8 Function; /*0x03 */
200 U16 Reserved2; /*0x04 */
201 U8 Reserved3; /*0x06 */
202 U8 MsgFlags; /*0x07 */
203 U8 VP_ID; /*0x08 */
204 U8 VF_ID; /*0x09 */
205 U16 Reserved4; /*0x0A */
206 U16 MsgVersion; /*0x0C */
207 U16 HeaderVersion; /*0x0E */
208 U32 Reserved5; /*0x10 */
209 U16 ConfigurationFlags; /* 0x14 */
210 U8 HostPageSize; /*0x16 */
211 U8 HostMSIxVectors; /*0x17 */
212 U16 Reserved8; /*0x18 */
213 U16 SystemRequestFrameSize; /*0x1A */
214 U16 ReplyDescriptorPostQueueDepth; /*0x1C */
215 U16 ReplyFreeQueueDepth; /*0x1E */
216 U32 SenseBufferAddressHigh; /*0x20 */
217 U32 SystemReplyAddressHigh; /*0x24 */
218 U64 SystemRequestFrameBaseAddress; /*0x28 */
219 U64 ReplyDescriptorPostQueueAddress; /*0x30 */
220 U64 ReplyFreeQueueAddress; /*0x38 */
221 U64 TimeStamp; /*0x40 */
222 } MPI2_IOC_INIT_REQUEST, *PTR_MPI2_IOC_INIT_REQUEST,
223 Mpi2IOCInitRequest_t, *pMpi2IOCInitRequest_t;
225 /*WhoInit values */
226 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
227 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
228 #define MPI2_WHOINIT_ROM_BIOS (0x02)
229 #define MPI2_WHOINIT_PCI_PEER (0x03)
230 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
231 #define MPI2_WHOINIT_MANUFACTURER (0x05)
233 /* MsgFlags */
234 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01)
237 /*MsgVersion */
238 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
239 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
240 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
241 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
243 /*HeaderVersion */
244 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
245 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
246 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
247 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
249 /*ConfigurationFlags */
250 #define MPI26_IOCINIT_CFGFLAGS_NVME_SGL_FORMAT (0x0001)
252 /*minimum depth for a Reply Descriptor Post Queue */
253 #define MPI2_RDPQ_DEPTH_MIN (16)
255 /* Reply Descriptor Post Queue Array Entry */
256 typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
257 U64 RDPQBaseAddress; /* 0x00 */
258 U32 Reserved1; /* 0x08 */
259 U32 Reserved2; /* 0x0C */
260 } MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
261 *PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
262 Mpi2IOCInitRDPQArrayEntry, *pMpi2IOCInitRDPQArrayEntry;
265 /*IOCInit Reply message */
266 typedef struct _MPI2_IOC_INIT_REPLY {
267 U8 WhoInit; /*0x00 */
268 U8 Reserved1; /*0x01 */
269 U8 MsgLength; /*0x02 */
270 U8 Function; /*0x03 */
271 U16 Reserved2; /*0x04 */
272 U8 Reserved3; /*0x06 */
273 U8 MsgFlags; /*0x07 */
274 U8 VP_ID; /*0x08 */
275 U8 VF_ID; /*0x09 */
276 U16 Reserved4; /*0x0A */
277 U16 Reserved5; /*0x0C */
278 U16 IOCStatus; /*0x0E */
279 U32 IOCLogInfo; /*0x10 */
280 } MPI2_IOC_INIT_REPLY, *PTR_MPI2_IOC_INIT_REPLY,
281 Mpi2IOCInitReply_t, *pMpi2IOCInitReply_t;
283 /****************************************************************************
284 * IOCFacts message
285 ****************************************************************************/
287 /*IOCFacts Request message */
288 typedef struct _MPI2_IOC_FACTS_REQUEST {
289 U16 Reserved1; /*0x00 */
290 U8 ChainOffset; /*0x02 */
291 U8 Function; /*0x03 */
292 U16 Reserved2; /*0x04 */
293 U8 Reserved3; /*0x06 */
294 U8 MsgFlags; /*0x07 */
295 U8 VP_ID; /*0x08 */
296 U8 VF_ID; /*0x09 */
297 U16 Reserved4; /*0x0A */
298 } MPI2_IOC_FACTS_REQUEST, *PTR_MPI2_IOC_FACTS_REQUEST,
299 Mpi2IOCFactsRequest_t, *pMpi2IOCFactsRequest_t;
301 /*IOCFacts Reply message */
302 typedef struct _MPI2_IOC_FACTS_REPLY {
303 U16 MsgVersion; /*0x00 */
304 U8 MsgLength; /*0x02 */
305 U8 Function; /*0x03 */
306 U16 HeaderVersion; /*0x04 */
307 U8 IOCNumber; /*0x06 */
308 U8 MsgFlags; /*0x07 */
309 U8 VP_ID; /*0x08 */
310 U8 VF_ID; /*0x09 */
311 U16 Reserved1; /*0x0A */
312 U16 IOCExceptions; /*0x0C */
313 U16 IOCStatus; /*0x0E */
314 U32 IOCLogInfo; /*0x10 */
315 U8 MaxChainDepth; /*0x14 */
316 U8 WhoInit; /*0x15 */
317 U8 NumberOfPorts; /*0x16 */
318 U8 MaxMSIxVectors; /*0x17 */
319 U16 RequestCredit; /*0x18 */
320 U16 ProductID; /*0x1A */
321 U32 IOCCapabilities; /*0x1C */
322 MPI2_VERSION_UNION FWVersion; /*0x20 */
323 U16 IOCRequestFrameSize; /*0x24 */
324 U16 IOCMaxChainSegmentSize; /*0x26 */
325 U16 MaxInitiators; /*0x28 */
326 U16 MaxTargets; /*0x2A */
327 U16 MaxSasExpanders; /*0x2C */
328 U16 MaxEnclosures; /*0x2E */
329 U16 ProtocolFlags; /*0x30 */
330 U16 HighPriorityCredit; /*0x32 */
331 U16 MaxReplyDescriptorPostQueueDepth; /*0x34 */
332 U8 ReplyFrameSize; /*0x36 */
333 U8 MaxVolumes; /*0x37 */
334 U16 MaxDevHandle; /*0x38 */
335 U16 MaxPersistentEntries; /*0x3A */
336 U16 MinDevHandle; /*0x3C */
337 U8 CurrentHostPageSize; /* 0x3E */
338 U8 Reserved4; /* 0x3F */
339 U8 SGEModifierMask; /*0x40 */
340 U8 SGEModifierValue; /*0x41 */
341 U8 SGEModifierShift; /*0x42 */
342 U8 Reserved5; /*0x43 */
343 } MPI2_IOC_FACTS_REPLY, *PTR_MPI2_IOC_FACTS_REPLY,
344 Mpi2IOCFactsReply_t, *pMpi2IOCFactsReply_t;
346 /*MsgVersion */
347 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
348 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
349 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
350 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
352 /*HeaderVersion */
353 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
354 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
355 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
356 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
358 /*IOCExceptions */
359 #define MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0400)
360 #define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0200)
361 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
363 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
364 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
365 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
366 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
367 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
369 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
370 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
371 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
372 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
373 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
375 /*defines for WhoInit field are after the IOCInit Request */
377 /*ProductID field uses MPI2_FW_HEADER_PID_ */
379 /*IOCCapabilities */
380 #define MPI26_IOCFACTS_CAPABILITY_PCIE_SRIOV (0x00100000)
381 #define MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ (0x00080000)
382 #define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE (0x00040000)
383 #define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000)
384 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000)
385 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
386 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
387 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
388 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
389 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
390 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
391 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
392 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
393 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
394 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
395 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
396 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
398 /*ProtocolFlags */
399 #define MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES (0x0008)
400 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
401 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
403 /****************************************************************************
404 * PortFacts message
405 ****************************************************************************/
407 /*PortFacts Request message */
408 typedef struct _MPI2_PORT_FACTS_REQUEST {
409 U16 Reserved1; /*0x00 */
410 U8 ChainOffset; /*0x02 */
411 U8 Function; /*0x03 */
412 U16 Reserved2; /*0x04 */
413 U8 PortNumber; /*0x06 */
414 U8 MsgFlags; /*0x07 */
415 U8 VP_ID; /*0x08 */
416 U8 VF_ID; /*0x09 */
417 U16 Reserved3; /*0x0A */
418 } MPI2_PORT_FACTS_REQUEST, *PTR_MPI2_PORT_FACTS_REQUEST,
419 Mpi2PortFactsRequest_t, *pMpi2PortFactsRequest_t;
421 /*PortFacts Reply message */
422 typedef struct _MPI2_PORT_FACTS_REPLY {
423 U16 Reserved1; /*0x00 */
424 U8 MsgLength; /*0x02 */
425 U8 Function; /*0x03 */
426 U16 Reserved2; /*0x04 */
427 U8 PortNumber; /*0x06 */
428 U8 MsgFlags; /*0x07 */
429 U8 VP_ID; /*0x08 */
430 U8 VF_ID; /*0x09 */
431 U16 Reserved3; /*0x0A */
432 U16 Reserved4; /*0x0C */
433 U16 IOCStatus; /*0x0E */
434 U32 IOCLogInfo; /*0x10 */
435 U8 Reserved5; /*0x14 */
436 U8 PortType; /*0x15 */
437 U16 Reserved6; /*0x16 */
438 U16 MaxPostedCmdBuffers; /*0x18 */
439 U16 Reserved7; /*0x1A */
440 } MPI2_PORT_FACTS_REPLY, *PTR_MPI2_PORT_FACTS_REPLY,
441 Mpi2PortFactsReply_t, *pMpi2PortFactsReply_t;
443 /*PortType values */
444 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
445 #define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
446 #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
447 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
448 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
449 #define MPI2_PORTFACTS_PORTTYPE_TRI_MODE (0x40)
452 /****************************************************************************
453 * PortEnable message
454 ****************************************************************************/
456 /*PortEnable Request message */
457 typedef struct _MPI2_PORT_ENABLE_REQUEST {
458 U16 Reserved1; /*0x00 */
459 U8 ChainOffset; /*0x02 */
460 U8 Function; /*0x03 */
461 U8 Reserved2; /*0x04 */
462 U8 PortFlags; /*0x05 */
463 U8 Reserved3; /*0x06 */
464 U8 MsgFlags; /*0x07 */
465 U8 VP_ID; /*0x08 */
466 U8 VF_ID; /*0x09 */
467 U16 Reserved4; /*0x0A */
468 } MPI2_PORT_ENABLE_REQUEST, *PTR_MPI2_PORT_ENABLE_REQUEST,
469 Mpi2PortEnableRequest_t, *pMpi2PortEnableRequest_t;
471 /*PortEnable Reply message */
472 typedef struct _MPI2_PORT_ENABLE_REPLY {
473 U16 Reserved1; /*0x00 */
474 U8 MsgLength; /*0x02 */
475 U8 Function; /*0x03 */
476 U8 Reserved2; /*0x04 */
477 U8 PortFlags; /*0x05 */
478 U8 Reserved3; /*0x06 */
479 U8 MsgFlags; /*0x07 */
480 U8 VP_ID; /*0x08 */
481 U8 VF_ID; /*0x09 */
482 U16 Reserved4; /*0x0A */
483 U16 Reserved5; /*0x0C */
484 U16 IOCStatus; /*0x0E */
485 U32 IOCLogInfo; /*0x10 */
486 } MPI2_PORT_ENABLE_REPLY, *PTR_MPI2_PORT_ENABLE_REPLY,
487 Mpi2PortEnableReply_t, *pMpi2PortEnableReply_t;
489 /****************************************************************************
490 * EventNotification message
491 ****************************************************************************/
493 /*EventNotification Request message */
494 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)
496 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST {
497 U16 Reserved1; /*0x00 */
498 U8 ChainOffset; /*0x02 */
499 U8 Function; /*0x03 */
500 U16 Reserved2; /*0x04 */
501 U8 Reserved3; /*0x06 */
502 U8 MsgFlags; /*0x07 */
503 U8 VP_ID; /*0x08 */
504 U8 VF_ID; /*0x09 */
505 U16 Reserved4; /*0x0A */
506 U32 Reserved5; /*0x0C */
507 U32 Reserved6; /*0x10 */
508 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS]; /*0x14 */
509 U16 SASBroadcastPrimitiveMasks; /*0x24 */
510 U16 SASNotifyPrimitiveMasks; /*0x26 */
511 U32 Reserved8; /*0x28 */
512 } MPI2_EVENT_NOTIFICATION_REQUEST,
513 *PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
514 Mpi2EventNotificationRequest_t,
515 *pMpi2EventNotificationRequest_t;
517 /*EventNotification Reply message */
518 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY {
519 U16 EventDataLength; /*0x00 */
520 U8 MsgLength; /*0x02 */
521 U8 Function; /*0x03 */
522 U16 Reserved1; /*0x04 */
523 U8 AckRequired; /*0x06 */
524 U8 MsgFlags; /*0x07 */
525 U8 VP_ID; /*0x08 */
526 U8 VF_ID; /*0x09 */
527 U16 Reserved2; /*0x0A */
528 U16 Reserved3; /*0x0C */
529 U16 IOCStatus; /*0x0E */
530 U32 IOCLogInfo; /*0x10 */
531 U16 Event; /*0x14 */
532 U16 Reserved4; /*0x16 */
533 U32 EventContext; /*0x18 */
534 U32 EventData[1]; /*0x1C */
535 } MPI2_EVENT_NOTIFICATION_REPLY, *PTR_MPI2_EVENT_NOTIFICATION_REPLY,
536 Mpi2EventNotificationReply_t,
537 *pMpi2EventNotificationReply_t;
539 /*AckRequired */
540 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
541 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
543 /*Event */
544 #define MPI2_EVENT_LOG_DATA (0x0001)
545 #define MPI2_EVENT_STATE_CHANGE (0x0002)
546 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
547 #define MPI2_EVENT_EVENT_CHANGE (0x000A)
548 #define MPI2_EVENT_TASK_SET_FULL (0x000E) /*obsolete */
549 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
550 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
551 #define MPI2_EVENT_SAS_DISCOVERY (0x0016)
552 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
553 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
554 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
555 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
556 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
557 #define MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x001D)
558 #define MPI2_EVENT_IR_VOLUME (0x001E)
559 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
560 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
561 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
562 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
563 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
564 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
565 #define MPI2_EVENT_SAS_QUIESCE (0x0025)
566 #define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026)
567 #define MPI2_EVENT_TEMP_THRESHOLD (0x0027)
568 #define MPI2_EVENT_HOST_MESSAGE (0x0028)
569 #define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029)
570 #define MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE (0x0030)
571 #define MPI2_EVENT_PCIE_ENUMERATION (0x0031)
572 #define MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x0032)
573 #define MPI2_EVENT_PCIE_LINK_COUNTER (0x0033)
574 #define MPI2_EVENT_ACTIVE_CABLE_EXCEPTION (0x0034)
575 #define MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x0035)
576 #define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E)
577 #define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F)
579 /*Log Entry Added Event data */
581 /*the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
582 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
584 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED {
585 U64 TimeStamp; /*0x00 */
586 U32 Reserved1; /*0x08 */
587 U16 LogSequence; /*0x0C */
588 U16 LogEntryQualifier; /*0x0E */
589 U8 VP_ID; /*0x10 */
590 U8 VF_ID; /*0x11 */
591 U16 Reserved2; /*0x12 */
592 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH]; /*0x14 */
593 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
594 *PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
595 Mpi2EventDataLogEntryAdded_t,
596 *pMpi2EventDataLogEntryAdded_t;
598 /*GPIO Interrupt Event data */
600 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
601 U8 GPIONum; /*0x00 */
602 U8 Reserved1; /*0x01 */
603 U16 Reserved2; /*0x02 */
604 } MPI2_EVENT_DATA_GPIO_INTERRUPT,
605 *PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
606 Mpi2EventDataGpioInterrupt_t,
607 *pMpi2EventDataGpioInterrupt_t;
609 /*Temperature Threshold Event data */
611 typedef struct _MPI2_EVENT_DATA_TEMPERATURE {
612 U16 Status; /*0x00 */
613 U8 SensorNum; /*0x02 */
614 U8 Reserved1; /*0x03 */
615 U16 CurrentTemperature; /*0x04 */
616 U16 Reserved2; /*0x06 */
617 U32 Reserved3; /*0x08 */
618 U32 Reserved4; /*0x0C */
619 } MPI2_EVENT_DATA_TEMPERATURE,
620 *PTR_MPI2_EVENT_DATA_TEMPERATURE,
621 Mpi2EventDataTemperature_t, *pMpi2EventDataTemperature_t;
623 /*Temperature Threshold Event data Status bits */
624 #define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008)
625 #define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004)
626 #define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002)
627 #define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001)
629 /*Host Message Event data */
631 typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE {
632 U8 SourceVF_ID; /*0x00 */
633 U8 Reserved1; /*0x01 */
634 U16 Reserved2; /*0x02 */
635 U32 Reserved3; /*0x04 */
636 U32 HostData[1]; /*0x08 */
637 } MPI2_EVENT_DATA_HOST_MESSAGE, *PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
638 Mpi2EventDataHostMessage_t, *pMpi2EventDataHostMessage_t;
640 /*Power Performance Change Event data */
642 typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE {
643 U8 CurrentPowerMode; /*0x00 */
644 U8 PreviousPowerMode; /*0x01 */
645 U16 Reserved1; /*0x02 */
646 } MPI2_EVENT_DATA_POWER_PERF_CHANGE,
647 *PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE,
648 Mpi2EventDataPowerPerfChange_t,
649 *pMpi2EventDataPowerPerfChange_t;
651 /*defines for CurrentPowerMode and PreviousPowerMode fields */
652 #define MPI2_EVENT_PM_INIT_MASK (0xC0)
653 #define MPI2_EVENT_PM_INIT_UNAVAILABLE (0x00)
654 #define MPI2_EVENT_PM_INIT_HOST (0x40)
655 #define MPI2_EVENT_PM_INIT_IO_UNIT (0x80)
656 #define MPI2_EVENT_PM_INIT_PCIE_DPA (0xC0)
658 #define MPI2_EVENT_PM_MODE_MASK (0x07)
659 #define MPI2_EVENT_PM_MODE_UNAVAILABLE (0x00)
660 #define MPI2_EVENT_PM_MODE_UNKNOWN (0x01)
661 #define MPI2_EVENT_PM_MODE_FULL_POWER (0x04)
662 #define MPI2_EVENT_PM_MODE_REDUCED_POWER (0x05)
663 #define MPI2_EVENT_PM_MODE_STANDBY (0x06)
665 /* Active Cable Exception Event data */
667 typedef struct _MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT {
668 U32 ActiveCablePowerRequirement; /* 0x00 */
669 U8 ReasonCode; /* 0x04 */
670 U8 ReceptacleID; /* 0x05 */
671 U16 Reserved1; /* 0x06 */
672 } MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
673 *PTR_MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
674 Mpi25EventDataActiveCableExcept_t,
675 *pMpi25EventDataActiveCableExcept_t,
676 MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
677 *PTR_MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
678 Mpi26EventDataActiveCableExcept_t,
679 *pMpi26EventDataActiveCableExcept_t;
681 /*MPI2.5 defines for the ReasonCode field */
682 #define MPI25_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00)
683 #define MPI25_EVENT_ACTIVE_CABLE_PRESENT (0x01)
684 #define MPI25_EVENT_ACTIVE_CABLE_DEGRADED (0x02)
686 /* defines for ReasonCode field */
687 #define MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00)
688 #define MPI26_EVENT_ACTIVE_CABLE_PRESENT (0x01)
689 #define MPI26_EVENT_ACTIVE_CABLE_DEGRADED (0x02)
691 /*Hard Reset Received Event data */
693 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED {
694 U8 Reserved1; /*0x00 */
695 U8 Port; /*0x01 */
696 U16 Reserved2; /*0x02 */
697 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
698 *PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
699 Mpi2EventDataHardResetReceived_t,
700 *pMpi2EventDataHardResetReceived_t;
702 /*Task Set Full Event data */
703 /* this event is obsolete */
705 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL {
706 U16 DevHandle; /*0x00 */
707 U16 CurrentDepth; /*0x02 */
708 } MPI2_EVENT_DATA_TASK_SET_FULL, *PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
709 Mpi2EventDataTaskSetFull_t, *pMpi2EventDataTaskSetFull_t;
711 /*SAS Device Status Change Event data */
713 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE {
714 U16 TaskTag; /*0x00 */
715 U8 ReasonCode; /*0x02 */
716 U8 PhysicalPort; /*0x03 */
717 U8 ASC; /*0x04 */
718 U8 ASCQ; /*0x05 */
719 U16 DevHandle; /*0x06 */
720 U32 Reserved2; /*0x08 */
721 U64 SASAddress; /*0x0C */
722 U8 LUN[8]; /*0x14 */
723 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
724 *PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
725 Mpi2EventDataSasDeviceStatusChange_t,
726 *pMpi2EventDataSasDeviceStatusChange_t;
728 /*SAS Device Status Change Event data ReasonCode values */
729 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
730 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
731 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
732 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
733 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
734 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
735 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
736 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
737 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
738 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
739 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
740 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11)
741 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12)
743 /*Integrated RAID Operation Status Event data */
745 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS {
746 U16 VolDevHandle; /*0x00 */
747 U16 Reserved1; /*0x02 */
748 U8 RAIDOperation; /*0x04 */
749 U8 PercentComplete; /*0x05 */
750 U16 Reserved2; /*0x06 */
751 U32 ElapsedSeconds; /*0x08 */
752 } MPI2_EVENT_DATA_IR_OPERATION_STATUS,
753 *PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
754 Mpi2EventDataIrOperationStatus_t,
755 *pMpi2EventDataIrOperationStatus_t;
757 /*Integrated RAID Operation Status Event data RAIDOperation values */
758 #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
759 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
760 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
761 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
762 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
764 /*Integrated RAID Volume Event data */
766 typedef struct _MPI2_EVENT_DATA_IR_VOLUME {
767 U16 VolDevHandle; /*0x00 */
768 U8 ReasonCode; /*0x02 */
769 U8 Reserved1; /*0x03 */
770 U32 NewValue; /*0x04 */
771 U32 PreviousValue; /*0x08 */
772 } MPI2_EVENT_DATA_IR_VOLUME, *PTR_MPI2_EVENT_DATA_IR_VOLUME,
773 Mpi2EventDataIrVolume_t, *pMpi2EventDataIrVolume_t;
775 /*Integrated RAID Volume Event data ReasonCode values */
776 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
777 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
778 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
780 /*Integrated RAID Physical Disk Event data */
782 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK {
783 U16 Reserved1; /*0x00 */
784 U8 ReasonCode; /*0x02 */
785 U8 PhysDiskNum; /*0x03 */
786 U16 PhysDiskDevHandle; /*0x04 */
787 U16 Reserved2; /*0x06 */
788 U16 Slot; /*0x08 */
789 U16 EnclosureHandle; /*0x0A */
790 U32 NewValue; /*0x0C */
791 U32 PreviousValue; /*0x10 */
792 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
793 *PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
794 Mpi2EventDataIrPhysicalDisk_t,
795 *pMpi2EventDataIrPhysicalDisk_t;
797 /*Integrated RAID Physical Disk Event data ReasonCode values */
798 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
799 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
800 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
802 /*Integrated RAID Configuration Change List Event data */
805 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
806 *one and check NumElements at runtime.
808 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
809 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1)
810 #endif
812 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT {
813 U16 ElementFlags; /*0x00 */
814 U16 VolDevHandle; /*0x02 */
815 U8 ReasonCode; /*0x04 */
816 U8 PhysDiskNum; /*0x05 */
817 U16 PhysDiskDevHandle; /*0x06 */
818 } MPI2_EVENT_IR_CONFIG_ELEMENT, *PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
819 Mpi2EventIrConfigElement_t, *pMpi2EventIrConfigElement_t;
821 /*IR Configuration Change List Event data ElementFlags values */
822 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
823 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
824 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
825 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
827 /*IR Configuration Change List Event data ReasonCode values */
828 #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
829 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
830 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
831 #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
832 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
833 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
834 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
835 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
836 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
838 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST {
839 U8 NumElements; /*0x00 */
840 U8 Reserved1; /*0x01 */
841 U8 Reserved2; /*0x02 */
842 U8 ConfigNum; /*0x03 */
843 U32 Flags; /*0x04 */
844 MPI2_EVENT_IR_CONFIG_ELEMENT
845 ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT];/*0x08 */
846 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
847 *PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
848 Mpi2EventDataIrConfigChangeList_t,
849 *pMpi2EventDataIrConfigChangeList_t;
851 /*IR Configuration Change List Event data Flags values */
852 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
854 /*SAS Discovery Event data */
856 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY {
857 U8 Flags; /*0x00 */
858 U8 ReasonCode; /*0x01 */
859 U8 PhysicalPort; /*0x02 */
860 U8 Reserved1; /*0x03 */
861 U32 DiscoveryStatus; /*0x04 */
862 } MPI2_EVENT_DATA_SAS_DISCOVERY,
863 *PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
864 Mpi2EventDataSasDiscovery_t, *pMpi2EventDataSasDiscovery_t;
866 /*SAS Discovery Event data Flags values */
867 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
868 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
870 /*SAS Discovery Event data ReasonCode values */
871 #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
872 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
874 /*SAS Discovery Event data DiscoveryStatus values */
875 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
876 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
877 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
878 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
879 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
880 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
881 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
882 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
883 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
884 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
885 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
886 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
887 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
888 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
889 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
890 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
891 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
892 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
893 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
894 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
896 /*SAS Broadcast Primitive Event data */
898 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE {
899 U8 PhyNum; /*0x00 */
900 U8 Port; /*0x01 */
901 U8 PortWidth; /*0x02 */
902 U8 Primitive; /*0x03 */
903 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
904 *PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
905 Mpi2EventDataSasBroadcastPrimitive_t,
906 *pMpi2EventDataSasBroadcastPrimitive_t;
908 /*defines for the Primitive field */
909 #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
910 #define MPI2_EVENT_PRIMITIVE_SES (0x02)
911 #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
912 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
913 #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
914 #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
915 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
916 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
918 /*SAS Notify Primitive Event data */
920 typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE {
921 U8 PhyNum; /*0x00 */
922 U8 Port; /*0x01 */
923 U8 Reserved1; /*0x02 */
924 U8 Primitive; /*0x03 */
925 } MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
926 *PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
927 Mpi2EventDataSasNotifyPrimitive_t,
928 *pMpi2EventDataSasNotifyPrimitive_t;
930 /*defines for the Primitive field */
931 #define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01)
932 #define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02)
933 #define MPI2_EVENT_NOTIFY_RESERVED1 (0x03)
934 #define MPI2_EVENT_NOTIFY_RESERVED2 (0x04)
936 /*SAS Initiator Device Status Change Event data */
938 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE {
939 U8 ReasonCode; /*0x00 */
940 U8 PhysicalPort; /*0x01 */
941 U16 DevHandle; /*0x02 */
942 U64 SASAddress; /*0x04 */
943 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
944 *PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
945 Mpi2EventDataSasInitDevStatusChange_t,
946 *pMpi2EventDataSasInitDevStatusChange_t;
948 /*SAS Initiator Device Status Change event ReasonCode values */
949 #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
950 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
952 /*SAS Initiator Device Table Overflow Event data */
954 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW {
955 U16 MaxInit; /*0x00 */
956 U16 CurrentInit; /*0x02 */
957 U64 SASAddress; /*0x04 */
958 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
959 *PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
960 Mpi2EventDataSasInitTableOverflow_t,
961 *pMpi2EventDataSasInitTableOverflow_t;
963 /*SAS Topology Change List Event data */
966 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
967 *one and check NumEntries at runtime.
969 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
970 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1)
971 #endif
973 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY {
974 U16 AttachedDevHandle; /*0x00 */
975 U8 LinkRate; /*0x02 */
976 U8 PhyStatus; /*0x03 */
977 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, *PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
978 Mpi2EventSasTopoPhyEntry_t, *pMpi2EventSasTopoPhyEntry_t;
980 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST {
981 U16 EnclosureHandle; /*0x00 */
982 U16 ExpanderDevHandle; /*0x02 */
983 U8 NumPhys; /*0x04 */
984 U8 Reserved1; /*0x05 */
985 U16 Reserved2; /*0x06 */
986 U8 NumEntries; /*0x08 */
987 U8 StartPhyNum; /*0x09 */
988 U8 ExpStatus; /*0x0A */
989 U8 PhysicalPort; /*0x0B */
990 MPI2_EVENT_SAS_TOPO_PHY_ENTRY
991 PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /*0x0C */
992 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
993 *PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
994 Mpi2EventDataSasTopologyChangeList_t,
995 *pMpi2EventDataSasTopologyChangeList_t;
997 /*values for the ExpStatus field */
998 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
999 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
1000 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
1001 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
1002 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
1004 /*defines for the LinkRate field */
1005 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
1006 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
1007 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
1008 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
1010 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
1011 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
1012 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
1013 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
1014 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
1015 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
1016 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06)
1017 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
1018 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
1019 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
1020 #define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B)
1021 #define MPI26_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0C)
1023 /*values for the PhyStatus field */
1024 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
1025 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
1026 /*values for the PhyStatus ReasonCode sub-field */
1027 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
1028 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
1029 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
1030 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
1031 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
1032 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
1034 /*SAS Enclosure Device Status Change Event data */
1036 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE {
1037 U16 EnclosureHandle; /*0x00 */
1038 U8 ReasonCode; /*0x02 */
1039 U8 PhysicalPort; /*0x03 */
1040 U64 EnclosureLogicalID; /*0x04 */
1041 U16 NumSlots; /*0x0C */
1042 U16 StartSlot; /*0x0E */
1043 U32 PhyBits; /*0x10 */
1044 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
1045 *PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
1046 Mpi2EventDataSasEnclDevStatusChange_t,
1047 *pMpi2EventDataSasEnclDevStatusChange_t,
1048 MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE,
1049 *PTR_MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE,
1050 Mpi26EventDataEnclDevStatusChange_t,
1051 *pMpi26EventDataEnclDevStatusChange_t;
1053 /*SAS Enclosure Device Status Change event ReasonCode values */
1054 #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
1055 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
1057 /*Enclosure Device Status Change event ReasonCode values */
1058 #define MPI26_EVENT_ENCL_RC_ADDED (0x01)
1059 #define MPI26_EVENT_ENCL_RC_NOT_RESPONDING (0x02)
1062 typedef struct _MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR {
1063 U16 DevHandle; /*0x00 */
1064 U8 ReasonCode; /*0x02 */
1065 U8 PhysicalPort; /*0x03 */
1066 U32 Reserved1[2]; /*0x04 */
1067 U64 SASAddress; /*0x0C */
1068 U32 Reserved2[2]; /*0x14 */
1069 } MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR,
1070 *PTR_MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR,
1071 Mpi25EventDataSasDeviceDiscoveryError_t,
1072 *pMpi25EventDataSasDeviceDiscoveryError_t;
1074 /*SAS Device Discovery Error Event data ReasonCode values */
1075 #define MPI25_EVENT_SAS_DISC_ERR_SMP_FAILED (0x01)
1076 #define MPI25_EVENT_SAS_DISC_ERR_SMP_TIMEOUT (0x02)
1078 /*SAS PHY Counter Event data */
1080 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
1081 U64 TimeStamp; /*0x00 */
1082 U32 Reserved1; /*0x08 */
1083 U8 PhyEventCode; /*0x0C */
1084 U8 PhyNum; /*0x0D */
1085 U16 Reserved2; /*0x0E */
1086 U32 PhyEventInfo; /*0x10 */
1087 U8 CounterType; /*0x14 */
1088 U8 ThresholdWindow; /*0x15 */
1089 U8 TimeUnits; /*0x16 */
1090 U8 Reserved3; /*0x17 */
1091 U32 EventThreshold; /*0x18 */
1092 U16 ThresholdFlags; /*0x1C */
1093 U16 Reserved4; /*0x1E */
1094 } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
1095 *PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
1096 Mpi2EventDataSasPhyCounter_t,
1097 *pMpi2EventDataSasPhyCounter_t;
1099 /*use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h
1100 *for the PhyEventCode field */
1102 /*use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h
1103 *for the CounterType field */
1105 /*use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h
1106 *for the TimeUnits field */
1108 /*use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h
1109 *for the ThresholdFlags field */
1111 /*SAS Quiesce Event data */
1113 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {
1114 U8 ReasonCode; /*0x00 */
1115 U8 Reserved1; /*0x01 */
1116 U16 Reserved2; /*0x02 */
1117 U32 Reserved3; /*0x04 */
1118 } MPI2_EVENT_DATA_SAS_QUIESCE,
1119 *PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
1120 Mpi2EventDataSasQuiesce_t, *pMpi2EventDataSasQuiesce_t;
1122 /*SAS Quiesce Event data ReasonCode values */
1123 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01)
1124 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02)
1126 /*Host Based Discovery Phy Event data */
1128 typedef struct _MPI2_EVENT_HBD_PHY_SAS {
1129 U8 Flags; /*0x00 */
1130 U8 NegotiatedLinkRate; /*0x01 */
1131 U8 PhyNum; /*0x02 */
1132 U8 PhysicalPort; /*0x03 */
1133 U32 Reserved1; /*0x04 */
1134 U8 InitialFrame[28]; /*0x08 */
1135 } MPI2_EVENT_HBD_PHY_SAS, *PTR_MPI2_EVENT_HBD_PHY_SAS,
1136 Mpi2EventHbdPhySas_t, *pMpi2EventHbdPhySas_t;
1138 /*values for the Flags field */
1139 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02)
1140 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01)
1142 /*use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h
1143 *for the NegotiatedLinkRate field */
1145 typedef union _MPI2_EVENT_HBD_DESCRIPTOR {
1146 MPI2_EVENT_HBD_PHY_SAS Sas;
1147 } MPI2_EVENT_HBD_DESCRIPTOR, *PTR_MPI2_EVENT_HBD_DESCRIPTOR,
1148 Mpi2EventHbdDescriptor_t, *pMpi2EventHbdDescriptor_t;
1150 typedef struct _MPI2_EVENT_DATA_HBD_PHY {
1151 U8 DescriptorType; /*0x00 */
1152 U8 Reserved1; /*0x01 */
1153 U16 Reserved2; /*0x02 */
1154 U32 Reserved3; /*0x04 */
1155 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /*0x08 */
1156 } MPI2_EVENT_DATA_HBD_PHY, *PTR_MPI2_EVENT_DATA_HBD_PHY,
1157 Mpi2EventDataHbdPhy_t,
1158 *pMpi2EventDataMpi2EventDataHbdPhy_t;
1160 /*values for the DescriptorType field */
1161 #define MPI2_EVENT_HBD_DT_SAS (0x01)
1164 /*PCIe Device Status Change Event data (MPI v2.6 and later) */
1166 typedef struct _MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE {
1167 U16 TaskTag; /*0x00 */
1168 U8 ReasonCode; /*0x02 */
1169 U8 PhysicalPort; /*0x03 */
1170 U8 ASC; /*0x04 */
1171 U8 ASCQ; /*0x05 */
1172 U16 DevHandle; /*0x06 */
1173 U32 Reserved2; /*0x08 */
1174 U64 WWID; /*0x0C */
1175 U8 LUN[8]; /*0x14 */
1176 } MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE,
1177 *PTR_MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE,
1178 Mpi26EventDataPCIeDeviceStatusChange_t,
1179 *pMpi26EventDataPCIeDeviceStatusChange_t;
1181 /*PCIe Device Status Change Event data ReasonCode values */
1182 #define MPI26_EVENT_PCIDEV_STAT_RC_SMART_DATA (0x05)
1183 #define MPI26_EVENT_PCIDEV_STAT_RC_UNSUPPORTED (0x07)
1184 #define MPI26_EVENT_PCIDEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
1185 #define MPI26_EVENT_PCIDEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
1186 #define MPI26_EVENT_PCIDEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
1187 #define MPI26_EVENT_PCIDEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
1188 #define MPI26_EVENT_PCIDEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
1189 #define MPI26_EVENT_PCIDEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
1190 #define MPI26_EVENT_PCIDEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
1191 #define MPI26_EVENT_PCIDEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
1192 #define MPI26_EVENT_PCIDEV_STAT_RC_DEV_INIT_FAILURE (0x10)
1193 #define MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED (0x11)
1196 /*PCIe Enumeration Event data (MPI v2.6 and later) */
1198 typedef struct _MPI26_EVENT_DATA_PCIE_ENUMERATION {
1199 U8 Flags; /*0x00 */
1200 U8 ReasonCode; /*0x01 */
1201 U8 PhysicalPort; /*0x02 */
1202 U8 Reserved1; /*0x03 */
1203 U32 EnumerationStatus; /*0x04 */
1204 } MPI26_EVENT_DATA_PCIE_ENUMERATION,
1205 *PTR_MPI26_EVENT_DATA_PCIE_ENUMERATION,
1206 Mpi26EventDataPCIeEnumeration_t,
1207 *pMpi26EventDataPCIeEnumeration_t;
1209 /*PCIe Enumeration Event data Flags values */
1210 #define MPI26_EVENT_PCIE_ENUM_DEVICE_CHANGE (0x02)
1211 #define MPI26_EVENT_PCIE_ENUM_IN_PROGRESS (0x01)
1213 /*PCIe Enumeration Event data ReasonCode values */
1214 #define MPI26_EVENT_PCIE_ENUM_RC_STARTED (0x01)
1215 #define MPI26_EVENT_PCIE_ENUM_RC_COMPLETED (0x02)
1217 /*PCIe Enumeration Event data EnumerationStatus values */
1218 #define MPI26_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000)
1219 #define MPI26_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000)
1220 #define MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000)
1223 /*PCIe Topology Change List Event data (MPI v2.6 and later) */
1226 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1227 *one and check NumEntries at runtime.
1229 #ifndef MPI26_EVENT_PCIE_TOPO_PORT_COUNT
1230 #define MPI26_EVENT_PCIE_TOPO_PORT_COUNT (1)
1231 #endif
1233 typedef struct _MPI26_EVENT_PCIE_TOPO_PORT_ENTRY {
1234 U16 AttachedDevHandle; /*0x00 */
1235 U8 PortStatus; /*0x02 */
1236 U8 Reserved1; /*0x03 */
1237 U8 CurrentPortInfo; /*0x04 */
1238 U8 Reserved2; /*0x05 */
1239 U8 PreviousPortInfo; /*0x06 */
1240 U8 Reserved3; /*0x07 */
1241 } MPI26_EVENT_PCIE_TOPO_PORT_ENTRY,
1242 *PTR_MPI26_EVENT_PCIE_TOPO_PORT_ENTRY,
1243 Mpi26EventPCIeTopoPortEntry_t,
1244 *pMpi26EventPCIeTopoPortEntry_t;
1246 /*PCIe Topology Change List Event data PortStatus values */
1247 #define MPI26_EVENT_PCIE_TOPO_PS_DEV_ADDED (0x01)
1248 #define MPI26_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02)
1249 #define MPI26_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03)
1250 #define MPI26_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04)
1251 #define MPI26_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05)
1253 /*PCIe Topology Change List Event data defines for CurrentPortInfo and
1254 *PreviousPortInfo
1256 #define MPI26_EVENT_PCIE_TOPO_PI_LANE_MASK (0xF0)
1257 #define MPI26_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00)
1258 #define MPI26_EVENT_PCIE_TOPO_PI_1_LANE (0x10)
1259 #define MPI26_EVENT_PCIE_TOPO_PI_2_LANES (0x20)
1260 #define MPI26_EVENT_PCIE_TOPO_PI_4_LANES (0x30)
1261 #define MPI26_EVENT_PCIE_TOPO_PI_8_LANES (0x40)
1262 #define MPI26_EVENT_PCIE_TOPO_PI_16_LANES (0x50)
1264 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0F)
1265 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00)
1266 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01)
1267 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02)
1268 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03)
1269 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04)
1270 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05)
1272 typedef struct _MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST {
1273 U16 EnclosureHandle; /*0x00 */
1274 U16 SwitchDevHandle; /*0x02 */
1275 U8 NumPorts; /*0x04 */
1276 U8 Reserved1; /*0x05 */
1277 U16 Reserved2; /*0x06 */
1278 U8 NumEntries; /*0x08 */
1279 U8 StartPortNum; /*0x09 */
1280 U8 SwitchStatus; /*0x0A */
1281 U8 PhysicalPort; /*0x0B */
1282 MPI26_EVENT_PCIE_TOPO_PORT_ENTRY
1283 PortEntry[MPI26_EVENT_PCIE_TOPO_PORT_COUNT]; /*0x0C */
1284 } MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST,
1285 *PTR_MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST,
1286 Mpi26EventDataPCIeTopologyChangeList_t,
1287 *pMpi26EventDataPCIeTopologyChangeList_t;
1289 /*PCIe Topology Change List Event data SwitchStatus values */
1290 #define MPI26_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00)
1291 #define MPI26_EVENT_PCIE_TOPO_SS_ADDED (0x01)
1292 #define MPI26_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02)
1293 #define MPI26_EVENT_PCIE_TOPO_SS_RESPONDING (0x03)
1294 #define MPI26_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04)
1296 /*PCIe Link Counter Event data (MPI v2.6 and later) */
1298 typedef struct _MPI26_EVENT_DATA_PCIE_LINK_COUNTER {
1299 U64 TimeStamp; /*0x00 */
1300 U32 Reserved1; /*0x08 */
1301 U8 LinkEventCode; /*0x0C */
1302 U8 LinkNum; /*0x0D */
1303 U16 Reserved2; /*0x0E */
1304 U32 LinkEventInfo; /*0x10 */
1305 U8 CounterType; /*0x14 */
1306 U8 ThresholdWindow; /*0x15 */
1307 U8 TimeUnits; /*0x16 */
1308 U8 Reserved3; /*0x17 */
1309 U32 EventThreshold; /*0x18 */
1310 U16 ThresholdFlags; /*0x1C */
1311 U16 Reserved4; /*0x1E */
1312 } MPI26_EVENT_DATA_PCIE_LINK_COUNTER,
1313 *PTR_MPI26_EVENT_DATA_PCIE_LINK_COUNTER,
1314 Mpi26EventDataPcieLinkCounter_t, *pMpi26EventDataPcieLinkCounter_t;
1317 /*use MPI26_PCIELINK3_EVTCODE_ values from mpi2_cnfg.h for the LinkEventCode
1318 *field
1321 /*use MPI26_PCIELINK3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType
1322 *field
1325 /*use MPI26_PCIELINK3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits
1326 *field
1329 /*use MPI26_PCIELINK3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags
1330 *field
1333 /****************************************************************************
1334 * EventAck message
1335 ****************************************************************************/
1337 /*EventAck Request message */
1338 typedef struct _MPI2_EVENT_ACK_REQUEST {
1339 U16 Reserved1; /*0x00 */
1340 U8 ChainOffset; /*0x02 */
1341 U8 Function; /*0x03 */
1342 U16 Reserved2; /*0x04 */
1343 U8 Reserved3; /*0x06 */
1344 U8 MsgFlags; /*0x07 */
1345 U8 VP_ID; /*0x08 */
1346 U8 VF_ID; /*0x09 */
1347 U16 Reserved4; /*0x0A */
1348 U16 Event; /*0x0C */
1349 U16 Reserved5; /*0x0E */
1350 U32 EventContext; /*0x10 */
1351 } MPI2_EVENT_ACK_REQUEST, *PTR_MPI2_EVENT_ACK_REQUEST,
1352 Mpi2EventAckRequest_t, *pMpi2EventAckRequest_t;
1354 /*EventAck Reply message */
1355 typedef struct _MPI2_EVENT_ACK_REPLY {
1356 U16 Reserved1; /*0x00 */
1357 U8 MsgLength; /*0x02 */
1358 U8 Function; /*0x03 */
1359 U16 Reserved2; /*0x04 */
1360 U8 Reserved3; /*0x06 */
1361 U8 MsgFlags; /*0x07 */
1362 U8 VP_ID; /*0x08 */
1363 U8 VF_ID; /*0x09 */
1364 U16 Reserved4; /*0x0A */
1365 U16 Reserved5; /*0x0C */
1366 U16 IOCStatus; /*0x0E */
1367 U32 IOCLogInfo; /*0x10 */
1368 } MPI2_EVENT_ACK_REPLY, *PTR_MPI2_EVENT_ACK_REPLY,
1369 Mpi2EventAckReply_t, *pMpi2EventAckReply_t;
1371 /****************************************************************************
1372 * SendHostMessage message
1373 ****************************************************************************/
1375 /*SendHostMessage Request message */
1376 typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST {
1377 U16 HostDataLength; /*0x00 */
1378 U8 ChainOffset; /*0x02 */
1379 U8 Function; /*0x03 */
1380 U16 Reserved1; /*0x04 */
1381 U8 Reserved2; /*0x06 */
1382 U8 MsgFlags; /*0x07 */
1383 U8 VP_ID; /*0x08 */
1384 U8 VF_ID; /*0x09 */
1385 U16 Reserved3; /*0x0A */
1386 U8 Reserved4; /*0x0C */
1387 U8 DestVF_ID; /*0x0D */
1388 U16 Reserved5; /*0x0E */
1389 U32 Reserved6; /*0x10 */
1390 U32 Reserved7; /*0x14 */
1391 U32 Reserved8; /*0x18 */
1392 U32 Reserved9; /*0x1C */
1393 U32 Reserved10; /*0x20 */
1394 U32 HostData[1]; /*0x24 */
1395 } MPI2_SEND_HOST_MESSAGE_REQUEST,
1396 *PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
1397 Mpi2SendHostMessageRequest_t,
1398 *pMpi2SendHostMessageRequest_t;
1400 /*SendHostMessage Reply message */
1401 typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY {
1402 U16 HostDataLength; /*0x00 */
1403 U8 MsgLength; /*0x02 */
1404 U8 Function; /*0x03 */
1405 U16 Reserved1; /*0x04 */
1406 U8 Reserved2; /*0x06 */
1407 U8 MsgFlags; /*0x07 */
1408 U8 VP_ID; /*0x08 */
1409 U8 VF_ID; /*0x09 */
1410 U16 Reserved3; /*0x0A */
1411 U16 Reserved4; /*0x0C */
1412 U16 IOCStatus; /*0x0E */
1413 U32 IOCLogInfo; /*0x10 */
1414 } MPI2_SEND_HOST_MESSAGE_REPLY, *PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
1415 Mpi2SendHostMessageReply_t, *pMpi2SendHostMessageReply_t;
1417 /****************************************************************************
1418 * FWDownload message
1419 ****************************************************************************/
1421 /*MPI v2.0 FWDownload Request message */
1422 typedef struct _MPI2_FW_DOWNLOAD_REQUEST {
1423 U8 ImageType; /*0x00 */
1424 U8 Reserved1; /*0x01 */
1425 U8 ChainOffset; /*0x02 */
1426 U8 Function; /*0x03 */
1427 U16 Reserved2; /*0x04 */
1428 U8 Reserved3; /*0x06 */
1429 U8 MsgFlags; /*0x07 */
1430 U8 VP_ID; /*0x08 */
1431 U8 VF_ID; /*0x09 */
1432 U16 Reserved4; /*0x0A */
1433 U32 TotalImageSize; /*0x0C */
1434 U32 Reserved5; /*0x10 */
1435 MPI2_MPI_SGE_UNION SGL; /*0x14 */
1436 } MPI2_FW_DOWNLOAD_REQUEST, *PTR_MPI2_FW_DOWNLOAD_REQUEST,
1437 Mpi2FWDownloadRequest, *pMpi2FWDownloadRequest;
1439 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
1441 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
1442 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
1443 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
1444 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
1445 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
1446 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
1447 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A)
1448 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1449 #define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY (0x0C)
1450 #define MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP (0x0D)
1451 #define MPI2_FW_DOWNLOAD_ITYPE_SBR (0x0E)
1452 #define MPI2_FW_DOWNLOAD_ITYPE_SBR_BACKUP (0x0F)
1453 #define MPI2_FW_DOWNLOAD_ITYPE_HIIM (0x10)
1454 #define MPI2_FW_DOWNLOAD_ITYPE_HIIA (0x11)
1455 #define MPI2_FW_DOWNLOAD_ITYPE_CTLR (0x12)
1456 #define MPI2_FW_DOWNLOAD_ITYPE_IMR_FIRMWARE (0x13)
1457 #define MPI2_FW_DOWNLOAD_ITYPE_MR_NVDATA (0x14)
1458 /*MPI v2.6 and newer */
1459 #define MPI2_FW_DOWNLOAD_ITYPE_CPLD (0x15)
1460 #define MPI2_FW_DOWNLOAD_ITYPE_PSOC (0x16)
1461 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1462 #define MPI2_FW_DOWNLOAD_ITYPE_TERMINATE (0xFF)
1464 /*MPI v2.0 FWDownload TransactionContext Element */
1465 typedef struct _MPI2_FW_DOWNLOAD_TCSGE {
1466 U8 Reserved1; /*0x00 */
1467 U8 ContextSize; /*0x01 */
1468 U8 DetailsLength; /*0x02 */
1469 U8 Flags; /*0x03 */
1470 U32 Reserved2; /*0x04 */
1471 U32 ImageOffset; /*0x08 */
1472 U32 ImageSize; /*0x0C */
1473 } MPI2_FW_DOWNLOAD_TCSGE, *PTR_MPI2_FW_DOWNLOAD_TCSGE,
1474 Mpi2FWDownloadTCSGE_t, *pMpi2FWDownloadTCSGE_t;
1476 /*MPI v2.5 FWDownload Request message */
1477 typedef struct _MPI25_FW_DOWNLOAD_REQUEST {
1478 U8 ImageType; /*0x00 */
1479 U8 Reserved1; /*0x01 */
1480 U8 ChainOffset; /*0x02 */
1481 U8 Function; /*0x03 */
1482 U16 Reserved2; /*0x04 */
1483 U8 Reserved3; /*0x06 */
1484 U8 MsgFlags; /*0x07 */
1485 U8 VP_ID; /*0x08 */
1486 U8 VF_ID; /*0x09 */
1487 U16 Reserved4; /*0x0A */
1488 U32 TotalImageSize; /*0x0C */
1489 U32 Reserved5; /*0x10 */
1490 U32 Reserved6; /*0x14 */
1491 U32 ImageOffset; /*0x18 */
1492 U32 ImageSize; /*0x1C */
1493 MPI25_SGE_IO_UNION SGL; /*0x20 */
1494 } MPI25_FW_DOWNLOAD_REQUEST, *PTR_MPI25_FW_DOWNLOAD_REQUEST,
1495 Mpi25FWDownloadRequest, *pMpi25FWDownloadRequest;
1497 /*FWDownload Reply message */
1498 typedef struct _MPI2_FW_DOWNLOAD_REPLY {
1499 U8 ImageType; /*0x00 */
1500 U8 Reserved1; /*0x01 */
1501 U8 MsgLength; /*0x02 */
1502 U8 Function; /*0x03 */
1503 U16 Reserved2; /*0x04 */
1504 U8 Reserved3; /*0x06 */
1505 U8 MsgFlags; /*0x07 */
1506 U8 VP_ID; /*0x08 */
1507 U8 VF_ID; /*0x09 */
1508 U16 Reserved4; /*0x0A */
1509 U16 Reserved5; /*0x0C */
1510 U16 IOCStatus; /*0x0E */
1511 U32 IOCLogInfo; /*0x10 */
1512 } MPI2_FW_DOWNLOAD_REPLY, *PTR_MPI2_FW_DOWNLOAD_REPLY,
1513 Mpi2FWDownloadReply_t, *pMpi2FWDownloadReply_t;
1515 /****************************************************************************
1516 * FWUpload message
1517 ****************************************************************************/
1519 /*MPI v2.0 FWUpload Request message */
1520 typedef struct _MPI2_FW_UPLOAD_REQUEST {
1521 U8 ImageType; /*0x00 */
1522 U8 Reserved1; /*0x01 */
1523 U8 ChainOffset; /*0x02 */
1524 U8 Function; /*0x03 */
1525 U16 Reserved2; /*0x04 */
1526 U8 Reserved3; /*0x06 */
1527 U8 MsgFlags; /*0x07 */
1528 U8 VP_ID; /*0x08 */
1529 U8 VF_ID; /*0x09 */
1530 U16 Reserved4; /*0x0A */
1531 U32 Reserved5; /*0x0C */
1532 U32 Reserved6; /*0x10 */
1533 MPI2_MPI_SGE_UNION SGL; /*0x14 */
1534 } MPI2_FW_UPLOAD_REQUEST, *PTR_MPI2_FW_UPLOAD_REQUEST,
1535 Mpi2FWUploadRequest_t, *pMpi2FWUploadRequest_t;
1537 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
1538 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1539 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1540 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1541 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1542 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1543 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1544 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1545 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1546 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1547 #define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP (0x0D)
1548 #define MPI2_FW_UPLOAD_ITYPE_SBR (0x0E)
1549 #define MPI2_FW_UPLOAD_ITYPE_SBR_BACKUP (0x0F)
1550 #define MPI2_FW_UPLOAD_ITYPE_HIIM (0x10)
1551 #define MPI2_FW_UPLOAD_ITYPE_HIIA (0x11)
1552 #define MPI2_FW_UPLOAD_ITYPE_CTLR (0x12)
1553 #define MPI2_FW_UPLOAD_ITYPE_IMR_FIRMWARE (0x13)
1554 #define MPI2_FW_UPLOAD_ITYPE_MR_NVDATA (0x14)
1557 /*MPI v2.0 FWUpload TransactionContext Element */
1558 typedef struct _MPI2_FW_UPLOAD_TCSGE {
1559 U8 Reserved1; /*0x00 */
1560 U8 ContextSize; /*0x01 */
1561 U8 DetailsLength; /*0x02 */
1562 U8 Flags; /*0x03 */
1563 U32 Reserved2; /*0x04 */
1564 U32 ImageOffset; /*0x08 */
1565 U32 ImageSize; /*0x0C */
1566 } MPI2_FW_UPLOAD_TCSGE, *PTR_MPI2_FW_UPLOAD_TCSGE,
1567 Mpi2FWUploadTCSGE_t, *pMpi2FWUploadTCSGE_t;
1569 /*MPI v2.5 FWUpload Request message */
1570 typedef struct _MPI25_FW_UPLOAD_REQUEST {
1571 U8 ImageType; /*0x00 */
1572 U8 Reserved1; /*0x01 */
1573 U8 ChainOffset; /*0x02 */
1574 U8 Function; /*0x03 */
1575 U16 Reserved2; /*0x04 */
1576 U8 Reserved3; /*0x06 */
1577 U8 MsgFlags; /*0x07 */
1578 U8 VP_ID; /*0x08 */
1579 U8 VF_ID; /*0x09 */
1580 U16 Reserved4; /*0x0A */
1581 U32 Reserved5; /*0x0C */
1582 U32 Reserved6; /*0x10 */
1583 U32 Reserved7; /*0x14 */
1584 U32 ImageOffset; /*0x18 */
1585 U32 ImageSize; /*0x1C */
1586 MPI25_SGE_IO_UNION SGL; /*0x20 */
1587 } MPI25_FW_UPLOAD_REQUEST, *PTR_MPI25_FW_UPLOAD_REQUEST,
1588 Mpi25FWUploadRequest_t, *pMpi25FWUploadRequest_t;
1590 /*FWUpload Reply message */
1591 typedef struct _MPI2_FW_UPLOAD_REPLY {
1592 U8 ImageType; /*0x00 */
1593 U8 Reserved1; /*0x01 */
1594 U8 MsgLength; /*0x02 */
1595 U8 Function; /*0x03 */
1596 U16 Reserved2; /*0x04 */
1597 U8 Reserved3; /*0x06 */
1598 U8 MsgFlags; /*0x07 */
1599 U8 VP_ID; /*0x08 */
1600 U8 VF_ID; /*0x09 */
1601 U16 Reserved4; /*0x0A */
1602 U16 Reserved5; /*0x0C */
1603 U16 IOCStatus; /*0x0E */
1604 U32 IOCLogInfo; /*0x10 */
1605 U32 ActualImageSize; /*0x14 */
1606 } MPI2_FW_UPLOAD_REPLY, *PTR_MPI2_FW_UPLOAD_REPLY,
1607 Mpi2FWUploadReply_t, *pMPi2FWUploadReply_t;
1610 /****************************************************************************
1611 * PowerManagementControl message
1612 ****************************************************************************/
1614 /*PowerManagementControl Request message */
1615 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {
1616 U8 Feature; /*0x00 */
1617 U8 Reserved1; /*0x01 */
1618 U8 ChainOffset; /*0x02 */
1619 U8 Function; /*0x03 */
1620 U16 Reserved2; /*0x04 */
1621 U8 Reserved3; /*0x06 */
1622 U8 MsgFlags; /*0x07 */
1623 U8 VP_ID; /*0x08 */
1624 U8 VF_ID; /*0x09 */
1625 U16 Reserved4; /*0x0A */
1626 U8 Parameter1; /*0x0C */
1627 U8 Parameter2; /*0x0D */
1628 U8 Parameter3; /*0x0E */
1629 U8 Parameter4; /*0x0F */
1630 U32 Reserved5; /*0x10 */
1631 U32 Reserved6; /*0x14 */
1632 } MPI2_PWR_MGMT_CONTROL_REQUEST, *PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1633 Mpi2PwrMgmtControlRequest_t, *pMpi2PwrMgmtControlRequest_t;
1635 /*defines for the Feature field */
1636 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01)
1637 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02)
1638 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /*obsolete */
1639 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04)
1640 #define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE (0x05)
1641 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80)
1642 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF)
1644 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1645 /*Parameter1 contains a PHY number */
1646 /*Parameter2 indicates power condition action using these defines */
1647 #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01)
1648 #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02)
1649 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03)
1650 /*Parameter3 and Parameter4 are reserved */
1652 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
1653 * Feature */
1654 /*Parameter1 contains SAS port width modulation group number */
1655 /*Parameter2 indicates IOC action using these defines */
1656 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01)
1657 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02)
1658 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03)
1659 /*Parameter3 indicates desired modulation level using these defines */
1660 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00)
1661 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01)
1662 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02)
1663 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03)
1664 /*Parameter4 is reserved */
1666 /*this next set (_PCIE_LINK) is obsolete */
1667 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1668 /*Parameter1 indicates desired PCIe link speed using these defines */
1669 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /*obsolete */
1670 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /*obsolete */
1671 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /*obsolete */
1672 /*Parameter2 indicates desired PCIe link width using these defines */
1673 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /*obsolete */
1674 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /*obsolete */
1675 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /*obsolete */
1676 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /*obsolete */
1677 /*Parameter3 and Parameter4 are reserved */
1679 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1680 /*Parameter1 indicates desired IOC hardware clock speed using these defines */
1681 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01)
1682 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02)
1683 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04)
1684 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08)
1685 /*Parameter2, Parameter3, and Parameter4 are reserved */
1687 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature*/
1688 /*Parameter1 indicates host action regarding global power management mode */
1689 #define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL (0x01)
1690 #define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE (0x02)
1691 #define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL (0x03)
1692 /*Parameter2 indicates the requested global power management mode */
1693 #define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF (0x01)
1694 #define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF (0x08)
1695 #define MPI2_PM_CONTROL_PARAM2_STANDBY (0x40)
1696 /*Parameter3 and Parameter4 are reserved */
1698 /*PowerManagementControl Reply message */
1699 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {
1700 U8 Feature; /*0x00 */
1701 U8 Reserved1; /*0x01 */
1702 U8 MsgLength; /*0x02 */
1703 U8 Function; /*0x03 */
1704 U16 Reserved2; /*0x04 */
1705 U8 Reserved3; /*0x06 */
1706 U8 MsgFlags; /*0x07 */
1707 U8 VP_ID; /*0x08 */
1708 U8 VF_ID; /*0x09 */
1709 U16 Reserved4; /*0x0A */
1710 U16 Reserved5; /*0x0C */
1711 U16 IOCStatus; /*0x0E */
1712 U32 IOCLogInfo; /*0x10 */
1713 } MPI2_PWR_MGMT_CONTROL_REPLY, *PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1714 Mpi2PwrMgmtControlReply_t, *pMpi2PwrMgmtControlReply_t;
1716 /****************************************************************************
1717 * IO Unit Control messages (MPI v2.6 and later only.)
1718 ****************************************************************************/
1720 /* IO Unit Control Request Message */
1721 typedef struct _MPI26_IOUNIT_CONTROL_REQUEST {
1722 U8 Operation; /* 0x00 */
1723 U8 Reserved1; /* 0x01 */
1724 U8 ChainOffset; /* 0x02 */
1725 U8 Function; /* 0x03 */
1726 U16 DevHandle; /* 0x04 */
1727 U8 IOCParameter; /* 0x06 */
1728 U8 MsgFlags; /* 0x07 */
1729 U8 VP_ID; /* 0x08 */
1730 U8 VF_ID; /* 0x09 */
1731 U16 Reserved3; /* 0x0A */
1732 U16 Reserved4; /* 0x0C */
1733 U8 PhyNum; /* 0x0E */
1734 U8 PrimFlags; /* 0x0F */
1735 U32 Primitive; /* 0x10 */
1736 U8 LookupMethod; /* 0x14 */
1737 U8 Reserved5; /* 0x15 */
1738 U16 SlotNumber; /* 0x16 */
1739 U64 LookupAddress; /* 0x18 */
1740 U32 IOCParameterValue; /* 0x20 */
1741 U32 Reserved7; /* 0x24 */
1742 U32 Reserved8; /* 0x28 */
1743 } MPI26_IOUNIT_CONTROL_REQUEST,
1744 *PTR_MPI26_IOUNIT_CONTROL_REQUEST,
1745 Mpi26IoUnitControlRequest_t,
1746 *pMpi26IoUnitControlRequest_t;
1748 /* values for the Operation field */
1749 #define MPI26_CTRL_OP_CLEAR_ALL_PERSISTENT (0x02)
1750 #define MPI26_CTRL_OP_SAS_PHY_LINK_RESET (0x06)
1751 #define MPI26_CTRL_OP_SAS_PHY_HARD_RESET (0x07)
1752 #define MPI26_CTRL_OP_PHY_CLEAR_ERROR_LOG (0x08)
1753 #define MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG (0x09)
1754 #define MPI26_CTRL_OP_SAS_SEND_PRIMITIVE (0x0A)
1755 #define MPI26_CTRL_OP_FORCE_FULL_DISCOVERY (0x0B)
1756 #define MPI26_CTRL_OP_REMOVE_DEVICE (0x0D)
1757 #define MPI26_CTRL_OP_LOOKUP_MAPPING (0x0E)
1758 #define MPI26_CTRL_OP_SET_IOC_PARAMETER (0x0F)
1759 #define MPI26_CTRL_OP_ENABLE_FP_DEVICE (0x10)
1760 #define MPI26_CTRL_OP_DISABLE_FP_DEVICE (0x11)
1761 #define MPI26_CTRL_OP_ENABLE_FP_ALL (0x12)
1762 #define MPI26_CTRL_OP_DISABLE_FP_ALL (0x13)
1763 #define MPI26_CTRL_OP_DEV_ENABLE_NCQ (0x14)
1764 #define MPI26_CTRL_OP_DEV_DISABLE_NCQ (0x15)
1765 #define MPI26_CTRL_OP_SHUTDOWN (0x16)
1766 #define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION (0x17)
1767 #define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION (0x18)
1768 #define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION (0x19)
1769 #define MPI26_CTRL_OP_ENABLE_NVME_SGL_FORMAT (0x1A)
1770 #define MPI26_CTRL_OP_DISABLE_NVME_SGL_FORMAT (0x1B)
1771 #define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN (0x80)
1773 /* values for the PrimFlags field */
1774 #define MPI26_CTRL_PRIMFLAGS_SINGLE (0x08)
1775 #define MPI26_CTRL_PRIMFLAGS_TRIPLE (0x02)
1776 #define MPI26_CTRL_PRIMFLAGS_REDUNDANT (0x01)
1778 /* values for the LookupMethod field */
1779 #define MPI26_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01)
1780 #define MPI26_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02)
1781 #define MPI26_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03)
1784 /* IO Unit Control Reply Message */
1785 typedef struct _MPI26_IOUNIT_CONTROL_REPLY {
1786 U8 Operation; /* 0x00 */
1787 U8 Reserved1; /* 0x01 */
1788 U8 MsgLength; /* 0x02 */
1789 U8 Function; /* 0x03 */
1790 U16 DevHandle; /* 0x04 */
1791 U8 IOCParameter; /* 0x06 */
1792 U8 MsgFlags; /* 0x07 */
1793 U8 VP_ID; /* 0x08 */
1794 U8 VF_ID; /* 0x09 */
1795 U16 Reserved3; /* 0x0A */
1796 U16 Reserved4; /* 0x0C */
1797 U16 IOCStatus; /* 0x0E */
1798 U32 IOCLogInfo; /* 0x10 */
1799 } MPI26_IOUNIT_CONTROL_REPLY,
1800 *PTR_MPI26_IOUNIT_CONTROL_REPLY,
1801 Mpi26IoUnitControlReply_t,
1802 *pMpi26IoUnitControlReply_t;
1805 #endif