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mic: vop: Fix use-after-free on remove
[linux/fpc-iii.git] / drivers / scsi / smartpqi / smartpqi.h
blobaf962368818be6e88a9b284bc8002d8b8f4ffa36
1 /*
2 * driver for Microsemi PQI-based storage controllers
3 * Copyright (c) 2016-2017 Microsemi Corporation
4 * Copyright (c) 2016 PMC-Sierra, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
15 * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
16 *
17 */
18
19 #include <linux/io-64-nonatomic-lo-hi.h>
20
21 #if !defined(_SMARTPQI_H)
22 #define _SMARTPQI_H
23
24 #include <scsi/scsi_host.h>
25 #include <linux/bsg-lib.h>
26
27 #pragma pack(1)
28
29 #define PQI_DEVICE_SIGNATURE "PQI DREG"
30
31 /* This structure is defined by the PQI specification. */
32 struct pqi_device_registers {
33 __le64 signature;
34 u8 function_and_status_code;
35 u8 reserved[7];
36 u8 max_admin_iq_elements;
37 u8 max_admin_oq_elements;
38 u8 admin_iq_element_length; /* in 16-byte units */
39 u8 admin_oq_element_length; /* in 16-byte units */
40 __le16 max_reset_timeout; /* in 100-millisecond units */
41 u8 reserved1[2];
42 __le32 legacy_intx_status;
43 __le32 legacy_intx_mask_set;
44 __le32 legacy_intx_mask_clear;
45 u8 reserved2[28];
46 __le32 device_status;
47 u8 reserved3[4];
48 __le64 admin_iq_pi_offset;
49 __le64 admin_oq_ci_offset;
50 __le64 admin_iq_element_array_addr;
51 __le64 admin_oq_element_array_addr;
52 __le64 admin_iq_ci_addr;
53 __le64 admin_oq_pi_addr;
54 u8 admin_iq_num_elements;
55 u8 admin_oq_num_elements;
56 __le16 admin_queue_int_msg_num;
57 u8 reserved4[4];
58 __le32 device_error;
59 u8 reserved5[4];
60 __le64 error_details;
61 __le32 device_reset;
62 __le32 power_action;
63 u8 reserved6[104];
64 };
65
66 /*
67 * controller registers
68 *
69 * These are defined by the Microsemi implementation.
70 *
71 * Some registers (those named sis_*) are only used when in
72 * legacy SIS mode before we transition the controller into
73 * PQI mode. There are a number of other SIS mode registers,
74 * but we don't use them, so only the SIS registers that we
75 * care about are defined here. The offsets mentioned in the
76 * comments are the offsets from the PCIe BAR 0.
77 */
78 struct pqi_ctrl_registers {
79 u8 reserved[0x20];
80 __le32 sis_host_to_ctrl_doorbell; /* 20h */
81 u8 reserved1[0x34 - (0x20 + sizeof(__le32))];
82 __le32 sis_interrupt_mask; /* 34h */
83 u8 reserved2[0x9c - (0x34 + sizeof(__le32))];
84 __le32 sis_ctrl_to_host_doorbell; /* 9Ch */
85 u8 reserved3[0xa0 - (0x9c + sizeof(__le32))];
86 __le32 sis_ctrl_to_host_doorbell_clear; /* A0h */
87 u8 reserved4[0xb0 - (0xa0 + sizeof(__le32))];
88 __le32 sis_driver_scratch; /* B0h */
89 u8 reserved5[0xbc - (0xb0 + sizeof(__le32))];
90 __le32 sis_firmware_status; /* BCh */
91 u8 reserved6[0x1000 - (0xbc + sizeof(__le32))];
92 __le32 sis_mailbox[8]; /* 1000h */
93 u8 reserved7[0x4000 - (0x1000 + (sizeof(__le32) * 8))];
94 /*
95 * The PQI spec states that the PQI registers should be at
96 * offset 0 from the PCIe BAR 0. However, we can't map
97 * them at offset 0 because that would break compatibility
98 * with the SIS registers. So we map them at offset 4000h.
99 */
100 struct pqi_device_registers pqi_registers; /* 4000h */
101 };
102
103 #if ((HZ) < 1000)
104 #define PQI_HZ 1000
105 #else
106 #define PQI_HZ (HZ)
107 #endif
108
109 #define PQI_DEVICE_REGISTERS_OFFSET 0x4000
110
111 enum pqi_io_path {
112 RAID_PATH = 0,
113 AIO_PATH = 1
114 };
115
116 enum pqi_irq_mode {
117 IRQ_MODE_NONE,
118 IRQ_MODE_INTX,
119 IRQ_MODE_MSIX
120 };
121
122 struct pqi_sg_descriptor {
123 __le64 address;
124 __le32 length;
125 __le32 flags;
126 };
127
128 /* manifest constants for the flags field of pqi_sg_descriptor */
129 #define CISS_SG_LAST 0x40000000
130 #define CISS_SG_CHAIN 0x80000000
131
132 struct pqi_iu_header {
133 u8 iu_type;
134 u8 reserved;
135 __le16 iu_length; /* in bytes - does not include the length */
136 /* of this header */
137 __le16 response_queue_id; /* specifies the OQ where the */
138 /* response IU is to be delivered */
139 u8 work_area[2]; /* reserved for driver use */
140 };
141
142 /*
143 * According to the PQI spec, the IU header is only the first 4 bytes of our
144 * pqi_iu_header structure.
145 */
146 #define PQI_REQUEST_HEADER_LENGTH 4
147
148 struct pqi_general_admin_request {
149 struct pqi_iu_header header;
150 __le16 request_id;
151 u8 function_code;
152 union {
153 struct {
154 u8 reserved[33];
155 __le32 buffer_length;
156 struct pqi_sg_descriptor sg_descriptor;
157 } report_device_capability;
158
159 struct {
160 u8 reserved;
161 __le16 queue_id;
162 u8 reserved1[2];
163 __le64 element_array_addr;
164 __le64 ci_addr;
165 __le16 num_elements;
166 __le16 element_length;
167 u8 queue_protocol;
168 u8 reserved2[23];
169 __le32 vendor_specific;
170 } create_operational_iq;
171
172 struct {
173 u8 reserved;
174 __le16 queue_id;
175 u8 reserved1[2];
176 __le64 element_array_addr;
177 __le64 pi_addr;
178 __le16 num_elements;
179 __le16 element_length;
180 u8 queue_protocol;
181 u8 reserved2[3];
182 __le16 int_msg_num;
183 __le16 coalescing_count;
184 __le32 min_coalescing_time;
185 __le32 max_coalescing_time;
186 u8 reserved3[8];
187 __le32 vendor_specific;
188 } create_operational_oq;
189
190 struct {
191 u8 reserved;
192 __le16 queue_id;
193 u8 reserved1[50];
194 } delete_operational_queue;
195
196 struct {
197 u8 reserved;
198 __le16 queue_id;
199 u8 reserved1[46];
200 __le32 vendor_specific;
201 } change_operational_iq_properties;
202
203 } data;
204 };
205
206 struct pqi_general_admin_response {
207 struct pqi_iu_header header;
208 __le16 request_id;
209 u8 function_code;
210 u8 status;
211 union {
212 struct {
213 u8 status_descriptor[4];
214 __le64 iq_pi_offset;
215 u8 reserved[40];
216 } create_operational_iq;
217
218 struct {
219 u8 status_descriptor[4];
220 __le64 oq_ci_offset;
221 u8 reserved[40];
222 } create_operational_oq;
223 } data;
224 };
225
226 struct pqi_iu_layer_descriptor {
227 u8 inbound_spanning_supported : 1;
228 u8 reserved : 7;
229 u8 reserved1[5];
230 __le16 max_inbound_iu_length;
231 u8 outbound_spanning_supported : 1;
232 u8 reserved2 : 7;
233 u8 reserved3[5];
234 __le16 max_outbound_iu_length;
235 };
236
237 struct pqi_device_capability {
238 __le16 data_length;
239 u8 reserved[6];
240 u8 iq_arbitration_priority_support_bitmask;
241 u8 maximum_aw_a;
242 u8 maximum_aw_b;
243 u8 maximum_aw_c;
244 u8 max_arbitration_burst : 3;
245 u8 reserved1 : 4;
246 u8 iqa : 1;
247 u8 reserved2[2];
248 u8 iq_freeze : 1;
249 u8 reserved3 : 7;
250 __le16 max_inbound_queues;
251 __le16 max_elements_per_iq;
252 u8 reserved4[4];
253 __le16 max_iq_element_length;
254 __le16 min_iq_element_length;
255 u8 reserved5[2];
256 __le16 max_outbound_queues;
257 __le16 max_elements_per_oq;
258 __le16 intr_coalescing_time_granularity;
259 __le16 max_oq_element_length;
260 __le16 min_oq_element_length;
261 u8 reserved6[24];
262 struct pqi_iu_layer_descriptor iu_layer_descriptors[32];
263 };
264
265 #define PQI_MAX_EMBEDDED_SG_DESCRIPTORS 4
266
267 struct pqi_raid_path_request {
268 struct pqi_iu_header header;
269 __le16 request_id;
270 __le16 nexus_id;
271 __le32 buffer_length;
272 u8 lun_number[8];
273 __le16 protocol_specific;
274 u8 data_direction : 2;
275 u8 partial : 1;
276 u8 reserved1 : 4;
277 u8 fence : 1;
278 __le16 error_index;
279 u8 reserved2;
280 u8 task_attribute : 3;
281 u8 command_priority : 4;
282 u8 reserved3 : 1;
283 u8 reserved4 : 2;
284 u8 additional_cdb_bytes_usage : 3;
285 u8 reserved5 : 3;
286 u8 cdb[32];
287 struct pqi_sg_descriptor
288 sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS];
289 };
290
291 struct pqi_aio_path_request {
292 struct pqi_iu_header header;
293 __le16 request_id;
294 u8 reserved1[2];
295 __le32 nexus_id;
296 __le32 buffer_length;
297 u8 data_direction : 2;
298 u8 partial : 1;
299 u8 memory_type : 1;
300 u8 fence : 1;
301 u8 encryption_enable : 1;
302 u8 reserved2 : 2;
303 u8 task_attribute : 3;
304 u8 command_priority : 4;
305 u8 reserved3 : 1;
306 __le16 data_encryption_key_index;
307 __le32 encrypt_tweak_lower;
308 __le32 encrypt_tweak_upper;
309 u8 cdb[16];
310 __le16 error_index;
311 u8 num_sg_descriptors;
312 u8 cdb_length;
313 u8 lun_number[8];
314 u8 reserved4[4];
315 struct pqi_sg_descriptor
316 sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS];
317 };
318
319 struct pqi_io_response {
320 struct pqi_iu_header header;
321 __le16 request_id;
322 __le16 error_index;
323 u8 reserved2[4];
324 };
325
326 struct pqi_general_management_request {
327 struct pqi_iu_header header;
328 __le16 request_id;
329 union {
330 struct {
331 u8 reserved[2];
332 __le32 buffer_length;
333 struct pqi_sg_descriptor sg_descriptors[3];
334 } report_event_configuration;
335
336 struct {
337 __le16 global_event_oq_id;
338 __le32 buffer_length;
339 struct pqi_sg_descriptor sg_descriptors[3];
340 } set_event_configuration;
341 } data;
342 };
343
344 struct pqi_event_descriptor {
345 u8 event_type;
346 u8 reserved;
347 __le16 oq_id;
348 };
349
350 struct pqi_event_config {
351 u8 reserved[2];
352 u8 num_event_descriptors;
353 u8 reserved1;
354 struct pqi_event_descriptor descriptors[1];
355 };
356
357 #define PQI_MAX_EVENT_DESCRIPTORS 255
358
359 #define PQI_EVENT_OFA_MEMORY_ALLOCATION 0x0
360 #define PQI_EVENT_OFA_QUIESCE 0x1
361 #define PQI_EVENT_OFA_CANCELLED 0x2
362
363 struct pqi_event_response {
364 struct pqi_iu_header header;
365 u8 event_type;
366 u8 reserved2 : 7;
367 u8 request_acknowlege : 1;
368 __le16 event_id;
369 __le32 additional_event_id;
370 union {
371 struct {
372 __le32 bytes_requested;
373 u8 reserved[12];
374 } ofa_memory_allocation;
375
376 struct {
377 __le16 reason; /* reason for cancellation */
378 u8 reserved[14];
379 } ofa_cancelled;
380 } data;
381 };
382
383 struct pqi_event_acknowledge_request {
384 struct pqi_iu_header header;
385 u8 event_type;
386 u8 reserved2;
387 __le16 event_id;
388 __le32 additional_event_id;
389 };
390
391 struct pqi_task_management_request {
392 struct pqi_iu_header header;
393 __le16 request_id;
394 __le16 nexus_id;
395 u8 reserved[4];
396 u8 lun_number[8];
397 __le16 protocol_specific;
398 __le16 outbound_queue_id_to_manage;
399 __le16 request_id_to_manage;
400 u8 task_management_function;
401 u8 reserved2 : 7;
402 u8 fence : 1;
403 };
404
405 #define SOP_TASK_MANAGEMENT_LUN_RESET 0x8
406
407 struct pqi_task_management_response {
408 struct pqi_iu_header header;
409 __le16 request_id;
410 __le16 nexus_id;
411 u8 additional_response_info[3];
412 u8 response_code;
413 };
414
415 struct pqi_vendor_general_request {
416 struct pqi_iu_header header;
417 __le16 request_id;
418 __le16 function_code;
419 union {
420 struct {
421 __le16 first_section;
422 __le16 last_section;
423 u8 reserved[48];
424 } config_table_update;
425
426 struct {
427 __le64 buffer_address;
428 __le32 buffer_length;
429 u8 reserved[40];
430 } ofa_memory_allocation;
431 } data;
432 };
433
434 struct pqi_vendor_general_response {
435 struct pqi_iu_header header;
436 __le16 request_id;
437 __le16 function_code;
438 __le16 status;
439 u8 reserved[2];
440 };
441
442 #define PQI_VENDOR_GENERAL_CONFIG_TABLE_UPDATE 0
443 #define PQI_VENDOR_GENERAL_HOST_MEMORY_UPDATE 1
444
445 #define PQI_OFA_VERSION 1
446 #define PQI_OFA_SIGNATURE "OFA_QRM"
447 #define PQI_OFA_MAX_SG_DESCRIPTORS 64
448
449 #define PQI_OFA_MEMORY_DESCRIPTOR_LENGTH \
450 (offsetof(struct pqi_ofa_memory, sg_descriptor) + \
451 (PQI_OFA_MAX_SG_DESCRIPTORS * sizeof(struct pqi_sg_descriptor)))
452
453 struct pqi_ofa_memory {
454 __le64 signature; /* "OFA_QRM" */
455 __le16 version; /* version of this struct(1 = 1st version) */
456 u8 reserved[62];
457 __le32 bytes_allocated; /* total allocated memory in bytes */
458 __le16 num_memory_descriptors;
459 u8 reserved1[2];
460 struct pqi_sg_descriptor sg_descriptor[1];
461 };
462
463 struct pqi_aio_error_info {
464 u8 status;
465 u8 service_response;
466 u8 data_present;
467 u8 reserved;
468 __le32 residual_count;
469 __le16 data_length;
470 __le16 reserved1;
471 u8 data[256];
472 };
473
474 struct pqi_raid_error_info {
475 u8 data_in_result;
476 u8 data_out_result;
477 u8 reserved[3];
478 u8 status;
479 __le16 status_qualifier;
480 __le16 sense_data_length;
481 __le16 response_data_length;
482 __le32 data_in_transferred;
483 __le32 data_out_transferred;
484 u8 data[256];
485 };
486
487 #define PQI_REQUEST_IU_TASK_MANAGEMENT 0x13
488 #define PQI_REQUEST_IU_RAID_PATH_IO 0x14
489 #define PQI_REQUEST_IU_AIO_PATH_IO 0x15
490 #define PQI_REQUEST_IU_GENERAL_ADMIN 0x60
491 #define PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG 0x72
492 #define PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG 0x73
493 #define PQI_REQUEST_IU_VENDOR_GENERAL 0x75
494 #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6
495
496 #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81
497 #define PQI_RESPONSE_IU_TASK_MANAGEMENT 0x93
498 #define PQI_RESPONSE_IU_GENERAL_ADMIN 0xe0
499 #define PQI_RESPONSE_IU_RAID_PATH_IO_SUCCESS 0xf0
500 #define PQI_RESPONSE_IU_AIO_PATH_IO_SUCCESS 0xf1
501 #define PQI_RESPONSE_IU_RAID_PATH_IO_ERROR 0xf2
502 #define PQI_RESPONSE_IU_AIO_PATH_IO_ERROR 0xf3
503 #define PQI_RESPONSE_IU_AIO_PATH_DISABLED 0xf4
504 #define PQI_RESPONSE_IU_VENDOR_EVENT 0xf5
505 #define PQI_RESPONSE_IU_VENDOR_GENERAL 0xf7
506
507 #define PQI_GENERAL_ADMIN_FUNCTION_REPORT_DEVICE_CAPABILITY 0x0
508 #define PQI_GENERAL_ADMIN_FUNCTION_CREATE_IQ 0x10
509 #define PQI_GENERAL_ADMIN_FUNCTION_CREATE_OQ 0x11
510 #define PQI_GENERAL_ADMIN_FUNCTION_DELETE_IQ 0x12
511 #define PQI_GENERAL_ADMIN_FUNCTION_DELETE_OQ 0x13
512 #define PQI_GENERAL_ADMIN_FUNCTION_CHANGE_IQ_PROPERTY 0x14
513
514 #define PQI_GENERAL_ADMIN_STATUS_SUCCESS 0x0
515
516 #define PQI_IQ_PROPERTY_IS_AIO_QUEUE 0x1
517
518 #define PQI_GENERAL_ADMIN_IU_LENGTH 0x3c
519 #define PQI_PROTOCOL_SOP 0x0
520
521 #define PQI_DATA_IN_OUT_GOOD 0x0
522 #define PQI_DATA_IN_OUT_UNDERFLOW 0x1
523 #define PQI_DATA_IN_OUT_BUFFER_ERROR 0x40
524 #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW 0x41
525 #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW_DESCRIPTOR_AREA 0x42
526 #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW_BRIDGE 0x43
527 #define PQI_DATA_IN_OUT_PCIE_FABRIC_ERROR 0x60
528 #define PQI_DATA_IN_OUT_PCIE_COMPLETION_TIMEOUT 0x61
529 #define PQI_DATA_IN_OUT_PCIE_COMPLETER_ABORT_RECEIVED 0x62
530 #define PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST_RECEIVED 0x63
531 #define PQI_DATA_IN_OUT_PCIE_ECRC_CHECK_FAILED 0x64
532 #define PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST 0x65
533 #define PQI_DATA_IN_OUT_PCIE_ACS_VIOLATION 0x66
534 #define PQI_DATA_IN_OUT_PCIE_TLP_PREFIX_BLOCKED 0x67
535 #define PQI_DATA_IN_OUT_PCIE_POISONED_MEMORY_READ 0x6F
536 #define PQI_DATA_IN_OUT_ERROR 0xf0
537 #define PQI_DATA_IN_OUT_PROTOCOL_ERROR 0xf1
538 #define PQI_DATA_IN_OUT_HARDWARE_ERROR 0xf2
539 #define PQI_DATA_IN_OUT_UNSOLICITED_ABORT 0xf3
540 #define PQI_DATA_IN_OUT_ABORTED 0xf4
541 #define PQI_DATA_IN_OUT_TIMEOUT 0xf5
542
543 #define CISS_CMD_STATUS_SUCCESS 0x0
544 #define CISS_CMD_STATUS_TARGET_STATUS 0x1
545 #define CISS_CMD_STATUS_DATA_UNDERRUN 0x2
546 #define CISS_CMD_STATUS_DATA_OVERRUN 0x3
547 #define CISS_CMD_STATUS_INVALID 0x4
548 #define CISS_CMD_STATUS_PROTOCOL_ERROR 0x5
549 #define CISS_CMD_STATUS_HARDWARE_ERROR 0x6
550 #define CISS_CMD_STATUS_CONNECTION_LOST 0x7
551 #define CISS_CMD_STATUS_ABORTED 0x8
552 #define CISS_CMD_STATUS_ABORT_FAILED 0x9
553 #define CISS_CMD_STATUS_UNSOLICITED_ABORT 0xa
554 #define CISS_CMD_STATUS_TIMEOUT 0xb
555 #define CISS_CMD_STATUS_UNABORTABLE 0xc
556 #define CISS_CMD_STATUS_TMF 0xd
557 #define CISS_CMD_STATUS_AIO_DISABLED 0xe
558
559 #define PQI_CMD_STATUS_ABORTED CISS_CMD_STATUS_ABORTED
560
561 #define PQI_NUM_EVENT_QUEUE_ELEMENTS 32
562 #define PQI_EVENT_OQ_ELEMENT_LENGTH sizeof(struct pqi_event_response)
563
564 #define PQI_EVENT_TYPE_HOTPLUG 0x1
565 #define PQI_EVENT_TYPE_HARDWARE 0x2
566 #define PQI_EVENT_TYPE_PHYSICAL_DEVICE 0x4
567 #define PQI_EVENT_TYPE_LOGICAL_DEVICE 0x5
568 #define PQI_EVENT_TYPE_OFA 0xfb
569 #define PQI_EVENT_TYPE_AIO_STATE_CHANGE 0xfd
570 #define PQI_EVENT_TYPE_AIO_CONFIG_CHANGE 0xfe
571
572 #pragma pack()
573
574 #define PQI_ERROR_BUFFER_ELEMENT_LENGTH \
575 sizeof(struct pqi_raid_error_info)
576
577 /* these values are based on our implementation */
578 #define PQI_ADMIN_IQ_NUM_ELEMENTS 8
579 #define PQI_ADMIN_OQ_NUM_ELEMENTS 20
580 #define PQI_ADMIN_IQ_ELEMENT_LENGTH 64
581 #define PQI_ADMIN_OQ_ELEMENT_LENGTH 64
582
583 #define PQI_OPERATIONAL_IQ_ELEMENT_LENGTH 128
584 #define PQI_OPERATIONAL_OQ_ELEMENT_LENGTH 16
585
586 #define PQI_MIN_MSIX_VECTORS 1
587 #define PQI_MAX_MSIX_VECTORS 64
588
589 /* these values are defined by the PQI spec */
590 #define PQI_MAX_NUM_ELEMENTS_ADMIN_QUEUE 255
591 #define PQI_MAX_NUM_ELEMENTS_OPERATIONAL_QUEUE 65535
592 #define PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT 64
593 #define PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT 16
594 #define PQI_ADMIN_INDEX_ALIGNMENT 64
595 #define PQI_OPERATIONAL_INDEX_ALIGNMENT 4
596
597 #define PQI_MIN_OPERATIONAL_QUEUE_ID 1
598 #define PQI_MAX_OPERATIONAL_QUEUE_ID 65535
599
600 #define PQI_AIO_SERV_RESPONSE_COMPLETE 0
601 #define PQI_AIO_SERV_RESPONSE_FAILURE 1
602 #define PQI_AIO_SERV_RESPONSE_TMF_COMPLETE 2
603 #define PQI_AIO_SERV_RESPONSE_TMF_SUCCEEDED 3
604 #define PQI_AIO_SERV_RESPONSE_TMF_REJECTED 4
605 #define PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN 5
606
607 #define PQI_AIO_STATUS_IO_ERROR 0x1
608 #define PQI_AIO_STATUS_IO_ABORTED 0x2
609 #define PQI_AIO_STATUS_NO_PATH_TO_DEVICE 0x3
610 #define PQI_AIO_STATUS_INVALID_DEVICE 0x4
611 #define PQI_AIO_STATUS_AIO_PATH_DISABLED 0xe
612 #define PQI_AIO_STATUS_UNDERRUN 0x51
613 #define PQI_AIO_STATUS_OVERRUN 0x75
614
615 typedef u32 pqi_index_t;
616
617 /* SOP data direction flags */
618 #define SOP_NO_DIRECTION_FLAG 0
619 #define SOP_WRITE_FLAG 1 /* host writes data to Data-Out */
620 /* buffer */
621 #define SOP_READ_FLAG 2 /* host receives data from Data-In */
622 /* buffer */
623 #define SOP_BIDIRECTIONAL 3 /* data is transferred from the */
624 /* Data-Out buffer and data is */
625 /* transferred to the Data-In buffer */
626
627 #define SOP_TASK_ATTRIBUTE_SIMPLE 0
628 #define SOP_TASK_ATTRIBUTE_HEAD_OF_QUEUE 1
629 #define SOP_TASK_ATTRIBUTE_ORDERED 2
630 #define SOP_TASK_ATTRIBUTE_ACA 4
631
632 #define SOP_TMF_COMPLETE 0x0
633 #define SOP_TMF_REJECTED 0x4
634 #define SOP_TMF_FUNCTION_SUCCEEDED 0x8
635
636 /* additional CDB bytes usage field codes */
637 #define SOP_ADDITIONAL_CDB_BYTES_0 0 /* 16-byte CDB */
638 #define SOP_ADDITIONAL_CDB_BYTES_4 1 /* 20-byte CDB */
639 #define SOP_ADDITIONAL_CDB_BYTES_8 2 /* 24-byte CDB */
640 #define SOP_ADDITIONAL_CDB_BYTES_12 3 /* 28-byte CDB */
641 #define SOP_ADDITIONAL_CDB_BYTES_16 4 /* 32-byte CDB */
642
643 /*
644 * The purpose of this structure is to obtain proper alignment of objects in
645 * an admin queue pair.
646 */
647 struct pqi_admin_queues_aligned {
648 __aligned(PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT)
649 u8 iq_element_array[PQI_ADMIN_IQ_ELEMENT_LENGTH]
650 [PQI_ADMIN_IQ_NUM_ELEMENTS];
651 __aligned(PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT)
652 u8 oq_element_array[PQI_ADMIN_OQ_ELEMENT_LENGTH]
653 [PQI_ADMIN_OQ_NUM_ELEMENTS];
654 __aligned(PQI_ADMIN_INDEX_ALIGNMENT) pqi_index_t iq_ci;
655 __aligned(PQI_ADMIN_INDEX_ALIGNMENT) pqi_index_t oq_pi;
656 };
657
658 struct pqi_admin_queues {
659 void *iq_element_array;
660 void *oq_element_array;
661 pqi_index_t *iq_ci;
662 pqi_index_t __iomem *oq_pi;
663 dma_addr_t iq_element_array_bus_addr;
664 dma_addr_t oq_element_array_bus_addr;
665 dma_addr_t iq_ci_bus_addr;
666 dma_addr_t oq_pi_bus_addr;
667 __le32 __iomem *iq_pi;
668 pqi_index_t iq_pi_copy;
669 __le32 __iomem *oq_ci;
670 pqi_index_t oq_ci_copy;
671 struct task_struct *task;
672 u16 int_msg_num;
673 };
674
675 struct pqi_queue_group {
676 struct pqi_ctrl_info *ctrl_info; /* backpointer */
677 u16 iq_id[2];
678 u16 oq_id;
679 u16 int_msg_num;
680 void *iq_element_array[2];
681 void *oq_element_array;
682 dma_addr_t iq_element_array_bus_addr[2];
683 dma_addr_t oq_element_array_bus_addr;
684 __le32 __iomem *iq_pi[2];
685 pqi_index_t iq_pi_copy[2];
686 pqi_index_t __iomem *iq_ci[2];
687 pqi_index_t __iomem *oq_pi;
688 dma_addr_t iq_ci_bus_addr[2];
689 dma_addr_t oq_pi_bus_addr;
690 __le32 __iomem *oq_ci;
691 pqi_index_t oq_ci_copy;
692 spinlock_t submit_lock[2]; /* protect submission queue */
693 struct list_head request_list[2];
694 };
695
696 struct pqi_event_queue {
697 u16 oq_id;
698 u16 int_msg_num;
699 void *oq_element_array;
700 pqi_index_t __iomem *oq_pi;
701 dma_addr_t oq_element_array_bus_addr;
702 dma_addr_t oq_pi_bus_addr;
703 __le32 __iomem *oq_ci;
704 pqi_index_t oq_ci_copy;
705 };
706
707 #define PQI_DEFAULT_QUEUE_GROUP 0
708 #define PQI_MAX_QUEUE_GROUPS PQI_MAX_MSIX_VECTORS
709
710 struct pqi_encryption_info {
711 u16 data_encryption_key_index;
712 u32 encrypt_tweak_lower;
713 u32 encrypt_tweak_upper;
714 };
715
716 #pragma pack(1)
717
718 #define PQI_CONFIG_TABLE_SIGNATURE "CFGTABLE"
719 #define PQI_CONFIG_TABLE_MAX_LENGTH ((u16)~0)
720
721 /* configuration table section IDs */
722 #define PQI_CONFIG_TABLE_ALL_SECTIONS (-1)
723 #define PQI_CONFIG_TABLE_SECTION_GENERAL_INFO 0
724 #define PQI_CONFIG_TABLE_SECTION_FIRMWARE_FEATURES 1
725 #define PQI_CONFIG_TABLE_SECTION_FIRMWARE_ERRATA 2
726 #define PQI_CONFIG_TABLE_SECTION_DEBUG 3
727 #define PQI_CONFIG_TABLE_SECTION_HEARTBEAT 4
728 #define PQI_CONFIG_TABLE_SECTION_SOFT_RESET 5
729
730 struct pqi_config_table {
731 u8 signature[8]; /* "CFGTABLE" */
732 __le32 first_section_offset; /* offset in bytes from the base */
733 /* address of this table to the */
734 /* first section */
735 };
736
737 struct pqi_config_table_section_header {
738 __le16 section_id; /* as defined by the */
739 /* PQI_CONFIG_TABLE_SECTION_* */
740 /* manifest constants above */
741 __le16 next_section_offset; /* offset in bytes from base */
742 /* address of the table of the */
743 /* next section or 0 if last entry */
744 };
745
746 struct pqi_config_table_general_info {
747 struct pqi_config_table_section_header header;
748 __le32 section_length; /* size of this section in bytes */
749 /* including the section header */
750 __le32 max_outstanding_requests; /* max. outstanding */
751 /* commands supported by */
752 /* the controller */
753 __le32 max_sg_size; /* max. transfer size of a single */
754 /* command */
755 __le32 max_sg_per_request; /* max. number of scatter-gather */
756 /* entries supported in a single */
757 /* command */
758 };
759
760 struct pqi_config_table_firmware_features {
761 struct pqi_config_table_section_header header;
762 __le16 num_elements;
763 u8 features_supported[];
764 /* u8 features_requested_by_host[]; */
765 /* u8 features_enabled[]; */
766 };
767
768 #define PQI_FIRMWARE_FEATURE_OFA 0
769 #define PQI_FIRMWARE_FEATURE_SMP 1
770 #define PQI_FIRMWARE_FEATURE_SOFT_RESET_HANDSHAKE 11
771
772 struct pqi_config_table_debug {
773 struct pqi_config_table_section_header header;
774 __le32 scratchpad;
775 };
776
777 struct pqi_config_table_heartbeat {
778 struct pqi_config_table_section_header header;
779 __le32 heartbeat_counter;
780 };
781
782 struct pqi_config_table_soft_reset {
783 struct pqi_config_table_section_header header;
784 u8 soft_reset_status;
785 };
786
787 #define PQI_SOFT_RESET_INITIATE 0x1
788 #define PQI_SOFT_RESET_ABORT 0x2
789
790 enum pqi_soft_reset_status {
791 RESET_INITIATE_FIRMWARE,
792 RESET_INITIATE_DRIVER,
793 RESET_ABORT,
794 RESET_NORESPONSE,
795 RESET_TIMEDOUT
796 };
797
798 union pqi_reset_register {
799 struct {
800 u32 reset_type : 3;
801 u32 reserved : 2;
802 u32 reset_action : 3;
803 u32 hold_in_pd1 : 1;
804 u32 reserved2 : 23;
805 } bits;
806 u32 all_bits;
807 };
808
809 #define PQI_RESET_ACTION_RESET 0x1
810
811 #define PQI_RESET_TYPE_NO_RESET 0x0
812 #define PQI_RESET_TYPE_SOFT_RESET 0x1
813 #define PQI_RESET_TYPE_FIRM_RESET 0x2
814 #define PQI_RESET_TYPE_HARD_RESET 0x3
815
816 #define PQI_RESET_ACTION_COMPLETED 0x2
817
818 #define PQI_RESET_POLL_INTERVAL_MSECS 100
819
820 #define PQI_MAX_OUTSTANDING_REQUESTS ((u32)~0)
821 #define PQI_MAX_OUTSTANDING_REQUESTS_KDUMP 32
822 #define PQI_MAX_TRANSFER_SIZE (1024U * 1024U)
823 #define PQI_MAX_TRANSFER_SIZE_KDUMP (512 * 1024U)
824
825 #define RAID_MAP_MAX_ENTRIES 1024
826
827 #define PQI_PHYSICAL_DEVICE_BUS 0
828 #define PQI_RAID_VOLUME_BUS 1
829 #define PQI_HBA_BUS 2
830 #define PQI_EXTERNAL_RAID_VOLUME_BUS 3
831 #define PQI_MAX_BUS PQI_EXTERNAL_RAID_VOLUME_BUS
832
833 struct report_lun_header {
834 __be32 list_length;
835 u8 extended_response;
836 u8 reserved[3];
837 };
838
839 struct report_log_lun_extended_entry {
840 u8 lunid[8];
841 u8 volume_id[16];
842 };
843
844 struct report_log_lun_extended {
845 struct report_lun_header header;
846 struct report_log_lun_extended_entry lun_entries[1];
847 };
848
849 struct report_phys_lun_extended_entry {
850 u8 lunid[8];
851 __be64 wwid;
852 u8 device_type;
853 u8 device_flags;
854 u8 lun_count; /* number of LUNs in a multi-LUN device */
855 u8 redundant_paths;
856 u32 aio_handle;
857 };
858
859 /* for device_flags field of struct report_phys_lun_extended_entry */
860 #define REPORT_PHYS_LUN_DEV_FLAG_AIO_ENABLED 0x8
861
862 struct report_phys_lun_extended {
863 struct report_lun_header header;
864 struct report_phys_lun_extended_entry lun_entries[1];
865 };
866
867 struct raid_map_disk_data {
868 u32 aio_handle;
869 u8 xor_mult[2];
870 u8 reserved[2];
871 };
872
873 /* constants for flags field of RAID map */
874 #define RAID_MAP_ENCRYPTION_ENABLED 0x1
875
876 struct raid_map {
877 __le32 structure_size; /* size of entire structure in bytes */
878 __le32 volume_blk_size; /* bytes / block in the volume */
879 __le64 volume_blk_cnt; /* logical blocks on the volume */
880 u8 phys_blk_shift; /* shift factor to convert between */
881 /* units of logical blocks and */
882 /* physical disk blocks */
883 u8 parity_rotation_shift; /* shift factor to convert between */
884 /* units of logical stripes and */
885 /* physical stripes */
886 __le16 strip_size; /* blocks used on each disk / stripe */
887 __le64 disk_starting_blk; /* first disk block used in volume */
888 __le64 disk_blk_cnt; /* disk blocks used by volume / disk */
889 __le16 data_disks_per_row; /* data disk entries / row in the map */
890 __le16 metadata_disks_per_row; /* mirror/parity disk entries / row */
891 /* in the map */
892 __le16 row_cnt; /* rows in each layout map */
893 __le16 layout_map_count; /* layout maps (1 map per */
894 /* mirror parity group) */
895 __le16 flags;
896 __le16 data_encryption_key_index;
897 u8 reserved[16];
898 struct raid_map_disk_data disk_data[RAID_MAP_MAX_ENTRIES];
899 };
900
901 #pragma pack()
902
903 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
904
905 struct pqi_scsi_dev {
906 int devtype; /* as reported by INQUIRY commmand */
907 u8 device_type; /* as reported by */
908 /* BMIC_IDENTIFY_PHYSICAL_DEVICE */
909 /* only valid for devtype = TYPE_DISK */
910 int bus;
911 int target;
912 int lun;
913 u8 scsi3addr[8];
914 __be64 wwid;
915 u8 volume_id[16];
916 u8 unique_id[16];
917 u8 is_physical_device : 1;
918 u8 is_external_raid_device : 1;
919 u8 is_expander_smp_device : 1;
920 u8 target_lun_valid : 1;
921 u8 device_gone : 1;
922 u8 new_device : 1;
923 u8 keep_device : 1;
924 u8 volume_offline : 1;
925 bool aio_enabled; /* only valid for physical disks */
926 bool in_reset;
927 bool in_remove;
928 bool device_offline;
929 u8 vendor[8]; /* bytes 8-15 of inquiry data */
930 u8 model[16]; /* bytes 16-31 of inquiry data */
931 u64 sas_address;
932 u8 raid_level;
933 u16 queue_depth; /* max. queue_depth for this device */
934 u16 advertised_queue_depth;
935 u32 aio_handle;
936 u8 volume_status;
937 u8 active_path_index;
938 u8 path_map;
939 u8 bay;
940 u8 box[8];
941 u16 phys_connector[8];
942 bool raid_bypass_configured; /* RAID bypass configured */
943 bool raid_bypass_enabled; /* RAID bypass enabled */
944 int offload_to_mirror; /* Send next RAID bypass request */
945 /* to mirror drive. */
946 struct raid_map *raid_map; /* RAID bypass map */
947
948 struct pqi_sas_port *sas_port;
949 struct scsi_device *sdev;
950
951 struct list_head scsi_device_list_entry;
952 struct list_head new_device_list_entry;
953 struct list_head add_list_entry;
954 struct list_head delete_list_entry;
955
956 atomic_t scsi_cmds_outstanding;
957 };
958
959 /* VPD inquiry pages */
960 #define SCSI_VPD_SUPPORTED_PAGES 0x0 /* standard page */
961 #define SCSI_VPD_DEVICE_ID 0x83 /* standard page */
962 #define CISS_VPD_LV_DEVICE_GEOMETRY 0xc1 /* vendor-specific page */
963 #define CISS_VPD_LV_BYPASS_STATUS 0xc2 /* vendor-specific page */
964 #define CISS_VPD_LV_STATUS 0xc3 /* vendor-specific page */
965 #define SCSI_VPD_HEADER_SZ 4
966 #define SCSI_VPD_DEVICE_ID_IDX 8 /* Index of page id in page */
967
968 #define VPD_PAGE (1 << 8)
969
970 #pragma pack(1)
971
972 /* structure for CISS_VPD_LV_STATUS */
973 struct ciss_vpd_logical_volume_status {
974 u8 peripheral_info;
975 u8 page_code;
976 u8 reserved;
977 u8 page_length;
978 u8 volume_status;
979 u8 reserved2[3];
980 __be32 flags;
981 };
982
983 #pragma pack()
984
985 /* constants for volume_status field of ciss_vpd_logical_volume_status */
986 #define CISS_LV_OK 0
987 #define CISS_LV_FAILED 1
988 #define CISS_LV_NOT_CONFIGURED 2
989 #define CISS_LV_DEGRADED 3
990 #define CISS_LV_READY_FOR_RECOVERY 4
991 #define CISS_LV_UNDERGOING_RECOVERY 5
992 #define CISS_LV_WRONG_PHYSICAL_DRIVE_REPLACED 6
993 #define CISS_LV_PHYSICAL_DRIVE_CONNECTION_PROBLEM 7
994 #define CISS_LV_HARDWARE_OVERHEATING 8
995 #define CISS_LV_HARDWARE_HAS_OVERHEATED 9
996 #define CISS_LV_UNDERGOING_EXPANSION 10
997 #define CISS_LV_NOT_AVAILABLE 11
998 #define CISS_LV_QUEUED_FOR_EXPANSION 12
999 #define CISS_LV_DISABLED_SCSI_ID_CONFLICT 13
1000 #define CISS_LV_EJECTED 14
1001 #define CISS_LV_UNDERGOING_ERASE 15
1002 /* state 16 not used */
1003 #define CISS_LV_READY_FOR_PREDICTIVE_SPARE_REBUILD 17
1004 #define CISS_LV_UNDERGOING_RPI 18
1005 #define CISS_LV_PENDING_RPI 19
1006 #define CISS_LV_ENCRYPTED_NO_KEY 20
1007 /* state 21 not used */
1008 #define CISS_LV_UNDERGOING_ENCRYPTION 22
1009 #define CISS_LV_UNDERGOING_ENCRYPTION_REKEYING 23
1010 #define CISS_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 24
1011 #define CISS_LV_PENDING_ENCRYPTION 25
1012 #define CISS_LV_PENDING_ENCRYPTION_REKEYING 26
1013 #define CISS_LV_NOT_SUPPORTED 27
1014 #define CISS_LV_STATUS_UNAVAILABLE 255
1015
1016 /* constants for flags field of ciss_vpd_logical_volume_status */
1017 #define CISS_LV_FLAGS_NO_HOST_IO 0x1 /* volume not available for */
1018 /* host I/O */
1019
1020 /* for SAS hosts and SAS expanders */
1021 struct pqi_sas_node {
1022 struct device *parent_dev;
1023 struct list_head port_list_head;
1024 };
1025
1026 struct pqi_sas_port {
1027 struct list_head port_list_entry;
1028 u64 sas_address;
1029 struct pqi_scsi_dev *device;
1030 struct sas_port *port;
1031 int next_phy_index;
1032 struct list_head phy_list_head;
1033 struct pqi_sas_node *parent_node;
1034 struct sas_rphy *rphy;
1035 };
1036
1037 struct pqi_sas_phy {
1038 struct list_head phy_list_entry;
1039 struct sas_phy *phy;
1040 struct pqi_sas_port *parent_port;
1041 bool added_to_port;
1042 };
1043
1044 struct pqi_io_request {
1045 atomic_t refcount;
1046 u16 index;
1047 void (*io_complete_callback)(struct pqi_io_request *io_request,
1048 void *context);
1049 void *context;
1050 u8 raid_bypass : 1;
1051 int status;
1052 struct pqi_queue_group *queue_group;
1053 struct scsi_cmnd *scmd;
1054 void *error_info;
1055 struct pqi_sg_descriptor *sg_chain_buffer;
1056 dma_addr_t sg_chain_buffer_dma_handle;
1057 void *iu;
1058 struct list_head request_list_entry;
1059 };
1060
1061 #define PQI_NUM_SUPPORTED_EVENTS 7
1062
1063 struct pqi_event {
1064 bool pending;
1065 u8 event_type;
1066 __le16 event_id;
1067 __le32 additional_event_id;
1068 __le32 ofa_bytes_requested;
1069 __le16 ofa_cancel_reason;
1070 };
1071
1072 #define PQI_RESERVED_IO_SLOTS_LUN_RESET 1
1073 #define PQI_RESERVED_IO_SLOTS_EVENT_ACK PQI_NUM_SUPPORTED_EVENTS
1074 #define PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS 3
1075 #define PQI_RESERVED_IO_SLOTS \
1076 (PQI_RESERVED_IO_SLOTS_LUN_RESET + PQI_RESERVED_IO_SLOTS_EVENT_ACK + \
1077 PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS)
1078
1079 struct pqi_ctrl_info {
1080 unsigned int ctrl_id;
1081 struct pci_dev *pci_dev;
1082 char firmware_version[11];
1083 void __iomem *iomem_base;
1084 struct pqi_ctrl_registers __iomem *registers;
1085 struct pqi_device_registers __iomem *pqi_registers;
1086 u32 max_sg_entries;
1087 u32 config_table_offset;
1088 u32 config_table_length;
1089 u16 max_inbound_queues;
1090 u16 max_elements_per_iq;
1091 u16 max_iq_element_length;
1092 u16 max_outbound_queues;
1093 u16 max_elements_per_oq;
1094 u16 max_oq_element_length;
1095 u32 max_transfer_size;
1096 u32 max_outstanding_requests;
1097 u32 max_io_slots;
1098 unsigned int scsi_ml_can_queue;
1099 unsigned short sg_tablesize;
1100 unsigned int max_sectors;
1101 u32 error_buffer_length;
1102 void *error_buffer;
1103 dma_addr_t error_buffer_dma_handle;
1104 size_t sg_chain_buffer_length;
1105 unsigned int num_queue_groups;
1106 u16 max_hw_queue_index;
1107 u16 num_elements_per_iq;
1108 u16 num_elements_per_oq;
1109 u16 max_inbound_iu_length_per_firmware;
1110 u16 max_inbound_iu_length;
1111 unsigned int max_sg_per_iu;
1112 void *admin_queue_memory_base;
1113 u32 admin_queue_memory_length;
1114 dma_addr_t admin_queue_memory_base_dma_handle;
1115 void *queue_memory_base;
1116 u32 queue_memory_length;
1117 dma_addr_t queue_memory_base_dma_handle;
1118 struct pqi_admin_queues admin_queues;
1119 struct pqi_queue_group queue_groups[PQI_MAX_QUEUE_GROUPS];
1120 struct pqi_event_queue event_queue;
1121 enum pqi_irq_mode irq_mode;
1122 int max_msix_vectors;
1123 int num_msix_vectors_enabled;
1124 int num_msix_vectors_initialized;
1125 int event_irq;
1126 struct Scsi_Host *scsi_host;
1127
1128 struct mutex scan_mutex;
1129 struct mutex lun_reset_mutex;
1130 struct mutex ofa_mutex; /* serialize ofa */
1131 bool controller_online;
1132 bool block_requests;
1133 bool in_shutdown;
1134 bool in_ofa;
1135 u8 inbound_spanning_supported : 1;
1136 u8 outbound_spanning_supported : 1;
1137 u8 pqi_mode_enabled : 1;
1138 u8 pqi_reset_quiesce_supported : 1;
1139 u8 soft_reset_handshake_supported : 1;
1140
1141 struct list_head scsi_device_list;
1142 spinlock_t scsi_device_list_lock;
1143
1144 struct delayed_work rescan_work;
1145 struct delayed_work update_time_work;
1146
1147 struct pqi_sas_node *sas_host;
1148 u64 sas_address;
1149
1150 struct pqi_io_request *io_request_pool;
1151 u16 next_io_request_slot;
1152
1153 struct pqi_event events[PQI_NUM_SUPPORTED_EVENTS];
1154 struct work_struct event_work;
1155
1156 atomic_t num_interrupts;
1157 int previous_num_interrupts;
1158 u32 previous_heartbeat_count;
1159 __le32 __iomem *heartbeat_counter;
1160 u8 __iomem *soft_reset_status;
1161 struct timer_list heartbeat_timer;
1162 struct work_struct ctrl_offline_work;
1163
1164 struct semaphore sync_request_sem;
1165 atomic_t num_busy_threads;
1166 atomic_t num_blocked_threads;
1167 wait_queue_head_t block_requests_wait;
1168
1169 struct list_head raid_bypass_retry_list;
1170 spinlock_t raid_bypass_retry_list_lock;
1171 struct work_struct raid_bypass_retry_work;
1172
1173 struct pqi_ofa_memory *pqi_ofa_mem_virt_addr;
1174 dma_addr_t pqi_ofa_mem_dma_handle;
1175 void **pqi_ofa_chunk_virt_addr;
1176 };
1177
1178 enum pqi_ctrl_mode {
1179 SIS_MODE = 0,
1180 PQI_MODE
1181 };
1182
1183 /*
1184 * assume worst case: SATA queue depth of 31 minus 4 internal firmware commands
1185 */
1186 #define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 27
1187
1188 /* CISS commands */
1189 #define CISS_READ 0xc0
1190 #define CISS_REPORT_LOG 0xc2 /* Report Logical LUNs */
1191 #define CISS_REPORT_PHYS 0xc3 /* Report Physical LUNs */
1192 #define CISS_GET_RAID_MAP 0xc8
1193
1194 /* constants for CISS_REPORT_LOG/CISS_REPORT_PHYS commands */
1195 #define CISS_REPORT_LOG_EXTENDED 0x1
1196 #define CISS_REPORT_PHYS_EXTENDED 0x2
1197
1198 /* BMIC commands */
1199 #define BMIC_IDENTIFY_CONTROLLER 0x11
1200 #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15
1201 #define BMIC_READ 0x26
1202 #define BMIC_WRITE 0x27
1203 #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64
1204 #define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66
1205 #define BMIC_CSMI_PASSTHRU 0x68
1206 #define BMIC_WRITE_HOST_WELLNESS 0xa5
1207 #define BMIC_FLUSH_CACHE 0xc2
1208 #define BMIC_SET_DIAG_OPTIONS 0xf4
1209 #define BMIC_SENSE_DIAG_OPTIONS 0xf5
1210
1211 #define CSMI_CC_SAS_SMP_PASSTHRU 0X17
1212
1213 #define SA_FLUSH_CACHE 0x1
1214
1215 #define MASKED_DEVICE(lunid) ((lunid)[3] & 0xc0)
1216 #define CISS_GET_LEVEL_2_BUS(lunid) ((lunid)[7] & 0x3f)
1217 #define CISS_GET_LEVEL_2_TARGET(lunid) ((lunid)[6])
1218 #define CISS_GET_DRIVE_NUMBER(lunid) \
1219 (((CISS_GET_LEVEL_2_BUS((lunid)) - 1) << 8) + \
1220 CISS_GET_LEVEL_2_TARGET((lunid)))
1221
1222 #define NO_TIMEOUT ((unsigned long) -1)
1223
1224 #pragma pack(1)
1225
1226 struct bmic_identify_controller {
1227 u8 configured_logical_drive_count;
1228 __le32 configuration_signature;
1229 u8 firmware_version[4];
1230 u8 reserved[145];
1231 __le16 extended_logical_unit_count;
1232 u8 reserved1[34];
1233 __le16 firmware_build_number;
1234 u8 reserved2[100];
1235 u8 controller_mode;
1236 u8 reserved3[32];
1237 };
1238
1239 #define SA_EXPANDER_SMP_DEVICE 0x05
1240 /*SCSI Invalid Device Type for SAS devices*/
1241 #define PQI_SAS_SCSI_INVALID_DEVTYPE 0xff
1242
1243 struct bmic_identify_physical_device {
1244 u8 scsi_bus; /* SCSI Bus number on controller */
1245 u8 scsi_id; /* SCSI ID on this bus */
1246 __le16 block_size; /* sector size in bytes */
1247 __le32 total_blocks; /* number for sectors on drive */
1248 __le32 reserved_blocks; /* controller reserved (RIS) */
1249 u8 model[40]; /* Physical Drive Model */
1250 u8 serial_number[40]; /* Drive Serial Number */
1251 u8 firmware_revision[8]; /* drive firmware revision */
1252 u8 scsi_inquiry_bits; /* inquiry byte 7 bits */
1253 u8 compaq_drive_stamp; /* 0 means drive not stamped */
1254 u8 last_failure_reason;
1255 u8 flags;
1256 u8 more_flags;
1257 u8 scsi_lun; /* SCSI LUN for phys drive */
1258 u8 yet_more_flags;
1259 u8 even_more_flags;
1260 __le32 spi_speed_rules;
1261 u8 phys_connector[2]; /* connector number on controller */
1262 u8 phys_box_on_bus; /* phys enclosure this drive resides */
1263 u8 phys_bay_in_box; /* phys drv bay this drive resides */
1264 __le32 rpm; /* drive rotational speed in RPM */
1265 u8 device_type; /* type of drive */
1266 u8 sata_version; /* only valid when device_type = */
1267 /* BMIC_DEVICE_TYPE_SATA */
1268 __le64 big_total_block_count;
1269 __le64 ris_starting_lba;
1270 __le32 ris_size;
1271 u8 wwid[20];
1272 u8 controller_phy_map[32];
1273 __le16 phy_count;
1274 u8 phy_connected_dev_type[256];
1275 u8 phy_to_drive_bay_num[256];
1276 __le16 phy_to_attached_dev_index[256];
1277 u8 box_index;
1278 u8 reserved;
1279 __le16 extra_physical_drive_flags;
1280 u8 negotiated_link_rate[256];
1281 u8 phy_to_phy_map[256];
1282 u8 redundant_path_present_map;
1283 u8 redundant_path_failure_map;
1284 u8 active_path_number;
1285 __le16 alternate_paths_phys_connector[8];
1286 u8 alternate_paths_phys_box_on_port[8];
1287 u8 multi_lun_device_lun_count;
1288 u8 minimum_good_fw_revision[8];
1289 u8 unique_inquiry_bytes[20];
1290 u8 current_temperature_degrees;
1291 u8 temperature_threshold_degrees;
1292 u8 max_temperature_degrees;
1293 u8 logical_blocks_per_phys_block_exp;
1294 __le16 current_queue_depth_limit;
1295 u8 switch_name[10];
1296 __le16 switch_port;
1297 u8 alternate_paths_switch_name[40];
1298 u8 alternate_paths_switch_port[8];
1299 __le16 power_on_hours;
1300 __le16 percent_endurance_used;
1301 u8 drive_authentication;
1302 u8 smart_carrier_authentication;
1303 u8 smart_carrier_app_fw_version;
1304 u8 smart_carrier_bootloader_fw_version;
1305 u8 sanitize_flags;
1306 u8 encryption_key_flags;
1307 u8 encryption_key_name[64];
1308 __le32 misc_drive_flags;
1309 __le16 dek_index;
1310 __le16 hba_drive_encryption_flags;
1311 __le16 max_overwrite_time;
1312 __le16 max_block_erase_time;
1313 __le16 max_crypto_erase_time;
1314 u8 connector_info[5];
1315 u8 connector_name[8][8];
1316 u8 page_83_identifier[16];
1317 u8 maximum_link_rate[256];
1318 u8 negotiated_physical_link_rate[256];
1319 u8 box_connector_name[8];
1320 u8 padding_to_multiple_of_512[9];
1321 };
1322
1323 struct bmic_smp_request {
1324 u8 frame_type;
1325 u8 function;
1326 u8 allocated_response_length;
1327 u8 request_length;
1328 u8 additional_request_bytes[1016];
1329 };
1330
1331 struct bmic_smp_response {
1332 u8 frame_type;
1333 u8 function;
1334 u8 function_result;
1335 u8 response_length;
1336 u8 additional_response_bytes[1016];
1337 };
1338
1339 struct bmic_csmi_ioctl_header {
1340 __le32 header_length;
1341 u8 signature[8];
1342 __le32 timeout;
1343 __le32 control_code;
1344 __le32 return_code;
1345 __le32 length;
1346 };
1347
1348 struct bmic_csmi_smp_passthru {
1349 u8 phy_identifier;
1350 u8 port_identifier;
1351 u8 connection_rate;
1352 u8 reserved;
1353 __be64 destination_sas_address;
1354 __le32 request_length;
1355 struct bmic_smp_request request;
1356 u8 connection_status;
1357 u8 reserved1[3];
1358 __le32 response_length;
1359 struct bmic_smp_response response;
1360 };
1361
1362 struct bmic_csmi_smp_passthru_buffer {
1363 struct bmic_csmi_ioctl_header ioctl_header;
1364 struct bmic_csmi_smp_passthru parameters;
1365 };
1366
1367 struct bmic_flush_cache {
1368 u8 disable_flag;
1369 u8 system_power_action;
1370 u8 ndu_flush;
1371 u8 shutdown_event;
1372 u8 reserved[28];
1373 };
1374
1375 /* for shutdown_event member of struct bmic_flush_cache */
1376 enum bmic_flush_cache_shutdown_event {
1377 NONE_CACHE_FLUSH_ONLY = 0,
1378 SHUTDOWN = 1,
1379 HIBERNATE = 2,
1380 SUSPEND = 3,
1381 RESTART = 4
1382 };
1383
1384 struct bmic_diag_options {
1385 __le32 options;
1386 };
1387
1388 #pragma pack()
1389
1390 static inline struct pqi_ctrl_info *shost_to_hba(struct Scsi_Host *shost)
1391 {
1392 void *hostdata = shost_priv(shost);
1393
1394 return *((struct pqi_ctrl_info **)hostdata);
1395 }
1396
1397 static inline bool pqi_ctrl_offline(struct pqi_ctrl_info *ctrl_info)
1398 {
1399 return !ctrl_info->controller_online;
1400 }
1401
1402 static inline void pqi_ctrl_busy(struct pqi_ctrl_info *ctrl_info)
1403 {
1404 atomic_inc(&ctrl_info->num_busy_threads);
1405 }
1406
1407 static inline void pqi_ctrl_unbusy(struct pqi_ctrl_info *ctrl_info)
1408 {
1409 atomic_dec(&ctrl_info->num_busy_threads);
1410 }
1411
1412 static inline bool pqi_ctrl_blocked(struct pqi_ctrl_info *ctrl_info)
1413 {
1414 return ctrl_info->block_requests;
1415 }
1416
1417 void pqi_sas_smp_handler(struct bsg_job *job, struct Scsi_Host *shost,
1418 struct sas_rphy *rphy);
1419
1420 int pqi_add_sas_host(struct Scsi_Host *shost, struct pqi_ctrl_info *ctrl_info);
1421 void pqi_delete_sas_host(struct pqi_ctrl_info *ctrl_info);
1422 int pqi_add_sas_device(struct pqi_sas_node *pqi_sas_node,
1423 struct pqi_scsi_dev *device);
1424 void pqi_remove_sas_device(struct pqi_scsi_dev *device);
1425 struct pqi_scsi_dev *pqi_find_device_by_sas_rphy(
1426 struct pqi_ctrl_info *ctrl_info, struct sas_rphy *rphy);
1427 void pqi_prep_for_scsi_done(struct scsi_cmnd *scmd);
1428 int pqi_csmi_smp_passthru(struct pqi_ctrl_info *ctrl_info,
1429 struct bmic_csmi_smp_passthru_buffer *buffer, size_t buffer_length,
1430 struct pqi_raid_error_info *error_info);
1431
1432 extern struct sas_function_template pqi_sas_transport_functions;
1433
1434 #endif /* _SMARTPQI_H */
Linux with added FPC-III support