drivers/spi/spi-mxs.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Freescale MXS SPI master driver
   4 //
   5 // Copyright 2012 DENX Software Engineering, GmbH.
   6 // Copyright 2012 Freescale Semiconductor, Inc.
   7 // Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   8 //
   9 // Rework and transition to new API by:
  10 // Marek Vasut <marex@denx.de>
  11 //
  12 // Based on previous attempt by:
  13 // Fabio Estevam <fabio.estevam@freescale.com>
  14 //
  15 // Based on code from U-Boot bootloader by:
  16 // Marek Vasut <marex@denx.de>
  17 //
  18 // Based on spi-stmp.c, which is:
  19 // Author: Dmitry Pervushin <dimka@embeddedalley.com>
  20
  21 #include <linux/kernel.h>
  22 #include <linux/ioport.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/of_gpio.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/delay.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/dmaengine.h>
  31 #include <linux/highmem.h>
  32 #include <linux/clk.h>
  33 #include <linux/err.h>
  34 #include <linux/completion.h>
  35 #include <linux/gpio.h>
  36 #include <linux/regulator/consumer.h>
  37 #include <linux/pm_runtime.h>
  38 #include <linux/module.h>
  39 #include <linux/stmp_device.h>
  40 #include <linux/spi/spi.h>
  41 #include <linux/spi/mxs-spi.h>
  42
  43 #define DRIVER_NAME             "mxs-spi"
  44
  45 /* Use 10S timeout for very long transfers, it should suffice. */
  46 #define SSP_TIMEOUT             10000
  47
  48 #define SG_MAXLEN               0xff00
  49
  50 /*
  51  * Flags for txrx functions.  More efficient that using an argument register for
  52  * each one.
  53  */
  54 #define TXRX_WRITE              (1<<0)  /* This is a write */
  55 #define TXRX_DEASSERT_CS        (1<<1)  /* De-assert CS at end of txrx */
  56
  57 struct mxs_spi {
  58         struct mxs_ssp          ssp;
  59         struct completion       c;
  60         unsigned int            sck;    /* Rate requested (vs actual) */
  61 };
  62
  63 static int mxs_spi_setup_transfer(struct spi_device *dev,
  64                                   const struct spi_transfer *t)
  65 {
  66         struct mxs_spi *spi = spi_master_get_devdata(dev->master);
  67         struct mxs_ssp *ssp = &spi->ssp;
  68         const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);
  69
  70         if (hz == 0) {
  71                 dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
  72                 return -EINVAL;
  73         }
  74
  75         if (hz != spi->sck) {
  76                 mxs_ssp_set_clk_rate(ssp, hz);
  77                 /*
  78                  * Save requested rate, hz, rather than the actual rate,
  79                  * ssp->clk_rate.  Otherwise we would set the rate every transfer
  80                  * when the actual rate is not quite the same as requested rate.
  81                  */
  82                 spi->sck = hz;
  83                 /*
  84                  * Perhaps we should return an error if the actual clock is
  85                  * nowhere close to what was requested?
  86                  */
  87         }
  88
  89         writel(BM_SSP_CTRL0_LOCK_CS,
  90                 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
  91
  92         writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
  93                BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
  94                ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
  95                ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
  96                ssp->base + HW_SSP_CTRL1(ssp));
  97
  98         writel(0x0, ssp->base + HW_SSP_CMD0);
  99         writel(0x0, ssp->base + HW_SSP_CMD1);
 100
 101         return 0;
 102 }
 103
 104 static u32 mxs_spi_cs_to_reg(unsigned cs)
 105 {
 106         u32 select = 0;
 107
 108         /*
 109          * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
 110          *
 111          * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
 112          * in HW_SSP_CTRL0 register do have multiple usage, please refer to
 113          * the datasheet for further details. In SPI mode, they are used to
 114          * toggle the chip-select lines (nCS pins).
 115          */
 116         if (cs & 1)
 117                 select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
 118         if (cs & 2)
 119                 select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;
 120
 121         return select;
 122 }
 123
 124 static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
 125 {
 126         const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
 127         struct mxs_ssp *ssp = &spi->ssp;
 128         u32 reg;
 129
 130         do {
 131                 reg = readl_relaxed(ssp->base + offset);
 132
 133                 if (!set)
 134                         reg = ~reg;
 135
 136                 reg &= mask;
 137
 138                 if (reg == mask)
 139                         return 0;
 140         } while (time_before(jiffies, timeout));
 141
 142         return -ETIMEDOUT;
 143 }
 144
 145 static void mxs_ssp_dma_irq_callback(void *param)
 146 {
 147         struct mxs_spi *spi = param;
 148
 149         complete(&spi->c);
 150 }
 151
 152 static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
 153 {
 154         struct mxs_ssp *ssp = dev_id;
 155
 156         dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
 157                 __func__, __LINE__,
 158                 readl(ssp->base + HW_SSP_CTRL1(ssp)),
 159                 readl(ssp->base + HW_SSP_STATUS(ssp)));
 160         return IRQ_HANDLED;
 161 }
 162
 163 static int mxs_spi_txrx_dma(struct mxs_spi *spi,
 164                             unsigned char *buf, int len,
 165                             unsigned int flags)
 166 {
 167         struct mxs_ssp *ssp = &spi->ssp;
 168         struct dma_async_tx_descriptor *desc = NULL;
 169         const bool vmalloced_buf = is_vmalloc_addr(buf);
 170         const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
 171         const int sgs = DIV_ROUND_UP(len, desc_len);
 172         int sg_count;
 173         int min, ret;
 174         u32 ctrl0;
 175         struct page *vm_page;
 176         struct {
 177                 u32                     pio[4];
 178                 struct scatterlist      sg;
 179         } *dma_xfer;
 180
 181         if (!len)
 182                 return -EINVAL;
 183
 184         dma_xfer = kcalloc(sgs, sizeof(*dma_xfer), GFP_KERNEL);
 185         if (!dma_xfer)
 186                 return -ENOMEM;
 187
 188         reinit_completion(&spi->c);
 189
 190         /* Chip select was already programmed into CTRL0 */
 191         ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
 192         ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC |
 193                  BM_SSP_CTRL0_READ);
 194         ctrl0 |= BM_SSP_CTRL0_DATA_XFER;
 195
 196         if (!(flags & TXRX_WRITE))
 197                 ctrl0 |= BM_SSP_CTRL0_READ;
 198
 199         /* Queue the DMA data transfer. */
 200         for (sg_count = 0; sg_count < sgs; sg_count++) {
 201                 /* Prepare the transfer descriptor. */
 202                 min = min(len, desc_len);
 203
 204                 /*
 205                  * De-assert CS on last segment if flag is set (i.e., no more
 206                  * transfers will follow)
 207                  */
 208                 if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
 209                         ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;
 210
 211                 if (ssp->devid == IMX23_SSP) {
 212                         ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
 213                         ctrl0 |= min;
 214                 }
 215
 216                 dma_xfer[sg_count].pio[0] = ctrl0;
 217                 dma_xfer[sg_count].pio[3] = min;
 218
 219                 if (vmalloced_buf) {
 220                         vm_page = vmalloc_to_page(buf);
 221                         if (!vm_page) {
 222                                 ret = -ENOMEM;
 223                                 goto err_vmalloc;
 224                         }
 225
 226                         sg_init_table(&dma_xfer[sg_count].sg, 1);
 227                         sg_set_page(&dma_xfer[sg_count].sg, vm_page,
 228                                     min, offset_in_page(buf));
 229                 } else {
 230                         sg_init_one(&dma_xfer[sg_count].sg, buf, min);
 231                 }
 232
 233                 ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
 234                         (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 235
 236                 len -= min;
 237                 buf += min;
 238
 239                 /* Queue the PIO register write transfer. */
 240                 desc = dmaengine_prep_slave_sg(ssp->dmach,
 241                                 (struct scatterlist *)dma_xfer[sg_count].pio,
 242                                 (ssp->devid == IMX23_SSP) ? 1 : 4,
 243                                 DMA_TRANS_NONE,
 244                                 sg_count ? DMA_PREP_INTERRUPT : 0);
 245                 if (!desc) {
 246                         dev_err(ssp->dev,
 247                                 "Failed to get PIO reg. write descriptor.\n");
 248                         ret = -EINVAL;
 249                         goto err_mapped;
 250                 }
 251
 252                 desc = dmaengine_prep_slave_sg(ssp->dmach,
 253                                 &dma_xfer[sg_count].sg, 1,
 254                                 (flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
 255                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 256
 257                 if (!desc) {
 258                         dev_err(ssp->dev,
 259                                 "Failed to get DMA data write descriptor.\n");
 260                         ret = -EINVAL;
 261                         goto err_mapped;
 262                 }
 263         }
 264
 265         /*
 266          * The last descriptor must have this callback,
 267          * to finish the DMA transaction.
 268          */
 269         desc->callback = mxs_ssp_dma_irq_callback;
 270         desc->callback_param = spi;
 271
 272         /* Start the transfer. */
 273         dmaengine_submit(desc);
 274         dma_async_issue_pending(ssp->dmach);
 275
 276         if (!wait_for_completion_timeout(&spi->c,
 277                                          msecs_to_jiffies(SSP_TIMEOUT))) {
 278                 dev_err(ssp->dev, "DMA transfer timeout\n");
 279                 ret = -ETIMEDOUT;
 280                 dmaengine_terminate_all(ssp->dmach);
 281                 goto err_vmalloc;
 282         }
 283
 284         ret = 0;
 285
 286 err_vmalloc:
 287         while (--sg_count >= 0) {
 288 err_mapped:
 289                 dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
 290                         (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 291         }
 292
 293         kfree(dma_xfer);
 294
 295         return ret;
 296 }
 297
 298 static int mxs_spi_txrx_pio(struct mxs_spi *spi,
 299                             unsigned char *buf, int len,
 300                             unsigned int flags)
 301 {
 302         struct mxs_ssp *ssp = &spi->ssp;
 303
 304         writel(BM_SSP_CTRL0_IGNORE_CRC,
 305                ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
 306
 307         while (len--) {
 308                 if (len == 0 && (flags & TXRX_DEASSERT_CS))
 309                         writel(BM_SSP_CTRL0_IGNORE_CRC,
 310                                ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 311
 312                 if (ssp->devid == IMX23_SSP) {
 313                         writel(BM_SSP_CTRL0_XFER_COUNT,
 314                                 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
 315                         writel(1,
 316                                 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 317                 } else {
 318                         writel(1, ssp->base + HW_SSP_XFER_SIZE);
 319                 }
 320
 321                 if (flags & TXRX_WRITE)
 322                         writel(BM_SSP_CTRL0_READ,
 323                                 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
 324                 else
 325                         writel(BM_SSP_CTRL0_READ,
 326                                 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 327
 328                 writel(BM_SSP_CTRL0_RUN,
 329                                 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 330
 331                 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
 332                         return -ETIMEDOUT;
 333
 334                 if (flags & TXRX_WRITE)
 335                         writel(*buf, ssp->base + HW_SSP_DATA(ssp));
 336
 337                 writel(BM_SSP_CTRL0_DATA_XFER,
 338                              ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 339
 340                 if (!(flags & TXRX_WRITE)) {
 341                         if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
 342                                                 BM_SSP_STATUS_FIFO_EMPTY, 0))
 343                                 return -ETIMEDOUT;
 344
 345                         *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
 346                 }
 347
 348                 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
 349                         return -ETIMEDOUT;
 350
 351                 buf++;
 352         }
 353
 354         if (len <= 0)
 355                 return 0;
 356
 357         return -ETIMEDOUT;
 358 }
 359
 360 static int mxs_spi_transfer_one(struct spi_master *master,
 361                                 struct spi_message *m)
 362 {
 363         struct mxs_spi *spi = spi_master_get_devdata(master);
 364         struct mxs_ssp *ssp = &spi->ssp;
 365         struct spi_transfer *t;
 366         unsigned int flag;
 367         int status = 0;
 368
 369         /* Program CS register bits here, it will be used for all transfers. */
 370         writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
 371                ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
 372         writel(mxs_spi_cs_to_reg(m->spi->chip_select),
 373                ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 374
 375         list_for_each_entry(t, &m->transfers, transfer_list) {
 376
 377                 status = mxs_spi_setup_transfer(m->spi, t);
 378                 if (status)
 379                         break;
 380
 381                 /* De-assert on last transfer, inverted by cs_change flag */
 382                 flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
 383                        TXRX_DEASSERT_CS : 0;
 384
 385                 /*
 386                  * Small blocks can be transfered via PIO.
 387                  * Measured by empiric means:
 388                  *
 389                  * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
 390                  *
 391                  * DMA only: 2.164808 seconds, 473.0KB/s
 392                  * Combined: 1.676276 seconds, 610.9KB/s
 393                  */
 394                 if (t->len < 32) {
 395                         writel(BM_SSP_CTRL1_DMA_ENABLE,
 396                                 ssp->base + HW_SSP_CTRL1(ssp) +
 397                                 STMP_OFFSET_REG_CLR);
 398
 399                         if (t->tx_buf)
 400                                 status = mxs_spi_txrx_pio(spi,
 401                                                 (void *)t->tx_buf,
 402                                                 t->len, flag | TXRX_WRITE);
 403                         if (t->rx_buf)
 404                                 status = mxs_spi_txrx_pio(spi,
 405                                                 t->rx_buf, t->len,
 406                                                 flag);
 407                 } else {
 408                         writel(BM_SSP_CTRL1_DMA_ENABLE,
 409                                 ssp->base + HW_SSP_CTRL1(ssp) +
 410                                 STMP_OFFSET_REG_SET);
 411
 412                         if (t->tx_buf)
 413                                 status = mxs_spi_txrx_dma(spi,
 414                                                 (void *)t->tx_buf, t->len,
 415                                                 flag | TXRX_WRITE);
 416                         if (t->rx_buf)
 417                                 status = mxs_spi_txrx_dma(spi,
 418                                                 t->rx_buf, t->len,
 419                                                 flag);
 420                 }
 421
 422                 if (status) {
 423                         stmp_reset_block(ssp->base);
 424                         break;
 425                 }
 426
 427                 m->actual_length += t->len;
 428         }
 429
 430         m->status = status;
 431         spi_finalize_current_message(master);
 432
 433         return status;
 434 }
 435
 436 static int mxs_spi_runtime_suspend(struct device *dev)
 437 {
 438         struct spi_master *master = dev_get_drvdata(dev);
 439         struct mxs_spi *spi = spi_master_get_devdata(master);
 440         struct mxs_ssp *ssp = &spi->ssp;
 441         int ret;
 442
 443         clk_disable_unprepare(ssp->clk);
 444
 445         ret = pinctrl_pm_select_idle_state(dev);
 446         if (ret) {
 447                 int ret2 = clk_prepare_enable(ssp->clk);
 448
 449                 if (ret2)
 450                         dev_warn(dev, "Failed to reenable clock after failing pinctrl request (pinctrl: %d, clk: %d)\n",
 451                                  ret, ret2);
 452         }
 453
 454         return ret;
 455 }
 456
 457 static int mxs_spi_runtime_resume(struct device *dev)
 458 {
 459         struct spi_master *master = dev_get_drvdata(dev);
 460         struct mxs_spi *spi = spi_master_get_devdata(master);
 461         struct mxs_ssp *ssp = &spi->ssp;
 462         int ret;
 463
 464         ret = pinctrl_pm_select_default_state(dev);
 465         if (ret)
 466                 return ret;
 467
 468         ret = clk_prepare_enable(ssp->clk);
 469         if (ret)
 470                 pinctrl_pm_select_idle_state(dev);
 471
 472         return ret;
 473 }
 474
 475 static int __maybe_unused mxs_spi_suspend(struct device *dev)
 476 {
 477         struct spi_master *master = dev_get_drvdata(dev);
 478         int ret;
 479
 480         ret = spi_master_suspend(master);
 481         if (ret)
 482                 return ret;
 483
 484         if (!pm_runtime_suspended(dev))
 485                 return mxs_spi_runtime_suspend(dev);
 486         else
 487                 return 0;
 488 }
 489
 490 static int __maybe_unused mxs_spi_resume(struct device *dev)
 491 {
 492         struct spi_master *master = dev_get_drvdata(dev);
 493         int ret;
 494
 495         if (!pm_runtime_suspended(dev))
 496                 ret = mxs_spi_runtime_resume(dev);
 497         else
 498                 ret = 0;
 499         if (ret)
 500                 return ret;
 501
 502         ret = spi_master_resume(master);
 503         if (ret < 0 && !pm_runtime_suspended(dev))
 504                 mxs_spi_runtime_suspend(dev);
 505
 506         return ret;
 507 }
 508
 509 static const struct dev_pm_ops mxs_spi_pm = {
 510         SET_RUNTIME_PM_OPS(mxs_spi_runtime_suspend,
 511                            mxs_spi_runtime_resume, NULL)
 512         SET_SYSTEM_SLEEP_PM_OPS(mxs_spi_suspend, mxs_spi_resume)
 513 };
 514
 515 static const struct of_device_id mxs_spi_dt_ids[] = {
 516         { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
 517         { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
 518         { /* sentinel */ }
 519 };
 520 MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
 521
 522 static int mxs_spi_probe(struct platform_device *pdev)
 523 {
 524         const struct of_device_id *of_id =
 525                         of_match_device(mxs_spi_dt_ids, &pdev->dev);
 526         struct device_node *np = pdev->dev.of_node;
 527         struct spi_master *master;
 528         struct mxs_spi *spi;
 529         struct mxs_ssp *ssp;
 530         struct resource *iores;
 531         struct clk *clk;
 532         void __iomem *base;
 533         int devid, clk_freq;
 534         int ret = 0, irq_err;
 535
 536         /*
 537          * Default clock speed for the SPI core. 160MHz seems to
 538          * work reasonably well with most SPI flashes, so use this
 539          * as a default. Override with "clock-frequency" DT prop.
 540          */
 541         const int clk_freq_default = 160000000;
 542
 543         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 544         irq_err = platform_get_irq(pdev, 0);
 545         if (irq_err < 0)
 546                 return irq_err;
 547
 548         base = devm_ioremap_resource(&pdev->dev, iores);
 549         if (IS_ERR(base))
 550                 return PTR_ERR(base);
 551
 552         clk = devm_clk_get(&pdev->dev, NULL);
 553         if (IS_ERR(clk))
 554                 return PTR_ERR(clk);
 555
 556         devid = (enum mxs_ssp_id) of_id->data;
 557         ret = of_property_read_u32(np, "clock-frequency",
 558                                    &clk_freq);
 559         if (ret)
 560                 clk_freq = clk_freq_default;
 561
 562         master = spi_alloc_master(&pdev->dev, sizeof(*spi));
 563         if (!master)
 564                 return -ENOMEM;
 565
 566         platform_set_drvdata(pdev, master);
 567
 568         master->transfer_one_message = mxs_spi_transfer_one;
 569         master->bits_per_word_mask = SPI_BPW_MASK(8);
 570         master->mode_bits = SPI_CPOL | SPI_CPHA;
 571         master->num_chipselect = 3;
 572         master->dev.of_node = np;
 573         master->flags = SPI_MASTER_HALF_DUPLEX;
 574         master->auto_runtime_pm = true;
 575
 576         spi = spi_master_get_devdata(master);
 577         ssp = &spi->ssp;
 578         ssp->dev = &pdev->dev;
 579         ssp->clk = clk;
 580         ssp->base = base;
 581         ssp->devid = devid;
 582
 583         init_completion(&spi->c);
 584
 585         ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
 586                                dev_name(&pdev->dev), ssp);
 587         if (ret)
 588                 goto out_master_free;
 589
 590         ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
 591         if (!ssp->dmach) {
 592                 dev_err(ssp->dev, "Failed to request DMA\n");
 593                 ret = -ENODEV;
 594                 goto out_master_free;
 595         }
 596
 597         pm_runtime_enable(ssp->dev);
 598         if (!pm_runtime_enabled(ssp->dev)) {
 599                 ret = mxs_spi_runtime_resume(ssp->dev);
 600                 if (ret < 0) {
 601                         dev_err(ssp->dev, "runtime resume failed\n");
 602                         goto out_dma_release;
 603                 }
 604         }
 605
 606         ret = pm_runtime_get_sync(ssp->dev);
 607         if (ret < 0) {
 608                 dev_err(ssp->dev, "runtime_get_sync failed\n");
 609                 goto out_pm_runtime_disable;
 610         }
 611
 612         clk_set_rate(ssp->clk, clk_freq);
 613
 614         ret = stmp_reset_block(ssp->base);
 615         if (ret)
 616                 goto out_pm_runtime_put;
 617
 618         ret = devm_spi_register_master(&pdev->dev, master);
 619         if (ret) {
 620                 dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
 621                 goto out_pm_runtime_put;
 622         }
 623
 624         pm_runtime_put(ssp->dev);
 625
 626         return 0;
 627
 628 out_pm_runtime_put:
 629         pm_runtime_put(ssp->dev);
 630 out_pm_runtime_disable:
 631         pm_runtime_disable(ssp->dev);
 632 out_dma_release:
 633         dma_release_channel(ssp->dmach);
 634 out_master_free:
 635         spi_master_put(master);
 636         return ret;
 637 }
 638
 639 static int mxs_spi_remove(struct platform_device *pdev)
 640 {
 641         struct spi_master *master;
 642         struct mxs_spi *spi;
 643         struct mxs_ssp *ssp;
 644
 645         master = platform_get_drvdata(pdev);
 646         spi = spi_master_get_devdata(master);
 647         ssp = &spi->ssp;
 648
 649         pm_runtime_disable(&pdev->dev);
 650         if (!pm_runtime_status_suspended(&pdev->dev))
 651                 mxs_spi_runtime_suspend(&pdev->dev);
 652
 653         dma_release_channel(ssp->dmach);
 654
 655         return 0;
 656 }
 657
 658 static struct platform_driver mxs_spi_driver = {
 659         .probe  = mxs_spi_probe,
 660         .remove = mxs_spi_remove,
 661         .driver = {
 662                 .name   = DRIVER_NAME,
 663                 .of_match_table = mxs_spi_dt_ids,
 664                 .pm = &mxs_spi_pm,
 665         },
 666 };
 667
 668 module_platform_driver(mxs_spi_driver);
 669
 670 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
 671 MODULE_DESCRIPTION("MXS SPI master driver");
 672 MODULE_LICENSE("GPL");
 673 MODULE_ALIAS("platform:mxs-spi");