drivers/spi/spi-stm32-qspi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
   4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
   5  */
   6 #include <linux/bitfield.h>
   7 #include <linux/clk.h>
   8 #include <linux/errno.h>
   9 #include <linux/io.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/module.h>
  13 #include <linux/mutex.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/reset.h>
  18 #include <linux/sizes.h>
  19 #include <linux/spi/spi-mem.h>
  20
  21 #define QSPI_CR                 0x00
  22 #define CR_EN                   BIT(0)
  23 #define CR_ABORT                BIT(1)
  24 #define CR_DMAEN                BIT(2)
  25 #define CR_TCEN                 BIT(3)
  26 #define CR_SSHIFT               BIT(4)
  27 #define CR_DFM                  BIT(6)
  28 #define CR_FSEL                 BIT(7)
  29 #define CR_FTHRES_MASK          GENMASK(12, 8)
  30 #define CR_TEIE                 BIT(16)
  31 #define CR_TCIE                 BIT(17)
  32 #define CR_FTIE                 BIT(18)
  33 #define CR_SMIE                 BIT(19)
  34 #define CR_TOIE                 BIT(20)
  35 #define CR_PRESC_MASK           GENMASK(31, 24)
  36
  37 #define QSPI_DCR                0x04
  38 #define DCR_FSIZE_MASK          GENMASK(20, 16)
  39
  40 #define QSPI_SR                 0x08
  41 #define SR_TEF                  BIT(0)
  42 #define SR_TCF                  BIT(1)
  43 #define SR_FTF                  BIT(2)
  44 #define SR_SMF                  BIT(3)
  45 #define SR_TOF                  BIT(4)
  46 #define SR_BUSY                 BIT(5)
  47 #define SR_FLEVEL_MASK          GENMASK(13, 8)
  48
  49 #define QSPI_FCR                0x0c
  50 #define FCR_CTEF                BIT(0)
  51 #define FCR_CTCF                BIT(1)
  52
  53 #define QSPI_DLR                0x10
  54
  55 #define QSPI_CCR                0x14
  56 #define CCR_INST_MASK           GENMASK(7, 0)
  57 #define CCR_IMODE_MASK          GENMASK(9, 8)
  58 #define CCR_ADMODE_MASK         GENMASK(11, 10)
  59 #define CCR_ADSIZE_MASK         GENMASK(13, 12)
  60 #define CCR_DCYC_MASK           GENMASK(22, 18)
  61 #define CCR_DMODE_MASK          GENMASK(25, 24)
  62 #define CCR_FMODE_MASK          GENMASK(27, 26)
  63 #define CCR_FMODE_INDW          (0U << 26)
  64 #define CCR_FMODE_INDR          (1U << 26)
  65 #define CCR_FMODE_APM           (2U << 26)
  66 #define CCR_FMODE_MM            (3U << 26)
  67 #define CCR_BUSWIDTH_0          0x0
  68 #define CCR_BUSWIDTH_1          0x1
  69 #define CCR_BUSWIDTH_2          0x2
  70 #define CCR_BUSWIDTH_4          0x3
  71
  72 #define QSPI_AR                 0x18
  73 #define QSPI_ABR                0x1c
  74 #define QSPI_DR                 0x20
  75 #define QSPI_PSMKR              0x24
  76 #define QSPI_PSMAR              0x28
  77 #define QSPI_PIR                0x2c
  78 #define QSPI_LPTR               0x30
  79 #define LPTR_DFT_TIMEOUT        0x10
  80
  81 #define STM32_QSPI_MAX_MMAP_SZ  SZ_256M
  82 #define STM32_QSPI_MAX_NORCHIP  2
  83
  84 #define STM32_FIFO_TIMEOUT_US 30000
  85 #define STM32_BUSY_TIMEOUT_US 100000
  86 #define STM32_ABT_TIMEOUT_US 100000
  87
  88 struct stm32_qspi_flash {
  89         struct stm32_qspi *qspi;
  90         u32 cs;
  91         u32 presc;
  92 };
  93
  94 struct stm32_qspi {
  95         struct device *dev;
  96         void __iomem *io_base;
  97         void __iomem *mm_base;
  98         resource_size_t mm_size;
  99         struct clk *clk;
 100         u32 clk_rate;
 101         struct stm32_qspi_flash flash[STM32_QSPI_MAX_NORCHIP];
 102         struct completion data_completion;
 103         u32 fmode;
 104
 105         /*
 106          * to protect device configuration, could be different between
 107          * 2 flash access (bk1, bk2)
 108          */
 109         struct mutex lock;
 110 };
 111
 112 static irqreturn_t stm32_qspi_irq(int irq, void *dev_id)
 113 {
 114         struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id;
 115         u32 cr, sr;
 116
 117         sr = readl_relaxed(qspi->io_base + QSPI_SR);
 118
 119         if (sr & (SR_TEF | SR_TCF)) {
 120                 /* disable irq */
 121                 cr = readl_relaxed(qspi->io_base + QSPI_CR);
 122                 cr &= ~CR_TCIE & ~CR_TEIE;
 123                 writel_relaxed(cr, qspi->io_base + QSPI_CR);
 124                 complete(&qspi->data_completion);
 125         }
 126
 127         return IRQ_HANDLED;
 128 }
 129
 130 static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
 131 {
 132         *val = readb_relaxed(addr);
 133 }
 134
 135 static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
 136 {
 137         writeb_relaxed(*val, addr);
 138 }
 139
 140 static int stm32_qspi_tx_poll(struct stm32_qspi *qspi,
 141                               const struct spi_mem_op *op)
 142 {
 143         void (*tx_fifo)(u8 *val, void __iomem *addr);
 144         u32 len = op->data.nbytes, sr;
 145         u8 *buf;
 146         int ret;
 147
 148         if (op->data.dir == SPI_MEM_DATA_IN) {
 149                 tx_fifo = stm32_qspi_read_fifo;
 150                 buf = op->data.buf.in;
 151
 152         } else {
 153                 tx_fifo = stm32_qspi_write_fifo;
 154                 buf = (u8 *)op->data.buf.out;
 155         }
 156
 157         while (len--) {
 158                 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR,
 159                                                         sr, (sr & SR_FTF), 1,
 160                                                         STM32_FIFO_TIMEOUT_US);
 161                 if (ret) {
 162                         dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n",
 163                                 len, sr);
 164                         return ret;
 165                 }
 166                 tx_fifo(buf++, qspi->io_base + QSPI_DR);
 167         }
 168
 169         return 0;
 170 }
 171
 172 static int stm32_qspi_tx_mm(struct stm32_qspi *qspi,
 173                             const struct spi_mem_op *op)
 174 {
 175         memcpy_fromio(op->data.buf.in, qspi->mm_base + op->addr.val,
 176                       op->data.nbytes);
 177         return 0;
 178 }
 179
 180 static int stm32_qspi_tx(struct stm32_qspi *qspi, const struct spi_mem_op *op)
 181 {
 182         if (!op->data.nbytes)
 183                 return 0;
 184
 185         if (qspi->fmode == CCR_FMODE_MM)
 186                 return stm32_qspi_tx_mm(qspi, op);
 187
 188         return stm32_qspi_tx_poll(qspi, op);
 189 }
 190
 191 static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi)
 192 {
 193         u32 sr;
 194
 195         return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr,
 196                                                  !(sr & SR_BUSY), 1,
 197                                                  STM32_BUSY_TIMEOUT_US);
 198 }
 199
 200 static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi,
 201                                const struct spi_mem_op *op)
 202 {
 203         u32 cr, sr;
 204         int err = 0;
 205
 206         if (!op->data.nbytes)
 207                 return stm32_qspi_wait_nobusy(qspi);
 208
 209         if (readl_relaxed(qspi->io_base + QSPI_SR) & SR_TCF)
 210                 goto out;
 211
 212         reinit_completion(&qspi->data_completion);
 213         cr = readl_relaxed(qspi->io_base + QSPI_CR);
 214         writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR);
 215
 216         if (!wait_for_completion_interruptible_timeout(&qspi->data_completion,
 217                                                 msecs_to_jiffies(1000))) {
 218                 err = -ETIMEDOUT;
 219         } else {
 220                 sr = readl_relaxed(qspi->io_base + QSPI_SR);
 221                 if (sr & SR_TEF)
 222                         err = -EIO;
 223         }
 224
 225 out:
 226         /* clear flags */
 227         writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR);
 228
 229         return err;
 230 }
 231
 232 static int stm32_qspi_get_mode(struct stm32_qspi *qspi, u8 buswidth)
 233 {
 234         if (buswidth == 4)
 235                 return CCR_BUSWIDTH_4;
 236
 237         return buswidth;
 238 }
 239
 240 static int stm32_qspi_send(struct spi_mem *mem, const struct spi_mem_op *op)
 241 {
 242         struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
 243         struct stm32_qspi_flash *flash = &qspi->flash[mem->spi->chip_select];
 244         u32 ccr, cr, addr_max;
 245         int timeout, err = 0;
 246
 247         dev_dbg(qspi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
 248                 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
 249                 op->dummy.buswidth, op->data.buswidth,
 250                 op->addr.val, op->data.nbytes);
 251
 252         err = stm32_qspi_wait_nobusy(qspi);
 253         if (err)
 254                 goto abort;
 255
 256         addr_max = op->addr.val + op->data.nbytes + 1;
 257
 258         if (op->data.dir == SPI_MEM_DATA_IN) {
 259                 if (addr_max < qspi->mm_size &&
 260                     op->addr.buswidth)
 261                         qspi->fmode = CCR_FMODE_MM;
 262                 else
 263                         qspi->fmode = CCR_FMODE_INDR;
 264         } else {
 265                 qspi->fmode = CCR_FMODE_INDW;
 266         }
 267
 268         cr = readl_relaxed(qspi->io_base + QSPI_CR);
 269         cr &= ~CR_PRESC_MASK & ~CR_FSEL;
 270         cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc);
 271         cr |= FIELD_PREP(CR_FSEL, flash->cs);
 272         writel_relaxed(cr, qspi->io_base + QSPI_CR);
 273
 274         if (op->data.nbytes)
 275                 writel_relaxed(op->data.nbytes - 1,
 276                                qspi->io_base + QSPI_DLR);
 277         else
 278                 qspi->fmode = CCR_FMODE_INDW;
 279
 280         ccr = qspi->fmode;
 281         ccr |= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode);
 282         ccr |= FIELD_PREP(CCR_IMODE_MASK,
 283                           stm32_qspi_get_mode(qspi, op->cmd.buswidth));
 284
 285         if (op->addr.nbytes) {
 286                 ccr |= FIELD_PREP(CCR_ADMODE_MASK,
 287                                   stm32_qspi_get_mode(qspi, op->addr.buswidth));
 288                 ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1);
 289         }
 290
 291         if (op->dummy.buswidth && op->dummy.nbytes)
 292                 ccr |= FIELD_PREP(CCR_DCYC_MASK,
 293                                   op->dummy.nbytes * 8 / op->dummy.buswidth);
 294
 295         if (op->data.nbytes) {
 296                 ccr |= FIELD_PREP(CCR_DMODE_MASK,
 297                                   stm32_qspi_get_mode(qspi, op->data.buswidth));
 298         }
 299
 300         writel_relaxed(ccr, qspi->io_base + QSPI_CCR);
 301
 302         if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM)
 303                 writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR);
 304
 305         err = stm32_qspi_tx(qspi, op);
 306
 307         /*
 308          * Abort in:
 309          * -error case
 310          * -read memory map: prefetching must be stopped if we read the last
 311          *  byte of device (device size - fifo size). like device size is not
 312          *  knows, the prefetching is always stop.
 313          */
 314         if (err || qspi->fmode == CCR_FMODE_MM)
 315                 goto abort;
 316
 317         /* wait end of tx in indirect mode */
 318         err = stm32_qspi_wait_cmd(qspi, op);
 319         if (err)
 320                 goto abort;
 321
 322         return 0;
 323
 324 abort:
 325         cr = readl_relaxed(qspi->io_base + QSPI_CR) | CR_ABORT;
 326         writel_relaxed(cr, qspi->io_base + QSPI_CR);
 327
 328         /* wait clear of abort bit by hw */
 329         timeout = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_CR,
 330                                                     cr, !(cr & CR_ABORT), 1,
 331                                                     STM32_ABT_TIMEOUT_US);
 332
 333         writel_relaxed(FCR_CTCF, qspi->io_base + QSPI_FCR);
 334
 335         if (err || timeout)
 336                 dev_err(qspi->dev, "%s err:%d abort timeout:%d\n",
 337                         __func__, err, timeout);
 338
 339         return err;
 340 }
 341
 342 static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
 343 {
 344         struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
 345         int ret;
 346
 347         mutex_lock(&qspi->lock);
 348         ret = stm32_qspi_send(mem, op);
 349         mutex_unlock(&qspi->lock);
 350
 351         return ret;
 352 }
 353
 354 static int stm32_qspi_setup(struct spi_device *spi)
 355 {
 356         struct spi_controller *ctrl = spi->master;
 357         struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl);
 358         struct stm32_qspi_flash *flash;
 359         u32 cr, presc;
 360
 361         if (ctrl->busy)
 362                 return -EBUSY;
 363
 364         if (!spi->max_speed_hz)
 365                 return -EINVAL;
 366
 367         presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1;
 368
 369         flash = &qspi->flash[spi->chip_select];
 370         flash->qspi = qspi;
 371         flash->cs = spi->chip_select;
 372         flash->presc = presc;
 373
 374         mutex_lock(&qspi->lock);
 375         writel_relaxed(LPTR_DFT_TIMEOUT, qspi->io_base + QSPI_LPTR);
 376         cr = FIELD_PREP(CR_FTHRES_MASK, 3) | CR_TCEN | CR_SSHIFT | CR_EN;
 377         writel_relaxed(cr, qspi->io_base + QSPI_CR);
 378
 379         /* set dcr fsize to max address */
 380         writel_relaxed(DCR_FSIZE_MASK, qspi->io_base + QSPI_DCR);
 381         mutex_unlock(&qspi->lock);
 382
 383         return 0;
 384 }
 385
 386 /*
 387  * no special host constraint, so use default spi_mem_default_supports_op
 388  * to check supported mode.
 389  */
 390 static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
 391         .exec_op = stm32_qspi_exec_op,
 392 };
 393
 394 static void stm32_qspi_release(struct stm32_qspi *qspi)
 395 {
 396         /* disable qspi */
 397         writel_relaxed(0, qspi->io_base + QSPI_CR);
 398         mutex_destroy(&qspi->lock);
 399         clk_disable_unprepare(qspi->clk);
 400 }
 401
 402 static int stm32_qspi_probe(struct platform_device *pdev)
 403 {
 404         struct device *dev = &pdev->dev;
 405         struct spi_controller *ctrl;
 406         struct reset_control *rstc;
 407         struct stm32_qspi *qspi;
 408         struct resource *res;
 409         int ret, irq;
 410
 411         ctrl = spi_alloc_master(dev, sizeof(*qspi));
 412         if (!ctrl)
 413                 return -ENOMEM;
 414
 415         qspi = spi_controller_get_devdata(ctrl);
 416
 417         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi");
 418         qspi->io_base = devm_ioremap_resource(dev, res);
 419         if (IS_ERR(qspi->io_base))
 420                 return PTR_ERR(qspi->io_base);
 421
 422         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm");
 423         qspi->mm_base = devm_ioremap_resource(dev, res);
 424         if (IS_ERR(qspi->mm_base))
 425                 return PTR_ERR(qspi->mm_base);
 426
 427         qspi->mm_size = resource_size(res);
 428         if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ)
 429                 return -EINVAL;
 430
 431         irq = platform_get_irq(pdev, 0);
 432         ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0,
 433                                dev_name(dev), qspi);
 434         if (ret) {
 435                 dev_err(dev, "failed to request irq\n");
 436                 return ret;
 437         }
 438
 439         init_completion(&qspi->data_completion);
 440
 441         qspi->clk = devm_clk_get(dev, NULL);
 442         if (IS_ERR(qspi->clk))
 443                 return PTR_ERR(qspi->clk);
 444
 445         qspi->clk_rate = clk_get_rate(qspi->clk);
 446         if (!qspi->clk_rate)
 447                 return -EINVAL;
 448
 449         ret = clk_prepare_enable(qspi->clk);
 450         if (ret) {
 451                 dev_err(dev, "can not enable the clock\n");
 452                 return ret;
 453         }
 454
 455         rstc = devm_reset_control_get_exclusive(dev, NULL);
 456         if (!IS_ERR(rstc)) {
 457                 reset_control_assert(rstc);
 458                 udelay(2);
 459                 reset_control_deassert(rstc);
 460         }
 461
 462         qspi->dev = dev;
 463         platform_set_drvdata(pdev, qspi);
 464         mutex_init(&qspi->lock);
 465
 466         ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD
 467                 | SPI_TX_DUAL | SPI_TX_QUAD;
 468         ctrl->setup = stm32_qspi_setup;
 469         ctrl->bus_num = -1;
 470         ctrl->mem_ops = &stm32_qspi_mem_ops;
 471         ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP;
 472         ctrl->dev.of_node = dev->of_node;
 473
 474         ret = devm_spi_register_master(dev, ctrl);
 475         if (ret)
 476                 goto err_spi_register;
 477
 478         return 0;
 479
 480 err_spi_register:
 481         stm32_qspi_release(qspi);
 482
 483         return ret;
 484 }
 485
 486 static int stm32_qspi_remove(struct platform_device *pdev)
 487 {
 488         struct stm32_qspi *qspi = platform_get_drvdata(pdev);
 489
 490         stm32_qspi_release(qspi);
 491         return 0;
 492 }
 493
 494 static const struct of_device_id stm32_qspi_match[] = {
 495         {.compatible = "st,stm32f469-qspi"},
 496         {}
 497 };
 498 MODULE_DEVICE_TABLE(of, stm32_qspi_match);
 499
 500 static struct platform_driver stm32_qspi_driver = {
 501         .probe  = stm32_qspi_probe,
 502         .remove = stm32_qspi_remove,
 503         .driver = {
 504                 .name = "stm32-qspi",
 505                 .of_match_table = stm32_qspi_match,
 506         },
 507 };
 508 module_platform_driver(stm32_qspi_driver);
 509
 510 MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
 511 MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver");
 512 MODULE_LICENSE("GPL v2");