| blob | 67874b82a4edf318ae3718ae6137393140405586 |
1 config ARM
2 bool
3 default y
4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_WANT_IPC_PARSE_VERSION
8 select BUILDTIME_EXTABLE_SORT if MMU
9 select CPU_PM if (SUSPEND || CPU_IDLE)
10 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
11 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
12 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
13 select GENERIC_IRQ_PROBE
14 select GENERIC_IRQ_SHOW
15 select GENERIC_PCI_IOMAP
16 select GENERIC_SMP_IDLE_THREAD
17 select GENERIC_STRNCPY_FROM_USER
18 select GENERIC_STRNLEN_USER
19 select HARDIRQS_SW_RESEND
20 select HAVE_AOUT
21 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
22 select HAVE_ARCH_KGDB
23 select HAVE_ARCH_SECCOMP_FILTER
24 select HAVE_ARCH_TRACEHOOK
25 select HAVE_BPF_JIT
26 select HAVE_C_RECORDMCOUNT
27 select HAVE_DEBUG_KMEMLEAK
28 select HAVE_DMA_API_DEBUG
29 select HAVE_DMA_ATTRS
30 select HAVE_DMA_CONTIGUOUS if MMU
31 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
32 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
33 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
34 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
35 select HAVE_GENERIC_DMA_COHERENT
36 select HAVE_GENERIC_HARDIRQS
37 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
38 select HAVE_IDE if PCI || ISA || PCMCIA
39 select HAVE_IRQ_WORK
40 select HAVE_KERNEL_GZIP
41 select HAVE_KERNEL_LZMA
42 select HAVE_KERNEL_LZO
43 select HAVE_KERNEL_XZ
44 select HAVE_KPROBES if !XIP_KERNEL
45 select HAVE_KRETPROBES if (HAVE_KPROBES)
46 select HAVE_MEMBLOCK
47 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
48 select HAVE_PERF_EVENTS
49 select HAVE_REGS_AND_STACK_ACCESS_API
50 select HAVE_SYSCALL_TRACEPOINTS
51 select HAVE_UID16
52 select KTIME_SCALAR
53 select PERF_USE_VMALLOC
54 select RTC_LIB
55 select SYS_SUPPORTS_APM_EMULATION
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select MODULES_USE_ELF_REL
58 select CLONE_BACKWARDS
59 help
60 The ARM series is a line of low-power-consumption RISC chip designs
61 licensed by ARM Ltd and targeted at embedded applications and
62 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
63 manufactured, but legacy ARM-based PC hardware remains popular in
64 Europe. There is an ARM Linux project with a web page at
65 <http://www.arm.linux.org.uk/>.
67 config ARM_HAS_SG_CHAIN
68 bool
70 config NEED_SG_DMA_LENGTH
71 bool
73 config ARM_DMA_USE_IOMMU
74 bool
75 select ARM_HAS_SG_CHAIN
76 select NEED_SG_DMA_LENGTH
78 config HAVE_PWM
79 bool
81 config MIGHT_HAVE_PCI
82 bool
84 config SYS_SUPPORTS_APM_EMULATION
85 bool
87 config GENERIC_GPIO
88 bool
90 config HAVE_TCM
91 bool
92 select GENERIC_ALLOCATOR
94 config HAVE_PROC_CPU
95 bool
97 config NO_IOPORT
98 bool
100 config EISA
101 bool
102 ---help---
103 The Extended Industry Standard Architecture (EISA) bus was
104 developed as an open alternative to the IBM MicroChannel bus.
106 The EISA bus provided some of the features of the IBM MicroChannel
107 bus while maintaining backward compatibility with cards made for
108 the older ISA bus. The EISA bus saw limited use between 1988 and
109 1995 when it was made obsolete by the PCI bus.
111 Say Y here if you are building a kernel for an EISA-based machine.
113 Otherwise, say N.
115 config SBUS
116 bool
118 config STACKTRACE_SUPPORT
119 bool
120 default y
122 config HAVE_LATENCYTOP_SUPPORT
123 bool
124 depends on !SMP
125 default y
127 config LOCKDEP_SUPPORT
128 bool
129 default y
131 config TRACE_IRQFLAGS_SUPPORT
132 bool
133 default y
135 config RWSEM_GENERIC_SPINLOCK
136 bool
137 default y
139 config RWSEM_XCHGADD_ALGORITHM
140 bool
142 config ARCH_HAS_ILOG2_U32
143 bool
145 config ARCH_HAS_ILOG2_U64
146 bool
148 config ARCH_HAS_CPUFREQ
149 bool
150 help
151 Internal node to signify that the ARCH has CPUFREQ support
152 and that the relevant menu configurations are displayed for
153 it.
155 config GENERIC_HWEIGHT
156 bool
157 default y
159 config GENERIC_CALIBRATE_DELAY
160 bool
161 default y
163 config ARCH_MAY_HAVE_PC_FDC
164 bool
166 config ZONE_DMA
167 bool
169 config NEED_DMA_MAP_STATE
170 def_bool y
172 config ARCH_HAS_DMA_SET_COHERENT_MASK
173 bool
175 config GENERIC_ISA_DMA
176 bool
178 config FIQ
179 bool
181 config NEED_RET_TO_USER
182 bool
184 config ARCH_MTD_XIP
185 bool
187 config VECTORS_BASE
188 hex
189 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
190 default DRAM_BASE if REMAP_VECTORS_TO_RAM
191 default 0x00000000
192 help
193 The base address of exception vectors.
195 config ARM_PATCH_PHYS_VIRT
196 bool "Patch physical to virtual translations at runtime" if EMBEDDED
197 default y
198 depends on !XIP_KERNEL && MMU
199 depends on !ARCH_REALVIEW || !SPARSEMEM
200 help
201 Patch phys-to-virt and virt-to-phys translation functions at
202 boot and module load time according to the position of the
203 kernel in system memory.
205 This can only be used with non-XIP MMU kernels where the base
206 of physical memory is at a 16MB boundary.
208 Only disable this option if you know that you do not require
209 this feature (eg, building a kernel for a single machine) and
210 you need to shrink the kernel to the minimal size.
212 config NEED_MACH_GPIO_H
213 bool
214 help
215 Select this when mach/gpio.h is required to provide special
216 definitions for this platform. The need for mach/gpio.h should
217 be avoided when possible.
219 config NEED_MACH_IO_H
220 bool
221 help
222 Select this when mach/io.h is required to provide special
223 definitions for this platform. The need for mach/io.h should
224 be avoided when possible.
226 config NEED_MACH_MEMORY_H
227 bool
228 help
229 Select this when mach/memory.h is required to provide special
230 definitions for this platform. The need for mach/memory.h should
231 be avoided when possible.
233 config PHYS_OFFSET
234 hex "Physical address of main memory" if MMU
235 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
236 default DRAM_BASE if !MMU
237 help
238 Please provide the physical address corresponding to the
239 location of main memory in your system.
241 config GENERIC_BUG
242 def_bool y
243 depends on BUG
245 source "init/Kconfig"
247 source "kernel/Kconfig.freezer"
249 menu "System Type"
251 config MMU
252 bool "MMU-based Paged Memory Management Support"
253 default y
254 help
255 Select if you want MMU-based virtualised addressing space
256 support by paged memory management. If unsure, say 'Y'.
258 #
259 # The "ARM system type" choice list is ordered alphabetically by option
260 # text. Please add new entries in the option alphabetic order.
261 #
262 choice
263 prompt "ARM system type"
264 default ARCH_MULTIPLATFORM
266 config ARCH_MULTIPLATFORM
267 bool "Allow multiple platforms to be selected"
268 depends on MMU
269 select ARM_PATCH_PHYS_VIRT
270 select AUTO_ZRELADDR
271 select COMMON_CLK
272 select MULTI_IRQ_HANDLER
273 select SPARSE_IRQ
274 select USE_OF
276 config ARCH_INTEGRATOR
277 bool "ARM Ltd. Integrator family"
278 select ARCH_HAS_CPUFREQ
279 select ARM_AMBA
280 select COMMON_CLK
281 select COMMON_CLK_VERSATILE
282 select GENERIC_CLOCKEVENTS
283 select HAVE_TCM
284 select ICST
285 select MULTI_IRQ_HANDLER
286 select NEED_MACH_MEMORY_H
287 select PLAT_VERSATILE
288 select SPARSE_IRQ
289 select VERSATILE_FPGA_IRQ
290 help
291 Support for ARM's Integrator platform.
293 config ARCH_REALVIEW
294 bool "ARM Ltd. RealView family"
295 select ARCH_WANT_OPTIONAL_GPIOLIB
296 select ARM_AMBA
297 select ARM_TIMER_SP804
298 select COMMON_CLK
299 select COMMON_CLK_VERSATILE
300 select GENERIC_CLOCKEVENTS
301 select GPIO_PL061 if GPIOLIB
302 select ICST
303 select NEED_MACH_MEMORY_H
304 select PLAT_VERSATILE
305 select PLAT_VERSATILE_CLCD
306 help
307 This enables support for ARM Ltd RealView boards.
309 config ARCH_VERSATILE
310 bool "ARM Ltd. Versatile family"
311 select ARCH_WANT_OPTIONAL_GPIOLIB
312 select ARM_AMBA
313 select ARM_TIMER_SP804
314 select ARM_VIC
315 select CLKDEV_LOOKUP
316 select GENERIC_CLOCKEVENTS
317 select HAVE_MACH_CLKDEV
318 select ICST
319 select PLAT_VERSATILE
320 select PLAT_VERSATILE_CLCD
321 select PLAT_VERSATILE_CLOCK
322 select VERSATILE_FPGA_IRQ
323 help
324 This enables support for ARM Ltd Versatile board.
326 config ARCH_AT91
327 bool "Atmel AT91"
328 select ARCH_REQUIRE_GPIOLIB
329 select CLKDEV_LOOKUP
330 select HAVE_CLK
331 select IRQ_DOMAIN
332 select NEED_MACH_GPIO_H
333 select NEED_MACH_IO_H if PCCARD
334 select PINCTRL
335 select PINCTRL_AT91 if USE_OF
336 help
337 This enables support for systems based on Atmel
338 AT91RM9200 and AT91SAM9* processors.
340 config ARCH_BCM2835
341 bool "Broadcom BCM2835 family"
342 select ARCH_REQUIRE_GPIOLIB
343 select ARM_AMBA
344 select ARM_ERRATA_411920
345 select ARM_TIMER_SP804
346 select CLKDEV_LOOKUP
347 select COMMON_CLK
348 select CPU_V6
349 select GENERIC_CLOCKEVENTS
350 select GENERIC_GPIO
351 select MULTI_IRQ_HANDLER
352 select PINCTRL
353 select PINCTRL_BCM2835
354 select SPARSE_IRQ
355 select USE_OF
356 help
357 This enables support for the Broadcom BCM2835 SoC. This SoC is
358 use in the Raspberry Pi, and Roku 2 devices.
360 config ARCH_CNS3XXX
361 bool "Cavium Networks CNS3XXX family"
362 select ARM_GIC
363 select CPU_V6K
364 select GENERIC_CLOCKEVENTS
365 select MIGHT_HAVE_CACHE_L2X0
366 select MIGHT_HAVE_PCI
367 select PCI_DOMAINS if PCI
368 help
369 Support for Cavium Networks CNS3XXX platform.
371 config ARCH_CLPS711X
372 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
373 select ARCH_REQUIRE_GPIOLIB
374 select AUTO_ZRELADDR
375 select CLKDEV_LOOKUP
376 select COMMON_CLK
377 select CPU_ARM720T
378 select GENERIC_CLOCKEVENTS
379 select MULTI_IRQ_HANDLER
380 select NEED_MACH_MEMORY_H
381 select SPARSE_IRQ
382 help
383 Support for Cirrus Logic 711x/721x/731x based boards.
385 config ARCH_GEMINI
386 bool "Cortina Systems Gemini"
387 select ARCH_REQUIRE_GPIOLIB
388 select ARCH_USES_GETTIMEOFFSET
389 select CPU_FA526
390 help
391 Support for the Cortina Systems Gemini family SoCs
393 config ARCH_SIRF
394 bool "CSR SiRF"
395 select ARCH_REQUIRE_GPIOLIB
396 select COMMON_CLK
397 select GENERIC_CLOCKEVENTS
398 select GENERIC_IRQ_CHIP
399 select MIGHT_HAVE_CACHE_L2X0
400 select NO_IOPORT
401 select PINCTRL
402 select PINCTRL_SIRF
403 select USE_OF
404 help
405 Support for CSR SiRFprimaII/Marco/Polo platforms
407 config ARCH_EBSA110
408 bool "EBSA-110"
409 select ARCH_USES_GETTIMEOFFSET
410 select CPU_SA110
411 select ISA
412 select NEED_MACH_IO_H
413 select NEED_MACH_MEMORY_H
414 select NO_IOPORT
415 help
416 This is an evaluation board for the StrongARM processor available
417 from Digital. It has limited hardware on-board, including an
418 Ethernet interface, two PCMCIA sockets, two serial ports and a
419 parallel port.
421 config ARCH_EP93XX
422 bool "EP93xx-based"
423 select ARCH_HAS_HOLES_MEMORYMODEL
424 select ARCH_REQUIRE_GPIOLIB
425 select ARCH_USES_GETTIMEOFFSET
426 select ARM_AMBA
427 select ARM_VIC
428 select CLKDEV_LOOKUP
429 select CPU_ARM920T
430 select NEED_MACH_MEMORY_H
431 help
432 This enables support for the Cirrus EP93xx series of CPUs.
434 config ARCH_FOOTBRIDGE
435 bool "FootBridge"
436 select CPU_SA110
437 select FOOTBRIDGE
438 select GENERIC_CLOCKEVENTS
439 select HAVE_IDE
440 select NEED_MACH_IO_H if !MMU
441 select NEED_MACH_MEMORY_H
442 help
443 Support for systems based on the DC21285 companion chip
444 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
446 config ARCH_MXS
447 bool "Freescale MXS-based"
448 select ARCH_REQUIRE_GPIOLIB
449 select CLKDEV_LOOKUP
450 select CLKSRC_MMIO
451 select COMMON_CLK
452 select GENERIC_CLOCKEVENTS
453 select HAVE_CLK_PREPARE
454 select MULTI_IRQ_HANDLER
455 select PINCTRL
456 select SPARSE_IRQ
457 select USE_OF
458 help
459 Support for Freescale MXS-based family of processors
461 config ARCH_NETX
462 bool "Hilscher NetX based"
463 select ARM_VIC
464 select CLKSRC_MMIO
465 select CPU_ARM926T
466 select GENERIC_CLOCKEVENTS
467 help
468 This enables support for systems based on the Hilscher NetX Soc
470 config ARCH_H720X
471 bool "Hynix HMS720x-based"
472 select ARCH_USES_GETTIMEOFFSET
473 select CPU_ARM720T
474 select ISA_DMA_API
475 help
476 This enables support for systems based on the Hynix HMS720x
478 config ARCH_IOP13XX
479 bool "IOP13xx-based"
480 depends on MMU
481 select ARCH_SUPPORTS_MSI
482 select CPU_XSC3
483 select NEED_MACH_MEMORY_H
484 select NEED_RET_TO_USER
485 select PCI
486 select PLAT_IOP
487 select VMSPLIT_1G
488 help
489 Support for Intel's IOP13XX (XScale) family of processors.
491 config ARCH_IOP32X
492 bool "IOP32x-based"
493 depends on MMU
494 select ARCH_REQUIRE_GPIOLIB
495 select CPU_XSCALE
496 select NEED_MACH_GPIO_H
497 select NEED_RET_TO_USER
498 select PCI
499 select PLAT_IOP
500 help
501 Support for Intel's 80219 and IOP32X (XScale) family of
502 processors.
504 config ARCH_IOP33X
505 bool "IOP33x-based"
506 depends on MMU
507 select ARCH_REQUIRE_GPIOLIB
508 select CPU_XSCALE
509 select NEED_MACH_GPIO_H
510 select NEED_RET_TO_USER
511 select PCI
512 select PLAT_IOP
513 help
514 Support for Intel's IOP33X (XScale) family of processors.
516 config ARCH_IXP4XX
517 bool "IXP4xx-based"
518 depends on MMU
519 select ARCH_HAS_DMA_SET_COHERENT_MASK
520 select ARCH_REQUIRE_GPIOLIB
521 select CLKSRC_MMIO
522 select CPU_XSCALE
523 select DMABOUNCE if PCI
524 select GENERIC_CLOCKEVENTS
525 select MIGHT_HAVE_PCI
526 select NEED_MACH_IO_H
527 help
528 Support for Intel's IXP4XX (XScale) family of processors.
530 config ARCH_DOVE
531 bool "Marvell Dove"
532 select ARCH_REQUIRE_GPIOLIB
533 select COMMON_CLK_DOVE
534 select CPU_V7
535 select GENERIC_CLOCKEVENTS
536 select MIGHT_HAVE_PCI
537 select PINCTRL
538 select PINCTRL_DOVE
539 select PLAT_ORION_LEGACY
540 select USB_ARCH_HAS_EHCI
541 help
542 Support for the Marvell Dove SoC 88AP510
544 config ARCH_KIRKWOOD
545 bool "Marvell Kirkwood"
546 select ARCH_REQUIRE_GPIOLIB
547 select CPU_FEROCEON
548 select GENERIC_CLOCKEVENTS
549 select PCI
550 select PCI_QUIRKS
551 select PINCTRL
552 select PINCTRL_KIRKWOOD
553 select PLAT_ORION_LEGACY
554 help
555 Support for the following Marvell Kirkwood series SoCs:
556 88F6180, 88F6192 and 88F6281.
558 config ARCH_MV78XX0
559 bool "Marvell MV78xx0"
560 select ARCH_REQUIRE_GPIOLIB
561 select CPU_FEROCEON
562 select GENERIC_CLOCKEVENTS
563 select PCI
564 select PLAT_ORION_LEGACY
565 help
566 Support for the following Marvell MV78xx0 series SoCs:
567 MV781x0, MV782x0.
569 config ARCH_ORION5X
570 bool "Marvell Orion"
571 depends on MMU
572 select ARCH_REQUIRE_GPIOLIB
573 select CPU_FEROCEON
574 select GENERIC_CLOCKEVENTS
575 select PCI
576 select PLAT_ORION_LEGACY
577 help
578 Support for the following Marvell Orion 5x series SoCs:
579 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
580 Orion-2 (5281), Orion-1-90 (6183).
582 config ARCH_MMP
583 bool "Marvell PXA168/910/MMP2"
584 depends on MMU
585 select ARCH_REQUIRE_GPIOLIB
586 select CLKDEV_LOOKUP
587 select GENERIC_ALLOCATOR
588 select GENERIC_CLOCKEVENTS
589 select GPIO_PXA
590 select IRQ_DOMAIN
591 select NEED_MACH_GPIO_H
592 select PINCTRL
593 select PLAT_PXA
594 select SPARSE_IRQ
595 help
596 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
598 config ARCH_KS8695
599 bool "Micrel/Kendin KS8695"
600 select ARCH_REQUIRE_GPIOLIB
601 select CLKSRC_MMIO
602 select CPU_ARM922T
603 select GENERIC_CLOCKEVENTS
604 select NEED_MACH_MEMORY_H
605 help
606 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
607 System-on-Chip devices.
609 config ARCH_W90X900
610 bool "Nuvoton W90X900 CPU"
611 select ARCH_REQUIRE_GPIOLIB
612 select CLKDEV_LOOKUP
613 select CLKSRC_MMIO
614 select CPU_ARM926T
615 select GENERIC_CLOCKEVENTS
616 help
617 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
618 At present, the w90x900 has been renamed nuc900, regarding
619 the ARM series product line, you can login the following
620 link address to know more.
622 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
623 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
625 config ARCH_LPC32XX
626 bool "NXP LPC32XX"
627 select ARCH_REQUIRE_GPIOLIB
628 select ARM_AMBA
629 select CLKDEV_LOOKUP
630 select CLKSRC_MMIO
631 select CPU_ARM926T
632 select GENERIC_CLOCKEVENTS
633 select HAVE_IDE
634 select HAVE_PWM
635 select USB_ARCH_HAS_OHCI
636 select USE_OF
637 help
638 Support for the NXP LPC32XX family of processors
640 config ARCH_TEGRA
641 bool "NVIDIA Tegra"
642 select ARCH_HAS_CPUFREQ
643 select CLKDEV_LOOKUP
644 select CLKSRC_MMIO
645 select COMMON_CLK
646 select GENERIC_CLOCKEVENTS
647 select GENERIC_GPIO
648 select HAVE_CLK
649 select HAVE_SMP
650 select MIGHT_HAVE_CACHE_L2X0
651 select SPARSE_IRQ
652 select USE_OF
653 help
654 This enables support for NVIDIA Tegra based systems (Tegra APX,
655 Tegra 6xx and Tegra 2 series).
657 config ARCH_PXA
658 bool "PXA2xx/PXA3xx-based"
659 depends on MMU
660 select ARCH_HAS_CPUFREQ
661 select ARCH_MTD_XIP
662 select ARCH_REQUIRE_GPIOLIB
663 select ARM_CPU_SUSPEND if PM
664 select AUTO_ZRELADDR
665 select CLKDEV_LOOKUP
666 select CLKSRC_MMIO
667 select GENERIC_CLOCKEVENTS
668 select GPIO_PXA
669 select HAVE_IDE
670 select MULTI_IRQ_HANDLER
671 select NEED_MACH_GPIO_H
672 select PLAT_PXA
673 select SPARSE_IRQ
674 help
675 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
677 config ARCH_MSM
678 bool "Qualcomm MSM"
679 select ARCH_REQUIRE_GPIOLIB
680 select CLKDEV_LOOKUP
681 select GENERIC_CLOCKEVENTS
682 select HAVE_CLK
683 help
684 Support for Qualcomm MSM/QSD based systems. This runs on the
685 apps processor of the MSM/QSD and depends on a shared memory
686 interface to the modem processor which runs the baseband
687 stack and controls some vital subsystems
688 (clock and power control, etc).
690 config ARCH_SHMOBILE
691 bool "Renesas SH-Mobile / R-Mobile"
692 select CLKDEV_LOOKUP
693 select GENERIC_CLOCKEVENTS
694 select HAVE_CLK
695 select HAVE_MACH_CLKDEV
696 select HAVE_SMP
697 select MIGHT_HAVE_CACHE_L2X0
698 select MULTI_IRQ_HANDLER
699 select NEED_MACH_MEMORY_H
700 select NO_IOPORT
701 select PM_GENERIC_DOMAINS if PM
702 select SPARSE_IRQ
703 help
704 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
706 config ARCH_RPC
707 bool "RiscPC"
708 select ARCH_ACORN
709 select ARCH_MAY_HAVE_PC_FDC
710 select ARCH_SPARSEMEM_ENABLE
711 select ARCH_USES_GETTIMEOFFSET
712 select FIQ
713 select HAVE_IDE
714 select HAVE_PATA_PLATFORM
715 select ISA_DMA_API
716 select NEED_MACH_IO_H
717 select NEED_MACH_MEMORY_H
718 select NO_IOPORT
719 help
720 On the Acorn Risc-PC, Linux can support the internal IDE disk and
721 CD-ROM interface, serial and parallel port, and the floppy drive.
723 config ARCH_SA1100
724 bool "SA1100-based"
725 select ARCH_HAS_CPUFREQ
726 select ARCH_MTD_XIP
727 select ARCH_REQUIRE_GPIOLIB
728 select ARCH_SPARSEMEM_ENABLE
729 select CLKDEV_LOOKUP
730 select CLKSRC_MMIO
731 select CPU_FREQ
732 select CPU_SA1100
733 select GENERIC_CLOCKEVENTS
734 select HAVE_IDE
735 select ISA
736 select NEED_MACH_GPIO_H
737 select NEED_MACH_MEMORY_H
738 select SPARSE_IRQ
739 help
740 Support for StrongARM 11x0 based boards.
742 config ARCH_S3C24XX
743 bool "Samsung S3C24XX SoCs"
744 select ARCH_HAS_CPUFREQ
745 select ARCH_USES_GETTIMEOFFSET
746 select CLKDEV_LOOKUP
747 select GENERIC_GPIO
748 select HAVE_CLK
749 select HAVE_S3C2410_I2C if I2C
750 select HAVE_S3C2410_WATCHDOG if WATCHDOG
751 select HAVE_S3C_RTC if RTC_CLASS
752 select NEED_MACH_GPIO_H
753 select NEED_MACH_IO_H
754 help
755 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
756 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
757 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
758 Samsung SMDK2410 development board (and derivatives).
760 config ARCH_S3C64XX
761 bool "Samsung S3C64XX"
762 select ARCH_HAS_CPUFREQ
763 select ARCH_REQUIRE_GPIOLIB
764 select ARCH_USES_GETTIMEOFFSET
765 select ARM_VIC
766 select CLKDEV_LOOKUP
767 select CPU_V6
768 select HAVE_CLK
769 select HAVE_S3C2410_I2C if I2C
770 select HAVE_S3C2410_WATCHDOG if WATCHDOG
771 select HAVE_TCM
772 select NEED_MACH_GPIO_H
773 select NO_IOPORT
774 select PLAT_SAMSUNG
775 select S3C_DEV_NAND
776 select S3C_GPIO_TRACK
777 select SAMSUNG_CLKSRC
778 select SAMSUNG_GPIOLIB_4BIT
779 select SAMSUNG_IRQ_VIC_TIMER
780 select USB_ARCH_HAS_OHCI
781 help
782 Samsung S3C64XX series based systems
784 config ARCH_S5P64X0
785 bool "Samsung S5P6440 S5P6450"
786 select CLKDEV_LOOKUP
787 select CLKSRC_MMIO
788 select CPU_V6
789 select GENERIC_CLOCKEVENTS
790 select GENERIC_GPIO
791 select HAVE_CLK
792 select HAVE_S3C2410_I2C if I2C
793 select HAVE_S3C2410_WATCHDOG if WATCHDOG
794 select HAVE_S3C_RTC if RTC_CLASS
795 select NEED_MACH_GPIO_H
796 help
797 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
798 SMDK6450.
800 config ARCH_S5PC100
801 bool "Samsung S5PC100"
802 select ARCH_USES_GETTIMEOFFSET
803 select CLKDEV_LOOKUP
804 select CPU_V7
805 select GENERIC_GPIO
806 select HAVE_CLK
807 select HAVE_S3C2410_I2C if I2C
808 select HAVE_S3C2410_WATCHDOG if WATCHDOG
809 select HAVE_S3C_RTC if RTC_CLASS
810 select NEED_MACH_GPIO_H
811 help
812 Samsung S5PC100 series based systems
814 config ARCH_S5PV210
815 bool "Samsung S5PV210/S5PC110"
816 select ARCH_HAS_CPUFREQ
817 select ARCH_HAS_HOLES_MEMORYMODEL
818 select ARCH_SPARSEMEM_ENABLE
819 select CLKDEV_LOOKUP
820 select CLKSRC_MMIO
821 select CPU_V7
822 select GENERIC_CLOCKEVENTS
823 select GENERIC_GPIO
824 select HAVE_CLK
825 select HAVE_S3C2410_I2C if I2C
826 select HAVE_S3C2410_WATCHDOG if WATCHDOG
827 select HAVE_S3C_RTC if RTC_CLASS
828 select NEED_MACH_GPIO_H
829 select NEED_MACH_MEMORY_H
830 help
831 Samsung S5PV210/S5PC110 series based systems
833 config ARCH_EXYNOS
834 bool "Samsung EXYNOS"
835 select ARCH_HAS_CPUFREQ
836 select ARCH_HAS_HOLES_MEMORYMODEL
837 select ARCH_SPARSEMEM_ENABLE
838 select CLKDEV_LOOKUP
839 select CPU_V7
840 select GENERIC_CLOCKEVENTS
841 select GENERIC_GPIO
842 select HAVE_CLK
843 select HAVE_S3C2410_I2C if I2C
844 select HAVE_S3C2410_WATCHDOG if WATCHDOG
845 select HAVE_S3C_RTC if RTC_CLASS
846 select NEED_MACH_GPIO_H
847 select NEED_MACH_MEMORY_H
848 help
849 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
851 config ARCH_SHARK
852 bool "Shark"
853 select ARCH_USES_GETTIMEOFFSET
854 select CPU_SA110
855 select ISA
856 select ISA_DMA
857 select NEED_MACH_MEMORY_H
858 select PCI
859 select ZONE_DMA
860 help
861 Support for the StrongARM based Digital DNARD machine, also known
862 as "Shark" (<http://www.shark-linux.de/shark.html>).
864 config ARCH_U300
865 bool "ST-Ericsson U300 Series"
866 depends on MMU
867 select ARCH_REQUIRE_GPIOLIB
868 select ARM_AMBA
869 select ARM_PATCH_PHYS_VIRT
870 select ARM_VIC
871 select CLKDEV_LOOKUP
872 select CLKSRC_MMIO
873 select COMMON_CLK
874 select CPU_ARM926T
875 select GENERIC_CLOCKEVENTS
876 select GENERIC_GPIO
877 select HAVE_TCM
878 select SPARSE_IRQ
879 help
880 Support for ST-Ericsson U300 series mobile platforms.
882 config ARCH_U8500
883 bool "ST-Ericsson U8500 Series"
884 depends on MMU
885 select ARCH_HAS_CPUFREQ
886 select ARCH_REQUIRE_GPIOLIB
887 select ARM_AMBA
888 select CLKDEV_LOOKUP
889 select CPU_V7
890 select GENERIC_CLOCKEVENTS
891 select HAVE_SMP
892 select MIGHT_HAVE_CACHE_L2X0
893 select SPARSE_IRQ
894 help
895 Support for ST-Ericsson's Ux500 architecture
897 config ARCH_NOMADIK
898 bool "STMicroelectronics Nomadik"
899 select ARCH_REQUIRE_GPIOLIB
900 select ARM_AMBA
901 select ARM_VIC
902 select COMMON_CLK
903 select CPU_ARM926T
904 select GENERIC_CLOCKEVENTS
905 select MIGHT_HAVE_CACHE_L2X0
906 select PINCTRL
907 select PINCTRL_STN8815
908 select SPARSE_IRQ
909 help
910 Support for the Nomadik platform by ST-Ericsson
912 config PLAT_SPEAR
913 bool "ST SPEAr"
914 select ARCH_HAS_CPUFREQ
915 select ARCH_REQUIRE_GPIOLIB
916 select ARM_AMBA
917 select CLKDEV_LOOKUP
918 select CLKSRC_MMIO
919 select COMMON_CLK
920 select GENERIC_CLOCKEVENTS
921 select HAVE_CLK
922 help
923 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
925 config ARCH_DAVINCI
926 bool "TI DaVinci"
927 select ARCH_HAS_HOLES_MEMORYMODEL
928 select ARCH_REQUIRE_GPIOLIB
929 select CLKDEV_LOOKUP
930 select GENERIC_ALLOCATOR
931 select GENERIC_CLOCKEVENTS
932 select GENERIC_IRQ_CHIP
933 select HAVE_IDE
934 select NEED_MACH_GPIO_H
935 select USE_OF
936 select ZONE_DMA
937 help
938 Support for TI's DaVinci platform.
940 config ARCH_OMAP
941 bool "TI OMAP"
942 depends on MMU
943 select ARCH_HAS_CPUFREQ
944 select ARCH_HAS_HOLES_MEMORYMODEL
945 select ARCH_REQUIRE_GPIOLIB
946 select CLKSRC_MMIO
947 select GENERIC_CLOCKEVENTS
948 select HAVE_CLK
949 help
950 Support for TI's OMAP platform (OMAP1/2/3/4).
952 config ARCH_VT8500_SINGLE
953 bool "VIA/WonderMedia 85xx"
954 select ARCH_HAS_CPUFREQ
955 select ARCH_REQUIRE_GPIOLIB
956 select CLKDEV_LOOKUP
957 select COMMON_CLK
958 select CPU_ARM926T
959 select GENERIC_CLOCKEVENTS
960 select GENERIC_GPIO
961 select HAVE_CLK
962 select MULTI_IRQ_HANDLER
963 select SPARSE_IRQ
964 select USE_OF
965 help
966 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
968 endchoice
970 menu "Multiple platform selection"
971 depends on ARCH_MULTIPLATFORM
973 comment "CPU Core family selection"
975 config ARCH_MULTI_V4
976 bool "ARMv4 based platforms (FA526, StrongARM)"
977 depends on !ARCH_MULTI_V6_V7
978 select ARCH_MULTI_V4_V5
980 config ARCH_MULTI_V4T
981 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
982 depends on !ARCH_MULTI_V6_V7
983 select ARCH_MULTI_V4_V5
985 config ARCH_MULTI_V5
986 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
987 depends on !ARCH_MULTI_V6_V7
988 select ARCH_MULTI_V4_V5
990 config ARCH_MULTI_V4_V5
991 bool
993 config ARCH_MULTI_V6
994 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
995 select ARCH_MULTI_V6_V7
996 select CPU_V6
998 config ARCH_MULTI_V7
999 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1000 default y
1001 select ARCH_MULTI_V6_V7
1002 select ARCH_VEXPRESS
1003 select CPU_V7
1005 config ARCH_MULTI_V6_V7
1006 bool
1008 config ARCH_MULTI_CPU_AUTO
1009 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1010 select ARCH_MULTI_V5
1012 endmenu
1014 #
1015 # This is sorted alphabetically by mach-* pathname. However, plat-*
1016 # Kconfigs may be included either alphabetically (according to the
1017 # plat- suffix) or along side the corresponding mach-* source.
1018 #
1019 source "arch/arm/mach-mvebu/Kconfig"
1021 source "arch/arm/mach-at91/Kconfig"
1023 source "arch/arm/mach-bcm/Kconfig"
1025 source "arch/arm/mach-clps711x/Kconfig"
1027 source "arch/arm/mach-cns3xxx/Kconfig"
1029 source "arch/arm/mach-davinci/Kconfig"
1031 source "arch/arm/mach-dove/Kconfig"
1033 source "arch/arm/mach-ep93xx/Kconfig"
1035 source "arch/arm/mach-footbridge/Kconfig"
1037 source "arch/arm/mach-gemini/Kconfig"
1039 source "arch/arm/mach-h720x/Kconfig"
1041 source "arch/arm/mach-highbank/Kconfig"
1043 source "arch/arm/mach-integrator/Kconfig"
1045 source "arch/arm/mach-iop32x/Kconfig"
1047 source "arch/arm/mach-iop33x/Kconfig"
1049 source "arch/arm/mach-iop13xx/Kconfig"
1051 source "arch/arm/mach-ixp4xx/Kconfig"
1053 source "arch/arm/mach-kirkwood/Kconfig"
1055 source "arch/arm/mach-ks8695/Kconfig"
1057 source "arch/arm/mach-msm/Kconfig"
1059 source "arch/arm/mach-mv78xx0/Kconfig"
1061 source "arch/arm/mach-imx/Kconfig"
1063 source "arch/arm/mach-mxs/Kconfig"
1065 source "arch/arm/mach-netx/Kconfig"
1067 source "arch/arm/mach-nomadik/Kconfig"
1069 source "arch/arm/plat-omap/Kconfig"
1071 source "arch/arm/mach-omap1/Kconfig"
1073 source "arch/arm/mach-omap2/Kconfig"
1075 source "arch/arm/mach-orion5x/Kconfig"
1077 source "arch/arm/mach-picoxcell/Kconfig"
1079 source "arch/arm/mach-pxa/Kconfig"
1080 source "arch/arm/plat-pxa/Kconfig"
1082 source "arch/arm/mach-mmp/Kconfig"
1084 source "arch/arm/mach-realview/Kconfig"
1086 source "arch/arm/mach-sa1100/Kconfig"
1088 source "arch/arm/plat-samsung/Kconfig"
1089 source "arch/arm/plat-s3c24xx/Kconfig"
1091 source "arch/arm/mach-socfpga/Kconfig"
1093 source "arch/arm/plat-spear/Kconfig"
1095 source "arch/arm/mach-s3c24xx/Kconfig"
1096 if ARCH_S3C24XX
1097 source "arch/arm/mach-s3c2412/Kconfig"
1098 source "arch/arm/mach-s3c2440/Kconfig"
1099 endif
1101 if ARCH_S3C64XX
1102 source "arch/arm/mach-s3c64xx/Kconfig"
1103 endif
1105 source "arch/arm/mach-s5p64x0/Kconfig"
1107 source "arch/arm/mach-s5pc100/Kconfig"
1109 source "arch/arm/mach-s5pv210/Kconfig"
1111 source "arch/arm/mach-exynos/Kconfig"
1113 source "arch/arm/mach-shmobile/Kconfig"
1115 source "arch/arm/mach-sunxi/Kconfig"
1117 source "arch/arm/mach-prima2/Kconfig"
1119 source "arch/arm/mach-tegra/Kconfig"
1121 source "arch/arm/mach-u300/Kconfig"
1123 source "arch/arm/mach-ux500/Kconfig"
1125 source "arch/arm/mach-versatile/Kconfig"
1127 source "arch/arm/mach-vexpress/Kconfig"
1128 source "arch/arm/plat-versatile/Kconfig"
1130 source "arch/arm/mach-vt8500/Kconfig"
1132 source "arch/arm/mach-w90x900/Kconfig"
1134 source "arch/arm/mach-zynq/Kconfig"
1136 # Definitions to make life easier
1137 config ARCH_ACORN
1138 bool
1140 config PLAT_IOP
1141 bool
1142 select GENERIC_CLOCKEVENTS
1144 config PLAT_ORION
1145 bool
1146 select CLKSRC_MMIO
1147 select COMMON_CLK
1148 select GENERIC_IRQ_CHIP
1149 select IRQ_DOMAIN
1151 config PLAT_ORION_LEGACY
1152 bool
1153 select PLAT_ORION
1155 config PLAT_PXA
1156 bool
1158 config PLAT_VERSATILE
1159 bool
1161 config ARM_TIMER_SP804
1162 bool
1163 select CLKSRC_MMIO
1164 select HAVE_SCHED_CLOCK
1166 source arch/arm/mm/Kconfig
1168 config ARM_NR_BANKS
1169 int
1170 default 16 if ARCH_EP93XX
1171 default 8
1173 config IWMMXT
1174 bool "Enable iWMMXt support"
1175 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1176 default y if PXA27x || PXA3xx || ARCH_MMP
1177 help
1178 Enable support for iWMMXt context switching at run time if
1179 running on a CPU that supports it.
1181 config XSCALE_PMU
1182 bool
1183 depends on CPU_XSCALE
1184 default y
1186 config MULTI_IRQ_HANDLER
1187 bool
1188 help
1189 Allow each machine to specify it's own IRQ handler at run time.
1191 if !MMU
1192 source "arch/arm/Kconfig-nommu"
1193 endif
1195 config ARM_ERRATA_326103
1196 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1197 depends on CPU_V6
1198 help
1199 Executing a SWP instruction to read-only memory does not set bit 11
1200 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1201 treat the access as a read, preventing a COW from occurring and
1202 causing the faulting task to livelock.
1204 config ARM_ERRATA_411920
1205 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1206 depends on CPU_V6 || CPU_V6K
1207 help
1208 Invalidation of the Instruction Cache operation can
1209 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1210 It does not affect the MPCore. This option enables the ARM Ltd.
1211 recommended workaround.
1213 config ARM_ERRATA_430973
1214 bool "ARM errata: Stale prediction on replaced interworking branch"
1215 depends on CPU_V7
1216 help
1217 This option enables the workaround for the 430973 Cortex-A8
1218 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1219 interworking branch is replaced with another code sequence at the
1220 same virtual address, whether due to self-modifying code or virtual
1221 to physical address re-mapping, Cortex-A8 does not recover from the
1222 stale interworking branch prediction. This results in Cortex-A8
1223 executing the new code sequence in the incorrect ARM or Thumb state.
1224 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1225 and also flushes the branch target cache at every context switch.
1226 Note that setting specific bits in the ACTLR register may not be
1227 available in non-secure mode.
1229 config ARM_ERRATA_458693
1230 bool "ARM errata: Processor deadlock when a false hazard is created"
1231 depends on CPU_V7
1232 depends on !ARCH_MULTIPLATFORM
1233 help
1234 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1235 erratum. For very specific sequences of memory operations, it is
1236 possible for a hazard condition intended for a cache line to instead
1237 be incorrectly associated with a different cache line. This false
1238 hazard might then cause a processor deadlock. The workaround enables
1239 the L1 caching of the NEON accesses and disables the PLD instruction
1240 in the ACTLR register. Note that setting specific bits in the ACTLR
1241 register may not be available in non-secure mode.
1243 config ARM_ERRATA_460075
1244 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1245 depends on CPU_V7
1246 depends on !ARCH_MULTIPLATFORM
1247 help
1248 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1249 erratum. Any asynchronous access to the L2 cache may encounter a
1250 situation in which recent store transactions to the L2 cache are lost
1251 and overwritten with stale memory contents from external memory. The
1252 workaround disables the write-allocate mode for the L2 cache via the
1253 ACTLR register. Note that setting specific bits in the ACTLR register
1254 may not be available in non-secure mode.
1256 config ARM_ERRATA_742230
1257 bool "ARM errata: DMB operation may be faulty"
1258 depends on CPU_V7 && SMP
1259 depends on !ARCH_MULTIPLATFORM
1260 help
1261 This option enables the workaround for the 742230 Cortex-A9
1262 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1263 between two write operations may not ensure the correct visibility
1264 ordering of the two writes. This workaround sets a specific bit in
1265 the diagnostic register of the Cortex-A9 which causes the DMB
1266 instruction to behave as a DSB, ensuring the correct behaviour of
1267 the two writes.
1269 config ARM_ERRATA_742231
1270 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1271 depends on CPU_V7 && SMP
1272 depends on !ARCH_MULTIPLATFORM
1273 help
1274 This option enables the workaround for the 742231 Cortex-A9
1275 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1276 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1277 accessing some data located in the same cache line, may get corrupted
1278 data due to bad handling of the address hazard when the line gets
1279 replaced from one of the CPUs at the same time as another CPU is
1280 accessing it. This workaround sets specific bits in the diagnostic
1281 register of the Cortex-A9 which reduces the linefill issuing
1282 capabilities of the processor.
1284 config PL310_ERRATA_588369
1285 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1286 depends on CACHE_L2X0
1287 help
1288 The PL310 L2 cache controller implements three types of Clean &
1289 Invalidate maintenance operations: by Physical Address
1290 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1291 They are architecturally defined to behave as the execution of a
1292 clean operation followed immediately by an invalidate operation,
1293 both performing to the same memory location. This functionality
1294 is not correctly implemented in PL310 as clean lines are not
1295 invalidated as a result of these operations.
1297 config ARM_ERRATA_720789
1298 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1299 depends on CPU_V7
1300 help
1301 This option enables the workaround for the 720789 Cortex-A9 (prior to
1302 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1303 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1304 As a consequence of this erratum, some TLB entries which should be
1305 invalidated are not, resulting in an incoherency in the system page
1306 tables. The workaround changes the TLB flushing routines to invalidate
1307 entries regardless of the ASID.
1309 config PL310_ERRATA_727915
1310 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1311 depends on CACHE_L2X0
1312 help
1313 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1314 operation (offset 0x7FC). This operation runs in background so that
1315 PL310 can handle normal accesses while it is in progress. Under very
1316 rare circumstances, due to this erratum, write data can be lost when
1317 PL310 treats a cacheable write transaction during a Clean &
1318 Invalidate by Way operation.
1320 config ARM_ERRATA_743622
1321 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1322 depends on CPU_V7
1323 depends on !ARCH_MULTIPLATFORM
1324 help
1325 This option enables the workaround for the 743622 Cortex-A9
1326 (r2p*) erratum. Under very rare conditions, a faulty
1327 optimisation in the Cortex-A9 Store Buffer may lead to data
1328 corruption. This workaround sets a specific bit in the diagnostic
1329 register of the Cortex-A9 which disables the Store Buffer
1330 optimisation, preventing the defect from occurring. This has no
1331 visible impact on the overall performance or power consumption of the
1332 processor.
1334 config ARM_ERRATA_751472
1335 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1336 depends on CPU_V7
1337 depends on !ARCH_MULTIPLATFORM
1338 help
1339 This option enables the workaround for the 751472 Cortex-A9 (prior
1340 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1341 completion of a following broadcasted operation if the second
1342 operation is received by a CPU before the ICIALLUIS has completed,
1343 potentially leading to corrupted entries in the cache or TLB.
1345 config PL310_ERRATA_753970
1346 bool "PL310 errata: cache sync operation may be faulty"
1347 depends on CACHE_PL310
1348 help
1349 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1351 Under some condition the effect of cache sync operation on
1352 the store buffer still remains when the operation completes.
1353 This means that the store buffer is always asked to drain and
1354 this prevents it from merging any further writes. The workaround
1355 is to replace the normal offset of cache sync operation (0x730)
1356 by another offset targeting an unmapped PL310 register 0x740.
1357 This has the same effect as the cache sync operation: store buffer
1358 drain and waiting for all buffers empty.
1360 config ARM_ERRATA_754322
1361 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1362 depends on CPU_V7
1363 help
1364 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1365 r3p*) erratum. A speculative memory access may cause a page table walk
1366 which starts prior to an ASID switch but completes afterwards. This
1367 can populate the micro-TLB with a stale entry which may be hit with
1368 the new ASID. This workaround places two dsb instructions in the mm
1369 switching code so that no page table walks can cross the ASID switch.
1371 config ARM_ERRATA_754327
1372 bool "ARM errata: no automatic Store Buffer drain"
1373 depends on CPU_V7 && SMP
1374 help
1375 This option enables the workaround for the 754327 Cortex-A9 (prior to
1376 r2p0) erratum. The Store Buffer does not have any automatic draining
1377 mechanism and therefore a livelock may occur if an external agent
1378 continuously polls a memory location waiting to observe an update.
1379 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1380 written polling loops from denying visibility of updates to memory.
1382 config ARM_ERRATA_364296
1383 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1384 depends on CPU_V6 && !SMP
1385 help
1386 This options enables the workaround for the 364296 ARM1136
1387 r0p2 erratum (possible cache data corruption with
1388 hit-under-miss enabled). It sets the undocumented bit 31 in
1389 the auxiliary control register and the FI bit in the control
1390 register, thus disabling hit-under-miss without putting the
1391 processor into full low interrupt latency mode. ARM11MPCore
1392 is not affected.
1394 config ARM_ERRATA_764369
1395 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1396 depends on CPU_V7 && SMP
1397 help
1398 This option enables the workaround for erratum 764369
1399 affecting Cortex-A9 MPCore with two or more processors (all
1400 current revisions). Under certain timing circumstances, a data
1401 cache line maintenance operation by MVA targeting an Inner
1402 Shareable memory region may fail to proceed up to either the
1403 Point of Coherency or to the Point of Unification of the
1404 system. This workaround adds a DSB instruction before the
1405 relevant cache maintenance functions and sets a specific bit
1406 in the diagnostic control register of the SCU.
1408 config PL310_ERRATA_769419
1409 bool "PL310 errata: no automatic Store Buffer drain"
1410 depends on CACHE_L2X0
1411 help
1412 On revisions of the PL310 prior to r3p2, the Store Buffer does
1413 not automatically drain. This can cause normal, non-cacheable
1414 writes to be retained when the memory system is idle, leading
1415 to suboptimal I/O performance for drivers using coherent DMA.
1416 This option adds a write barrier to the cpu_idle loop so that,
1417 on systems with an outer cache, the store buffer is drained
1418 explicitly.
1420 config ARM_ERRATA_775420
1421 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1422 depends on CPU_V7
1423 help
1424 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1425 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1426 operation aborts with MMU exception, it might cause the processor
1427 to deadlock. This workaround puts DSB before executing ISB if
1428 an abort may occur on cache maintenance.
1430 endmenu
1432 source "arch/arm/common/Kconfig"
1434 menu "Bus support"
1436 config ARM_AMBA
1437 bool
1439 config ISA
1440 bool
1441 help
1442 Find out whether you have ISA slots on your motherboard. ISA is the
1443 name of a bus system, i.e. the way the CPU talks to the other stuff
1444 inside your box. Other bus systems are PCI, EISA, MicroChannel
1445 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1446 newer boards don't support it. If you have ISA, say Y, otherwise N.
1448 # Select ISA DMA controller support
1449 config ISA_DMA
1450 bool
1451 select ISA_DMA_API
1453 # Select ISA DMA interface
1454 config ISA_DMA_API
1455 bool
1457 config PCI
1458 bool "PCI support" if MIGHT_HAVE_PCI
1459 help
1460 Find out whether you have a PCI motherboard. PCI is the name of a
1461 bus system, i.e. the way the CPU talks to the other stuff inside
1462 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1463 VESA. If you have PCI, say Y, otherwise N.
1465 config PCI_DOMAINS
1466 bool
1467 depends on PCI
1469 config PCI_NANOENGINE
1470 bool "BSE nanoEngine PCI support"
1471 depends on SA1100_NANOENGINE
1472 help
1473 Enable PCI on the BSE nanoEngine board.
1475 config PCI_SYSCALL
1476 def_bool PCI
1478 # Select the host bridge type
1479 config PCI_HOST_VIA82C505
1480 bool
1481 depends on PCI && ARCH_SHARK
1482 default y
1484 config PCI_HOST_ITE8152
1485 bool
1486 depends on PCI && MACH_ARMCORE
1487 default y
1488 select DMABOUNCE
1490 source "drivers/pci/Kconfig"
1492 source "drivers/pcmcia/Kconfig"
1494 endmenu
1496 menu "Kernel Features"
1498 config HAVE_SMP
1499 bool
1500 help
1501 This option should be selected by machines which have an SMP-
1502 capable CPU.
1504 The only effect of this option is to make the SMP-related
1505 options available to the user for configuration.
1507 config SMP
1508 bool "Symmetric Multi-Processing"
1509 depends on CPU_V6K || CPU_V7
1510 depends on GENERIC_CLOCKEVENTS
1511 depends on HAVE_SMP
1512 depends on MMU
1513 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1514 select USE_GENERIC_SMP_HELPERS
1515 help
1516 This enables support for systems with more than one CPU. If you have
1517 a system with only one CPU, like most personal computers, say N. If
1518 you have a system with more than one CPU, say Y.
1520 If you say N here, the kernel will run on single and multiprocessor
1521 machines, but will use only one CPU of a multiprocessor machine. If
1522 you say Y here, the kernel will run on many, but not all, single
1523 processor machines. On a single processor machine, the kernel will
1524 run faster if you say N here.
1526 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1527 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1528 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1530 If you don't know what to do here, say N.
1532 config SMP_ON_UP
1533 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1534 depends on EXPERIMENTAL
1535 depends on SMP && !XIP_KERNEL
1536 default y
1537 help
1538 SMP kernels contain instructions which fail on non-SMP processors.
1539 Enabling this option allows the kernel to modify itself to make
1540 these instructions safe. Disabling it allows about 1K of space
1541 savings.
1543 If you don't know what to do here, say Y.
1545 config ARM_CPU_TOPOLOGY
1546 bool "Support cpu topology definition"
1547 depends on SMP && CPU_V7
1548 default y
1549 help
1550 Support ARM cpu topology definition. The MPIDR register defines
1551 affinity between processors which is then used to describe the cpu
1552 topology of an ARM System.
1554 config SCHED_MC
1555 bool "Multi-core scheduler support"
1556 depends on ARM_CPU_TOPOLOGY
1557 help
1558 Multi-core scheduler support improves the CPU scheduler's decision
1559 making when dealing with multi-core CPU chips at a cost of slightly
1560 increased overhead in some places. If unsure say N here.
1562 config SCHED_SMT
1563 bool "SMT scheduler support"
1564 depends on ARM_CPU_TOPOLOGY
1565 help
1566 Improves the CPU scheduler's decision making when dealing with
1567 MultiThreading at a cost of slightly increased overhead in some
1568 places. If unsure say N here.
1570 config HAVE_ARM_SCU
1571 bool
1572 help
1573 This option enables support for the ARM system coherency unit
1575 config ARM_ARCH_TIMER
1576 bool "Architected timer support"
1577 depends on CPU_V7
1578 help
1579 This option enables support for the ARM architected timer
1581 config HAVE_ARM_TWD
1582 bool
1583 depends on SMP
1584 help
1585 This options enables support for the ARM timer and watchdog unit
1587 choice
1588 prompt "Memory split"
1589 default VMSPLIT_3G
1590 help
1591 Select the desired split between kernel and user memory.
1593 If you are not absolutely sure what you are doing, leave this
1594 option alone!
1596 config VMSPLIT_3G
1597 bool "3G/1G user/kernel split"
1598 config VMSPLIT_2G
1599 bool "2G/2G user/kernel split"
1600 config VMSPLIT_1G
1601 bool "1G/3G user/kernel split"
1602 endchoice
1604 config PAGE_OFFSET
1605 hex
1606 default 0x40000000 if VMSPLIT_1G
1607 default 0x80000000 if VMSPLIT_2G
1608 default 0xC0000000
1610 config NR_CPUS
1611 int "Maximum number of CPUs (2-32)"
1612 range 2 32
1613 depends on SMP
1614 default "4"
1616 config HOTPLUG_CPU
1617 bool "Support for hot-pluggable CPUs"
1618 depends on SMP && HOTPLUG
1619 help
1620 Say Y here to experiment with turning CPUs off and on. CPUs
1621 can be controlled through /sys/devices/system/cpu.
1623 config LOCAL_TIMERS
1624 bool "Use local timer interrupts"
1625 depends on SMP
1626 default y
1627 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1628 help
1629 Enable support for local timers on SMP platforms, rather then the
1630 legacy IPI broadcast method. Local timers allows the system
1631 accounting to be spread across the timer interval, preventing a
1632 "thundering herd" at every timer tick.
1634 config ARCH_NR_GPIO
1635 int
1636 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1637 default 355 if ARCH_U8500
1638 default 264 if MACH_H4700
1639 default 512 if SOC_OMAP5
1640 default 288 if ARCH_VT8500
1641 default 0
1642 help
1643 Maximum number of GPIOs in the system.
1645 If unsure, leave the default value.
1647 source kernel/Kconfig.preempt
1649 config HZ
1650 int
1651 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1652 ARCH_S5PV210 || ARCH_EXYNOS4
1653 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1654 default AT91_TIMER_HZ if ARCH_AT91
1655 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1656 default 100
1658 config THUMB2_KERNEL
1659 bool "Compile the kernel in Thumb-2 mode"
1660 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1661 select AEABI
1662 select ARM_ASM_UNIFIED
1663 select ARM_UNWIND
1664 help
1665 By enabling this option, the kernel will be compiled in
1666 Thumb-2 mode. A compiler/assembler that understand the unified
1667 ARM-Thumb syntax is needed.
1669 If unsure, say N.
1671 config THUMB2_AVOID_R_ARM_THM_JUMP11
1672 bool "Work around buggy Thumb-2 short branch relocations in gas"
1673 depends on THUMB2_KERNEL && MODULES
1674 default y
1675 help
1676 Various binutils versions can resolve Thumb-2 branches to
1677 locally-defined, preemptible global symbols as short-range "b.n"
1678 branch instructions.
1680 This is a problem, because there's no guarantee the final
1681 destination of the symbol, or any candidate locations for a
1682 trampoline, are within range of the branch. For this reason, the
1683 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1684 relocation in modules at all, and it makes little sense to add
1685 support.
1687 The symptom is that the kernel fails with an "unsupported
1688 relocation" error when loading some modules.
1690 Until fixed tools are available, passing
1691 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1692 code which hits this problem, at the cost of a bit of extra runtime
1693 stack usage in some cases.
1695 The problem is described in more detail at:
1696 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1698 Only Thumb-2 kernels are affected.
1700 Unless you are sure your tools don't have this problem, say Y.
1702 config ARM_ASM_UNIFIED
1703 bool
1705 config AEABI
1706 bool "Use the ARM EABI to compile the kernel"
1707 help
1708 This option allows for the kernel to be compiled using the latest
1709 ARM ABI (aka EABI). This is only useful if you are using a user
1710 space environment that is also compiled with EABI.
1712 Since there are major incompatibilities between the legacy ABI and
1713 EABI, especially with regard to structure member alignment, this
1714 option also changes the kernel syscall calling convention to
1715 disambiguate both ABIs and allow for backward compatibility support
1716 (selected with CONFIG_OABI_COMPAT).
1718 To use this you need GCC version 4.0.0 or later.
1720 config OABI_COMPAT
1721 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1722 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1723 default y
1724 help
1725 This option preserves the old syscall interface along with the
1726 new (ARM EABI) one. It also provides a compatibility layer to
1727 intercept syscalls that have structure arguments which layout
1728 in memory differs between the legacy ABI and the new ARM EABI
1729 (only for non "thumb" binaries). This option adds a tiny
1730 overhead to all syscalls and produces a slightly larger kernel.
1731 If you know you'll be using only pure EABI user space then you
1732 can say N here. If this option is not selected and you attempt
1733 to execute a legacy ABI binary then the result will be
1734 UNPREDICTABLE (in fact it can be predicted that it won't work
1735 at all). If in doubt say Y.
1737 config ARCH_HAS_HOLES_MEMORYMODEL
1738 bool
1740 config ARCH_SPARSEMEM_ENABLE
1741 bool
1743 config ARCH_SPARSEMEM_DEFAULT
1744 def_bool ARCH_SPARSEMEM_ENABLE
1746 config ARCH_SELECT_MEMORY_MODEL
1747 def_bool ARCH_SPARSEMEM_ENABLE
1749 config HAVE_ARCH_PFN_VALID
1750 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1752 config HIGHMEM
1753 bool "High Memory Support"
1754 depends on MMU
1755 help
1756 The address space of ARM processors is only 4 Gigabytes large
1757 and it has to accommodate user address space, kernel address
1758 space as well as some memory mapped IO. That means that, if you
1759 have a large amount of physical memory and/or IO, not all of the
1760 memory can be "permanently mapped" by the kernel. The physical
1761 memory that is not permanently mapped is called "high memory".
1763 Depending on the selected kernel/user memory split, minimum
1764 vmalloc space and actual amount of RAM, you may not need this
1765 option which should result in a slightly faster kernel.
1767 If unsure, say n.
1769 config HIGHPTE
1770 bool "Allocate 2nd-level pagetables from highmem"
1771 depends on HIGHMEM
1773 config HW_PERF_EVENTS
1774 bool "Enable hardware performance counter support for perf events"
1775 depends on PERF_EVENTS
1776 default y
1777 help
1778 Enable hardware performance counter support for perf events. If
1779 disabled, perf events will use software events only.
1781 source "mm/Kconfig"
1783 config FORCE_MAX_ZONEORDER
1784 int "Maximum zone order" if ARCH_SHMOBILE
1785 range 11 64 if ARCH_SHMOBILE
1786 default "12" if SOC_AM33XX
1787 default "9" if SA1111
1788 default "11"
1789 help
1790 The kernel memory allocator divides physically contiguous memory
1791 blocks into "zones", where each zone is a power of two number of
1792 pages. This option selects the largest power of two that the kernel
1793 keeps in the memory allocator. If you need to allocate very large
1794 blocks of physically contiguous memory, then you may need to
1795 increase this value.
1797 This config option is actually maximum order plus one. For example,
1798 a value of 11 means that the largest free memory block is 2^10 pages.
1800 config ALIGNMENT_TRAP
1801 bool
1802 depends on CPU_CP15_MMU
1803 default y if !ARCH_EBSA110
1804 select HAVE_PROC_CPU if PROC_FS
1805 help
1806 ARM processors cannot fetch/store information which is not
1807 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1808 address divisible by 4. On 32-bit ARM processors, these non-aligned
1809 fetch/store instructions will be emulated in software if you say
1810 here, which has a severe performance impact. This is necessary for
1811 correct operation of some network protocols. With an IP-only
1812 configuration it is safe to say N, otherwise say Y.
1814 config UACCESS_WITH_MEMCPY
1815 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1816 depends on MMU
1817 default y if CPU_FEROCEON
1818 help
1819 Implement faster copy_to_user and clear_user methods for CPU
1820 cores where a 8-word STM instruction give significantly higher
1821 memory write throughput than a sequence of individual 32bit stores.
1823 A possible side effect is a slight increase in scheduling latency
1824 between threads sharing the same address space if they invoke
1825 such copy operations with large buffers.
1827 However, if the CPU data cache is using a write-allocate mode,
1828 this option is unlikely to provide any performance gain.
1830 config SECCOMP
1831 bool
1832 prompt "Enable seccomp to safely compute untrusted bytecode"
1833 ---help---
1834 This kernel feature is useful for number crunching applications
1835 that may need to compute untrusted bytecode during their
1836 execution. By using pipes or other transports made available to
1837 the process as file descriptors supporting the read/write
1838 syscalls, it's possible to isolate those applications in
1839 their own address space using seccomp. Once seccomp is
1840 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1841 and the task is only allowed to execute a few safe syscalls
1842 defined by each seccomp mode.
1844 config CC_STACKPROTECTOR
1845 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1846 depends on EXPERIMENTAL
1847 help
1848 This option turns on the -fstack-protector GCC feature. This
1849 feature puts, at the beginning of functions, a canary value on
1850 the stack just before the return address, and validates
1851 the value just before actually returning. Stack based buffer
1852 overflows (that need to overwrite this return address) now also
1853 overwrite the canary, which gets detected and the attack is then
1854 neutralized via a kernel panic.
1855 This feature requires gcc version 4.2 or above.
1857 config XEN_DOM0
1858 def_bool y
1859 depends on XEN
1861 config XEN
1862 bool "Xen guest support on ARM (EXPERIMENTAL)"
1863 depends on EXPERIMENTAL && ARM && OF
1864 depends on CPU_V7 && !CPU_V6
1865 help
1866 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1868 endmenu
1870 menu "Boot options"
1872 config USE_OF
1873 bool "Flattened Device Tree support"
1874 select IRQ_DOMAIN
1875 select OF
1876 select OF_EARLY_FLATTREE
1877 help
1878 Include support for flattened device tree machine descriptions.
1880 config ATAGS
1881 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1882 default y
1883 help
1884 This is the traditional way of passing data to the kernel at boot
1885 time. If you are solely relying on the flattened device tree (or
1886 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1887 to remove ATAGS support from your kernel binary. If unsure,
1888 leave this to y.
1890 config DEPRECATED_PARAM_STRUCT
1891 bool "Provide old way to pass kernel parameters"
1892 depends on ATAGS
1893 help
1894 This was deprecated in 2001 and announced to live on for 5 years.
1895 Some old boot loaders still use this way.
1897 # Compressed boot loader in ROM. Yes, we really want to ask about
1898 # TEXT and BSS so we preserve their values in the config files.
1899 config ZBOOT_ROM_TEXT
1900 hex "Compressed ROM boot loader base address"
1901 default "0"
1902 help
1903 The physical address at which the ROM-able zImage is to be
1904 placed in the target. Platforms which normally make use of
1905 ROM-able zImage formats normally set this to a suitable
1906 value in their defconfig file.
1908 If ZBOOT_ROM is not enabled, this has no effect.
1910 config ZBOOT_ROM_BSS
1911 hex "Compressed ROM boot loader BSS address"
1912 default "0"
1913 help
1914 The base address of an area of read/write memory in the target
1915 for the ROM-able zImage which must be available while the
1916 decompressor is running. It must be large enough to hold the
1917 entire decompressed kernel plus an additional 128 KiB.
1918 Platforms which normally make use of ROM-able zImage formats
1919 normally set this to a suitable value in their defconfig file.
1921 If ZBOOT_ROM is not enabled, this has no effect.
1923 config ZBOOT_ROM
1924 bool "Compressed boot loader in ROM/flash"
1925 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1926 help
1927 Say Y here if you intend to execute your compressed kernel image
1928 (zImage) directly from ROM or flash. If unsure, say N.
1930 choice
1931 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1932 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1933 default ZBOOT_ROM_NONE
1934 help
1935 Include experimental SD/MMC loading code in the ROM-able zImage.
1936 With this enabled it is possible to write the ROM-able zImage
1937 kernel image to an MMC or SD card and boot the kernel straight
1938 from the reset vector. At reset the processor Mask ROM will load
1939 the first part of the ROM-able zImage which in turn loads the
1940 rest the kernel image to RAM.
1942 config ZBOOT_ROM_NONE
1943 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1944 help
1945 Do not load image from SD or MMC
1947 config ZBOOT_ROM_MMCIF
1948 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1949 help
1950 Load image from MMCIF hardware block.
1952 config ZBOOT_ROM_SH_MOBILE_SDHI
1953 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1954 help
1955 Load image from SDHI hardware block
1957 endchoice
1959 config ARM_APPENDED_DTB
1960 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1961 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1962 help
1963 With this option, the boot code will look for a device tree binary
1964 (DTB) appended to zImage
1965 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1967 This is meant as a backward compatibility convenience for those
1968 systems with a bootloader that can't be upgraded to accommodate
1969 the documented boot protocol using a device tree.
1971 Beware that there is very little in terms of protection against
1972 this option being confused by leftover garbage in memory that might
1973 look like a DTB header after a reboot if no actual DTB is appended
1974 to zImage. Do not leave this option active in a production kernel
1975 if you don't intend to always append a DTB. Proper passing of the
1976 location into r2 of a bootloader provided DTB is always preferable
1977 to this option.
1979 config ARM_ATAG_DTB_COMPAT
1980 bool "Supplement the appended DTB with traditional ATAG information"
1981 depends on ARM_APPENDED_DTB
1982 help
1983 Some old bootloaders can't be updated to a DTB capable one, yet
1984 they provide ATAGs with memory configuration, the ramdisk address,
1985 the kernel cmdline string, etc. Such information is dynamically
1986 provided by the bootloader and can't always be stored in a static
1987 DTB. To allow a device tree enabled kernel to be used with such
1988 bootloaders, this option allows zImage to extract the information
1989 from the ATAG list and store it at run time into the appended DTB.
1991 choice
1992 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1993 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1995 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1996 bool "Use bootloader kernel arguments if available"
1997 help
1998 Uses the command-line options passed by the boot loader instead of
1999 the device tree bootargs property. If the boot loader doesn't provide
2000 any, the device tree bootargs property will be used.
2002 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2003 bool "Extend with bootloader kernel arguments"
2004 help
2005 The command-line arguments provided by the boot loader will be
2006 appended to the the device tree bootargs property.
2008 endchoice
2010 config CMDLINE
2011 string "Default kernel command string"
2012 default ""
2013 help
2014 On some architectures (EBSA110 and CATS), there is currently no way
2015 for the boot loader to pass arguments to the kernel. For these
2016 architectures, you should supply some command-line options at build
2017 time by entering them here. As a minimum, you should specify the
2018 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2020 choice
2021 prompt "Kernel command line type" if CMDLINE != ""
2022 default CMDLINE_FROM_BOOTLOADER
2023 depends on ATAGS
2025 config CMDLINE_FROM_BOOTLOADER
2026 bool "Use bootloader kernel arguments if available"
2027 help
2028 Uses the command-line options passed by the boot loader. If
2029 the boot loader doesn't provide any, the default kernel command
2030 string provided in CMDLINE will be used.
2032 config CMDLINE_EXTEND
2033 bool "Extend bootloader kernel arguments"
2034 help
2035 The command-line arguments provided by the boot loader will be
2036 appended to the default kernel command string.
2038 config CMDLINE_FORCE
2039 bool "Always use the default kernel command string"
2040 help
2041 Always use the default kernel command string, even if the boot
2042 loader passes other arguments to the kernel.
2043 This is useful if you cannot or don't want to change the
2044 command-line options your boot loader passes to the kernel.
2045 endchoice
2047 config XIP_KERNEL
2048 bool "Kernel Execute-In-Place from ROM"
2049 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2050 help
2051 Execute-In-Place allows the kernel to run from non-volatile storage
2052 directly addressable by the CPU, such as NOR flash. This saves RAM
2053 space since the text section of the kernel is not loaded from flash
2054 to RAM. Read-write sections, such as the data section and stack,
2055 are still copied to RAM. The XIP kernel is not compressed since
2056 it has to run directly from flash, so it will take more space to
2057 store it. The flash address used to link the kernel object files,
2058 and for storing it, is configuration dependent. Therefore, if you
2059 say Y here, you must know the proper physical address where to
2060 store the kernel image depending on your own flash memory usage.
2062 Also note that the make target becomes "make xipImage" rather than
2063 "make zImage" or "make Image". The final kernel binary to put in
2064 ROM memory will be arch/arm/boot/xipImage.
2066 If unsure, say N.
2068 config XIP_PHYS_ADDR
2069 hex "XIP Kernel Physical Location"
2070 depends on XIP_KERNEL
2071 default "0x00080000"
2072 help
2073 This is the physical address in your flash memory the kernel will
2074 be linked for and stored to. This address is dependent on your
2075 own flash usage.
2077 config KEXEC
2078 bool "Kexec system call (EXPERIMENTAL)"
2079 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2080 help
2081 kexec is a system call that implements the ability to shutdown your
2082 current kernel, and to start another kernel. It is like a reboot
2083 but it is independent of the system firmware. And like a reboot
2084 you can start any kernel with it, not just Linux.
2086 It is an ongoing process to be certain the hardware in a machine
2087 is properly shutdown, so do not be surprised if this code does not
2088 initially work for you. It may help to enable device hotplugging
2089 support.
2091 config ATAGS_PROC
2092 bool "Export atags in procfs"
2093 depends on ATAGS && KEXEC
2094 default y
2095 help
2096 Should the atags used to boot the kernel be exported in an "atags"
2097 file in procfs. Useful with kexec.
2099 config CRASH_DUMP
2100 bool "Build kdump crash kernel (EXPERIMENTAL)"
2101 depends on EXPERIMENTAL
2102 help
2103 Generate crash dump after being started by kexec. This should
2104 be normally only set in special crash dump kernels which are
2105 loaded in the main kernel with kexec-tools into a specially
2106 reserved region and then later executed after a crash by
2107 kdump/kexec. The crash dump kernel must be compiled to a
2108 memory address not used by the main kernel
2110 For more details see Documentation/kdump/kdump.txt
2112 config AUTO_ZRELADDR
2113 bool "Auto calculation of the decompressed kernel image address"
2114 depends on !ZBOOT_ROM && !ARCH_U300
2115 help
2116 ZRELADDR is the physical address where the decompressed kernel
2117 image will be placed. If AUTO_ZRELADDR is selected, the address
2118 will be determined at run-time by masking the current IP with
2119 0xf8000000. This assumes the zImage being placed in the first 128MB
2120 from start of memory.
2122 endmenu
2124 menu "CPU Power Management"
2126 if ARCH_HAS_CPUFREQ
2128 source "drivers/cpufreq/Kconfig"
2130 config CPU_FREQ_IMX
2131 tristate "CPUfreq driver for i.MX CPUs"
2132 depends on ARCH_MXC && CPU_FREQ
2133 select CPU_FREQ_TABLE
2134 help
2135 This enables the CPUfreq driver for i.MX CPUs.
2137 config CPU_FREQ_SA1100
2138 bool
2140 config CPU_FREQ_SA1110
2141 bool
2143 config CPU_FREQ_INTEGRATOR
2144 tristate "CPUfreq driver for ARM Integrator CPUs"
2145 depends on ARCH_INTEGRATOR && CPU_FREQ
2146 default y
2147 help
2148 This enables the CPUfreq driver for ARM Integrator CPUs.
2150 For details, take a look at <file:Documentation/cpu-freq>.
2152 If in doubt, say Y.
2154 config CPU_FREQ_PXA
2155 bool
2156 depends on CPU_FREQ && ARCH_PXA && PXA25x
2157 default y
2158 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2159 select CPU_FREQ_TABLE
2161 config CPU_FREQ_S3C
2162 bool
2163 help
2164 Internal configuration node for common cpufreq on Samsung SoC
2166 config CPU_FREQ_S3C24XX
2167 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2168 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2169 select CPU_FREQ_S3C
2170 help
2171 This enables the CPUfreq driver for the Samsung S3C24XX family
2172 of CPUs.
2174 For details, take a look at <file:Documentation/cpu-freq>.
2176 If in doubt, say N.
2178 config CPU_FREQ_S3C24XX_PLL
2179 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2180 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2181 help
2182 Compile in support for changing the PLL frequency from the
2183 S3C24XX series CPUfreq driver. The PLL takes time to settle
2184 after a frequency change, so by default it is not enabled.
2186 This also means that the PLL tables for the selected CPU(s) will
2187 be built which may increase the size of the kernel image.
2189 config CPU_FREQ_S3C24XX_DEBUG
2190 bool "Debug CPUfreq Samsung driver core"
2191 depends on CPU_FREQ_S3C24XX
2192 help
2193 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2195 config CPU_FREQ_S3C24XX_IODEBUG
2196 bool "Debug CPUfreq Samsung driver IO timing"
2197 depends on CPU_FREQ_S3C24XX
2198 help
2199 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2201 config CPU_FREQ_S3C24XX_DEBUGFS
2202 bool "Export debugfs for CPUFreq"
2203 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2204 help
2205 Export status information via debugfs.
2207 endif
2209 source "drivers/cpuidle/Kconfig"
2211 endmenu
2213 menu "Floating point emulation"
2215 comment "At least one emulation must be selected"
2217 config FPE_NWFPE
2218 bool "NWFPE math emulation"
2219 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2220 ---help---
2221 Say Y to include the NWFPE floating point emulator in the kernel.
2222 This is necessary to run most binaries. Linux does not currently
2223 support floating point hardware so you need to say Y here even if
2224 your machine has an FPA or floating point co-processor podule.
2226 You may say N here if you are going to load the Acorn FPEmulator
2227 early in the bootup.
2229 config FPE_NWFPE_XP
2230 bool "Support extended precision"
2231 depends on FPE_NWFPE
2232 help
2233 Say Y to include 80-bit support in the kernel floating-point
2234 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2235 Note that gcc does not generate 80-bit operations by default,
2236 so in most cases this option only enlarges the size of the
2237 floating point emulator without any good reason.
2239 You almost surely want to say N here.
2241 config FPE_FASTFPE
2242 bool "FastFPE math emulation (EXPERIMENTAL)"
2243 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2244 ---help---
2245 Say Y here to include the FAST floating point emulator in the kernel.
2246 This is an experimental much faster emulator which now also has full
2247 precision for the mantissa. It does not support any exceptions.
2248 It is very simple, and approximately 3-6 times faster than NWFPE.
2250 It should be sufficient for most programs. It may be not suitable
2251 for scientific calculations, but you have to check this for yourself.
2252 If you do not feel you need a faster FP emulation you should better
2253 choose NWFPE.
2255 config VFP
2256 bool "VFP-format floating point maths"
2257 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2258 help
2259 Say Y to include VFP support code in the kernel. This is needed
2260 if your hardware includes a VFP unit.
2262 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2263 release notes and additional status information.
2265 Say N if your target does not have VFP hardware.
2267 config VFPv3
2268 bool
2269 depends on VFP
2270 default y if CPU_V7
2272 config NEON
2273 bool "Advanced SIMD (NEON) Extension support"
2274 depends on VFPv3 && CPU_V7
2275 help
2276 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2277 Extension.
2279 endmenu
2281 menu "Userspace binary formats"
2283 source "fs/Kconfig.binfmt"
2285 config ARTHUR
2286 tristate "RISC OS personality"
2287 depends on !AEABI
2288 help
2289 Say Y here to include the kernel code necessary if you want to run
2290 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2291 experimental; if this sounds frightening, say N and sleep in peace.
2292 You can also say M here to compile this support as a module (which
2293 will be called arthur).
2295 endmenu
2297 menu "Power management options"
2299 source "kernel/power/Kconfig"
2301 config ARCH_SUSPEND_POSSIBLE
2302 depends on !ARCH_S5PC100
2303 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2304 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2305 def_bool y
2307 config ARM_CPU_SUSPEND
2308 def_bool PM_SLEEP
2310 endmenu
2312 source "net/Kconfig"
2314 source "drivers/Kconfig"
2316 source "fs/Kconfig"
2318 source "arch/arm/Kconfig.debug"
2320 source "security/Kconfig"
2322 source "crypto/Kconfig"
2324 source "lib/Kconfig"