2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/linkage.h>
12 #include <asm/assembler.h>
17 * Note that these macros must not contain any code which is not
18 * 100% relocatable. Any attempt to do so will result in a crash.
19 * Please select one of the following when turning on debugging.
23 #if defined(CONFIG_DEBUG_ICEDCC)
25 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
26 .macro loadsp, rb, tmp
29 mcr p14, 0, \ch, c0, c5, 0
31 #elif defined(CONFIG_CPU_XSCALE)
32 .macro loadsp, rb, tmp
35 mcr p14, 0, \ch, c8, c0, 0
38 .macro loadsp, rb, tmp
41 mcr p14, 0, \ch, c1, c0, 0
47 #include CONFIG_DEBUG_LL_INCLUDE
53 #if defined(CONFIG_ARCH_SA1100)
54 .macro loadsp, rb, tmp
55 mov \rb, #0x80000000 @ physical base address
56 #ifdef CONFIG_DEBUG_LL_SER3
57 add \rb, \rb, #0x00050000 @ Ser3
59 add \rb, \rb, #0x00010000 @ Ser1
62 #elif defined(CONFIG_ARCH_S3C24XX)
63 .macro loadsp, rb, tmp
65 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
68 .macro loadsp, rb, tmp
86 .macro debug_reloc_start
89 kphex r6, 8 /* processor id */
91 kphex r7, 8 /* architecture id */
92 #ifdef CONFIG_CPU_CP15
94 mrc p15, 0, r0, c1, c0
95 kphex r0, 8 /* control reg */
98 kphex r5, 8 /* decompressed kernel start */
100 kphex r9, 8 /* decompressed kernel end */
102 kphex r4, 8 /* kernel execution address */
107 .macro debug_reloc_end
109 kphex r5, 8 /* end of kernel */
112 bl memdump /* dump 256 bytes at start of kernel */
116 .section ".start", #alloc, #execinstr
118 * sort out different calling conventions
121 .arm @ Always enter in ARM state
123 .type start,#function
129 THUMB( adr r12, BSYM(1f) )
132 .word 0x016f2818 @ Magic numbers to help the loader
133 .word start @ absolute load/run zImage address
134 .word _edata @ zImage end address
138 #ifdef CONFIG_ARM_VIRT_EXT
139 bl __hyp_stub_install @ get into SVC mode, reversibly
141 mov r7, r1 @ save architecture ID
142 mov r8, r2 @ save atags pointer
144 #ifndef __ARM_ARCH_2__
146 * Booting from Angel - need to enter SVC mode and disable
147 * FIQs/IRQs (numeric definitions from angel arm.h source).
148 * We only do this if we were in user mode on entry.
150 mrs r2, cpsr @ get current mode
151 tst r2, #3 @ not user?
153 mov r0, #0x17 @ angel_SWIreason_EnterSVC
154 ARM( swi 0x123456 ) @ angel_SWI_ARM
155 THUMB( svc 0xab ) @ angel_SWI_THUMB
157 safe_svcmode_maskall r0
158 msr spsr_cxsf, r9 @ Save the CPU boot mode in
161 teqp pc, #0x0c000003 @ turn off interrupts
165 * Note that some cache flushing and other stuff may
166 * be needed here - is there an Angel SWI call for this?
170 * some architecture specific code can be inserted
171 * by the linker here, but it should preserve r7, r8, and r9.
176 #ifdef CONFIG_AUTO_ZRELADDR
177 @ determine final kernel image address
179 and r4, r4, #0xf8000000
180 add r4, r4, #TEXT_OFFSET
188 ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
192 * We might be running at a different address. We need
193 * to fix up various pointers.
195 sub r0, r0, r1 @ calculate the delta offset
196 add r6, r6, r0 @ _edata
197 add r10, r10, r0 @ inflated kernel size location
200 * The kernel build system appends the size of the
201 * decompressed kernel at the end of the compressed data
202 * in little-endian form.
206 orr r9, r9, lr, lsl #8
209 orr r9, r9, lr, lsl #16
210 orr r9, r9, r10, lsl #24
212 #ifndef CONFIG_ZBOOT_ROM
213 /* malloc space is above the relocated stack (64k max) */
215 add r10, sp, #0x10000
218 * With ZBOOT_ROM the bss/stack is non relocatable,
219 * but someone could still run this code from RAM,
220 * in which case our reference is _edata.
225 mov r5, #0 @ init dtb size to 0
226 #ifdef CONFIG_ARM_APPENDED_DTB
231 * r4 = final kernel address
232 * r5 = appended dtb size (still unknown)
234 * r7 = architecture ID
235 * r8 = atags/device tree pointer
236 * r9 = size of decompressed image
237 * r10 = end of this image, including bss/stack/malloc space if non XIP
242 * if there are device trees (dtb) appended to zImage, advance r10 so that the
243 * dtb data will get relocated along with the kernel if necessary.
248 ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian
253 bne dtb_check_done @ not found
255 #ifdef CONFIG_ARM_ATAG_DTB_COMPAT
257 * OK... Let's do some funky business here.
258 * If we do have a DTB appended to zImage, and we do have
259 * an ATAG list around, we want the later to be translated
260 * and folded into the former here. To be on the safe side,
261 * let's temporarily move the stack away into the malloc
262 * area. No GOT fixup has occurred yet, but none of the
263 * code we're about to call uses any global variable.
266 stmfd sp!, {r0-r3, ip, lr}
273 * If returned value is 1, there is no ATAG at the location
274 * pointed by r8. Try the typical 0x100 offset from start
275 * of RAM and hope for the best.
278 sub r0, r4, #TEXT_OFFSET
284 ldmfd sp!, {r0-r3, ip, lr}
288 mov r8, r6 @ use the appended device tree
291 * Make sure that the DTB doesn't end up in the final
292 * kernel's .bss area. To do so, we adjust the decompressed
293 * kernel size to compensate if that .bss size is larger
294 * than the relocated code.
296 ldr r5, =_kernel_bss_size
297 adr r1, wont_overwrite
302 /* Get the dtb's size */
305 /* convert r5 (dtb size) to little endian */
306 eor r1, r5, r5, ror #16
307 bic r1, r1, #0x00ff0000
309 eor r5, r5, r1, lsr #8
312 /* preserve 64-bit alignment */
316 /* relocate some pointers past the appended dtb */
324 * Check to see if we will overwrite ourselves.
325 * r4 = final kernel address
326 * r9 = size of decompressed image
327 * r10 = end of this image, including bss/stack/malloc space if non XIP
329 * r4 - 16k page directory >= r10 -> OK
330 * r4 + image length <= address of wont_overwrite -> OK
336 adr r9, wont_overwrite
341 * Relocate ourselves past the end of the decompressed kernel.
343 * r10 = end of the decompressed kernel
344 * Because we always copy ahead, we need to do it from the end and go
345 * backward in case the source and destination overlap.
348 * Bump to the next 256-byte boundary with the size of
349 * the relocation code added. This avoids overwriting
350 * ourself when the offset is small.
352 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
355 /* Get start of code we want to copy and align it down. */
359 /* Relocate the hyp vector base if necessary */
360 #ifdef CONFIG_ARM_VIRT_EXT
362 and r0, r0, #MODE_MASK
373 sub r9, r6, r5 @ size to copy
374 add r9, r9, #31 @ rounded up to a multiple
375 bic r9, r9, #31 @ ... of 32 bytes
379 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
381 stmdb r9!, {r0 - r3, r10 - r12, lr}
384 /* Preserve offset to relocated code. */
387 #ifndef CONFIG_ZBOOT_ROM
388 /* cache_clean_flush may use the stack, so relocate it */
394 adr r0, BSYM(restart)
400 * If delta is zero, we are running at the address we were linked at.
404 * r4 = kernel execution address
405 * r5 = appended dtb size (0 if not present)
406 * r7 = architecture ID
418 #ifndef CONFIG_ZBOOT_ROM
420 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
421 * we need to fix up pointers into the BSS region.
422 * Note that the stack pointer has already been fixed up.
428 * Relocate all entries in the GOT table.
429 * Bump bss entries to _edata + dtb size
431 1: ldr r1, [r11, #0] @ relocate entries in the GOT
432 add r1, r1, r0 @ This fixes up C references
433 cmp r1, r2 @ if entry >= bss_start &&
434 cmphs r3, r1 @ bss_end > entry
435 addhi r1, r1, r5 @ entry += dtb size
436 str r1, [r11], #4 @ next entry
440 /* bump our bss pointers too */
447 * Relocate entries in the GOT table. We only relocate
448 * the entries that are outside the (relocated) BSS region.
450 1: ldr r1, [r11, #0] @ relocate entries in the GOT
451 cmp r1, r2 @ entry < bss_start ||
452 cmphs r3, r1 @ _end < entry
453 addlo r1, r1, r0 @ table. This fixes up the
454 str r1, [r11], #4 @ C references.
459 not_relocated: mov r0, #0
460 1: str r0, [r2], #4 @ clear bss
468 * The C runtime environment should now be setup sufficiently.
469 * Set up some pointers, and start decompressing.
470 * r4 = kernel execution address
471 * r7 = architecture ID
475 mov r1, sp @ malloc space above stack
476 add r2, sp, #0x10000 @ 64k max
481 mov r1, r7 @ restore architecture number
482 mov r2, r8 @ restore atags pointer
484 #ifdef CONFIG_ARM_VIRT_EXT
485 mrs r0, spsr @ Get saved CPU boot mode
486 and r0, r0, #MODE_MASK
487 cmp r0, #HYP_MODE @ if not booted in HYP mode...
488 bne __enter_kernel @ boot kernel directly
490 adr r12, .L__hyp_reentry_vectors_offset
495 __HVC(0) @ otherwise bounce to hyp mode
497 b . @ should never be reached
500 .L__hyp_reentry_vectors_offset: .long __hyp_reentry_vectors - .
508 .word __bss_start @ r2
511 .word input_data_end - 4 @ r10 (inflated size location)
512 .word _got_start @ r11
514 .word .L_user_stack_end @ sp
517 #ifdef CONFIG_ARCH_RPC
519 params: ldr r0, =0x10000100 @ params_phys for RPC
526 * Turn on the cache. We need to setup some page tables so that we
527 * can have both the I and D caches on.
529 * We place the page tables 16k down from the kernel execution address,
530 * and we hope that nothing else is using it. If we're using it, we
534 * r4 = kernel execution address
535 * r7 = architecture number
538 * r0, r1, r2, r3, r9, r10, r12 corrupted
539 * This routine must preserve:
543 cache_on: mov r3, #8 @ cache_on function
547 * Initialize the highest priority protection region, PR7
548 * to cover all 32bit address and cacheable and bufferable.
550 __armv4_mpu_cache_on:
551 mov r0, #0x3f @ 4G, the whole
552 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
553 mcr p15, 0, r0, c6, c7, 1
556 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
557 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
558 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
561 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
562 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
565 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
566 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
567 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
568 mrc p15, 0, r0, c1, c0, 0 @ read control reg
569 @ ...I .... ..D. WC.M
570 orr r0, r0, #0x002d @ .... .... ..1. 11.1
571 orr r0, r0, #0x1000 @ ...1 .... .... ....
573 mcr p15, 0, r0, c1, c0, 0 @ write control reg
576 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
577 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
580 __armv3_mpu_cache_on:
581 mov r0, #0x3f @ 4G, the whole
582 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
585 mcr p15, 0, r0, c2, c0, 0 @ cache on
586 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
589 mcr p15, 0, r0, c5, c0, 0 @ access permission
592 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
594 * ?? ARMv3 MMU does not allow reading the control register,
595 * does this really work on ARMv3 MPU?
597 mrc p15, 0, r0, c1, c0, 0 @ read control reg
598 @ .... .... .... WC.M
599 orr r0, r0, #0x000d @ .... .... .... 11.1
600 /* ?? this overwrites the value constructed above? */
602 mcr p15, 0, r0, c1, c0, 0 @ write control reg
604 /* ?? invalidate for the second time? */
605 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
608 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
614 __setup_mmu: sub r3, r4, #16384 @ Page directory size
615 bic r3, r3, #0xff @ Align the pointer
618 * Initialise the page tables, turning on the cacheable and bufferable
619 * bits for the RAM area only.
623 mov r9, r9, lsl #18 @ start of RAM
624 add r10, r9, #0x10000000 @ a reasonable RAM size
625 mov r1, #0x12 @ XN|U + section mapping
626 orr r1, r1, #3 << 10 @ AP=11
628 1: cmp r1, r9 @ if virt > start of RAM
629 cmphs r10, r1 @ && end of RAM > virt
630 bic r1, r1, #0x1c @ clear XN|U + C + B
631 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
632 orrhs r1, r1, r6 @ set RAM section settings
633 str r1, [r0], #4 @ 1:1 mapping
638 * If ever we are running from Flash, then we surely want the cache
639 * to be enabled also for our execution instance... We map 2MB of it
640 * so there is no map overlap problem for up to 1 MB compressed kernel.
641 * If the execution is in RAM then we would only be duplicating the above.
643 orr r1, r6, #0x04 @ ensure B is set for this
647 orr r1, r1, r2, lsl #20
648 add r0, r3, r2, lsl #2
655 @ Enable unaligned access on v6, to allow better code generation
656 @ for the decompressor C code:
657 __armv6_mmu_cache_on:
658 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
659 bic r0, r0, #2 @ A (no unaligned access fault)
660 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
661 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
662 b __armv4_mmu_cache_on
664 __arm926ejs_mmu_cache_on:
665 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
666 mov r0, #4 @ put dcache in WT mode
667 mcr p15, 7, r0, c15, c0, 0
670 __armv4_mmu_cache_on:
673 mov r6, #CB_BITS | 0x12 @ U
676 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
677 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
678 mrc p15, 0, r0, c1, c0, 0 @ read control reg
679 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
681 #ifdef CONFIG_CPU_ENDIAN_BE8
682 orr r0, r0, #1 << 25 @ big-endian page tables
684 bl __common_mmu_cache_on
686 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
690 __armv7_mmu_cache_on:
693 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
695 movne r6, #CB_BITS | 0x02 @ !XN
698 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
700 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
702 mrc p15, 0, r0, c1, c0, 0 @ read control reg
703 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
704 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
705 orr r0, r0, #0x003c @ write buffer
706 bic r0, r0, #2 @ A (no unaligned access fault)
707 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
708 @ (needed for ARM1176)
710 #ifdef CONFIG_CPU_ENDIAN_BE8
711 orr r0, r0, #1 << 25 @ big-endian page tables
713 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
714 orrne r0, r0, #1 @ MMU enabled
715 movne r1, #0xfffffffd @ domain 0 = client
716 bic r6, r6, #1 << 31 @ 32-bit translation system
717 bic r6, r6, #3 << 0 @ use only ttbr0
718 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
719 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
720 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
722 mcr p15, 0, r0, c7, c5, 4 @ ISB
723 mcr p15, 0, r0, c1, c0, 0 @ load control register
724 mrc p15, 0, r0, c1, c0, 0 @ and read it back
726 mcr p15, 0, r0, c7, c5, 4 @ ISB
731 mov r6, #CB_BITS | 0x12 @ U
734 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
735 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
736 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
737 mrc p15, 0, r0, c1, c0, 0 @ read control reg
738 orr r0, r0, #0x1000 @ I-cache enable
739 bl __common_mmu_cache_on
741 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
744 __common_mmu_cache_on:
745 #ifndef CONFIG_THUMB2_KERNEL
747 orr r0, r0, #0x000d @ Write buffer, mmu
750 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
751 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
753 .align 5 @ cache line aligned
754 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
755 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
756 sub pc, lr, r0, lsr #32 @ properly flush pipeline
759 #define PROC_ENTRY_SIZE (4*5)
762 * Here follow the relocatable cache support functions for the
763 * various processors. This is a generic hook for locating an
764 * entry and jumping to an instruction at the specified offset
765 * from the start of the block. Please note this is all position
775 call_cache_fn: adr r12, proc_types
776 #ifdef CONFIG_CPU_CP15
777 mrc p15, 0, r9, c0, c0 @ get processor ID
779 ldr r9, =CONFIG_PROCESSOR_ID
781 1: ldr r1, [r12, #0] @ get value
782 ldr r2, [r12, #4] @ get mask
783 eor r1, r1, r9 @ (real ^ match)
785 ARM( addeq pc, r12, r3 ) @ call cache function
786 THUMB( addeq r12, r3 )
787 THUMB( moveq pc, r12 ) @ call cache function
788 add r12, r12, #PROC_ENTRY_SIZE
792 * Table for cache operations. This is basically:
795 * - 'cache on' method instruction
796 * - 'cache off' method instruction
797 * - 'cache flush' method instruction
799 * We match an entry using: ((real_id ^ match) & mask) == 0
801 * Writethrough caches generally only need 'on' and 'off'
802 * methods. Writeback caches _must_ have the flush method
806 .type proc_types,#object
808 .word 0x00000000 @ old ARM ID
817 .word 0x41007000 @ ARM7/710
826 .word 0x41807200 @ ARM720T (writethrough)
828 W(b) __armv4_mmu_cache_on
829 W(b) __armv4_mmu_cache_off
833 .word 0x41007400 @ ARM74x
835 W(b) __armv3_mpu_cache_on
836 W(b) __armv3_mpu_cache_off
837 W(b) __armv3_mpu_cache_flush
839 .word 0x41009400 @ ARM94x
841 W(b) __armv4_mpu_cache_on
842 W(b) __armv4_mpu_cache_off
843 W(b) __armv4_mpu_cache_flush
845 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
847 W(b) __arm926ejs_mmu_cache_on
848 W(b) __armv4_mmu_cache_off
849 W(b) __armv5tej_mmu_cache_flush
851 .word 0x00007000 @ ARM7 IDs
860 @ Everything from here on will be the new ID system.
862 .word 0x4401a100 @ sa110 / sa1100
864 W(b) __armv4_mmu_cache_on
865 W(b) __armv4_mmu_cache_off
866 W(b) __armv4_mmu_cache_flush
868 .word 0x6901b110 @ sa1110
870 W(b) __armv4_mmu_cache_on
871 W(b) __armv4_mmu_cache_off
872 W(b) __armv4_mmu_cache_flush
875 .word 0xffffff00 @ PXA9xx
876 W(b) __armv4_mmu_cache_on
877 W(b) __armv4_mmu_cache_off
878 W(b) __armv4_mmu_cache_flush
880 .word 0x56158000 @ PXA168
882 W(b) __armv4_mmu_cache_on
883 W(b) __armv4_mmu_cache_off
884 W(b) __armv5tej_mmu_cache_flush
886 .word 0x56050000 @ Feroceon
888 W(b) __armv4_mmu_cache_on
889 W(b) __armv4_mmu_cache_off
890 W(b) __armv5tej_mmu_cache_flush
892 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
893 /* this conflicts with the standard ARMv5TE entry */
894 .long 0x41009260 @ Old Feroceon
896 b __armv4_mmu_cache_on
897 b __armv4_mmu_cache_off
898 b __armv5tej_mmu_cache_flush
901 .word 0x66015261 @ FA526
903 W(b) __fa526_cache_on
904 W(b) __armv4_mmu_cache_off
905 W(b) __fa526_cache_flush
907 @ These match on the architecture ID
909 .word 0x00020000 @ ARMv4T
911 W(b) __armv4_mmu_cache_on
912 W(b) __armv4_mmu_cache_off
913 W(b) __armv4_mmu_cache_flush
915 .word 0x00050000 @ ARMv5TE
917 W(b) __armv4_mmu_cache_on
918 W(b) __armv4_mmu_cache_off
919 W(b) __armv4_mmu_cache_flush
921 .word 0x00060000 @ ARMv5TEJ
923 W(b) __armv4_mmu_cache_on
924 W(b) __armv4_mmu_cache_off
925 W(b) __armv5tej_mmu_cache_flush
927 .word 0x0007b000 @ ARMv6
929 W(b) __armv6_mmu_cache_on
930 W(b) __armv4_mmu_cache_off
931 W(b) __armv6_mmu_cache_flush
933 .word 0x000f0000 @ new CPU Id
935 W(b) __armv7_mmu_cache_on
936 W(b) __armv7_mmu_cache_off
937 W(b) __armv7_mmu_cache_flush
939 .word 0 @ unrecognised type
948 .size proc_types, . - proc_types
951 * If you get a "non-constant expression in ".if" statement"
952 * error from the assembler on this line, check that you have
953 * not accidentally written a "b" instruction where you should
956 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
957 .error "The size of one or more proc_types entries is wrong."
961 * Turn off the Cache and MMU. ARMv3 does not support
962 * reading the control register, but ARMv4 does.
965 * r0, r1, r2, r3, r9, r12 corrupted
966 * This routine must preserve:
970 cache_off: mov r3, #12 @ cache_off function
973 __armv4_mpu_cache_off:
974 mrc p15, 0, r0, c1, c0
976 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
978 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
979 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
980 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
983 __armv3_mpu_cache_off:
984 mrc p15, 0, r0, c1, c0
986 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
988 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
991 __armv4_mmu_cache_off:
993 mrc p15, 0, r0, c1, c0
995 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
997 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
998 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1002 __armv7_mmu_cache_off:
1003 mrc p15, 0, r0, c1, c0
1009 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1011 bl __armv7_mmu_cache_flush
1014 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1016 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1017 mcr p15, 0, r0, c7, c10, 4 @ DSB
1018 mcr p15, 0, r0, c7, c5, 4 @ ISB
1022 * Clean and flush the cache to maintain consistency.
1025 * r1, r2, r3, r9, r10, r11, r12 corrupted
1026 * This routine must preserve:
1034 __armv4_mpu_cache_flush:
1037 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1038 mov r1, #7 << 5 @ 8 segments
1039 1: orr r3, r1, #63 << 26 @ 64 entries
1040 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1041 subs r3, r3, #1 << 26
1042 bcs 2b @ entries 63 to 0
1043 subs r1, r1, #1 << 5
1044 bcs 1b @ segments 7 to 0
1047 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
1048 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1051 __fa526_cache_flush:
1053 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1054 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1055 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1058 __armv6_mmu_cache_flush:
1060 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1061 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1062 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1063 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1066 __armv7_mmu_cache_flush:
1067 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1068 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
1071 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1074 mcr p15, 0, r10, c7, c10, 5 @ DMB
1075 stmfd sp!, {r0-r7, r9-r11}
1076 mrc p15, 1, r0, c0, c0, 1 @ read clidr
1077 ands r3, r0, #0x7000000 @ extract loc from clidr
1078 mov r3, r3, lsr #23 @ left align loc bit field
1079 beq finished @ if loc is 0, then no need to clean
1080 mov r10, #0 @ start clean at cache level 0
1082 add r2, r10, r10, lsr #1 @ work out 3x current cache level
1083 mov r1, r0, lsr r2 @ extract cache type bits from clidr
1084 and r1, r1, #7 @ mask of the bits for current cache only
1085 cmp r1, #2 @ see what cache we have at this level
1086 blt skip @ skip if no cache, or just i-cache
1087 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1088 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
1089 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
1090 and r2, r1, #7 @ extract the length of the cache lines
1091 add r2, r2, #4 @ add 4 (line length offset)
1093 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
1094 clz r5, r4 @ find bit position of way size increment
1096 ands r7, r7, r1, lsr #13 @ extract max number of the index size
1098 mov r9, r4 @ create working copy of max way size
1100 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
1101 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
1102 THUMB( lsl r6, r9, r5 )
1103 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
1104 THUMB( lsl r6, r7, r2 )
1105 THUMB( orr r11, r11, r6 ) @ factor index number into r11
1106 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
1107 subs r9, r9, #1 @ decrement the way
1109 subs r7, r7, #1 @ decrement the index
1112 add r10, r10, #2 @ increment cache number
1116 ldmfd sp!, {r0-r7, r9-r11}
1117 mov r10, #0 @ swith back to cache level 0
1118 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1120 mcr p15, 0, r10, c7, c10, 4 @ DSB
1121 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1122 mcr p15, 0, r10, c7, c10, 4 @ DSB
1123 mcr p15, 0, r10, c7, c5, 4 @ ISB
1126 __armv5tej_mmu_cache_flush:
1127 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
1129 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1130 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1133 __armv4_mmu_cache_flush:
1134 mov r2, #64*1024 @ default: 32K dcache size (*2)
1135 mov r11, #32 @ default: 32 byte line size
1136 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1137 teq r3, r9 @ cache ID register present?
1142 mov r2, r2, lsl r1 @ base dcache size *2
1143 tst r3, #1 << 14 @ test M bit
1144 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
1148 mov r11, r11, lsl r3 @ cache line size in bytes
1151 bic r1, r1, #63 @ align to longest cache line
1154 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
1155 THUMB( ldr r3, [r1] ) @ s/w flush D cache
1156 THUMB( add r1, r1, r11 )
1160 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1161 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1162 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1165 __armv3_mmu_cache_flush:
1166 __armv3_mpu_cache_flush:
1168 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1172 * Various debugging routines for printing hex characters and
1173 * memory, which again must be relocatable.
1177 .type phexbuf,#object
1179 .size phexbuf, . - phexbuf
1181 @ phex corrupts {r0, r1, r2, r3}
1182 phex: adr r3, phexbuf
1196 @ puts corrupts {r0, r1, r2, r3}
1198 1: ldrb r2, [r0], #1
1211 @ putc corrupts {r0, r1, r2, r3}
1218 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1219 memdump: mov r12, r0
1222 2: mov r0, r11, lsl #2
1230 ldr r0, [r12, r11, lsl #2]
1250 #ifdef CONFIG_ARM_VIRT_EXT
1252 __hyp_reentry_vectors:
1258 W(b) __enter_kernel @ hyp
1261 #endif /* CONFIG_ARM_VIRT_EXT */
1264 mov r0, #0 @ must be 0
1265 ARM( mov pc, r4 ) @ call kernel
1266 THUMB( bx r4 ) @ entry point is always ARM
1271 .section ".stack", "aw", %nobits
1272 .L_user_stack: .space 4096