arch/arm/boot/compressed/mmcif-sh7372.c

   1 /*
   2  * sh7372 MMCIF loader
   3  *
   4  * Copyright (C) 2010 Magnus Damm
   5  * Copyright (C) 2010 Simon Horman
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11
  12 #include <linux/mmc/sh_mmcif.h>
  13 #include <linux/mmc/boot.h>
  14 #include <mach/mmc.h>
  15
  16 #define MMCIF_BASE      (void __iomem *)0xe6bd0000
  17
  18 #define PORT84CR        (void __iomem *)0xe6050054
  19 #define PORT85CR        (void __iomem *)0xe6050055
  20 #define PORT86CR        (void __iomem *)0xe6050056
  21 #define PORT87CR        (void __iomem *)0xe6050057
  22 #define PORT88CR        (void __iomem *)0xe6050058
  23 #define PORT89CR        (void __iomem *)0xe6050059
  24 #define PORT90CR        (void __iomem *)0xe605005a
  25 #define PORT91CR        (void __iomem *)0xe605005b
  26 #define PORT92CR        (void __iomem *)0xe605005c
  27 #define PORT99CR        (void __iomem *)0xe6050063
  28
  29 #define SMSTPCR3        (void __iomem *)0xe615013c
  30
  31 /* SH7372 specific MMCIF loader
  32  *
  33  * loads the zImage from an MMC card starting from block 1.
  34  *
  35  * The image must be start with a vrl4 header and
  36  * the zImage must start at offset 512 of the image. That is,
  37  * at block 2 (=byte 1024) on the media
  38  *
  39  * Use the following line to write the vrl4 formated zImage
  40  * to an MMC card
  41  * # dd if=vrl4.out of=/dev/sdx bs=512 seek=1
  42  */
  43 asmlinkage void mmc_loader(unsigned char *buf, unsigned long len)
  44 {
  45         mmc_init_progress();
  46         mmc_update_progress(MMC_PROGRESS_ENTER);
  47
  48         /* Initialise MMC
  49          * registers: PORT84CR-PORT92CR
  50          *            (MMCD0_0-MMCD0_7,MMCCMD0 Control)
  51          * value: 0x04 - select function 4
  52          */
  53          __raw_writeb(0x04, PORT84CR);
  54          __raw_writeb(0x04, PORT85CR);
  55          __raw_writeb(0x04, PORT86CR);
  56          __raw_writeb(0x04, PORT87CR);
  57          __raw_writeb(0x04, PORT88CR);
  58          __raw_writeb(0x04, PORT89CR);
  59          __raw_writeb(0x04, PORT90CR);
  60          __raw_writeb(0x04, PORT91CR);
  61          __raw_writeb(0x04, PORT92CR);
  62
  63         /* Initialise MMC
  64          * registers: PORT99CR (MMCCLK0 Control)
  65          * value: 0x10 | 0x04 - enable output | select function 4
  66          */
  67         __raw_writeb(0x14, PORT99CR);
  68
  69         /* Enable clock to MMC hardware block */
  70         __raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 12), SMSTPCR3);
  71
  72         mmc_update_progress(MMC_PROGRESS_INIT);
  73
  74         /* setup MMCIF hardware */
  75         sh_mmcif_boot_init(MMCIF_BASE);
  76
  77         mmc_update_progress(MMC_PROGRESS_LOAD);
  78
  79         /* load kernel via MMCIF interface */
  80         sh_mmcif_boot_do_read(MMCIF_BASE, 2, /* Kernel is at block 2 */
  81                               (len + SH_MMCIF_BBS - 1) / SH_MMCIF_BBS, buf);
  82
  83
  84         /* Disable clock to MMC hardware block */
  85         __raw_writel(__raw_readl(SMSTPCR3) | (1 << 12), SMSTPCR3);
  86
  87         mmc_update_progress(MMC_PROGRESS_DONE);
  88 }