arch/arm/common/vic.c

   1 /*
   2  *  linux/arch/arm/common/vic.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include <linux/export.h>
  23 #include <linux/init.h>
  24 #include <linux/list.h>
  25 #include <linux/io.h>
  26 #include <linux/irqdomain.h>
  27 #include <linux/of.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_irq.h>
  30 #include <linux/syscore_ops.h>
  31 #include <linux/device.h>
  32 #include <linux/amba/bus.h>
  33
  34 #include <asm/exception.h>
  35 #include <asm/mach/irq.h>
  36 #include <asm/hardware/vic.h>
  37
  38 /**
  39  * struct vic_device - VIC PM device
  40  * @irq: The IRQ number for the base of the VIC.
  41  * @base: The register base for the VIC.
  42  * @valid_sources: A bitmask of valid interrupts
  43  * @resume_sources: A bitmask of interrupts for resume.
  44  * @resume_irqs: The IRQs enabled for resume.
  45  * @int_select: Save for VIC_INT_SELECT.
  46  * @int_enable: Save for VIC_INT_ENABLE.
  47  * @soft_int: Save for VIC_INT_SOFT.
  48  * @protect: Save for VIC_PROTECT.
  49  * @domain: The IRQ domain for the VIC.
  50  */
  51 struct vic_device {
  52         void __iomem    *base;
  53         int             irq;
  54         u32             valid_sources;
  55         u32             resume_sources;
  56         u32             resume_irqs;
  57         u32             int_select;
  58         u32             int_enable;
  59         u32             soft_int;
  60         u32             protect;
  61         struct irq_domain *domain;
  62 };
  63
  64 /* we cannot allocate memory when VICs are initially registered */
  65 static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
  66
  67 static int vic_id;
  68
  69 /**
  70  * vic_init2 - common initialisation code
  71  * @base: Base of the VIC.
  72  *
  73  * Common initialisation code for registration
  74  * and resume.
  75 */
  76 static void vic_init2(void __iomem *base)
  77 {
  78         int i;
  79
  80         for (i = 0; i < 16; i++) {
  81                 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
  82                 writel(VIC_VECT_CNTL_ENABLE | i, reg);
  83         }
  84
  85         writel(32, base + VIC_PL190_DEF_VECT_ADDR);
  86 }
  87
  88 #ifdef CONFIG_PM
  89 static void resume_one_vic(struct vic_device *vic)
  90 {
  91         void __iomem *base = vic->base;
  92
  93         printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
  94
  95         /* re-initialise static settings */
  96         vic_init2(base);
  97
  98         writel(vic->int_select, base + VIC_INT_SELECT);
  99         writel(vic->protect, base + VIC_PROTECT);
 100
 101         /* set the enabled ints and then clear the non-enabled */
 102         writel(vic->int_enable, base + VIC_INT_ENABLE);
 103         writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
 104
 105         /* and the same for the soft-int register */
 106
 107         writel(vic->soft_int, base + VIC_INT_SOFT);
 108         writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
 109 }
 110
 111 static void vic_resume(void)
 112 {
 113         int id;
 114
 115         for (id = vic_id - 1; id >= 0; id--)
 116                 resume_one_vic(vic_devices + id);
 117 }
 118
 119 static void suspend_one_vic(struct vic_device *vic)
 120 {
 121         void __iomem *base = vic->base;
 122
 123         printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
 124
 125         vic->int_select = readl(base + VIC_INT_SELECT);
 126         vic->int_enable = readl(base + VIC_INT_ENABLE);
 127         vic->soft_int = readl(base + VIC_INT_SOFT);
 128         vic->protect = readl(base + VIC_PROTECT);
 129
 130         /* set the interrupts (if any) that are used for
 131          * resuming the system */
 132
 133         writel(vic->resume_irqs, base + VIC_INT_ENABLE);
 134         writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
 135 }
 136
 137 static int vic_suspend(void)
 138 {
 139         int id;
 140
 141         for (id = 0; id < vic_id; id++)
 142                 suspend_one_vic(vic_devices + id);
 143
 144         return 0;
 145 }
 146
 147 struct syscore_ops vic_syscore_ops = {
 148         .suspend        = vic_suspend,
 149         .resume         = vic_resume,
 150 };
 151
 152 /**
 153  * vic_pm_init - initicall to register VIC pm
 154  *
 155  * This is called via late_initcall() to register
 156  * the resources for the VICs due to the early
 157  * nature of the VIC's registration.
 158 */
 159 static int __init vic_pm_init(void)
 160 {
 161         if (vic_id > 0)
 162                 register_syscore_ops(&vic_syscore_ops);
 163
 164         return 0;
 165 }
 166 late_initcall(vic_pm_init);
 167 #endif /* CONFIG_PM */
 168
 169 static struct irq_chip vic_chip;
 170
 171 static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq,
 172                              irq_hw_number_t hwirq)
 173 {
 174         struct vic_device *v = d->host_data;
 175
 176         /* Skip invalid IRQs, only register handlers for the real ones */
 177         if (!(v->valid_sources & (1 << hwirq)))
 178                 return -ENOTSUPP;
 179         irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq);
 180         irq_set_chip_data(irq, v->base);
 181         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 182         return 0;
 183 }
 184
 185 static struct irq_domain_ops vic_irqdomain_ops = {
 186         .map = vic_irqdomain_map,
 187         .xlate = irq_domain_xlate_onetwocell,
 188 };
 189
 190 /**
 191  * vic_register() - Register a VIC.
 192  * @base: The base address of the VIC.
 193  * @irq: The base IRQ for the VIC.
 194  * @valid_sources: bitmask of valid interrupts
 195  * @resume_sources: bitmask of interrupts allowed for resume sources.
 196  * @node: The device tree node associated with the VIC.
 197  *
 198  * Register the VIC with the system device tree so that it can be notified
 199  * of suspend and resume requests and ensure that the correct actions are
 200  * taken to re-instate the settings on resume.
 201  *
 202  * This also configures the IRQ domain for the VIC.
 203  */
 204 static void __init vic_register(void __iomem *base, unsigned int irq,
 205                                 u32 valid_sources, u32 resume_sources,
 206                                 struct device_node *node)
 207 {
 208         struct vic_device *v;
 209         int i;
 210
 211         if (vic_id >= ARRAY_SIZE(vic_devices)) {
 212                 printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
 213                 return;
 214         }
 215
 216         v = &vic_devices[vic_id];
 217         v->base = base;
 218         v->valid_sources = valid_sources;
 219         v->resume_sources = resume_sources;
 220         v->irq = irq;
 221         vic_id++;
 222         v->domain = irq_domain_add_simple(node, fls(valid_sources), irq,
 223                                           &vic_irqdomain_ops, v);
 224         /* create an IRQ mapping for each valid IRQ */
 225         for (i = 0; i < fls(valid_sources); i++)
 226                 if (valid_sources & (1 << i))
 227                         irq_create_mapping(v->domain, i);
 228 }
 229
 230 static void vic_ack_irq(struct irq_data *d)
 231 {
 232         void __iomem *base = irq_data_get_irq_chip_data(d);
 233         unsigned int irq = d->hwirq;
 234         writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
 235         /* moreover, clear the soft-triggered, in case it was the reason */
 236         writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
 237 }
 238
 239 static void vic_mask_irq(struct irq_data *d)
 240 {
 241         void __iomem *base = irq_data_get_irq_chip_data(d);
 242         unsigned int irq = d->hwirq;
 243         writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
 244 }
 245
 246 static void vic_unmask_irq(struct irq_data *d)
 247 {
 248         void __iomem *base = irq_data_get_irq_chip_data(d);
 249         unsigned int irq = d->hwirq;
 250         writel(1 << irq, base + VIC_INT_ENABLE);
 251 }
 252
 253 #if defined(CONFIG_PM)
 254 static struct vic_device *vic_from_irq(unsigned int irq)
 255 {
 256         struct vic_device *v = vic_devices;
 257         unsigned int base_irq = irq & ~31;
 258         int id;
 259
 260         for (id = 0; id < vic_id; id++, v++) {
 261                 if (v->irq == base_irq)
 262                         return v;
 263         }
 264
 265         return NULL;
 266 }
 267
 268 static int vic_set_wake(struct irq_data *d, unsigned int on)
 269 {
 270         struct vic_device *v = vic_from_irq(d->irq);
 271         unsigned int off = d->hwirq;
 272         u32 bit = 1 << off;
 273
 274         if (!v)
 275                 return -EINVAL;
 276
 277         if (!(bit & v->resume_sources))
 278                 return -EINVAL;
 279
 280         if (on)
 281                 v->resume_irqs |= bit;
 282         else
 283                 v->resume_irqs &= ~bit;
 284
 285         return 0;
 286 }
 287 #else
 288 #define vic_set_wake NULL
 289 #endif /* CONFIG_PM */
 290
 291 static struct irq_chip vic_chip = {
 292         .name           = "VIC",
 293         .irq_ack        = vic_ack_irq,
 294         .irq_mask       = vic_mask_irq,
 295         .irq_unmask     = vic_unmask_irq,
 296         .irq_set_wake   = vic_set_wake,
 297 };
 298
 299 static void __init vic_disable(void __iomem *base)
 300 {
 301         writel(0, base + VIC_INT_SELECT);
 302         writel(0, base + VIC_INT_ENABLE);
 303         writel(~0, base + VIC_INT_ENABLE_CLEAR);
 304         writel(0, base + VIC_ITCR);
 305         writel(~0, base + VIC_INT_SOFT_CLEAR);
 306 }
 307
 308 static void __init vic_clear_interrupts(void __iomem *base)
 309 {
 310         unsigned int i;
 311
 312         writel(0, base + VIC_PL190_VECT_ADDR);
 313         for (i = 0; i < 19; i++) {
 314                 unsigned int value;
 315
 316                 value = readl(base + VIC_PL190_VECT_ADDR);
 317                 writel(value, base + VIC_PL190_VECT_ADDR);
 318         }
 319 }
 320
 321 /*
 322  * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
 323  * The original cell has 32 interrupts, while the modified one has 64,
 324  * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
 325  * the probe function is called twice, with base set to offset 000
 326  *  and 020 within the page. We call this "second block".
 327  */
 328 static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
 329                                u32 vic_sources, struct device_node *node)
 330 {
 331         unsigned int i;
 332         int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
 333
 334         /* Disable all interrupts initially. */
 335         vic_disable(base);
 336
 337         /*
 338          * Make sure we clear all existing interrupts. The vector registers
 339          * in this cell are after the second block of general registers,
 340          * so we can address them using standard offsets, but only from
 341          * the second base address, which is 0x20 in the page
 342          */
 343         if (vic_2nd_block) {
 344                 vic_clear_interrupts(base);
 345
 346                 /* ST has 16 vectors as well, but we don't enable them by now */
 347                 for (i = 0; i < 16; i++) {
 348                         void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
 349                         writel(0, reg);
 350                 }
 351
 352                 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
 353         }
 354
 355         vic_register(base, irq_start, vic_sources, 0, node);
 356 }
 357
 358 void __init __vic_init(void __iomem *base, int irq_start,
 359                               u32 vic_sources, u32 resume_sources,
 360                               struct device_node *node)
 361 {
 362         unsigned int i;
 363         u32 cellid = 0;
 364         enum amba_vendor vendor;
 365
 366         /* Identify which VIC cell this one is, by reading the ID */
 367         for (i = 0; i < 4; i++) {
 368                 void __iomem *addr;
 369                 addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
 370                 cellid |= (readl(addr) & 0xff) << (8 * i);
 371         }
 372         vendor = (cellid >> 12) & 0xff;
 373         printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
 374                base, cellid, vendor);
 375
 376         switch(vendor) {
 377         case AMBA_VENDOR_ST:
 378                 vic_init_st(base, irq_start, vic_sources, node);
 379                 return;
 380         default:
 381                 printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
 382                 /* fall through */
 383         case AMBA_VENDOR_ARM:
 384                 break;
 385         }
 386
 387         /* Disable all interrupts initially. */
 388         vic_disable(base);
 389
 390         /* Make sure we clear all existing interrupts */
 391         vic_clear_interrupts(base);
 392
 393         vic_init2(base);
 394
 395         vic_register(base, irq_start, vic_sources, resume_sources, node);
 396 }
 397
 398 /**
 399  * vic_init() - initialise a vectored interrupt controller
 400  * @base: iomem base address
 401  * @irq_start: starting interrupt number, must be muliple of 32
 402  * @vic_sources: bitmask of interrupt sources to allow
 403  * @resume_sources: bitmask of interrupt sources to allow for resume
 404  */
 405 void __init vic_init(void __iomem *base, unsigned int irq_start,
 406                      u32 vic_sources, u32 resume_sources)
 407 {
 408         __vic_init(base, irq_start, vic_sources, resume_sources, NULL);
 409 }
 410
 411 #ifdef CONFIG_OF
 412 int __init vic_of_init(struct device_node *node, struct device_node *parent)
 413 {
 414         void __iomem *regs;
 415
 416         if (WARN(parent, "non-root VICs are not supported"))
 417                 return -EINVAL;
 418
 419         regs = of_iomap(node, 0);
 420         if (WARN_ON(!regs))
 421                 return -EIO;
 422
 423         /*
 424          * Passing 0 as first IRQ makes the simple domain allocate descriptors
 425          */
 426         __vic_init(regs, 0, ~0, ~0, node);
 427
 428         return 0;
 429 }
 430 #endif /* CONFIG OF */
 431
 432 /*
 433  * Handle each interrupt in a single VIC.  Returns non-zero if we've
 434  * handled at least one interrupt.  This reads the status register
 435  * before handling each interrupt, which is necessary given that
 436  * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
 437  */
 438 static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
 439 {
 440         u32 stat, irq;
 441         int handled = 0;
 442
 443         while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
 444                 irq = ffs(stat) - 1;
 445                 handle_IRQ(irq_find_mapping(vic->domain, irq), regs);
 446                 handled = 1;
 447         }
 448
 449         return handled;
 450 }
 451
 452 /*
 453  * Keep iterating over all registered VIC's until there are no pending
 454  * interrupts.
 455  */
 456 asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
 457 {
 458         int i, handled;
 459
 460         do {
 461                 for (i = 0, handled = 0; i < vic_id; ++i)
 462                         handled |= handle_one_vic(&vic_devices[i], regs);
 463         } while (handled);
 464 }