arch/arm/mach-at91/at91_aic.h

   1 /*
   2  * arch/arm/mach-at91/include/mach/at91_aic.h
   3  *
   4  * Copyright (C) 2005 Ivan Kokshaysky
   5  * Copyright (C) SAN People
   6  *
   7  * Advanced Interrupt Controller (AIC) - System peripherals registers.
   8  * Based on AT91RM9200 datasheet revision E.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  */
  15
  16 #ifndef AT91_AIC_H
  17 #define AT91_AIC_H
  18
  19 #ifndef __ASSEMBLY__
  20 extern void __iomem *at91_aic_base;
  21
  22 #define at91_aic_read(field) \
  23         __raw_readl(at91_aic_base + field)
  24
  25 #define at91_aic_write(field, value) \
  26         __raw_writel(value, at91_aic_base + field)
  27 #else
  28 .extern at91_aic_base
  29 #endif
  30
  31 /* Number of irq lines managed by AIC */
  32 #define NR_AIC_IRQS     32
  33 #define NR_AIC5_IRQS    128
  34
  35 #define AT91_AIC5_SSR           0x0                     /* Source Select Register [AIC5] */
  36 #define         AT91_AIC5_INTSEL_MSK    (0x7f << 0)             /* Interrupt Line Selection Mask */
  37
  38 #define AT91_AIC_IRQ_MIN_PRIORITY       0
  39 #define AT91_AIC_IRQ_MAX_PRIORITY       7
  40
  41 #define AT91_AIC_SMR(n)         ((n) * 4)               /* Source Mode Registers 0-31 */
  42 #define AT91_AIC5_SMR           0x4                     /* Source Mode Register [AIC5] */
  43 #define         AT91_AIC_PRIOR          (7 << 0)                /* Priority Level */
  44 #define         AT91_AIC_SRCTYPE        (3 << 5)                /* Interrupt Source Type */
  45 #define                 AT91_AIC_SRCTYPE_LOW            (0 << 5)
  46 #define                 AT91_AIC_SRCTYPE_FALLING        (1 << 5)
  47 #define                 AT91_AIC_SRCTYPE_HIGH           (2 << 5)
  48 #define                 AT91_AIC_SRCTYPE_RISING         (3 << 5)
  49
  50 #define AT91_AIC_SVR(n)         (0x80 + ((n) * 4))      /* Source Vector Registers 0-31 */
  51 #define AT91_AIC5_SVR           0x8                     /* Source Vector Register [AIC5] */
  52 #define AT91_AIC_IVR            0x100                   /* Interrupt Vector Register */
  53 #define AT91_AIC5_IVR           0x10                    /* Interrupt Vector Register [AIC5] */
  54 #define AT91_AIC_FVR            0x104                   /* Fast Interrupt Vector Register */
  55 #define AT91_AIC5_FVR           0x14                    /* Fast Interrupt Vector Register [AIC5] */
  56 #define AT91_AIC_ISR            0x108                   /* Interrupt Status Register */
  57 #define AT91_AIC5_ISR           0x18                    /* Interrupt Status Register [AIC5] */
  58 #define         AT91_AIC_IRQID          (0x1f << 0)             /* Current Interrupt Identifier */
  59
  60 #define AT91_AIC_IPR            0x10c                   /* Interrupt Pending Register */
  61 #define AT91_AIC5_IPR0          0x20                    /* Interrupt Pending Register 0 [AIC5] */
  62 #define AT91_AIC5_IPR1          0x24                    /* Interrupt Pending Register 1 [AIC5] */
  63 #define AT91_AIC5_IPR2          0x28                    /* Interrupt Pending Register 2 [AIC5] */
  64 #define AT91_AIC5_IPR3          0x2c                    /* Interrupt Pending Register 3 [AIC5] */
  65 #define AT91_AIC_IMR            0x110                   /* Interrupt Mask Register */
  66 #define AT91_AIC5_IMR           0x30                    /* Interrupt Mask Register [AIC5] */
  67 #define AT91_AIC_CISR           0x114                   /* Core Interrupt Status Register */
  68 #define AT91_AIC5_CISR          0x34                    /* Core Interrupt Status Register [AIC5] */
  69 #define         AT91_AIC_NFIQ           (1 << 0)                /* nFIQ Status */
  70 #define         AT91_AIC_NIRQ           (1 << 1)                /* nIRQ Status */
  71
  72 #define AT91_AIC_IECR           0x120                   /* Interrupt Enable Command Register */
  73 #define AT91_AIC5_IECR          0x40                    /* Interrupt Enable Command Register [AIC5] */
  74 #define AT91_AIC_IDCR           0x124                   /* Interrupt Disable Command Register */
  75 #define AT91_AIC5_IDCR          0x44                    /* Interrupt Disable Command Register [AIC5] */
  76 #define AT91_AIC_ICCR           0x128                   /* Interrupt Clear Command Register */
  77 #define AT91_AIC5_ICCR          0x48                    /* Interrupt Clear Command Register [AIC5] */
  78 #define AT91_AIC_ISCR           0x12c                   /* Interrupt Set Command Register */
  79 #define AT91_AIC5_ISCR          0x4c                    /* Interrupt Set Command Register [AIC5] */
  80 #define AT91_AIC_EOICR          0x130                   /* End of Interrupt Command Register */
  81 #define AT91_AIC5_EOICR         0x38                    /* End of Interrupt Command Register [AIC5] */
  82 #define AT91_AIC_SPU            0x134                   /* Spurious Interrupt Vector Register */
  83 #define AT91_AIC5_SPU           0x3c                    /* Spurious Interrupt Vector Register [AIC5] */
  84 #define AT91_AIC_DCR            0x138                   /* Debug Control Register */
  85 #define AT91_AIC5_DCR           0x6c                    /* Debug Control Register [AIC5] */
  86 #define         AT91_AIC_DCR_PROT       (1 << 0)                /* Protection Mode */
  87 #define         AT91_AIC_DCR_GMSK       (1 << 1)                /* General Mask */
  88
  89 #define AT91_AIC_FFER           0x140                   /* Fast Forcing Enable Register [SAM9 only] */
  90 #define AT91_AIC5_FFER          0x50                    /* Fast Forcing Enable Register [AIC5] */
  91 #define AT91_AIC_FFDR           0x144                   /* Fast Forcing Disable Register [SAM9 only] */
  92 #define AT91_AIC5_FFDR          0x54                    /* Fast Forcing Disable Register [AIC5] */
  93 #define AT91_AIC_FFSR           0x148                   /* Fast Forcing Status Register [SAM9 only] */
  94 #define AT91_AIC5_FFSR          0x58                    /* Fast Forcing Status Register [AIC5] */
  95
  96 void at91_aic_handle_irq(struct pt_regs *regs);
  97 void at91_aic5_handle_irq(struct pt_regs *regs);
  98
  99 #endif