arch/arm/mach-at91/at91sam926x_time.c

   1 /*
   2  * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
   3  *
   4  * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
   5  * Revision      2005 M. Nicolas Diremdjian, ATMEL Rousset, France
   6  * Converted to ClockSource/ClockEvents by David Brownell.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/interrupt.h>
  13 #include <linux/irq.h>
  14 #include <linux/kernel.h>
  15 #include <linux/clk.h>
  16 #include <linux/clockchips.h>
  17 #include <linux/of.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_irq.h>
  20
  21 #include <asm/mach/time.h>
  22
  23 #define AT91_PIT_MR             0x00                    /* Mode Register */
  24 #define         AT91_PIT_PITIEN         (1 << 25)               /* Timer Interrupt Enable */
  25 #define         AT91_PIT_PITEN          (1 << 24)               /* Timer Enabled */
  26 #define         AT91_PIT_PIV            (0xfffff)               /* Periodic Interval Value */
  27
  28 #define AT91_PIT_SR             0x04                    /* Status Register */
  29 #define         AT91_PIT_PITS           (1 << 0)                /* Timer Status */
  30
  31 #define AT91_PIT_PIVR           0x08                    /* Periodic Interval Value Register */
  32 #define AT91_PIT_PIIR           0x0c                    /* Periodic Interval Image Register */
  33 #define         AT91_PIT_PICNT          (0xfff << 20)           /* Interval Counter */
  34 #define         AT91_PIT_CPIV           (0xfffff)               /* Inverval Value */
  35
  36 #define PIT_CPIV(x)     ((x) & AT91_PIT_CPIV)
  37 #define PIT_PICNT(x)    (((x) & AT91_PIT_PICNT) >> 20)
  38
  39 static u32 pit_cycle;           /* write-once */
  40 static u32 pit_cnt;             /* access only w/system irq blocked */
  41 static void __iomem *pit_base_addr __read_mostly;
  42
  43 static inline unsigned int pit_read(unsigned int reg_offset)
  44 {
  45         return __raw_readl(pit_base_addr + reg_offset);
  46 }
  47
  48 static inline void pit_write(unsigned int reg_offset, unsigned long value)
  49 {
  50         __raw_writel(value, pit_base_addr + reg_offset);
  51 }
  52
  53 /*
  54  * Clocksource:  just a monotonic counter of MCK/16 cycles.
  55  * We don't care whether or not PIT irqs are enabled.
  56  */
  57 static cycle_t read_pit_clk(struct clocksource *cs)
  58 {
  59         unsigned long flags;
  60         u32 elapsed;
  61         u32 t;
  62
  63         raw_local_irq_save(flags);
  64         elapsed = pit_cnt;
  65         t = pit_read(AT91_PIT_PIIR);
  66         raw_local_irq_restore(flags);
  67
  68         elapsed += PIT_PICNT(t) * pit_cycle;
  69         elapsed += PIT_CPIV(t);
  70         return elapsed;
  71 }
  72
  73 static struct clocksource pit_clk = {
  74         .name           = "pit",
  75         .rating         = 175,
  76         .read           = read_pit_clk,
  77         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  78 };
  79
  80
  81 /*
  82  * Clockevent device:  interrupts every 1/HZ (== pit_cycles * MCK/16)
  83  */
  84 static void
  85 pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
  86 {
  87         switch (mode) {
  88         case CLOCK_EVT_MODE_PERIODIC:
  89                 /* update clocksource counter */
  90                 pit_cnt += pit_cycle * PIT_PICNT(pit_read(AT91_PIT_PIVR));
  91                 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
  92                                 | AT91_PIT_PITIEN);
  93                 break;
  94         case CLOCK_EVT_MODE_ONESHOT:
  95                 BUG();
  96                 /* FALLTHROUGH */
  97         case CLOCK_EVT_MODE_SHUTDOWN:
  98         case CLOCK_EVT_MODE_UNUSED:
  99                 /* disable irq, leaving the clocksource active */
 100                 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
 101                 break;
 102         case CLOCK_EVT_MODE_RESUME:
 103                 break;
 104         }
 105 }
 106
 107 static struct clock_event_device pit_clkevt = {
 108         .name           = "pit",
 109         .features       = CLOCK_EVT_FEAT_PERIODIC,
 110         .shift          = 32,
 111         .rating         = 100,
 112         .set_mode       = pit_clkevt_mode,
 113 };
 114
 115
 116 /*
 117  * IRQ handler for the timer.
 118  */
 119 static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
 120 {
 121         /*
 122          * irqs should be disabled here, but as the irq is shared they are only
 123          * guaranteed to be off if the timer irq is registered first.
 124          */
 125         WARN_ON_ONCE(!irqs_disabled());
 126
 127         /* The PIT interrupt may be disabled, and is shared */
 128         if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
 129                         && (pit_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
 130                 unsigned nr_ticks;
 131
 132                 /* Get number of ticks performed before irq, and ack it */
 133                 nr_ticks = PIT_PICNT(pit_read(AT91_PIT_PIVR));
 134                 do {
 135                         pit_cnt += pit_cycle;
 136                         pit_clkevt.event_handler(&pit_clkevt);
 137                         nr_ticks--;
 138                 } while (nr_ticks);
 139
 140                 return IRQ_HANDLED;
 141         }
 142
 143         return IRQ_NONE;
 144 }
 145
 146 static struct irqaction at91sam926x_pit_irq = {
 147         .name           = "at91_tick",
 148         .flags          = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 149         .handler        = at91sam926x_pit_interrupt,
 150         .irq            = NR_IRQS_LEGACY + AT91_ID_SYS,
 151 };
 152
 153 static void at91sam926x_pit_reset(void)
 154 {
 155         /* Disable timer and irqs */
 156         pit_write(AT91_PIT_MR, 0);
 157
 158         /* Clear any pending interrupts, wait for PIT to stop counting */
 159         while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0)
 160                 cpu_relax();
 161
 162         /* Start PIT but don't enable IRQ */
 163         pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
 164 }
 165
 166 #ifdef CONFIG_OF
 167 static struct of_device_id pit_timer_ids[] = {
 168         { .compatible = "atmel,at91sam9260-pit" },
 169         { /* sentinel */ }
 170 };
 171
 172 static int __init of_at91sam926x_pit_init(void)
 173 {
 174         struct device_node      *np;
 175         int                     ret;
 176
 177         np = of_find_matching_node(NULL, pit_timer_ids);
 178         if (!np)
 179                 goto err;
 180
 181         pit_base_addr = of_iomap(np, 0);
 182         if (!pit_base_addr)
 183                 goto node_err;
 184
 185         /* Get the interrupts property */
 186         ret = irq_of_parse_and_map(np, 0);
 187         if (!ret) {
 188                 pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
 189                 goto ioremap_err;
 190         }
 191         at91sam926x_pit_irq.irq = ret;
 192
 193         of_node_put(np);
 194
 195         return 0;
 196
 197 ioremap_err:
 198         iounmap(pit_base_addr);
 199 node_err:
 200         of_node_put(np);
 201 err:
 202         return -EINVAL;
 203 }
 204 #else
 205 static int __init of_at91sam926x_pit_init(void)
 206 {
 207         return -EINVAL;
 208 }
 209 #endif
 210
 211 /*
 212  * Set up both clocksource and clockevent support.
 213  */
 214 static void __init at91sam926x_pit_init(void)
 215 {
 216         unsigned long   pit_rate;
 217         unsigned        bits;
 218         int             ret;
 219
 220         /* For device tree enabled device: initialize here */
 221         of_at91sam926x_pit_init();
 222
 223         /*
 224          * Use our actual MCK to figure out how many MCK/16 ticks per
 225          * 1/HZ period (instead of a compile-time constant LATCH).
 226          */
 227         pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
 228         pit_cycle = (pit_rate + HZ/2) / HZ;
 229         WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
 230
 231         /* Initialize and enable the timer */
 232         at91sam926x_pit_reset();
 233
 234         /*
 235          * Register clocksource.  The high order bits of PIV are unused,
 236          * so this isn't a 32-bit counter unless we get clockevent irqs.
 237          */
 238         bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
 239         pit_clk.mask = CLOCKSOURCE_MASK(bits);
 240         clocksource_register_hz(&pit_clk, pit_rate);
 241
 242         /* Set up irq handler */
 243         ret = setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
 244         if (ret)
 245                 pr_crit("AT91: PIT: Unable to setup IRQ\n");
 246
 247         /* Set up and register clockevents */
 248         pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
 249         pit_clkevt.cpumask = cpumask_of(0);
 250         clockevents_register_device(&pit_clkevt);
 251 }
 252
 253 static void at91sam926x_pit_suspend(void)
 254 {
 255         /* Disable timer */
 256         pit_write(AT91_PIT_MR, 0);
 257 }
 258
 259 void __init at91sam926x_ioremap_pit(u32 addr)
 260 {
 261 #if defined(CONFIG_OF)
 262         struct device_node *np =
 263                 of_find_matching_node(NULL, pit_timer_ids);
 264
 265         if (np) {
 266                 of_node_put(np);
 267                 return;
 268         }
 269 #endif
 270         pit_base_addr = ioremap(addr, 16);
 271
 272         if (!pit_base_addr)
 273                 panic("Impossible to ioremap PIT\n");
 274 }
 275
 276 struct sys_timer at91sam926x_timer = {
 277         .init           = at91sam926x_pit_init,
 278         .suspend        = at91sam926x_pit_suspend,
 279         .resume         = at91sam926x_pit_reset,
 280 };