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x86, efi: Set runtime_version to the EFI spec revision
[linux/fpc-iii.git] / arch / arm / mach-imx / clk-imx6q.c
blob7f2c10c7413abaf0786b45a29933bc60745bd12c
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13 #include <linux/init.h>
14 #include <linux/types.h>
15 #include <linux/clk.h>
16 #include <linux/clkdev.h>
17 #include <linux/err.h>
18 #include <linux/io.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22
23 #include "clk.h"
24 #include "common.h"
25
26 #define CCGR0 0x68
27 #define CCGR1 0x6c
28 #define CCGR2 0x70
29 #define CCGR3 0x74
30 #define CCGR4 0x78
31 #define CCGR5 0x7c
32 #define CCGR6 0x80
33 #define CCGR7 0x84
34
35 #define CLPCR 0x54
36 #define BP_CLPCR_LPM 0
37 #define BM_CLPCR_LPM (0x3 << 0)
38 #define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
39 #define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
40 #define BM_CLPCR_SBYOS (0x1 << 6)
41 #define BM_CLPCR_DIS_REF_OSC (0x1 << 7)
42 #define BM_CLPCR_VSTBY (0x1 << 8)
43 #define BP_CLPCR_STBY_COUNT 9
44 #define BM_CLPCR_STBY_COUNT (0x3 << 9)
45 #define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
46 #define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)
47 #define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)
48 #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)
49 #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
50 #define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)
51 #define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)
52 #define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)
53 #define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)
54 #define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
55 #define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
56
57 static void __iomem *ccm_base;
58
59 void __init imx6q_clock_map_io(void) { }
60
61 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
62 {
63 u32 val = readl_relaxed(ccm_base + CLPCR);
64
65 val &= ~BM_CLPCR_LPM;
66 switch (mode) {
67 case WAIT_CLOCKED:
68 break;
69 case WAIT_UNCLOCKED:
70 val |= 0x1 << BP_CLPCR_LPM;
71 break;
72 case STOP_POWER_ON:
73 val |= 0x2 << BP_CLPCR_LPM;
74 break;
75 case WAIT_UNCLOCKED_POWER_OFF:
76 val |= 0x1 << BP_CLPCR_LPM;
77 val &= ~BM_CLPCR_VSTBY;
78 val &= ~BM_CLPCR_SBYOS;
79 break;
80 case STOP_POWER_OFF:
81 val |= 0x2 << BP_CLPCR_LPM;
82 val |= 0x3 << BP_CLPCR_STBY_COUNT;
83 val |= BM_CLPCR_VSTBY;
84 val |= BM_CLPCR_SBYOS;
85 break;
86 default:
87 return -EINVAL;
88 }
89
90 writel_relaxed(val, ccm_base + CLPCR);
91
92 return 0;
93 }
94
95 static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
96 static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
97 static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
98 static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", };
99 static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
100 static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
101 static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", };
102 static const char *audio_sels[] = { "pll4_audio", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
103 static const char *gpu_axi_sels[] = { "axi", "ahb", };
104 static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
105 static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
106 static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", };
107 static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
108 static const char *ldb_di_sels[] = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_pfd1_540m", };
109 static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
110 static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
111 static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
112 static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
113 static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
114 static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", };
115 static const char *pcie_axi_sels[] = { "axi", "ahb", };
116 static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio", };
117 static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
118 static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
119 static const char *emi_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
120 static const char *vdo_axi_sels[] = { "axi", "ahb", };
121 static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
122 static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video",
123 "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
124 "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio", };
125
126 enum mx6q_clks {
127 dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
128 pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
129 pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw,
130 periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel,
131 esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel,
132 gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel,
133 ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel,
134 ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel,
135 ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel,
136 usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel,
137 emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2,
138 periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf,
139 asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root,
140 gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf,
141 ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre,
142 ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf,
143 ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf,
144 usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf,
145 emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf,
146 mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial,
147 can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet,
148 esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
149 hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
150 ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
151 mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
152 gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
153 ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
154 usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
155 pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
156 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
157 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref,
158 clk_max
159 };
160
161 static struct clk *clk[clk_max];
162 static struct clk_onecell_data clk_data;
163
164 static enum mx6q_clks const clks_init_on[] __initconst = {
165 mmdc_ch0_axi, rom,
166 };
167
168 static struct clk_div_table clk_enet_ref_table[] = {
169 { .val = 0, .div = 20, },
170 { .val = 1, .div = 10, },
171 { .val = 2, .div = 5, },
172 { .val = 3, .div = 4, },
173 };
174
175 int __init mx6q_clocks_init(void)
176 {
177 struct device_node *np;
178 void __iomem *base;
179 int i, irq;
180
181 clk[dummy] = imx_clk_fixed("dummy", 0);
182
183 /* retrieve the freqency of fixed clocks from device tree */
184 for_each_compatible_node(np, NULL, "fixed-clock") {
185 u32 rate;
186 if (of_property_read_u32(np, "clock-frequency", &rate))
187 continue;
188
189 if (of_device_is_compatible(np, "fsl,imx-ckil"))
190 clk[ckil] = imx_clk_fixed("ckil", rate);
191 else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
192 clk[ckih] = imx_clk_fixed("ckih", rate);
193 else if (of_device_is_compatible(np, "fsl,imx-osc"))
194 clk[osc] = imx_clk_fixed("osc", rate);
195 }
196
197 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
198 base = of_iomap(np, 0);
199 WARN_ON(!base);
200
201 /* type name parent_name base div_mask */
202 clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
203 clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
204 clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
205 clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
206 clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
207 clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
208 clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
209 clk[pll8_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x0);
210
211 clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
212 clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
213
214 clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
215 clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
216
217 clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
218 clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
219
220 clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
221 base + 0xe0, 0, 2, 0, clk_enet_ref_table,
222 &imx_ccm_lock);
223
224 /* name parent_name reg idx */
225 clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
226 clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
227 clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
228 clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
229 clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
230 clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
231 clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
232
233 /* name parent_name mult div */
234 clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
235 clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
236 clk[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
237 clk[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
238 clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2);
239
240 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm");
241 base = of_iomap(np, 0);
242 WARN_ON(!base);
243 ccm_base = base;
244
245 /* name reg shift width parent_names num_parents */
246 clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
247 clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
248 clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
249 clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
250 clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
251 clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
252 clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
253 clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
254 clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
255 clk[spdif_sel] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
256 clk[gpu2d_axi] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
257 clk[gpu3d_axi] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
258 clk[gpu2d_core_sel] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
259 clk[gpu3d_core_sel] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
260 clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
261 clk[ipu1_sel] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
262 clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
263 clk[ldb_di0_sel] = imx_clk_mux("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
264 clk[ldb_di1_sel] = imx_clk_mux("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
265 clk[ipu1_di0_pre_sel] = imx_clk_mux("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
266 clk[ipu1_di1_pre_sel] = imx_clk_mux("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
267 clk[ipu2_di0_pre_sel] = imx_clk_mux("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
268 clk[ipu2_di1_pre_sel] = imx_clk_mux("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
269 clk[ipu1_di0_sel] = imx_clk_mux("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels));
270 clk[ipu1_di1_sel] = imx_clk_mux("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels));
271 clk[ipu2_di0_sel] = imx_clk_mux("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels));
272 clk[ipu2_di1_sel] = imx_clk_mux("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels));
273 clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
274 clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
275 clk[ssi1_sel] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
276 clk[ssi2_sel] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
277 clk[ssi3_sel] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
278 clk[usdhc1_sel] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
279 clk[usdhc2_sel] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
280 clk[usdhc3_sel] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
281 clk[usdhc4_sel] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
282 clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
283 clk[emi_sel] = imx_clk_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels));
284 clk[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_sels, ARRAY_SIZE(emi_sels));
285 clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
286 clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
287 clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
288
289 /* name reg shift width busy: reg, shift parent_names num_parents */
290 clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
291 clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
292
293 /* name parent_name reg shift width */
294 clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
295 clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
296 clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
297 clk[ipg_per] = imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6);
298 clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
299 clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
300 clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
301 clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
302 clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
303 clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
304 clk[can_root] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6);
305 clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
306 clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
307 clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
308 clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
309 clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
310 clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
311 clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
312 clk[ldb_di0_podf] = imx_clk_divider("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1);
313 clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
314 clk[ldb_di1_podf] = imx_clk_divider("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1);
315 clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
316 clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
317 clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
318 clk[ipu2_di1_pre] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3);
319 clk[hsi_tx_podf] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3);
320 clk[ssi1_pred] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
321 clk[ssi1_podf] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
322 clk[ssi2_pred] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
323 clk[ssi2_podf] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
324 clk[ssi3_pred] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
325 clk[ssi3_podf] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
326 clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
327 clk[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
328 clk[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
329 clk[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
330 clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
331 clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
332 clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
333 clk[emi_podf] = imx_clk_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3);
334 clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3);
335 clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
336 clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
337
338 /* name parent_name reg shift width busy: reg, shift */
339 clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
340 clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
341 clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
342 clk[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
343 clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
344
345 /* name parent_name reg shift */
346 clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
347 clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
348 clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
349 clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
350 clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
351 clk[can2_serial] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
352 clk[ecspi1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
353 clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
354 clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
355 clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
356 clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
357 clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
358 clk[esai] = imx_clk_gate2("esai", "esai_podf", base + 0x6c, 16);
359 clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
360 clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
361 clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
362 clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
363 clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
364 clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
365 clk[i2c1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
366 clk[i2c2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
367 clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
368 clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
369 clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
370 clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
371 clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
372 clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
373 clk[ipu2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
374 clk[ipu2_di0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
375 clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
376 clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
377 clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
378 clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
379 clk[mlb] = imx_clk_gate2("mlb", "pll8_mlb", base + 0x74, 18);
380 clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
381 clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
382 clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
383 clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
384 clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
385 clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
386 clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
387 clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
388 clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
389 clk[pwm4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22);
390 clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
391 clk[gpmi_bch] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
392 clk[gpmi_io] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
393 clk[gpmi_apb] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
394 clk[rom] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
395 clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
396 clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
397 clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
398 clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
399 clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
400 clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
401 clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
402 clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
403 clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
404 clk[usdhc1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
405 clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
406 clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
407 clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
408 clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
409 clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
410 clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
411
412 for (i = 0; i < ARRAY_SIZE(clk); i++)
413 if (IS_ERR(clk[i]))
414 pr_err("i.MX6q clk %d: register failed with %ld\n",
415 i, PTR_ERR(clk[i]));
416
417 clk_data.clks = clk;
418 clk_data.clk_num = ARRAY_SIZE(clk);
419 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
420
421 clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
422 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
423 clk_register_clkdev(clk[twd], NULL, "smp_twd");
424 clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
425 clk_register_clkdev(clk[ahb], "ahb", NULL);
426 clk_register_clkdev(clk[cko1], "cko1", NULL);
427 clk_register_clkdev(clk[arm], NULL, "cpu0");
428
429 /*
430 * The gpmi needs 100MHz frequency in the EDO/Sync mode,
431 * We can not get the 100MHz from the pll2_pfd0_352m.
432 * So choose pll2_pfd2_396m as enfc_sel's parent.
433 */
434 clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
435
436 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
437 clk_prepare_enable(clk[clks_init_on[i]]);
438
439 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
440 base = of_iomap(np, 0);
441 WARN_ON(!base);
442 irq = irq_of_parse_and_map(np, 0);
443 mxc_timer_init(base, irq);
444
445 return 0;
446 }
Linux with added FPC-III support