arch/arm/mach-imx/mm-imx5.c

   1 /*
   2  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License.  You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  *
  11  * Create static mapping between physical to virtual memory.
  12  */
  13
  14 #include <linux/mm.h>
  15 #include <linux/init.h>
  16 #include <linux/clk.h>
  17 #include <linux/pinctrl/machine.h>
  18
  19 #include <asm/mach/map.h>
  20
  21 #include "common.h"
  22 #include "devices/devices-common.h"
  23 #include "hardware.h"
  24 #include "iomux-v3.h"
  25
  26 /*
  27  * Define the MX50 memory map.
  28  */
  29 static struct map_desc mx50_io_desc[] __initdata = {
  30         imx_map_entry(MX50, TZIC, MT_DEVICE),
  31         imx_map_entry(MX50, SPBA0, MT_DEVICE),
  32         imx_map_entry(MX50, AIPS1, MT_DEVICE),
  33         imx_map_entry(MX50, AIPS2, MT_DEVICE),
  34 };
  35
  36 /*
  37  * Define the MX51 memory map.
  38  */
  39 static struct map_desc mx51_io_desc[] __initdata = {
  40         imx_map_entry(MX51, TZIC, MT_DEVICE),
  41         imx_map_entry(MX51, IRAM, MT_DEVICE),
  42         imx_map_entry(MX51, AIPS1, MT_DEVICE),
  43         imx_map_entry(MX51, SPBA0, MT_DEVICE),
  44         imx_map_entry(MX51, AIPS2, MT_DEVICE),
  45 };
  46
  47 /*
  48  * Define the MX53 memory map.
  49  */
  50 static struct map_desc mx53_io_desc[] __initdata = {
  51         imx_map_entry(MX53, TZIC, MT_DEVICE),
  52         imx_map_entry(MX53, AIPS1, MT_DEVICE),
  53         imx_map_entry(MX53, SPBA0, MT_DEVICE),
  54         imx_map_entry(MX53, AIPS2, MT_DEVICE),
  55 };
  56
  57 /*
  58  * This function initializes the memory map. It is called during the
  59  * system startup to create static physical to virtual memory mappings
  60  * for the IO modules.
  61  */
  62 void __init mx50_map_io(void)
  63 {
  64         iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
  65 }
  66
  67 void __init mx51_map_io(void)
  68 {
  69         iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
  70 }
  71
  72 void __init mx53_map_io(void)
  73 {
  74         iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
  75 }
  76
  77 void __init imx50_init_early(void)
  78 {
  79         mxc_set_cpu_type(MXC_CPU_MX50);
  80         mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
  81         mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
  82 }
  83
  84 /*
  85  * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
  86  * the Freescale marketing division. However this did not remove the
  87  * hardware from the chip which still needs to be configured for proper
  88  * IPU support.
  89  */
  90 static void __init imx51_ipu_mipi_setup(void)
  91 {
  92         void __iomem *hsc_addr;
  93         hsc_addr = MX51_IO_ADDRESS(MX51_MIPI_HSC_BASE_ADDR);
  94
  95         /* setup MIPI module to legacy mode */
  96         __raw_writel(0xf00, hsc_addr);
  97
  98         /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
  99         __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff,
 100                 hsc_addr + 0x800);
 101 }
 102
 103 void __init imx51_init_early(void)
 104 {
 105         imx51_ipu_mipi_setup();
 106         mxc_set_cpu_type(MXC_CPU_MX51);
 107         mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
 108         mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
 109 }
 110
 111 void __init imx53_init_early(void)
 112 {
 113         mxc_set_cpu_type(MXC_CPU_MX53);
 114         mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
 115         mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
 116 }
 117
 118 void __init mx50_init_irq(void)
 119 {
 120         tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
 121 }
 122
 123 void __init mx51_init_irq(void)
 124 {
 125         tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
 126 }
 127
 128 void __init mx53_init_irq(void)
 129 {
 130         tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
 131 }
 132
 133 static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
 134         .ap_2_ap_addr = 642,
 135         .uart_2_mcu_addr = 817,
 136         .mcu_2_app_addr = 747,
 137         .mcu_2_shp_addr = 961,
 138         .ata_2_mcu_addr = 1473,
 139         .mcu_2_ata_addr = 1392,
 140         .app_2_per_addr = 1033,
 141         .app_2_mcu_addr = 683,
 142         .shp_2_per_addr = 1251,
 143         .shp_2_mcu_addr = 892,
 144 };
 145
 146 static struct sdma_platform_data imx51_sdma_pdata __initdata = {
 147         .fw_name = "sdma-imx51.bin",
 148         .script_addrs = &imx51_sdma_script,
 149 };
 150
 151 static const struct resource imx50_audmux_res[] __initconst = {
 152         DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K),
 153 };
 154
 155 static const struct resource imx51_audmux_res[] __initconst = {
 156         DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
 157 };
 158
 159 void __init imx50_soc_init(void)
 160 {
 161         mxc_device_init();
 162
 163         /* i.mx50 has the i.mx35 type gpio */
 164         mxc_register_gpio("imx35-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
 165         mxc_register_gpio("imx35-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
 166         mxc_register_gpio("imx35-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
 167         mxc_register_gpio("imx35-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
 168         mxc_register_gpio("imx35-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
 169         mxc_register_gpio("imx35-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
 170
 171         /* i.mx50 has the i.mx31 type audmux */
 172         platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res,
 173                                         ARRAY_SIZE(imx50_audmux_res));
 174 }
 175
 176 void __init imx51_soc_init(void)
 177 {
 178         mxc_device_init();
 179
 180         /* i.mx51 has the i.mx35 type gpio */
 181         mxc_register_gpio("imx35-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
 182         mxc_register_gpio("imx35-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
 183         mxc_register_gpio("imx35-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
 184         mxc_register_gpio("imx35-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
 185
 186         pinctrl_provide_dummies();
 187
 188         /* i.mx51 has the i.mx35 type sdma */
 189         imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
 190
 191         /* Setup AIPS registers */
 192         imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
 193         imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR));
 194
 195         /* i.mx51 has the i.mx31 type audmux */
 196         platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res,
 197                                         ARRAY_SIZE(imx51_audmux_res));
 198 }
 199
 200 void __init imx51_init_late(void)
 201 {
 202         mx51_neon_fixup();
 203         imx51_pm_init();
 204 }
 205
 206 void __init imx53_init_late(void)
 207 {
 208         imx53_pm_init();
 209 }