arch/arm/mach-imx/mx50.h

   1 #ifndef __MACH_MX50_H__
   2 #define __MACH_MX50_H__
   3
   4 /*
   5  * IROM
   6  */
   7 #define MX50_IROM_BASE_ADDR             0x0
   8 #define MX50_IROM_SIZE                  SZ_64K
   9
  10 /* TZIC */
  11 #define MX50_TZIC_BASE_ADDR             0x0fffc000
  12 #define MX50_TZIC_SIZE                  SZ_16K
  13
  14 /*
  15  * IRAM
  16  */
  17 #define MX50_IRAM_BASE_ADDR     0xf8000000      /* internal ram */
  18 #define MX50_IRAM_PARTITIONS    16
  19 #define MX50_IRAM_SIZE          (MX50_IRAM_PARTITIONS * SZ_8K)  /* 128KB */
  20
  21 /*
  22  * Databahn
  23  */
  24 #define MX50_DATABAHN_BASE_ADDR                 0x14000000
  25
  26 /*
  27  * Graphics Memory of GPU
  28  */
  29 #define MX50_GPU2D_BASE_ADDR            0x20000000
  30
  31 #define MX50_DEBUG_BASE_ADDR            0x40000000
  32 #define MX50_DEBUG_SIZE                 SZ_1M
  33 #define MX50_ETB_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x00001000)
  34 #define MX50_ETM_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x00002000)
  35 #define MX50_TPIU_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x00003000)
  36 #define MX50_CTI0_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x00004000)
  37 #define MX50_CTI1_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x00005000)
  38 #define MX50_CTI2_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x00006000)
  39 #define MX50_CTI3_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x00007000)
  40 #define MX50_CORTEX_DBG_BASE_ADDR       (MX50_DEBUG_BASE_ADDR + 0x00008000)
  41
  42 #define MX50_APBHDMA_BASE_ADDR          (MX50_DEBUG_BASE_ADDR + 0x01000000)
  43 #define MX50_OCOTP_CTRL_BASE_ADDR       (MX50_DEBUG_BASE_ADDR + 0x01002000)
  44 #define MX50_DIGCTL_BASE_ADDR           (MX50_DEBUG_BASE_ADDR + 0x01004000)
  45 #define MX50_GPMI_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x01006000)
  46 #define MX50_BCH_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x01008000)
  47 #define MX50_ELCDIF_BASE_ADDR           (MX50_DEBUG_BASE_ADDR + 0x0100a000)
  48 #define MX50_EPXP_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x0100c000)
  49 #define MX50_DCP_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x0100e000)
  50 #define MX50_EPDC_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x01010000)
  51 #define MX50_QOSC_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x01012000)
  52 #define MX50_PERFMON_BASE_ADDR          (MX50_DEBUG_BASE_ADDR + 0x01014000)
  53 #define MX50_SSP_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x01016000)
  54 #define MX50_ANATOP_BASE_ADDR           (MX50_DEBUG_BASE_ADDR + 0x01018000)
  55 #define MX50_NIC_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x08000000)
  56
  57 /*
  58  * SPBA global module enabled #0
  59  */
  60 #define MX50_SPBA0_BASE_ADDR            0x50000000
  61 #define MX50_SPBA0_SIZE                 SZ_1M
  62
  63 #define MX50_MMC_SDHC1_BASE_ADDR        (MX50_SPBA0_BASE_ADDR + 0x00004000)
  64 #define MX50_MMC_SDHC2_BASE_ADDR        (MX50_SPBA0_BASE_ADDR + 0x00008000)
  65 #define MX50_UART3_BASE_ADDR            (MX50_SPBA0_BASE_ADDR + 0x0000c000)
  66 #define MX50_CSPI1_BASE_ADDR            (MX50_SPBA0_BASE_ADDR + 0x00010000)
  67 #define MX50_SSI2_BASE_ADDR             (MX50_SPBA0_BASE_ADDR + 0x00014000)
  68 #define MX50_MMC_SDHC3_BASE_ADDR        (MX50_SPBA0_BASE_ADDR + 0x00020000)
  69 #define MX50_MMC_SDHC4_BASE_ADDR        (MX50_SPBA0_BASE_ADDR + 0x00024000)
  70
  71 /*
  72  * AIPS 1
  73  */
  74 #define MX50_AIPS1_BASE_ADDR    0x53f00000
  75 #define MX50_AIPS1_SIZE         SZ_1M
  76
  77 #define MX50_OTG_BASE_ADDR      (MX50_AIPS1_BASE_ADDR + 0x00080000)
  78 #define MX50_GPIO1_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x00084000)
  79 #define MX50_GPIO2_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x00088000)
  80 #define MX50_GPIO3_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x0008c000)
  81 #define MX50_GPIO4_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x00090000)
  82 #define MX50_KPP_BASE_ADDR      (MX50_AIPS1_BASE_ADDR + 0x00094000)
  83 #define MX50_WDOG_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x00098000)
  84 #define MX50_GPT1_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000a0000)
  85 #define MX50_SRTC_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000a4000)
  86 #define MX50_IOMUXC_BASE_ADDR   (MX50_AIPS1_BASE_ADDR + 0x000a8000)
  87 #define MX50_EPIT1_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000ac000)
  88 #define MX50_PWM1_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000b4000)
  89 #define MX50_PWM2_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000b8000)
  90 #define MX50_UART1_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000bc000)
  91 #define MX50_UART2_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000c0000)
  92 #define MX50_SRC_BASE_ADDR      (MX50_AIPS1_BASE_ADDR + 0x000d0000)
  93 #define MX50_CCM_BASE_ADDR      (MX50_AIPS1_BASE_ADDR + 0x000d4000)
  94 #define MX50_GPC_BASE_ADDR      (MX50_AIPS1_BASE_ADDR + 0x000d8000)
  95 #define MX50_GPIO5_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000dc000)
  96 #define MX50_GPIO6_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000e0000)
  97 #define MX50_I2C3_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000ec000)
  98 #define MX50_UART4_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000f0000)
  99
 100 #define MX50_MSHC_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000f4000)
 101 #define MX50_RNGB_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000f8000)
 102
 103 /*
 104  * AIPS 2
 105  */
 106 #define MX50_AIPS2_BASE_ADDR    0x63f00000
 107 #define MX50_AIPS2_SIZE         SZ_1M
 108
 109 #define MX50_PLL1_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x00080000)
 110 #define MX50_PLL2_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x00084000)
 111 #define MX50_PLL3_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x00088000)
 112 #define MX50_UART5_BASE_ADDR    (MX50_AIPS2_BASE_ADDR + 0x00090000)
 113 #define MX50_AHBMAX_BASE_ADDR   (MX50_AIPS2_BASE_ADDR + 0x00094000)
 114 #define MX50_ARM_BASE_ADDR      (MX50_AIPS2_BASE_ADDR + 0x000a0000)
 115 #define MX50_OWIRE_BASE_ADDR    (MX50_AIPS2_BASE_ADDR + 0x000a4000)
 116 #define MX50_CSPI2_BASE_ADDR    (MX50_AIPS2_BASE_ADDR + 0x000ac000)
 117 #define MX50_SDMA_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x000b0000)
 118 #define MX50_ROMCP_BASE_ADDR    (MX50_AIPS2_BASE_ADDR + 0x000b8000)
 119 #define MX50_CSPI3_BASE_ADDR    (MX50_AIPS2_BASE_ADDR + 0x000c0000)
 120 #define MX50_I2C2_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x000c4000)
 121 #define MX50_I2C1_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x000c8000)
 122 #define MX50_SSI1_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x000cc000)
 123 #define MX50_AUDMUX_BASE_ADDR   (MX50_AIPS2_BASE_ADDR + 0x000d0000)
 124 #define MX50_WEIM_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x000d8000)
 125 #define MX50_FEC_BASE_ADDR      (MX50_AIPS2_BASE_ADDR + 0x000ec000)
 126
 127 /*
 128  * Memory regions and CS
 129  */
 130 #define MX50_CSD0_BASE_ADDR             0x70000000
 131 #define MX50_CSD1_BASE_ADDR             0xb0000000
 132 #define MX50_CS0_BASE_ADDR              0xf0000000
 133
 134 #define MX50_IO_P2V(x)                  IMX_IO_P2V(x)
 135 #define MX50_IO_ADDRESS(x)              IOMEM(MX50_IO_P2V(x))
 136
 137 /*
 138  * defines for SPBA modules
 139  */
 140 #define MX50_SPBA_SDHC1         0x04
 141 #define MX50_SPBA_SDHC2         0x08
 142 #define MX50_SPBA_UART3         0x0c
 143 #define MX50_SPBA_CSPI1         0x10
 144 #define MX50_SPBA_SSI2          0x14
 145 #define MX50_SPBA_SDHC3         0x20
 146 #define MX50_SPBA_SDHC4         0x24
 147 #define MX50_SPBA_SPDIF         0x28
 148 #define MX50_SPBA_ATA           0x30
 149 #define MX50_SPBA_SLIM          0x34
 150 #define MX50_SPBA_HSI2C         0x38
 151 #define MX50_SPBA_CTRL          0x3c
 152
 153 /*
 154  * DMA request assignments
 155  */
 156 #define MX50_DMA_REQ_GPC                1
 157 #define MX50_DMA_REQ_ATA_UART4_RX       2
 158 #define MX50_DMA_REQ_ATA_UART4_TX       3
 159 #define MX50_DMA_REQ_CSPI1_RX           6
 160 #define MX50_DMA_REQ_CSPI1_TX           7
 161 #define MX50_DMA_REQ_CSPI2_RX           8
 162 #define MX50_DMA_REQ_CSPI2_TX           9
 163 #define MX50_DMA_REQ_I2C3_SDHC3         10
 164 #define MX50_DMA_REQ_SDHC4              11
 165 #define MX50_DMA_REQ_UART2_FIRI_RX      12
 166 #define MX50_DMA_REQ_UART2_FIRI_TX      13
 167 #define MX50_DMA_REQ_EXT0               14
 168 #define MX50_DMA_REQ_EXT1               15
 169 #define MX50_DMA_REQ_UART5_RX           16
 170 #define MX50_DMA_REQ_UART5_TX           17
 171 #define MX50_DMA_REQ_UART1_RX           18
 172 #define MX50_DMA_REQ_UART1_TX           19
 173 #define MX50_DMA_REQ_I2C1_SDHC1         20
 174 #define MX50_DMA_REQ_I2C2_SDHC2         21
 175 #define MX50_DMA_REQ_SSI2_RX2           22
 176 #define MX50_DMA_REQ_SSI2_TX2           23
 177 #define MX50_DMA_REQ_SSI2_RX1           24
 178 #define MX50_DMA_REQ_SSI2_TX1           25
 179 #define MX50_DMA_REQ_SSI1_RX2           26
 180 #define MX50_DMA_REQ_SSI1_TX2           27
 181 #define MX50_DMA_REQ_SSI1_RX1           28
 182 #define MX50_DMA_REQ_SSI1_TX1           29
 183 #define MX50_DMA_REQ_CSPI_RX            38
 184 #define MX50_DMA_REQ_CSPI_TX            39
 185 #define MX50_DMA_REQ_UART3_RX           42
 186 #define MX50_DMA_REQ_UART3_TX           43
 187
 188 /*
 189  * Interrupt numbers
 190  */
 191 #include <asm/irq.h>
 192 #define MX50_INT_MMC_SDHC1      (NR_IRQS_LEGACY + 1)
 193 #define MX50_INT_MMC_SDHC2      (NR_IRQS_LEGACY + 2)
 194 #define MX50_INT_MMC_SDHC3      (NR_IRQS_LEGACY + 3)
 195 #define MX50_INT_MMC_SDHC4      (NR_IRQS_LEGACY + 4)
 196 #define MX50_INT_DAP            (NR_IRQS_LEGACY + 5)
 197 #define MX50_INT_SDMA           (NR_IRQS_LEGACY + 6)
 198 #define MX50_INT_IOMUX          (NR_IRQS_LEGACY + 7)
 199 #define MX50_INT_UART4          (NR_IRQS_LEGACY + 13)
 200 #define MX50_INT_USB_H1         (NR_IRQS_LEGACY + 14)
 201 #define MX50_INT_USB_OTG        (NR_IRQS_LEGACY + 18)
 202 #define MX50_INT_DATABAHN       (NR_IRQS_LEGACY + 19)
 203 #define MX50_INT_ELCDIF         (NR_IRQS_LEGACY + 20)
 204 #define MX50_INT_EPXP           (NR_IRQS_LEGACY + 21)
 205 #define MX50_INT_SRTC_NTZ       (NR_IRQS_LEGACY + 24)
 206 #define MX50_INT_SRTC_TZ        (NR_IRQS_LEGACY + 25)
 207 #define MX50_INT_EPDC           (NR_IRQS_LEGACY + 27)
 208 #define MX50_INT_NIC            (NR_IRQS_LEGACY + 28)
 209 #define MX50_INT_SSI1           (NR_IRQS_LEGACY + 29)
 210 #define MX50_INT_SSI2           (NR_IRQS_LEGACY + 30)
 211 #define MX50_INT_UART1          (NR_IRQS_LEGACY + 31)
 212 #define MX50_INT_UART2          (NR_IRQS_LEGACY + 32)
 213 #define MX50_INT_UART3          (NR_IRQS_LEGACY + 33)
 214 #define MX50_INT_RESV34         (NR_IRQS_LEGACY + 34)
 215 #define MX50_INT_RESV35         (NR_IRQS_LEGACY + 35)
 216 #define MX50_INT_CSPI1          (NR_IRQS_LEGACY + 36)
 217 #define MX50_INT_CSPI2          (NR_IRQS_LEGACY + 37)
 218 #define MX50_INT_CSPI           (NR_IRQS_LEGACY + 38)
 219 #define MX50_INT_GPT            (NR_IRQS_LEGACY + 39)
 220 #define MX50_INT_EPIT1          (NR_IRQS_LEGACY + 40)
 221 #define MX50_INT_GPIO1_INT7     (NR_IRQS_LEGACY + 42)
 222 #define MX50_INT_GPIO1_INT6     (NR_IRQS_LEGACY + 43)
 223 #define MX50_INT_GPIO1_INT5     (NR_IRQS_LEGACY + 44)
 224 #define MX50_INT_GPIO1_INT4     (NR_IRQS_LEGACY + 45)
 225 #define MX50_INT_GPIO1_INT3     (NR_IRQS_LEGACY + 46)
 226 #define MX50_INT_GPIO1_INT2     (NR_IRQS_LEGACY + 47)
 227 #define MX50_INT_GPIO1_INT1     (NR_IRQS_LEGACY + 48)
 228 #define MX50_INT_GPIO1_INT0     (NR_IRQS_LEGACY + 49)
 229 #define MX50_INT_GPIO1_LOW      (NR_IRQS_LEGACY + 50)
 230 #define MX50_INT_GPIO1_HIGH     (NR_IRQS_LEGACY + 51)
 231 #define MX50_INT_GPIO2_LOW      (NR_IRQS_LEGACY + 52)
 232 #define MX50_INT_GPIO2_HIGH     (NR_IRQS_LEGACY + 53)
 233 #define MX50_INT_GPIO3_LOW      (NR_IRQS_LEGACY + 54)
 234 #define MX50_INT_GPIO3_HIGH     (NR_IRQS_LEGACY + 55)
 235 #define MX50_INT_GPIO4_LOW      (NR_IRQS_LEGACY + 56)
 236 #define MX50_INT_GPIO4_HIGH     (NR_IRQS_LEGACY + 57)
 237 #define MX50_INT_WDOG1          (NR_IRQS_LEGACY + 58)
 238 #define MX50_INT_KPP            (NR_IRQS_LEGACY + 60)
 239 #define MX50_INT_PWM1           (NR_IRQS_LEGACY + 61)
 240 #define MX50_INT_I2C1           (NR_IRQS_LEGACY + 62)
 241 #define MX50_INT_I2C2           (NR_IRQS_LEGACY + 63)
 242 #define MX50_INT_I2C3           (NR_IRQS_LEGACY + 64)
 243 #define MX50_INT_RESV65         (NR_IRQS_LEGACY + 65)
 244 #define MX50_INT_DCDC           (NR_IRQS_LEGACY + 66)
 245 #define MX50_INT_THERMAL_ALARM  (NR_IRQS_LEGACY + 67)
 246 #define MX50_INT_ANA3           (NR_IRQS_LEGACY + 68)
 247 #define MX50_INT_ANA4           (NR_IRQS_LEGACY + 69)
 248 #define MX50_INT_CCM1           (NR_IRQS_LEGACY + 71)
 249 #define MX50_INT_CCM2           (NR_IRQS_LEGACY + 72)
 250 #define MX50_INT_GPC1           (NR_IRQS_LEGACY + 73)
 251 #define MX50_INT_GPC2           (NR_IRQS_LEGACY + 74)
 252 #define MX50_INT_SRC            (NR_IRQS_LEGACY + 75)
 253 #define MX50_INT_NM             (NR_IRQS_LEGACY + 76)
 254 #define MX50_INT_PMU            (NR_IRQS_LEGACY + 77)
 255 #define MX50_INT_CTI_IRQ        (NR_IRQS_LEGACY + 78)
 256 #define MX50_INT_CTI1_TG0       (NR_IRQS_LEGACY + 79)
 257 #define MX50_INT_CTI1_TG1       (NR_IRQS_LEGACY + 80)
 258 #define MX50_INT_GPU2_IRQ       (NR_IRQS_LEGACY + 84)
 259 #define MX50_INT_GPU2_BUSY      (NR_IRQS_LEGACY + 85)
 260 #define MX50_INT_UART5          (NR_IRQS_LEGACY + 86)
 261 #define MX50_INT_FEC            (NR_IRQS_LEGACY + 87)
 262 #define MX50_INT_OWIRE          (NR_IRQS_LEGACY + 88)
 263 #define MX50_INT_CTI1_TG2       (NR_IRQS_LEGACY + 89)
 264 #define MX50_INT_SJC            (NR_IRQS_LEGACY + 90)
 265 #define MX50_INT_DCP_CHAN1_3    (NR_IRQS_LEGACY + 91)
 266 #define MX50_INT_DCP_CHAN0      (NR_IRQS_LEGACY + 92)
 267 #define MX50_INT_PWM2           (NR_IRQS_LEGACY + 94)
 268 #define MX50_INT_RNGB           (NR_IRQS_LEGACY + 97)
 269 #define MX50_INT_CTI1_TG3       (NR_IRQS_LEGACY + 98)
 270 #define MX50_INT_RAWNAND_BCH    (NR_IRQS_LEGACY + 100)
 271 #define MX50_INT_RAWNAND_GPMI   (NR_IRQS_LEGACY + 102)
 272 #define MX50_INT_GPIO5_LOW      (NR_IRQS_LEGACY + 103)
 273 #define MX50_INT_GPIO5_HIGH     (NR_IRQS_LEGACY + 104)
 274 #define MX50_INT_GPIO6_LOW      (NR_IRQS_LEGACY + 105)
 275 #define MX50_INT_GPIO6_HIGH     (NR_IRQS_LEGACY + 106)
 276 #define MX50_INT_MSHC           (NR_IRQS_LEGACY + 109)
 277 #define MX50_INT_APBHDMA_CHAN0  (NR_IRQS_LEGACY + 110)
 278 #define MX50_INT_APBHDMA_CHAN1  (NR_IRQS_LEGACY + 111)
 279 #define MX50_INT_APBHDMA_CHAN2  (NR_IRQS_LEGACY + 112)
 280 #define MX50_INT_APBHDMA_CHAN3  (NR_IRQS_LEGACY + 113)
 281 #define MX50_INT_APBHDMA_CHAN4  (NR_IRQS_LEGACY + 114)
 282 #define MX50_INT_APBHDMA_CHAN5  (NR_IRQS_LEGACY + 115)
 283 #define MX50_INT_APBHDMA_CHAN6  (NR_IRQS_LEGACY + 116)
 284 #define MX50_INT_APBHDMA_CHAN7  (NR_IRQS_LEGACY + 117)
 285
 286 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
 287 extern int mx50_revision(void);
 288 #endif
 289
 290 #endif /* ifndef __MACH_MX50_H__ */