arch/arm/mach-mvebu/irq-armada-370-xp.c

   1 /*
   2  * Marvell Armada 370 and Armada XP SoC IRQ handling
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  * Ben Dooks <ben.dooks@codethink.co.uk>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2.  This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/irq.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/irqdomain.h>
  25 #include <asm/mach/arch.h>
  26 #include <asm/exception.h>
  27 #include <asm/smp_plat.h>
  28 #include <asm/hardware/cache-l2x0.h>
  29
  30 /* Interrupt Controller Registers Map */
  31 #define ARMADA_370_XP_INT_SET_MASK_OFFS         (0x48)
  32 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS       (0x4C)
  33
  34 #define ARMADA_370_XP_INT_CONTROL               (0x00)
  35 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS       (0x30)
  36 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS     (0x34)
  37
  38 #define ARMADA_370_XP_CPU_INTACK_OFFS           (0x44)
  39
  40 #define ARMADA_370_XP_SW_TRIG_INT_OFFS           (0x4)
  41 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS          (0xc)
  42 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS        (0x8)
  43
  44 #define ACTIVE_DOORBELLS                        (8)
  45
  46 static void __iomem *per_cpu_int_base;
  47 static void __iomem *main_int_base;
  48 static struct irq_domain *armada_370_xp_mpic_domain;
  49
  50 static void armada_370_xp_irq_mask(struct irq_data *d)
  51 {
  52         writel(irqd_to_hwirq(d),
  53                per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
  54 }
  55
  56 static void armada_370_xp_irq_unmask(struct irq_data *d)
  57 {
  58         writel(irqd_to_hwirq(d),
  59                per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
  60 }
  61
  62 #ifdef CONFIG_SMP
  63 static int armada_xp_set_affinity(struct irq_data *d,
  64                                   const struct cpumask *mask_val, bool force)
  65 {
  66         return 0;
  67 }
  68 #endif
  69
  70 static struct irq_chip armada_370_xp_irq_chip = {
  71         .name           = "armada_370_xp_irq",
  72         .irq_mask       = armada_370_xp_irq_mask,
  73         .irq_mask_ack   = armada_370_xp_irq_mask,
  74         .irq_unmask     = armada_370_xp_irq_unmask,
  75 #ifdef CONFIG_SMP
  76         .irq_set_affinity = armada_xp_set_affinity,
  77 #endif
  78 };
  79
  80 static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
  81                                       unsigned int virq, irq_hw_number_t hw)
  82 {
  83         armada_370_xp_irq_mask(irq_get_irq_data(virq));
  84         writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
  85
  86         irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
  87                                  handle_level_irq);
  88         irq_set_status_flags(virq, IRQ_LEVEL);
  89         set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
  90
  91         return 0;
  92 }
  93
  94 #ifdef CONFIG_SMP
  95 void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq)
  96 {
  97         int cpu;
  98         unsigned long map = 0;
  99
 100         /* Convert our logical CPU mask into a physical one. */
 101         for_each_cpu(cpu, mask)
 102                 map |= 1 << cpu_logical_map(cpu);
 103
 104         /*
 105          * Ensure that stores to Normal memory are visible to the
 106          * other CPUs before issuing the IPI.
 107          */
 108         dsb();
 109
 110         /* submit softirq */
 111         writel((map << 8) | irq, main_int_base +
 112                 ARMADA_370_XP_SW_TRIG_INT_OFFS);
 113 }
 114
 115 void armada_xp_mpic_smp_cpu_init(void)
 116 {
 117         /* Clear pending IPIs */
 118         writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
 119
 120         /* Enable first 8 IPIs */
 121         writel((1 << ACTIVE_DOORBELLS) - 1, per_cpu_int_base +
 122                 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
 123
 124         /* Unmask IPI interrupt */
 125         writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
 126 }
 127 #endif /* CONFIG_SMP */
 128
 129 static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
 130         .map = armada_370_xp_mpic_irq_map,
 131         .xlate = irq_domain_xlate_onecell,
 132 };
 133
 134 static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 135                                              struct device_node *parent)
 136 {
 137         u32 control;
 138
 139         main_int_base = of_iomap(node, 0);
 140         per_cpu_int_base = of_iomap(node, 1);
 141
 142         BUG_ON(!main_int_base);
 143         BUG_ON(!per_cpu_int_base);
 144
 145         control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
 146
 147         armada_370_xp_mpic_domain =
 148                 irq_domain_add_linear(node, (control >> 2) & 0x3ff,
 149                                 &armada_370_xp_mpic_irq_ops, NULL);
 150
 151         if (!armada_370_xp_mpic_domain)
 152                 panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
 153
 154         irq_set_default_host(armada_370_xp_mpic_domain);
 155
 156 #ifdef CONFIG_SMP
 157         armada_xp_mpic_smp_cpu_init();
 158 #endif
 159
 160         return 0;
 161 }
 162
 163 asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
 164                                                                *regs)
 165 {
 166         u32 irqstat, irqnr;
 167
 168         do {
 169                 irqstat = readl_relaxed(per_cpu_int_base +
 170                                         ARMADA_370_XP_CPU_INTACK_OFFS);
 171                 irqnr = irqstat & 0x3FF;
 172
 173                 if (irqnr > 1022)
 174                         break;
 175
 176                 if (irqnr >= 8) {
 177                         irqnr = irq_find_mapping(armada_370_xp_mpic_domain,
 178                                         irqnr);
 179                         handle_IRQ(irqnr, regs);
 180                         continue;
 181                 }
 182 #ifdef CONFIG_SMP
 183                 /* IPI Handling */
 184                 if (irqnr == 0) {
 185                         u32 ipimask, ipinr;
 186
 187                         ipimask = readl_relaxed(per_cpu_int_base +
 188                                                 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
 189                                 & 0xFF;
 190
 191                         writel(0x0, per_cpu_int_base +
 192                                 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
 193
 194                         /* Handle all pending doorbells */
 195                         for (ipinr = 0; ipinr < ACTIVE_DOORBELLS; ipinr++) {
 196                                 if (ipimask & (0x1 << ipinr))
 197                                         handle_IPI(ipinr, regs);
 198                         }
 199                         continue;
 200                 }
 201 #endif
 202
 203         } while (1);
 204 }
 205
 206 static const struct of_device_id mpic_of_match[] __initconst = {
 207         {.compatible = "marvell,mpic", .data = armada_370_xp_mpic_of_init},
 208         {},
 209 };
 210
 211 void __init armada_370_xp_init_irq(void)
 212 {
 213         of_irq_init(mpic_of_match);
 214 #ifdef CONFIG_CACHE_L2X0
 215         l2x0_of_init(0, ~0UL);
 216 #endif
 217 }