arch/arm/mach-omap2/gpmc-nand.c

   1 /*
   2  * gpmc-nand.c
   3  *
   4  * Copyright (C) 2009 Texas Instruments
   5  * Vimal Singh <vimalsingh@ti.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/io.h>
  15 #include <linux/mtd/nand.h>
  16 #include <linux/platform_data/mtd-nand-omap2.h>
  17
  18 #include <asm/mach/flash.h>
  19
  20 #include "gpmc.h"
  21 #include "soc.h"
  22 #include "gpmc-nand.h"
  23
  24 /* minimum size for IO mapping */
  25 #define NAND_IO_SIZE    4
  26
  27 static struct resource gpmc_nand_resource[] = {
  28         {
  29                 .flags          = IORESOURCE_MEM,
  30         },
  31         {
  32                 .flags          = IORESOURCE_IRQ,
  33         },
  34         {
  35                 .flags          = IORESOURCE_IRQ,
  36         },
  37 };
  38
  39 static struct platform_device gpmc_nand_device = {
  40         .name           = "omap2-nand",
  41         .id             = 0,
  42         .num_resources  = ARRAY_SIZE(gpmc_nand_resource),
  43         .resource       = gpmc_nand_resource,
  44 };
  45
  46 static int omap2_nand_gpmc_retime(
  47                                 struct omap_nand_platform_data *gpmc_nand_data,
  48                                 struct gpmc_timings *gpmc_t)
  49 {
  50         struct gpmc_timings t;
  51         int err;
  52
  53         memset(&t, 0, sizeof(t));
  54         t.sync_clk = gpmc_t->sync_clk;
  55         t.cs_on = gpmc_t->cs_on;
  56         t.adv_on = gpmc_t->adv_on;
  57
  58         /* Read */
  59         t.adv_rd_off = gpmc_t->adv_rd_off;
  60         t.oe_on  = t.adv_on;
  61         t.access = gpmc_t->access;
  62         t.oe_off = gpmc_t->oe_off;
  63         t.cs_rd_off = gpmc_t->cs_rd_off;
  64         t.rd_cycle = gpmc_t->rd_cycle;
  65
  66         /* Write */
  67         t.adv_wr_off = gpmc_t->adv_wr_off;
  68         t.we_on  = t.oe_on;
  69         if (cpu_is_omap34xx()) {
  70                 t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus;
  71                 t.wr_access = gpmc_t->wr_access;
  72         }
  73         t.we_off = gpmc_t->we_off;
  74         t.cs_wr_off = gpmc_t->cs_wr_off;
  75         t.wr_cycle = gpmc_t->wr_cycle;
  76
  77         /* Configure GPMC */
  78         if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
  79                 gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1);
  80         else
  81                 gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
  82         gpmc_cs_configure(gpmc_nand_data->cs,
  83                         GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
  84         gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_WP, 0);
  85         err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
  86         if (err)
  87                 return err;
  88
  89         return 0;
  90 }
  91
  92 static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
  93 {
  94         /* support only OMAP3 class */
  95         if (!cpu_is_omap34xx()) {
  96                 pr_err("BCH ecc is not supported on this CPU\n");
  97                 return 0;
  98         }
  99
 100         /*
 101          * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
 102          * Other chips may be added if confirmed to work.
 103          */
 104         if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&
 105             (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
 106                 pr_err("BCH 4-bit mode is not supported on this CPU\n");
 107                 return 0;
 108         }
 109
 110         return 1;
 111 }
 112
 113 int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
 114                           struct gpmc_timings *gpmc_t)
 115 {
 116         int err = 0;
 117         struct device *dev = &gpmc_nand_device.dev;
 118
 119         gpmc_nand_device.dev.platform_data = gpmc_nand_data;
 120
 121         err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
 122                                 (unsigned long *)&gpmc_nand_resource[0].start);
 123         if (err < 0) {
 124                 dev_err(dev, "Cannot request GPMC CS\n");
 125                 return err;
 126         }
 127
 128         gpmc_nand_resource[0].end = gpmc_nand_resource[0].start +
 129                                                         NAND_IO_SIZE - 1;
 130
 131         gpmc_nand_resource[1].start =
 132                                 gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
 133         gpmc_nand_resource[2].start =
 134                                 gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
 135
 136         if (gpmc_t) {
 137                 err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t);
 138                 if (err < 0) {
 139                         dev_err(dev, "Unable to set gpmc timings: %d\n", err);
 140                         return err;
 141                 }
 142         }
 143
 144         /* Enable RD PIN Monitoring Reg */
 145         if (gpmc_nand_data->dev_ready) {
 146                 gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1);
 147         }
 148
 149         gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
 150
 151         if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt))
 152                 return -EINVAL;
 153
 154         err = platform_device_register(&gpmc_nand_device);
 155         if (err < 0) {
 156                 dev_err(dev, "Unable to register NAND device\n");
 157                 goto out_free_cs;
 158         }
 159
 160         return 0;
 161
 162 out_free_cs:
 163         gpmc_cs_free(gpmc_nand_data->cs);
 164
 165         return err;
 166 }