arch/arm/mach-omap2/omap-wakeupgen.c

   1 /*
   2  * OMAP WakeupGen Source file
   3  *
   4  * OMAP WakeupGen is the interrupt controller extension used along
   5  * with ARM GIC to wake the CPU out from low power states on
   6  * external interrupts. It is responsible for generating wakeup
   7  * event from the incoming interrupts and enable bits. It is
   8  * implemented in MPU always ON power domain. During normal operation,
   9  * WakeupGen delivers external interrupts directly to the GIC.
  10  *
  11  * Copyright (C) 2011 Texas Instruments, Inc.
  12  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22 #include <linux/irq.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/cpu.h>
  25 #include <linux/notifier.h>
  26 #include <linux/cpu_pm.h>
  27
  28 #include <asm/hardware/gic.h>
  29
  30 #include "omap-wakeupgen.h"
  31 #include "omap-secure.h"
  32
  33 #include "soc.h"
  34 #include "omap4-sar-layout.h"
  35 #include "common.h"
  36
  37 #define MAX_NR_REG_BANKS        5
  38 #define MAX_IRQS                160
  39 #define WKG_MASK_ALL            0x00000000
  40 #define WKG_UNMASK_ALL          0xffffffff
  41 #define CPU_ENA_OFFSET          0x400
  42 #define CPU0_ID                 0x0
  43 #define CPU1_ID                 0x1
  44 #define OMAP4_NR_BANKS          4
  45 #define OMAP4_NR_IRQS           128
  46
  47 static void __iomem *wakeupgen_base;
  48 static void __iomem *sar_base;
  49 static DEFINE_SPINLOCK(wakeupgen_lock);
  50 static unsigned int irq_target_cpu[MAX_IRQS];
  51 static unsigned int irq_banks = MAX_NR_REG_BANKS;
  52 static unsigned int max_irqs = MAX_IRQS;
  53 static unsigned int omap_secure_apis;
  54
  55 /*
  56  * Static helper functions.
  57  */
  58 static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
  59 {
  60         return __raw_readl(wakeupgen_base + OMAP_WKG_ENB_A_0 +
  61                                 (cpu * CPU_ENA_OFFSET) + (idx * 4));
  62 }
  63
  64 static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
  65 {
  66         __raw_writel(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
  67                                 (cpu * CPU_ENA_OFFSET) + (idx * 4));
  68 }
  69
  70 static inline void sar_writel(u32 val, u32 offset, u8 idx)
  71 {
  72         __raw_writel(val, sar_base + offset + (idx * 4));
  73 }
  74
  75 static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
  76 {
  77         unsigned int spi_irq;
  78
  79         /*
  80          * PPIs and SGIs are not supported.
  81          */
  82         if (irq < OMAP44XX_IRQ_GIC_START)
  83                 return -EINVAL;
  84
  85         /*
  86          * Subtract the GIC offset.
  87          */
  88         spi_irq = irq - OMAP44XX_IRQ_GIC_START;
  89         if (spi_irq > MAX_IRQS) {
  90                 pr_err("omap wakeupGen: Invalid IRQ%d\n", irq);
  91                 return -EINVAL;
  92         }
  93
  94         /*
  95          * Each WakeupGen register controls 32 interrupt.
  96          * i.e. 1 bit per SPI IRQ
  97          */
  98         *reg_index = spi_irq >> 5;
  99         *bit_posn = spi_irq %= 32;
 100
 101         return 0;
 102 }
 103
 104 static void _wakeupgen_clear(unsigned int irq, unsigned int cpu)
 105 {
 106         u32 val, bit_number;
 107         u8 i;
 108
 109         if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
 110                 return;
 111
 112         val = wakeupgen_readl(i, cpu);
 113         val &= ~BIT(bit_number);
 114         wakeupgen_writel(val, i, cpu);
 115 }
 116
 117 static void _wakeupgen_set(unsigned int irq, unsigned int cpu)
 118 {
 119         u32 val, bit_number;
 120         u8 i;
 121
 122         if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
 123                 return;
 124
 125         val = wakeupgen_readl(i, cpu);
 126         val |= BIT(bit_number);
 127         wakeupgen_writel(val, i, cpu);
 128 }
 129
 130 /*
 131  * Architecture specific Mask extension
 132  */
 133 static void wakeupgen_mask(struct irq_data *d)
 134 {
 135         unsigned long flags;
 136
 137         spin_lock_irqsave(&wakeupgen_lock, flags);
 138         _wakeupgen_clear(d->irq, irq_target_cpu[d->irq]);
 139         spin_unlock_irqrestore(&wakeupgen_lock, flags);
 140 }
 141
 142 /*
 143  * Architecture specific Unmask extension
 144  */
 145 static void wakeupgen_unmask(struct irq_data *d)
 146 {
 147         unsigned long flags;
 148
 149         spin_lock_irqsave(&wakeupgen_lock, flags);
 150         _wakeupgen_set(d->irq, irq_target_cpu[d->irq]);
 151         spin_unlock_irqrestore(&wakeupgen_lock, flags);
 152 }
 153
 154 #ifdef CONFIG_HOTPLUG_CPU
 155 static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
 156
 157 static void _wakeupgen_save_masks(unsigned int cpu)
 158 {
 159         u8 i;
 160
 161         for (i = 0; i < irq_banks; i++)
 162                 per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
 163 }
 164
 165 static void _wakeupgen_restore_masks(unsigned int cpu)
 166 {
 167         u8 i;
 168
 169         for (i = 0; i < irq_banks; i++)
 170                 wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
 171 }
 172
 173 static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
 174 {
 175         u8 i;
 176
 177         for (i = 0; i < irq_banks; i++)
 178                 wakeupgen_writel(reg, i, cpu);
 179 }
 180
 181 /*
 182  * Mask or unmask all interrupts on given CPU.
 183  *      0 = Mask all interrupts on the 'cpu'
 184  *      1 = Unmask all interrupts on the 'cpu'
 185  * Ensure that the initial mask is maintained. This is faster than
 186  * iterating through GIC registers to arrive at the correct masks.
 187  */
 188 static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
 189 {
 190         unsigned long flags;
 191
 192         spin_lock_irqsave(&wakeupgen_lock, flags);
 193         if (set) {
 194                 _wakeupgen_save_masks(cpu);
 195                 _wakeupgen_set_all(cpu, WKG_MASK_ALL);
 196         } else {
 197                 _wakeupgen_set_all(cpu, WKG_UNMASK_ALL);
 198                 _wakeupgen_restore_masks(cpu);
 199         }
 200         spin_unlock_irqrestore(&wakeupgen_lock, flags);
 201 }
 202 #endif
 203
 204 #ifdef CONFIG_CPU_PM
 205 static inline void omap4_irq_save_context(void)
 206 {
 207         u32 i, val;
 208
 209         if (omap_rev() == OMAP4430_REV_ES1_0)
 210                 return;
 211
 212         for (i = 0; i < irq_banks; i++) {
 213                 /* Save the CPUx interrupt mask for IRQ 0 to 127 */
 214                 val = wakeupgen_readl(i, 0);
 215                 sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
 216                 val = wakeupgen_readl(i, 1);
 217                 sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);
 218
 219                 /*
 220                  * Disable the secure interrupts for CPUx. The restore
 221                  * code blindly restores secure and non-secure interrupt
 222                  * masks from SAR RAM. Secure interrupts are not suppose
 223                  * to be enabled from HLOS. So overwrite the SAR location
 224                  * so that the secure interrupt remains disabled.
 225                  */
 226                 sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
 227                 sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
 228         }
 229
 230         /* Save AuxBoot* registers */
 231         val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
 232         __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
 233         val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
 234         __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
 235
 236         /* Save SyncReq generation logic */
 237         val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
 238         __raw_writel(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
 239         val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
 240         __raw_writel(val, sar_base + PTMSYNCREQ_EN_OFFSET);
 241
 242         /* Set the Backup Bit Mask status */
 243         val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
 244         val |= SAR_BACKUP_STATUS_WAKEUPGEN;
 245         __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
 246
 247 }
 248
 249 static inline void omap5_irq_save_context(void)
 250 {
 251         u32 i, val;
 252
 253         for (i = 0; i < irq_banks; i++) {
 254                 /* Save the CPUx interrupt mask for IRQ 0 to 159 */
 255                 val = wakeupgen_readl(i, 0);
 256                 sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);
 257                 val = wakeupgen_readl(i, 1);
 258                 sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);
 259                 sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
 260                 sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
 261         }
 262
 263         /* Save AuxBoot* registers */
 264         val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
 265         __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
 266         val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
 267         __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
 268
 269         /* Set the Backup Bit Mask status */
 270         val = __raw_readl(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
 271         val |= SAR_BACKUP_STATUS_WAKEUPGEN;
 272         __raw_writel(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
 273
 274 }
 275
 276 /*
 277  * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
 278  * ROM code. WakeupGen IP is integrated along with GIC to manage the
 279  * interrupt wakeups from CPU low power states. It manages
 280  * masking/unmasking of Shared peripheral interrupts(SPI). So the
 281  * interrupt enable/disable control should be in sync and consistent
 282  * at WakeupGen and GIC so that interrupts are not lost.
 283  */
 284 static void irq_save_context(void)
 285 {
 286         if (!sar_base)
 287                 sar_base = omap4_get_sar_ram_base();
 288
 289         if (soc_is_omap54xx())
 290                 omap5_irq_save_context();
 291         else
 292                 omap4_irq_save_context();
 293 }
 294
 295 /*
 296  * Clear WakeupGen SAR backup status.
 297  */
 298 static void irq_sar_clear(void)
 299 {
 300         u32 val;
 301         u32 offset = SAR_BACKUP_STATUS_OFFSET;
 302
 303         if (soc_is_omap54xx())
 304                 offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
 305
 306         val = __raw_readl(sar_base + offset);
 307         val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
 308         __raw_writel(val, sar_base + offset);
 309 }
 310
 311 /*
 312  * Save GIC and Wakeupgen interrupt context using secure API
 313  * for HS/EMU devices.
 314  */
 315 static void irq_save_secure_context(void)
 316 {
 317         u32 ret;
 318         ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX,
 319                                 FLAG_START_CRITICAL,
 320                                 0, 0, 0, 0, 0);
 321         if (ret != API_HAL_RET_VALUE_OK)
 322                 pr_err("GIC and Wakeupgen context save failed\n");
 323 }
 324 #endif
 325
 326 #ifdef CONFIG_HOTPLUG_CPU
 327 static int __cpuinit irq_cpu_hotplug_notify(struct notifier_block *self,
 328                                          unsigned long action, void *hcpu)
 329 {
 330         unsigned int cpu = (unsigned int)hcpu;
 331
 332         switch (action) {
 333         case CPU_ONLINE:
 334                 wakeupgen_irqmask_all(cpu, 0);
 335                 break;
 336         case CPU_DEAD:
 337                 wakeupgen_irqmask_all(cpu, 1);
 338                 break;
 339         }
 340         return NOTIFY_OK;
 341 }
 342
 343 static struct notifier_block __refdata irq_hotplug_notifier = {
 344         .notifier_call = irq_cpu_hotplug_notify,
 345 };
 346
 347 static void __init irq_hotplug_init(void)
 348 {
 349         register_hotcpu_notifier(&irq_hotplug_notifier);
 350 }
 351 #else
 352 static void __init irq_hotplug_init(void)
 353 {}
 354 #endif
 355
 356 #ifdef CONFIG_CPU_PM
 357 static int irq_notifier(struct notifier_block *self, unsigned long cmd, void *v)
 358 {
 359         switch (cmd) {
 360         case CPU_CLUSTER_PM_ENTER:
 361                 if (omap_type() == OMAP2_DEVICE_TYPE_GP)
 362                         irq_save_context();
 363                 else
 364                         irq_save_secure_context();
 365                 break;
 366         case CPU_CLUSTER_PM_EXIT:
 367                 if (omap_type() == OMAP2_DEVICE_TYPE_GP)
 368                         irq_sar_clear();
 369                 break;
 370         }
 371         return NOTIFY_OK;
 372 }
 373
 374 static struct notifier_block irq_notifier_block = {
 375         .notifier_call = irq_notifier,
 376 };
 377
 378 static void __init irq_pm_init(void)
 379 {
 380         /* FIXME: Remove this when MPU OSWR support is added */
 381         if (!soc_is_omap54xx())
 382                 cpu_pm_register_notifier(&irq_notifier_block);
 383 }
 384 #else
 385 static void __init irq_pm_init(void)
 386 {}
 387 #endif
 388
 389 void __iomem *omap_get_wakeupgen_base(void)
 390 {
 391         return wakeupgen_base;
 392 }
 393
 394 int omap_secure_apis_support(void)
 395 {
 396         return omap_secure_apis;
 397 }
 398
 399 /*
 400  * Initialise the wakeupgen module.
 401  */
 402 int __init omap_wakeupgen_init(void)
 403 {
 404         int i;
 405         unsigned int boot_cpu = smp_processor_id();
 406
 407         /* Not supported on OMAP4 ES1.0 silicon */
 408         if (omap_rev() == OMAP4430_REV_ES1_0) {
 409                 WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
 410                 return -EPERM;
 411         }
 412
 413         /* Static mapping, never released */
 414         wakeupgen_base = ioremap(OMAP_WKUPGEN_BASE, SZ_4K);
 415         if (WARN_ON(!wakeupgen_base))
 416                 return -ENOMEM;
 417
 418         if (cpu_is_omap44xx()) {
 419                 irq_banks = OMAP4_NR_BANKS;
 420                 max_irqs = OMAP4_NR_IRQS;
 421                 omap_secure_apis = 1;
 422         }
 423
 424         /* Clear all IRQ bitmasks at wakeupGen level */
 425         for (i = 0; i < irq_banks; i++) {
 426                 wakeupgen_writel(0, i, CPU0_ID);
 427                 wakeupgen_writel(0, i, CPU1_ID);
 428         }
 429
 430         /*
 431          * Override GIC architecture specific functions to add
 432          * OMAP WakeupGen interrupt controller along with GIC
 433          */
 434         gic_arch_extn.irq_mask = wakeupgen_mask;
 435         gic_arch_extn.irq_unmask = wakeupgen_unmask;
 436         gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;
 437
 438         /*
 439          * FIXME: Add support to set_smp_affinity() once the core
 440          * GIC code has necessary hooks in place.
 441          */
 442
 443         /* Associate all the IRQs to boot CPU like GIC init does. */
 444         for (i = 0; i < max_irqs; i++)
 445                 irq_target_cpu[i] = boot_cpu;
 446
 447         irq_hotplug_init();
 448         irq_pm_init();
 449
 450         return 0;
 451 }