x86, efi: Set runtime_version to the EFI spec revision
[linux/fpc-iii.git] / arch / arm / mach-omap2 / omap_hwmod_2xxx_interconnect_data.c
blob47901a5e76de517b9f86d5f4bc83b0614857e5e1
1 /*
2 * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * XXX handle crossbar/shared link difference for L3?
12 * XXX these should be marked initdata for multi-OMAP kernels
14 #include <asm/sizes.h>
16 #include "omap_hwmod.h"
17 #include "l3_2xxx.h"
18 #include "l4_2xxx.h"
19 #include "serial.h"
21 #include "omap_hwmod_common_data.h"
23 static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
25 .pa_start = OMAP2_UART1_BASE,
26 .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
27 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
29 { }
32 static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
34 .pa_start = OMAP2_UART2_BASE,
35 .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
36 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
38 { }
41 static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
43 .pa_start = OMAP2_UART3_BASE,
44 .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
45 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
47 { }
50 static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
52 .pa_start = 0x4802a000,
53 .pa_end = 0x4802a000 + SZ_1K - 1,
54 .flags = ADDR_TYPE_RT
56 { }
59 static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
61 .pa_start = 0x48078000,
62 .pa_end = 0x48078000 + SZ_1K - 1,
63 .flags = ADDR_TYPE_RT
65 { }
68 static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
70 .pa_start = 0x4807a000,
71 .pa_end = 0x4807a000 + SZ_1K - 1,
72 .flags = ADDR_TYPE_RT
74 { }
77 static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
79 .pa_start = 0x4807c000,
80 .pa_end = 0x4807c000 + SZ_1K - 1,
81 .flags = ADDR_TYPE_RT
83 { }
86 static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
88 .pa_start = 0x4807e000,
89 .pa_end = 0x4807e000 + SZ_1K - 1,
90 .flags = ADDR_TYPE_RT
92 { }
95 static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
97 .pa_start = 0x48080000,
98 .pa_end = 0x48080000 + SZ_1K - 1,
99 .flags = ADDR_TYPE_RT
104 static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
106 .pa_start = 0x48082000,
107 .pa_end = 0x48082000 + SZ_1K - 1,
108 .flags = ADDR_TYPE_RT
113 static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
115 .pa_start = 0x48084000,
116 .pa_end = 0x48084000 + SZ_1K - 1,
117 .flags = ADDR_TYPE_RT
122 struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
124 .name = "mpu",
125 .pa_start = 0x48076000,
126 .pa_end = 0x480760ff,
127 .flags = ADDR_TYPE_RT
132 static struct omap_hwmod_addr_space omap2_rng_addr_space[] = {
134 .pa_start = 0x480a0000,
135 .pa_end = 0x480a004f,
136 .flags = ADDR_TYPE_RT
142 * Common interconnect data
145 /* L3 -> L4_CORE interface */
146 struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
147 .master = &omap2xxx_l3_main_hwmod,
148 .slave = &omap2xxx_l4_core_hwmod,
149 .user = OCP_USER_MPU | OCP_USER_SDMA,
152 /* MPU -> L3 interface */
153 struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
154 .master = &omap2xxx_mpu_hwmod,
155 .slave = &omap2xxx_l3_main_hwmod,
156 .user = OCP_USER_MPU,
159 /* DSS -> l3 */
160 struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
161 .master = &omap2xxx_dss_core_hwmod,
162 .slave = &omap2xxx_l3_main_hwmod,
163 .fw = {
164 .omap2 = {
165 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
166 .flags = OMAP_FIREWALL_L3,
169 .user = OCP_USER_MPU | OCP_USER_SDMA,
172 /* L4_CORE -> L4_WKUP interface */
173 struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
174 .master = &omap2xxx_l4_core_hwmod,
175 .slave = &omap2xxx_l4_wkup_hwmod,
176 .user = OCP_USER_MPU | OCP_USER_SDMA,
179 /* L4 CORE -> UART1 interface */
180 struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
181 .master = &omap2xxx_l4_core_hwmod,
182 .slave = &omap2xxx_uart1_hwmod,
183 .clk = "uart1_ick",
184 .addr = omap2xxx_uart1_addr_space,
185 .user = OCP_USER_MPU | OCP_USER_SDMA,
188 /* L4 CORE -> UART2 interface */
189 struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
190 .master = &omap2xxx_l4_core_hwmod,
191 .slave = &omap2xxx_uart2_hwmod,
192 .clk = "uart2_ick",
193 .addr = omap2xxx_uart2_addr_space,
194 .user = OCP_USER_MPU | OCP_USER_SDMA,
197 /* L4 PER -> UART3 interface */
198 struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
199 .master = &omap2xxx_l4_core_hwmod,
200 .slave = &omap2xxx_uart3_hwmod,
201 .clk = "uart3_ick",
202 .addr = omap2xxx_uart3_addr_space,
203 .user = OCP_USER_MPU | OCP_USER_SDMA,
206 /* l4 core -> mcspi1 interface */
207 struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
208 .master = &omap2xxx_l4_core_hwmod,
209 .slave = &omap2xxx_mcspi1_hwmod,
210 .clk = "mcspi1_ick",
211 .addr = omap2_mcspi1_addr_space,
212 .user = OCP_USER_MPU | OCP_USER_SDMA,
215 /* l4 core -> mcspi2 interface */
216 struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
217 .master = &omap2xxx_l4_core_hwmod,
218 .slave = &omap2xxx_mcspi2_hwmod,
219 .clk = "mcspi2_ick",
220 .addr = omap2_mcspi2_addr_space,
221 .user = OCP_USER_MPU | OCP_USER_SDMA,
224 /* l4_core -> timer2 */
225 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
226 .master = &omap2xxx_l4_core_hwmod,
227 .slave = &omap2xxx_timer2_hwmod,
228 .clk = "gpt2_ick",
229 .addr = omap2xxx_timer2_addrs,
230 .user = OCP_USER_MPU | OCP_USER_SDMA,
233 /* l4_core -> timer3 */
234 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
235 .master = &omap2xxx_l4_core_hwmod,
236 .slave = &omap2xxx_timer3_hwmod,
237 .clk = "gpt3_ick",
238 .addr = omap2xxx_timer3_addrs,
239 .user = OCP_USER_MPU | OCP_USER_SDMA,
242 /* l4_core -> timer4 */
243 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
244 .master = &omap2xxx_l4_core_hwmod,
245 .slave = &omap2xxx_timer4_hwmod,
246 .clk = "gpt4_ick",
247 .addr = omap2xxx_timer4_addrs,
248 .user = OCP_USER_MPU | OCP_USER_SDMA,
251 /* l4_core -> timer5 */
252 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
253 .master = &omap2xxx_l4_core_hwmod,
254 .slave = &omap2xxx_timer5_hwmod,
255 .clk = "gpt5_ick",
256 .addr = omap2xxx_timer5_addrs,
257 .user = OCP_USER_MPU | OCP_USER_SDMA,
260 /* l4_core -> timer6 */
261 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
262 .master = &omap2xxx_l4_core_hwmod,
263 .slave = &omap2xxx_timer6_hwmod,
264 .clk = "gpt6_ick",
265 .addr = omap2xxx_timer6_addrs,
266 .user = OCP_USER_MPU | OCP_USER_SDMA,
269 /* l4_core -> timer7 */
270 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
271 .master = &omap2xxx_l4_core_hwmod,
272 .slave = &omap2xxx_timer7_hwmod,
273 .clk = "gpt7_ick",
274 .addr = omap2xxx_timer7_addrs,
275 .user = OCP_USER_MPU | OCP_USER_SDMA,
278 /* l4_core -> timer8 */
279 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
280 .master = &omap2xxx_l4_core_hwmod,
281 .slave = &omap2xxx_timer8_hwmod,
282 .clk = "gpt8_ick",
283 .addr = omap2xxx_timer8_addrs,
284 .user = OCP_USER_MPU | OCP_USER_SDMA,
287 /* l4_core -> timer9 */
288 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
289 .master = &omap2xxx_l4_core_hwmod,
290 .slave = &omap2xxx_timer9_hwmod,
291 .clk = "gpt9_ick",
292 .addr = omap2xxx_timer9_addrs,
293 .user = OCP_USER_MPU | OCP_USER_SDMA,
296 /* l4_core -> timer10 */
297 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
298 .master = &omap2xxx_l4_core_hwmod,
299 .slave = &omap2xxx_timer10_hwmod,
300 .clk = "gpt10_ick",
301 .addr = omap2_timer10_addrs,
302 .user = OCP_USER_MPU | OCP_USER_SDMA,
305 /* l4_core -> timer11 */
306 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
307 .master = &omap2xxx_l4_core_hwmod,
308 .slave = &omap2xxx_timer11_hwmod,
309 .clk = "gpt11_ick",
310 .addr = omap2_timer11_addrs,
311 .user = OCP_USER_MPU | OCP_USER_SDMA,
314 /* l4_core -> timer12 */
315 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
316 .master = &omap2xxx_l4_core_hwmod,
317 .slave = &omap2xxx_timer12_hwmod,
318 .clk = "gpt12_ick",
319 .addr = omap2xxx_timer12_addrs,
320 .user = OCP_USER_MPU | OCP_USER_SDMA,
323 /* l4_core -> dss */
324 struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
325 .master = &omap2xxx_l4_core_hwmod,
326 .slave = &omap2xxx_dss_core_hwmod,
327 .clk = "dss_ick",
328 .addr = omap2_dss_addrs,
329 .fw = {
330 .omap2 = {
331 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
332 .flags = OMAP_FIREWALL_L4,
335 .user = OCP_USER_MPU | OCP_USER_SDMA,
338 /* l4_core -> dss_dispc */
339 struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
340 .master = &omap2xxx_l4_core_hwmod,
341 .slave = &omap2xxx_dss_dispc_hwmod,
342 .clk = "dss_ick",
343 .addr = omap2_dss_dispc_addrs,
344 .fw = {
345 .omap2 = {
346 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
347 .flags = OMAP_FIREWALL_L4,
350 .user = OCP_USER_MPU | OCP_USER_SDMA,
353 /* l4_core -> dss_rfbi */
354 struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
355 .master = &omap2xxx_l4_core_hwmod,
356 .slave = &omap2xxx_dss_rfbi_hwmod,
357 .clk = "dss_ick",
358 .addr = omap2_dss_rfbi_addrs,
359 .fw = {
360 .omap2 = {
361 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
362 .flags = OMAP_FIREWALL_L4,
365 .user = OCP_USER_MPU | OCP_USER_SDMA,
368 /* l4_core -> dss_venc */
369 struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
370 .master = &omap2xxx_l4_core_hwmod,
371 .slave = &omap2xxx_dss_venc_hwmod,
372 .clk = "dss_ick",
373 .addr = omap2_dss_venc_addrs,
374 .fw = {
375 .omap2 = {
376 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
377 .flags = OMAP_FIREWALL_L4,
380 .flags = OCPIF_SWSUP_IDLE,
381 .user = OCP_USER_MPU | OCP_USER_SDMA,
384 /* l4_core -> rng */
385 struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
386 .master = &omap2xxx_l4_core_hwmod,
387 .slave = &omap2xxx_rng_hwmod,
388 .clk = "rng_ick",
389 .addr = omap2_rng_addr_space,
390 .user = OCP_USER_MPU | OCP_USER_SDMA,