| blob | b0a2142eeb9145680576722012d877aac0e4f1a2 |
1 /*
2 * OMAP3430 Power/Reset Management register bits
3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
14 #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
19 /* Shared register bits */
21 /* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
22 #define OMAP3430_ON_SHIFT 24
23 #define OMAP3430_ON_MASK (0xff << 24)
24 #define OMAP3430_ONLP_SHIFT 16
25 #define OMAP3430_ONLP_MASK (0xff << 16)
26 #define OMAP3430_RET_SHIFT 8
27 #define OMAP3430_RET_MASK (0xff << 8)
28 #define OMAP3430_OFF_SHIFT 0
29 #define OMAP3430_OFF_MASK (0xff << 0)
31 /* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
32 #define OMAP3430_ERROROFFSET_SHIFT 24
33 #define OMAP3430_ERROROFFSET_MASK (0xff << 24)
34 #define OMAP3430_ERRORGAIN_SHIFT 16
35 #define OMAP3430_ERRORGAIN_MASK (0xff << 16)
36 #define OMAP3430_INITVOLTAGE_SHIFT 8
37 #define OMAP3430_INITVOLTAGE_MASK (0xff << 8)
38 #define OMAP3430_TIMEOUTEN_MASK (1 << 3)
39 #define OMAP3430_INITVDD_MASK (1 << 2)
40 #define OMAP3430_FORCEUPDATE_MASK (1 << 1)
41 #define OMAP3430_VPENABLE_MASK (1 << 0)
43 /* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
44 #define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8
45 #define OMAP3430_SMPSWAITTIMEMIN_MASK (0xffff << 8)
46 #define OMAP3430_VSTEPMIN_SHIFT 0
47 #define OMAP3430_VSTEPMIN_MASK (0xff << 0)
49 /* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
50 #define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8
51 #define OMAP3430_SMPSWAITTIMEMAX_MASK (0xffff << 8)
52 #define OMAP3430_VSTEPMAX_SHIFT 0
53 #define OMAP3430_VSTEPMAX_MASK (0xff << 0)
55 /* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
56 #define OMAP3430_VDDMAX_SHIFT 24
57 #define OMAP3430_VDDMAX_MASK (0xff << 24)
58 #define OMAP3430_VDDMIN_SHIFT 16
59 #define OMAP3430_VDDMIN_MASK (0xff << 16)
60 #define OMAP3430_TIMEOUT_SHIFT 0
61 #define OMAP3430_TIMEOUT_MASK (0xffff << 0)
63 /* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
64 #define OMAP3430_VPVOLTAGE_SHIFT 0
65 #define OMAP3430_VPVOLTAGE_MASK (0xff << 0)
67 /* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
68 #define OMAP3430_VPINIDLE_MASK (1 << 0)
70 /* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
71 #define OMAP3430_EN_PER_SHIFT 7
72 #define OMAP3430_EN_PER_MASK (1 << 7)
74 /* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
75 #define OMAP3430_MEMORYCHANGE_MASK (1 << 3)
77 /* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
78 #define OMAP3430_LOGICSTATEST_MASK (1 << 2)
80 /* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
81 #define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2)
83 /*
84 * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
85 * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
86 * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
87 */
88 #define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0
89 #define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0)
91 /* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
92 #define OMAP3430_WKUP_ST_MASK (1 << 0)
94 /* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
95 #define OMAP3430_WKUP_EN_MASK (1 << 0)
97 /* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
98 #define OMAP3430_GRPSEL_MMC2_MASK (1 << 25)
99 #define OMAP3430_GRPSEL_MMC1_MASK (1 << 24)
100 #define OMAP3430_GRPSEL_MCSPI4_MASK (1 << 21)
101 #define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20)
102 #define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19)
103 #define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18)
104 #define OMAP3430_GRPSEL_I2C3_SHIFT 17
105 #define OMAP3430_GRPSEL_I2C3_MASK (1 << 17)
106 #define OMAP3430_GRPSEL_I2C2_SHIFT 16
107 #define OMAP3430_GRPSEL_I2C2_MASK (1 << 16)
108 #define OMAP3430_GRPSEL_I2C1_SHIFT 15
109 #define OMAP3430_GRPSEL_I2C1_MASK (1 << 15)
110 #define OMAP3430_GRPSEL_UART2_MASK (1 << 14)
111 #define OMAP3430_GRPSEL_UART1_MASK (1 << 13)
112 #define OMAP3430_GRPSEL_GPT11_MASK (1 << 12)
113 #define OMAP3430_GRPSEL_GPT10_MASK (1 << 11)
114 #define OMAP3430_GRPSEL_MCBSP5_MASK (1 << 10)
115 #define OMAP3430_GRPSEL_MCBSP1_MASK (1 << 9)
116 #define OMAP3430_GRPSEL_HSOTGUSB_MASK (1 << 4)
117 #define OMAP3430_GRPSEL_D2D_MASK (1 << 3)
119 /*
120 * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
121 * PM_PWSTCTRL_PER shared bits
122 */
123 #define OMAP3430_MEMONSTATE_SHIFT 16
124 #define OMAP3430_MEMONSTATE_MASK (0x3 << 16)
125 #define OMAP3430_MEMRETSTATE_MASK (1 << 8)
127 /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
128 #define OMAP3630_GRPSEL_UART4_MASK (1 << 18)
129 #define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17)
130 #define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16)
131 #define OMAP3430_GRPSEL_GPIO4_MASK (1 << 15)
132 #define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14)
133 #define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13)
134 #define OMAP3430_GRPSEL_UART3_MASK (1 << 11)
135 #define OMAP3430_GRPSEL_GPT9_MASK (1 << 10)
136 #define OMAP3430_GRPSEL_GPT8_MASK (1 << 9)
137 #define OMAP3430_GRPSEL_GPT7_MASK (1 << 8)
138 #define OMAP3430_GRPSEL_GPT6_MASK (1 << 7)
139 #define OMAP3430_GRPSEL_GPT5_MASK (1 << 6)
140 #define OMAP3430_GRPSEL_GPT4_MASK (1 << 5)
141 #define OMAP3430_GRPSEL_GPT3_MASK (1 << 4)
142 #define OMAP3430_GRPSEL_GPT2_MASK (1 << 3)
143 #define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2)
144 #define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1)
145 #define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0)
147 /* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
148 #define OMAP3430_GRPSEL_IO_MASK (1 << 8)
149 #define OMAP3430_GRPSEL_SR2_MASK (1 << 7)
150 #define OMAP3430_GRPSEL_SR1_MASK (1 << 6)
151 #define OMAP3430_GRPSEL_GPIO1_MASK (1 << 3)
152 #define OMAP3430_GRPSEL_GPT12_MASK (1 << 1)
153 #define OMAP3430_GRPSEL_GPT1_MASK (1 << 0)
155 /* Bits specific to each register */
157 /* RM_RSTCTRL_IVA2 */
158 #define OMAP3430_RST3_IVA2_MASK (1 << 2)
159 #define OMAP3430_RST2_IVA2_MASK (1 << 1)
160 #define OMAP3430_RST1_IVA2_MASK (1 << 0)
162 /* RM_RSTST_IVA2 specific bits */
163 #define OMAP3430_EMULATION_VSEQ_RST_MASK (1 << 13)
164 #define OMAP3430_EMULATION_VHWA_RST_MASK (1 << 12)
165 #define OMAP3430_EMULATION_IVA2_RST_MASK (1 << 11)
166 #define OMAP3430_IVA2_SW_RST3_MASK (1 << 10)
167 #define OMAP3430_IVA2_SW_RST2_MASK (1 << 9)
168 #define OMAP3430_IVA2_SW_RST1_MASK (1 << 8)
170 /* PM_WKDEP_IVA2 specific bits */
172 /* PM_PWSTCTRL_IVA2 specific bits */
173 #define OMAP3430_L2FLATMEMONSTATE_SHIFT 22
174 #define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22)
175 #define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT 20
176 #define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20)
177 #define OMAP3430_L1FLATMEMONSTATE_SHIFT 18
178 #define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18)
179 #define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16
180 #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16)
181 #define OMAP3430_L2FLATMEMRETSTATE_MASK (1 << 11)
182 #define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK (1 << 10)
183 #define OMAP3430_L1FLATMEMRETSTATE_MASK (1 << 9)
184 #define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK (1 << 8)
186 /* PM_PWSTST_IVA2 specific bits */
187 #define OMAP3430_L2FLATMEMSTATEST_SHIFT 10
188 #define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10)
189 #define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT 8
190 #define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8)
191 #define OMAP3430_L1FLATMEMSTATEST_SHIFT 6
192 #define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6)
193 #define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT 4
194 #define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4)
196 /* PM_PREPWSTST_IVA2 specific bits */
197 #define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT 10
198 #define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10)
199 #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT 8
200 #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8)
201 #define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT 6
202 #define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK (0x3 << 6)
203 #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT 4
204 #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4)
206 /* PRM_IRQSTATUS_IVA2 specific bits */
207 #define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST_MASK (1 << 2)
208 #define OMAP3430_FORCEWKUP_ST_MASK (1 << 1)
210 /* PRM_IRQENABLE_IVA2 specific bits */
211 #define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN_MASK (1 << 2)
212 #define OMAP3430_FORCEWKUP_EN_MASK (1 << 1)
214 /* PRM_REVISION specific bits */
216 /* PRM_SYSCONFIG specific bits */
218 /* PRM_IRQSTATUS_MPU specific bits */
219 #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25
220 #define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK (1 << 25)
221 #define OMAP3430_VC_TIMEOUTERR_ST_MASK (1 << 24)
222 #define OMAP3430_VC_RAERR_ST_MASK (1 << 23)
223 #define OMAP3430_VC_SAERR_ST_MASK (1 << 22)
224 #define OMAP3430_VP2_TRANXDONE_ST_MASK (1 << 21)
225 #define OMAP3430_VP2_EQVALUE_ST_MASK (1 << 20)
226 #define OMAP3430_VP2_NOSMPSACK_ST_MASK (1 << 19)
227 #define OMAP3430_VP2_MAXVDD_ST_MASK (1 << 18)
228 #define OMAP3430_VP2_MINVDD_ST_MASK (1 << 17)
229 #define OMAP3430_VP2_OPPCHANGEDONE_ST_MASK (1 << 16)
230 #define OMAP3430_VP1_TRANXDONE_ST_MASK (1 << 15)
231 #define OMAP3430_VP1_EQVALUE_ST_MASK (1 << 14)
232 #define OMAP3430_VP1_NOSMPSACK_ST_MASK (1 << 13)
233 #define OMAP3430_VP1_MAXVDD_ST_MASK (1 << 12)
234 #define OMAP3430_VP1_MINVDD_ST_MASK (1 << 11)
235 #define OMAP3430_VP1_OPPCHANGEDONE_ST_MASK (1 << 10)
236 #define OMAP3430_IO_ST_MASK (1 << 9)
237 #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_MASK (1 << 8)
238 #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8
239 #define OMAP3430_MPU_DPLL_ST_MASK (1 << 7)
240 #define OMAP3430_MPU_DPLL_ST_SHIFT 7
241 #define OMAP3430_PERIPH_DPLL_ST_MASK (1 << 6)
242 #define OMAP3430_PERIPH_DPLL_ST_SHIFT 6
243 #define OMAP3430_CORE_DPLL_ST_MASK (1 << 5)
244 #define OMAP3430_CORE_DPLL_ST_SHIFT 5
245 #define OMAP3430_TRANSITION_ST_MASK (1 << 4)
246 #define OMAP3430_EVGENOFF_ST_MASK (1 << 3)
247 #define OMAP3430_EVGENON_ST_MASK (1 << 2)
248 #define OMAP3430_FS_USB_WKUP_ST_MASK (1 << 1)
250 /* PRM_IRQENABLE_MPU specific bits */
251 #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25
252 #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK (1 << 25)
253 #define OMAP3430_VC_TIMEOUTERR_EN_MASK (1 << 24)
254 #define OMAP3430_VC_RAERR_EN_MASK (1 << 23)
255 #define OMAP3430_VC_SAERR_EN_MASK (1 << 22)
256 #define OMAP3430_VP2_TRANXDONE_EN_MASK (1 << 21)
257 #define OMAP3430_VP2_EQVALUE_EN_MASK (1 << 20)
258 #define OMAP3430_VP2_NOSMPSACK_EN_MASK (1 << 19)
259 #define OMAP3430_VP2_MAXVDD_EN_MASK (1 << 18)
260 #define OMAP3430_VP2_MINVDD_EN_MASK (1 << 17)
261 #define OMAP3430_VP2_OPPCHANGEDONE_EN_MASK (1 << 16)
262 #define OMAP3430_VP1_TRANXDONE_EN_MASK (1 << 15)
263 #define OMAP3430_VP1_EQVALUE_EN_MASK (1 << 14)
264 #define OMAP3430_VP1_NOSMPSACK_EN_MASK (1 << 13)
265 #define OMAP3430_VP1_MAXVDD_EN_MASK (1 << 12)
266 #define OMAP3430_VP1_MINVDD_EN_MASK (1 << 11)
267 #define OMAP3430_VP1_OPPCHANGEDONE_EN_MASK (1 << 10)
268 #define OMAP3430_IO_EN_MASK (1 << 9)
269 #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_MASK (1 << 8)
270 #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8
271 #define OMAP3430_MPU_DPLL_RECAL_EN_MASK (1 << 7)
272 #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7
273 #define OMAP3430_PERIPH_DPLL_RECAL_EN_MASK (1 << 6)
274 #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6
275 #define OMAP3430_CORE_DPLL_RECAL_EN_MASK (1 << 5)
276 #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5
277 #define OMAP3430_TRANSITION_EN_MASK (1 << 4)
278 #define OMAP3430_EVGENOFF_EN_MASK (1 << 3)
279 #define OMAP3430_EVGENON_EN_MASK (1 << 2)
280 #define OMAP3430_FS_USB_WKUP_EN_MASK (1 << 1)
282 /* RM_RSTST_MPU specific bits */
283 #define OMAP3430_EMULATION_MPU_RST_MASK (1 << 11)
285 /* PM_WKDEP_MPU specific bits */
286 #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5
287 #define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK (1 << 5)
288 #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2
289 #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK (1 << 2)
291 /* PM_EVGENCTRL_MPU */
292 #define OMAP3430_OFFLOADMODE_SHIFT 3
293 #define OMAP3430_OFFLOADMODE_MASK (0x3 << 3)
294 #define OMAP3430_ONLOADMODE_SHIFT 1
295 #define OMAP3430_ONLOADMODE_MASK (0x3 << 1)
296 #define OMAP3430_ENABLE_MASK (1 << 0)
298 /* PM_EVGENONTIM_MPU */
299 #define OMAP3430_ONTIMEVAL_SHIFT 0
300 #define OMAP3430_ONTIMEVAL_MASK (0xffffffff << 0)
302 /* PM_EVGENOFFTIM_MPU */
303 #define OMAP3430_OFFTIMEVAL_SHIFT 0
304 #define OMAP3430_OFFTIMEVAL_MASK (0xffffffff << 0)
306 /* PM_PWSTCTRL_MPU specific bits */
307 #define OMAP3430_L2CACHEONSTATE_SHIFT 16
308 #define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16)
309 #define OMAP3430_L2CACHERETSTATE_MASK (1 << 8)
310 #define OMAP3430_LOGICL1CACHERETSTATE_MASK (1 << 2)
312 /* PM_PWSTST_MPU specific bits */
313 #define OMAP3430_L2CACHESTATEST_SHIFT 6
314 #define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6)
315 #define OMAP3430_LOGICL1CACHESTATEST_MASK (1 << 2)
317 /* PM_PREPWSTST_MPU specific bits */
318 #define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6
319 #define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6)
320 #define OMAP3430_LASTLOGICL1CACHESTATEENTERED_MASK (1 << 2)
322 /* RM_RSTCTRL_CORE */
323 #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK (1 << 1)
324 #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK (1 << 0)
326 /* RM_RSTST_CORE specific bits */
327 #define OMAP3430_MODEM_SECURITY_VIOL_RST_MASK (1 << 10)
328 #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON_MASK (1 << 9)
329 #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST_MASK (1 << 8)
331 /* PM_WKEN1_CORE specific bits */
333 /* PM_MPUGRPSEL1_CORE specific bits */
334 #define OMAP3430_GRPSEL_FSHOSTUSB_MASK (1 << 5)
336 /* PM_IVA2GRPSEL1_CORE specific bits */
338 /* PM_WKST1_CORE specific bits */
340 /* PM_PWSTCTRL_CORE specific bits */
341 #define OMAP3430_MEM2ONSTATE_SHIFT 18
342 #define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18)
343 #define OMAP3430_MEM1ONSTATE_SHIFT 16
344 #define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16)
345 #define OMAP3430_MEM2RETSTATE_MASK (1 << 9)
346 #define OMAP3430_MEM1RETSTATE_MASK (1 << 8)
348 /* PM_PWSTST_CORE specific bits */
349 #define OMAP3430_MEM2STATEST_SHIFT 6
350 #define OMAP3430_MEM2STATEST_MASK (0x3 << 6)
351 #define OMAP3430_MEM1STATEST_SHIFT 4
352 #define OMAP3430_MEM1STATEST_MASK (0x3 << 4)
354 /* PM_PREPWSTST_CORE specific bits */
355 #define OMAP3430_LASTMEM2STATEENTERED_SHIFT 6
356 #define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6)
357 #define OMAP3430_LASTMEM1STATEENTERED_SHIFT 4
358 #define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4)
360 /* RM_RSTST_GFX specific bits */
362 /* PM_WKDEP_GFX specific bits */
363 #define OMAP3430_PM_WKDEP_GFX_EN_IVA2_MASK (1 << 2)
365 /* PM_PWSTCTRL_GFX specific bits */
367 /* PM_PWSTST_GFX specific bits */
369 /* PM_PREPWSTST_GFX specific bits */
371 /* PM_WKEN_WKUP specific bits */
372 #define OMAP3430_EN_IO_CHAIN_MASK (1 << 16)
373 #define OMAP3430_EN_IO_MASK (1 << 8)
374 #define OMAP3430_EN_GPIO1_MASK (1 << 3)
376 /* PM_MPUGRPSEL_WKUP specific bits */
378 /* PM_IVA2GRPSEL_WKUP specific bits */
380 /* PM_WKST_WKUP specific bits */
381 #define OMAP3430_ST_IO_CHAIN_MASK (1 << 16)
382 #define OMAP3430_ST_IO_MASK (1 << 8)
384 /* PRM_CLKSEL */
385 #define OMAP3430_SYS_CLKIN_SEL_SHIFT 0
386 #define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0)
387 #define OMAP3430_SYS_CLKIN_SEL_WIDTH 3
389 /* PRM_CLKOUT_CTRL */
390 #define OMAP3430_CLKOUT_EN_MASK (1 << 7)
391 #define OMAP3430_CLKOUT_EN_SHIFT 7
393 /* RM_RSTST_DSS specific bits */
395 /* PM_WKEN_DSS */
396 #define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK (1 << 0)
398 /* PM_WKDEP_DSS specific bits */
399 #define OMAP3430_PM_WKDEP_DSS_EN_IVA2_MASK (1 << 2)
401 /* PM_PWSTCTRL_DSS specific bits */
403 /* PM_PWSTST_DSS specific bits */
405 /* PM_PREPWSTST_DSS specific bits */
407 /* RM_RSTST_CAM specific bits */
409 /* PM_WKDEP_CAM specific bits */
410 #define OMAP3430_PM_WKDEP_CAM_EN_IVA2_MASK (1 << 2)
412 /* PM_PWSTCTRL_CAM specific bits */
414 /* PM_PWSTST_CAM specific bits */
416 /* PM_PREPWSTST_CAM specific bits */
418 /* PM_PWSTCTRL_USBHOST specific bits */
419 #define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4
421 /* RM_RSTST_PER specific bits */
423 /* PM_WKEN_PER specific bits */
425 /* PM_MPUGRPSEL_PER specific bits */
427 /* PM_IVA2GRPSEL_PER specific bits */
429 /* PM_WKST_PER specific bits */
431 /* PM_WKDEP_PER specific bits */
432 #define OMAP3430_PM_WKDEP_PER_EN_IVA2_MASK (1 << 2)
434 /* PM_PWSTCTRL_PER specific bits */
436 /* PM_PWSTST_PER specific bits */
438 /* PM_PREPWSTST_PER specific bits */
440 /* RM_RSTST_EMU specific bits */
442 /* PM_PWSTST_EMU specific bits */
444 /* PRM_VC_SMPS_SA */
445 #define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16
446 #define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16)
447 #define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0
448 #define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0)
450 /* PRM_VC_SMPS_VOL_RA */
451 #define OMAP3430_VOLRA1_SHIFT 16
452 #define OMAP3430_VOLRA1_MASK (0xff << 16)
453 #define OMAP3430_VOLRA0_SHIFT 0
454 #define OMAP3430_VOLRA0_MASK (0xff << 0)
456 /* PRM_VC_SMPS_CMD_RA */
457 #define OMAP3430_CMDRA1_SHIFT 16
458 #define OMAP3430_CMDRA1_MASK (0xff << 16)
459 #define OMAP3430_CMDRA0_SHIFT 0
460 #define OMAP3430_CMDRA0_MASK (0xff << 0)
462 /* PRM_VC_CMD_VAL_0 specific bits */
463 #define OMAP3430_VC_CMD_ON_SHIFT 24
464 #define OMAP3430_VC_CMD_ON_MASK (0xFF << 24)
465 #define OMAP3430_VC_CMD_ONLP_SHIFT 16
466 #define OMAP3430_VC_CMD_ONLP_MASK (0xFF << 16)
467 #define OMAP3430_VC_CMD_RET_SHIFT 8
468 #define OMAP3430_VC_CMD_RET_MASK (0xFF << 8)
469 #define OMAP3430_VC_CMD_OFF_SHIFT 0
470 #define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0)
472 /* PRM_VC_CMD_VAL_1 specific bits */
474 /* PRM_VC_CH_CONF */
475 #define OMAP3430_CMD1_MASK (1 << 20)
476 #define OMAP3430_RACEN1_MASK (1 << 19)
477 #define OMAP3430_RAC1_MASK (1 << 18)
478 #define OMAP3430_RAV1_MASK (1 << 17)
479 #define OMAP3430_PRM_VC_CH_CONF_SA1_MASK (1 << 16)
480 #define OMAP3430_CMD0_MASK (1 << 4)
481 #define OMAP3430_RACEN0_MASK (1 << 3)
482 #define OMAP3430_RAC0_MASK (1 << 2)
483 #define OMAP3430_RAV0_MASK (1 << 1)
484 #define OMAP3430_PRM_VC_CH_CONF_SA0_MASK (1 << 0)
486 /* PRM_VC_I2C_CFG */
487 #define OMAP3430_HSMASTER_MASK (1 << 5)
488 #define OMAP3430_SREN_MASK (1 << 4)
489 #define OMAP3430_HSEN_MASK (1 << 3)
490 #define OMAP3430_MCODE_SHIFT 0
491 #define OMAP3430_MCODE_MASK (0x7 << 0)
493 /* PRM_VC_BYPASS_VAL */
494 #define OMAP3430_VALID_MASK (1 << 24)
495 #define OMAP3430_DATA_SHIFT 16
496 #define OMAP3430_DATA_MASK (0xff << 16)
497 #define OMAP3430_REGADDR_SHIFT 8
498 #define OMAP3430_REGADDR_MASK (0xff << 8)
499 #define OMAP3430_SLAVEADDR_SHIFT 0
500 #define OMAP3430_SLAVEADDR_MASK (0x7f << 0)
502 /* PRM_RSTCTRL */
503 #define OMAP3430_RST_DPLL3_MASK (1 << 2)
504 #define OMAP3430_RST_GS_MASK (1 << 1)
506 /* PRM_RSTTIME */
507 #define OMAP3430_RSTTIME2_SHIFT 8
508 #define OMAP3430_RSTTIME2_MASK (0x1f << 8)
509 #define OMAP3430_RSTTIME1_SHIFT 0
510 #define OMAP3430_RSTTIME1_MASK (0xff << 0)
512 /* PRM_RSTST */
513 #define OMAP3430_ICECRUSHER_RST_SHIFT 10
514 #define OMAP3430_ICECRUSHER_RST_MASK (1 << 10)
515 #define OMAP3430_ICEPICK_RST_SHIFT 9
516 #define OMAP3430_ICEPICK_RST_MASK (1 << 9)
517 #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT 8
518 #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK (1 << 8)
519 #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT 7
520 #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK (1 << 7)
521 #define OMAP3430_EXTERNAL_WARM_RST_SHIFT 6
522 #define OMAP3430_EXTERNAL_WARM_RST_MASK (1 << 6)
523 #define OMAP3430_SECURE_WD_RST_SHIFT 5
524 #define OMAP3430_SECURE_WD_RST_MASK (1 << 5)
525 #define OMAP3430_MPU_WD_RST_SHIFT 4
526 #define OMAP3430_MPU_WD_RST_MASK (1 << 4)
527 #define OMAP3430_SECURITY_VIOL_RST_SHIFT 3
528 #define OMAP3430_SECURITY_VIOL_RST_MASK (1 << 3)
529 #define OMAP3430_GLOBAL_SW_RST_SHIFT 1
530 #define OMAP3430_GLOBAL_SW_RST_MASK (1 << 1)
531 #define OMAP3430_GLOBAL_COLD_RST_SHIFT 0
532 #define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0)
534 /* PRM_VOLTCTRL */
535 #define OMAP3430_SEL_VMODE_MASK (1 << 4)
536 #define OMAP3430_SEL_OFF_MASK (1 << 3)
537 #define OMAP3430_AUTO_OFF_MASK (1 << 2)
538 #define OMAP3430_AUTO_RET_MASK (1 << 1)
539 #define OMAP3430_AUTO_SLEEP_MASK (1 << 0)
541 /* PRM_SRAM_PCHARGE */
542 #define OMAP3430_PCHARGE_TIME_SHIFT 0
543 #define OMAP3430_PCHARGE_TIME_MASK (0xff << 0)
545 /* PRM_CLKSRC_CTRL */
546 #define OMAP3430_SYSCLKDIV_SHIFT 6
547 #define OMAP3430_SYSCLKDIV_MASK (0x3 << 6)
548 #define OMAP3430_AUTOEXTCLKMODE_SHIFT 3
549 #define OMAP3430_AUTOEXTCLKMODE_MASK (0x3 << 3)
550 #define OMAP3430_SYSCLKSEL_SHIFT 0
551 #define OMAP3430_SYSCLKSEL_MASK (0x3 << 0)
553 /* PRM_VOLTSETUP1 */
554 #define OMAP3430_SETUP_TIME2_SHIFT 16
555 #define OMAP3430_SETUP_TIME2_MASK (0xffff << 16)
556 #define OMAP3430_SETUP_TIME1_SHIFT 0
557 #define OMAP3430_SETUP_TIME1_MASK (0xffff << 0)
559 /* PRM_VOLTOFFSET */
560 #define OMAP3430_OFFSET_TIME_SHIFT 0
561 #define OMAP3430_OFFSET_TIME_MASK (0xffff << 0)
563 /* PRM_CLKSETUP */
564 #define OMAP3430_SETUP_TIME_SHIFT 0
565 #define OMAP3430_SETUP_TIME_MASK (0xffff << 0)
567 /* PRM_POLCTRL */
568 #define OMAP3430_OFFMODE_POL_MASK (1 << 3)
569 #define OMAP3430_CLKOUT_POL_MASK (1 << 2)
570 #define OMAP3430_CLKREQ_POL_MASK (1 << 1)
571 #define OMAP3430_EXTVOL_POL_MASK (1 << 0)
573 /* PRM_VOLTSETUP2 */
574 #define OMAP3430_OFFMODESETUPTIME_SHIFT 0
575 #define OMAP3430_OFFMODESETUPTIME_MASK (0xffff << 0)
577 /* PRM_VP1_CONFIG specific bits */
579 /* PRM_VP1_VSTEPMIN specific bits */
581 /* PRM_VP1_VSTEPMAX specific bits */
583 /* PRM_VP1_VLIMITTO specific bits */
585 /* PRM_VP1_VOLTAGE specific bits */
587 /* PRM_VP1_STATUS specific bits */
589 /* PRM_VP2_CONFIG specific bits */
591 /* PRM_VP2_VSTEPMIN specific bits */
593 /* PRM_VP2_VSTEPMAX specific bits */
595 /* PRM_VP2_VLIMITTO specific bits */
597 /* PRM_VP2_VOLTAGE specific bits */
599 /* PRM_VP2_STATUS specific bits */
601 /* RM_RSTST_NEON specific bits */
603 /* PM_WKDEP_NEON specific bits */
605 /* PM_PWSTCTRL_NEON specific bits */
607 /* PM_PWSTST_NEON specific bits */
609 /* PM_PREPWSTST_NEON specific bits */
611 #endif