arch/arm/mach-omap2/prm2xxx_3xxx.c

   1 /*
   2  * OMAP2/3 PRM module functions
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2010 Nokia Corporation
   6  * Benoît Cousson
   7  * Paul Walmsley
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/errno.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18
  19 #include "common.h"
  20 #include "powerdomain.h"
  21 #include "prm2xxx_3xxx.h"
  22 #include "prm-regbits-24xx.h"
  23 #include "clockdomain.h"
  24
  25 /**
  26  * omap2_prm_is_hardreset_asserted - read the HW reset line state of
  27  * submodules contained in the hwmod module
  28  * @prm_mod: PRM submodule base (e.g. CORE_MOD)
  29  * @shift: register bit shift corresponding to the reset line to check
  30  *
  31  * Returns 1 if the (sub)module hardreset line is currently asserted,
  32  * 0 if the (sub)module hardreset line is not currently asserted, or
  33  * -EINVAL if called while running on a non-OMAP2/3 chip.
  34  */
  35 int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
  36 {
  37         return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
  38                                        (1 << shift));
  39 }
  40
  41 /**
  42  * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
  43  * @prm_mod: PRM submodule base (e.g. CORE_MOD)
  44  * @shift: register bit shift corresponding to the reset line to assert
  45  *
  46  * Some IPs like dsp or iva contain processors that require an HW
  47  * reset line to be asserted / deasserted in order to fully enable the
  48  * IP.  These modules may have multiple hard-reset lines that reset
  49  * different 'submodules' inside the IP block.  This function will
  50  * place the submodule into reset.  Returns 0 upon success or -EINVAL
  51  * upon an argument error.
  52  */
  53 int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
  54 {
  55         u32 mask;
  56
  57         mask = 1 << shift;
  58         omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
  59
  60         return 0;
  61 }
  62
  63 /**
  64  * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait
  65  * @prm_mod: PRM submodule base (e.g. CORE_MOD)
  66  * @rst_shift: register bit shift corresponding to the reset line to deassert
  67  * @st_shift: register bit shift for the status of the deasserted submodule
  68  *
  69  * Some IPs like dsp or iva contain processors that require an HW
  70  * reset line to be asserted / deasserted in order to fully enable the
  71  * IP.  These modules may have multiple hard-reset lines that reset
  72  * different 'submodules' inside the IP block.  This function will
  73  * take the submodule out of reset and wait until the PRCM indicates
  74  * that the reset has completed before returning.  Returns 0 upon success or
  75  * -EINVAL upon an argument error, -EEXIST if the submodule was already out
  76  * of reset, or -EBUSY if the submodule did not exit reset promptly.
  77  */
  78 int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
  79 {
  80         u32 rst, st;
  81         int c;
  82
  83         rst = 1 << rst_shift;
  84         st = 1 << st_shift;
  85
  86         /* Check the current status to avoid de-asserting the line twice */
  87         if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, rst) == 0)
  88                 return -EEXIST;
  89
  90         /* Clear the reset status by writing 1 to the status bit */
  91         omap2_prm_rmw_mod_reg_bits(0xffffffff, st, prm_mod, OMAP2_RM_RSTST);
  92         /* de-assert the reset control line */
  93         omap2_prm_rmw_mod_reg_bits(rst, 0, prm_mod, OMAP2_RM_RSTCTRL);
  94         /* wait the status to be set */
  95         omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST,
  96                                                   st),
  97                           MAX_MODULE_HARDRESET_WAIT, c);
  98
  99         return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
 100 }
 101
 102
 103 /* Powerdomain low-level functions */
 104
 105 /* Common functions across OMAP2 and OMAP3 */
 106 int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
 107                                                                 u8 pwrst)
 108 {
 109         u32 m;
 110
 111         m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
 112
 113         omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
 114                                    OMAP2_PM_PWSTCTRL);
 115
 116         return 0;
 117 }
 118
 119 int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
 120                                                                 u8 pwrst)
 121 {
 122         u32 m;
 123
 124         m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
 125
 126         omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
 127                                    OMAP2_PM_PWSTCTRL);
 128
 129         return 0;
 130 }
 131
 132 int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 133 {
 134         u32 m;
 135
 136         m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
 137
 138         return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,
 139                                              m);
 140 }
 141
 142 int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
 143 {
 144         u32 m;
 145
 146         m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
 147
 148         return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
 149                                              OMAP2_PM_PWSTCTRL, m);
 150 }
 151
 152 int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
 153 {
 154         u32 v;
 155
 156         v = pwrst << __ffs(OMAP_LOGICRETSTATE_MASK);
 157         omap2_prm_rmw_mod_reg_bits(OMAP_LOGICRETSTATE_MASK, v, pwrdm->prcm_offs,
 158                                    OMAP2_PM_PWSTCTRL);
 159
 160         return 0;
 161 }
 162
 163 int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
 164 {
 165         u32 c = 0;
 166
 167         /*
 168          * REVISIT: pwrdm_wait_transition() may be better implemented
 169          * via a callback and a periodic timer check -- how long do we expect
 170          * powerdomain transitions to take?
 171          */
 172
 173         /* XXX Is this udelay() value meaningful? */
 174         while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) &
 175                 OMAP_INTRANSITION_MASK) &&
 176                 (c++ < PWRDM_TRANSITION_BAILOUT))
 177                         udelay(1);
 178
 179         if (c > PWRDM_TRANSITION_BAILOUT) {
 180                 pr_err("powerdomain: %s: waited too long to complete transition\n",
 181                        pwrdm->name);
 182                 return -EAGAIN;
 183         }
 184
 185         pr_debug("powerdomain: completed transition in %d loops\n", c);
 186
 187         return 0;
 188 }
 189
 190 int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
 191                           struct clockdomain *clkdm2)
 192 {
 193         omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
 194                                    clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
 195         return 0;
 196 }
 197
 198 int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
 199                           struct clockdomain *clkdm2)
 200 {
 201         omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
 202                                      clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
 203         return 0;
 204 }
 205
 206 int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
 207                            struct clockdomain *clkdm2)
 208 {
 209         return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
 210                                              PM_WKDEP, (1 << clkdm2->dep_bit));
 211 }
 212
 213 int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
 214 {
 215         struct clkdm_dep *cd;
 216         u32 mask = 0;
 217
 218         for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
 219                 if (!cd->clkdm)
 220                         continue; /* only happens if data is erroneous */
 221
 222                 /* PRM accesses are slow, so minimize them */
 223                 mask |= 1 << cd->clkdm->dep_bit;
 224                 atomic_set(&cd->wkdep_usecount, 0);
 225         }
 226
 227         omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
 228                                      PM_WKDEP);
 229         return 0;
 230 }
 231