arch/arm/mach-pxa/time.c

   1 /*
   2  * arch/arm/mach-pxa/time.c
   3  *
   4  * PXA clocksource, clockevents, and OST interrupt handlers.
   5  * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
   6  *
   7  * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
   8  * by MontaVista Software, Inc.  (Nico, your code rocks!)
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/clockchips.h>
  19
  20 #include <asm/div64.h>
  21 #include <asm/mach/irq.h>
  22 #include <asm/mach/time.h>
  23 #include <asm/sched_clock.h>
  24 #include <mach/regs-ost.h>
  25 #include <mach/irqs.h>
  26
  27 /*
  28  * This is PXA's sched_clock implementation. This has a resolution
  29  * of at least 308 ns and a maximum value of 208 days.
  30  *
  31  * The return value is guaranteed to be monotonic in that range as
  32  * long as there is always less than 582 seconds between successive
  33  * calls to sched_clock() which should always be the case in practice.
  34  */
  35
  36 static u32 notrace pxa_read_sched_clock(void)
  37 {
  38         return readl_relaxed(OSCR);
  39 }
  40
  41
  42 #define MIN_OSCR_DELTA 16
  43
  44 static irqreturn_t
  45 pxa_ost0_interrupt(int irq, void *dev_id)
  46 {
  47         struct clock_event_device *c = dev_id;
  48
  49         /* Disarm the compare/match, signal the event. */
  50         writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
  51         writel_relaxed(OSSR_M0, OSSR);
  52         c->event_handler(c);
  53
  54         return IRQ_HANDLED;
  55 }
  56
  57 static int
  58 pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
  59 {
  60         unsigned long next, oscr;
  61
  62         writel_relaxed(readl_relaxed(OIER) | OIER_E0, OIER);
  63         next = readl_relaxed(OSCR) + delta;
  64         writel_relaxed(next, OSMR0);
  65         oscr = readl_relaxed(OSCR);
  66
  67         return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
  68 }
  69
  70 static void
  71 pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
  72 {
  73         switch (mode) {
  74         case CLOCK_EVT_MODE_ONESHOT:
  75                 writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
  76                 writel_relaxed(OSSR_M0, OSSR);
  77                 break;
  78
  79         case CLOCK_EVT_MODE_UNUSED:
  80         case CLOCK_EVT_MODE_SHUTDOWN:
  81                 /* initializing, released, or preparing for suspend */
  82                 writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
  83                 writel_relaxed(OSSR_M0, OSSR);
  84                 break;
  85
  86         case CLOCK_EVT_MODE_RESUME:
  87         case CLOCK_EVT_MODE_PERIODIC:
  88                 break;
  89         }
  90 }
  91
  92 static struct clock_event_device ckevt_pxa_osmr0 = {
  93         .name           = "osmr0",
  94         .features       = CLOCK_EVT_FEAT_ONESHOT,
  95         .rating         = 200,
  96         .set_next_event = pxa_osmr0_set_next_event,
  97         .set_mode       = pxa_osmr0_set_mode,
  98 };
  99
 100 static struct irqaction pxa_ost0_irq = {
 101         .name           = "ost0",
 102         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 103         .handler        = pxa_ost0_interrupt,
 104         .dev_id         = &ckevt_pxa_osmr0,
 105 };
 106
 107 static void __init pxa_timer_init(void)
 108 {
 109         unsigned long clock_tick_rate = get_clock_tick_rate();
 110
 111         writel_relaxed(0, OIER);
 112         writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
 113
 114         setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate);
 115
 116         clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4);
 117         ckevt_pxa_osmr0.max_delta_ns =
 118                 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
 119         ckevt_pxa_osmr0.min_delta_ns =
 120                 clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
 121         ckevt_pxa_osmr0.cpumask = cpumask_of(0);
 122
 123         setup_irq(IRQ_OST0, &pxa_ost0_irq);
 124
 125         clocksource_mmio_init(OSCR, "oscr0", clock_tick_rate, 200, 32,
 126                 clocksource_mmio_readl_up);
 127         clockevents_register_device(&ckevt_pxa_osmr0);
 128 }
 129
 130 #ifdef CONFIG_PM
 131 static unsigned long osmr[4], oier, oscr;
 132
 133 static void pxa_timer_suspend(void)
 134 {
 135         osmr[0] = readl_relaxed(OSMR0);
 136         osmr[1] = readl_relaxed(OSMR1);
 137         osmr[2] = readl_relaxed(OSMR2);
 138         osmr[3] = readl_relaxed(OSMR3);
 139         oier = readl_relaxed(OIER);
 140         oscr = readl_relaxed(OSCR);
 141 }
 142
 143 static void pxa_timer_resume(void)
 144 {
 145         /*
 146          * Ensure that we have at least MIN_OSCR_DELTA between match
 147          * register 0 and the OSCR, to guarantee that we will receive
 148          * the one-shot timer interrupt.  We adjust OSMR0 in preference
 149          * to OSCR to guarantee that OSCR is monotonically incrementing.
 150          */
 151         if (osmr[0] - oscr < MIN_OSCR_DELTA)
 152                 osmr[0] += MIN_OSCR_DELTA;
 153
 154         writel_relaxed(osmr[0], OSMR0);
 155         writel_relaxed(osmr[1], OSMR1);
 156         writel_relaxed(osmr[2], OSMR2);
 157         writel_relaxed(osmr[3], OSMR3);
 158         writel_relaxed(oier, OIER);
 159         writel_relaxed(oscr, OSCR);
 160 }
 161 #else
 162 #define pxa_timer_suspend NULL
 163 #define pxa_timer_resume NULL
 164 #endif
 165
 166 struct sys_timer pxa_timer = {
 167         .init           = pxa_timer_init,
 168         .suspend        = pxa_timer_suspend,
 169         .resume         = pxa_timer_resume,
 170 };