x86, efi: Set runtime_version to the EFI spec revision
[linux/fpc-iii.git] / arch / arm / mach-realview / realview_eb.c
blob28511d43637a28401e5f690b778496e27c2978f7
1 /*
2 * linux/arch/arm/mach-realview/realview_eb.c
4 * Copyright (C) 2004 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/init.h>
23 #include <linux/platform_device.h>
24 #include <linux/device.h>
25 #include <linux/amba/bus.h>
26 #include <linux/amba/pl061.h>
27 #include <linux/amba/mmci.h>
28 #include <linux/amba/pl022.h>
29 #include <linux/io.h>
30 #include <linux/platform_data/clk-realview.h>
32 #include <mach/hardware.h>
33 #include <asm/irq.h>
34 #include <asm/mach-types.h>
35 #include <asm/pgtable.h>
36 #include <asm/hardware/gic.h>
37 #include <asm/hardware/cache-l2x0.h>
38 #include <asm/smp_twd.h>
40 #include <asm/mach/arch.h>
41 #include <asm/mach/map.h>
42 #include <asm/mach/time.h>
44 #include <mach/board-eb.h>
45 #include <mach/irqs.h>
47 #include "core.h"
49 static struct map_desc realview_eb_io_desc[] __initdata = {
51 .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
52 .pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
53 .length = SZ_4K,
54 .type = MT_DEVICE,
55 }, {
56 .virtual = IO_ADDRESS(REALVIEW_EB_GIC_CPU_BASE),
57 .pfn = __phys_to_pfn(REALVIEW_EB_GIC_CPU_BASE),
58 .length = SZ_4K,
59 .type = MT_DEVICE,
60 }, {
61 .virtual = IO_ADDRESS(REALVIEW_EB_GIC_DIST_BASE),
62 .pfn = __phys_to_pfn(REALVIEW_EB_GIC_DIST_BASE),
63 .length = SZ_4K,
64 .type = MT_DEVICE,
65 }, {
66 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
67 .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
68 .length = SZ_4K,
69 .type = MT_DEVICE,
70 }, {
71 .virtual = IO_ADDRESS(REALVIEW_EB_TIMER0_1_BASE),
72 .pfn = __phys_to_pfn(REALVIEW_EB_TIMER0_1_BASE),
73 .length = SZ_4K,
74 .type = MT_DEVICE,
75 }, {
76 .virtual = IO_ADDRESS(REALVIEW_EB_TIMER2_3_BASE),
77 .pfn = __phys_to_pfn(REALVIEW_EB_TIMER2_3_BASE),
78 .length = SZ_4K,
79 .type = MT_DEVICE,
81 #ifdef CONFIG_DEBUG_LL
83 .virtual = IO_ADDRESS(REALVIEW_EB_UART0_BASE),
84 .pfn = __phys_to_pfn(REALVIEW_EB_UART0_BASE),
85 .length = SZ_4K,
86 .type = MT_DEVICE,
88 #endif
91 static struct map_desc realview_eb11mp_io_desc[] __initdata = {
93 .virtual = IO_ADDRESS(REALVIEW_EB11MP_PRIV_MEM_BASE),
94 .pfn = __phys_to_pfn(REALVIEW_EB11MP_PRIV_MEM_BASE),
95 .length = REALVIEW_EB11MP_PRIV_MEM_SIZE,
96 .type = MT_DEVICE,
97 }, {
98 .virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE),
99 .pfn = __phys_to_pfn(REALVIEW_EB11MP_L220_BASE),
100 .length = SZ_8K,
101 .type = MT_DEVICE,
105 static void __init realview_eb_map_io(void)
107 iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc));
108 if (core_tile_eb11mp() || core_tile_a9mp())
109 iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc));
112 static struct pl061_platform_data gpio0_plat_data = {
113 .gpio_base = 0,
116 static struct pl061_platform_data gpio1_plat_data = {
117 .gpio_base = 8,
120 static struct pl061_platform_data gpio2_plat_data = {
121 .gpio_base = 16,
124 static struct pl022_ssp_controller ssp0_plat_data = {
125 .bus_id = 0,
126 .enable_dma = 0,
127 .num_chipselect = 1,
131 * RealView EB AMBA devices
135 * These devices are connected via the core APB bridge
137 #define GPIO2_IRQ { IRQ_EB_GPIO2 }
138 #define GPIO3_IRQ { IRQ_EB_GPIO3 }
140 #define AACI_IRQ { IRQ_EB_AACI }
141 #define MMCI0_IRQ { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B }
142 #define KMI0_IRQ { IRQ_EB_KMI0 }
143 #define KMI1_IRQ { IRQ_EB_KMI1 }
146 * These devices are connected directly to the multi-layer AHB switch
148 #define EB_SMC_IRQ { }
149 #define MPMC_IRQ { }
150 #define EB_CLCD_IRQ { IRQ_EB_CLCD }
151 #define DMAC_IRQ { IRQ_EB_DMA }
154 * These devices are connected via the core APB bridge
156 #define SCTL_IRQ { }
157 #define EB_WATCHDOG_IRQ { IRQ_EB_WDOG }
158 #define EB_GPIO0_IRQ { IRQ_EB_GPIO0 }
159 #define GPIO1_IRQ { IRQ_EB_GPIO1 }
160 #define EB_RTC_IRQ { IRQ_EB_RTC }
163 * These devices are connected via the DMA APB bridge
165 #define SCI_IRQ { IRQ_EB_SCI }
166 #define EB_UART0_IRQ { IRQ_EB_UART0 }
167 #define EB_UART1_IRQ { IRQ_EB_UART1 }
168 #define EB_UART2_IRQ { IRQ_EB_UART2 }
169 #define EB_UART3_IRQ { IRQ_EB_UART3 }
170 #define EB_SSP_IRQ { IRQ_EB_SSP }
172 /* FPGA Primecells */
173 APB_DEVICE(aaci, "fpga:aaci", AACI, NULL);
174 APB_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
175 APB_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
176 APB_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
177 APB_DEVICE(uart3, "fpga:uart3", EB_UART3, NULL);
179 /* DevChip Primecells */
180 AHB_DEVICE(smc, "dev:smc", EB_SMC, NULL);
181 AHB_DEVICE(clcd, "dev:clcd", EB_CLCD, &clcd_plat_data);
182 AHB_DEVICE(dmac, "dev:dmac", DMAC, NULL);
183 AHB_DEVICE(sctl, "dev:sctl", SCTL, NULL);
184 APB_DEVICE(wdog, "dev:wdog", EB_WATCHDOG, NULL);
185 APB_DEVICE(gpio0, "dev:gpio0", EB_GPIO0, &gpio0_plat_data);
186 APB_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
187 APB_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
188 APB_DEVICE(rtc, "dev:rtc", EB_RTC, NULL);
189 APB_DEVICE(sci0, "dev:sci0", SCI, NULL);
190 APB_DEVICE(uart0, "dev:uart0", EB_UART0, NULL);
191 APB_DEVICE(uart1, "dev:uart1", EB_UART1, NULL);
192 APB_DEVICE(uart2, "dev:uart2", EB_UART2, NULL);
193 APB_DEVICE(ssp0, "dev:ssp0", EB_SSP, &ssp0_plat_data);
195 static struct amba_device *amba_devs[] __initdata = {
196 &dmac_device,
197 &uart0_device,
198 &uart1_device,
199 &uart2_device,
200 &uart3_device,
201 &smc_device,
202 &clcd_device,
203 &sctl_device,
204 &wdog_device,
205 &gpio0_device,
206 &gpio1_device,
207 &gpio2_device,
208 &rtc_device,
209 &sci0_device,
210 &ssp0_device,
211 &aaci_device,
212 &mmc0_device,
213 &kmi0_device,
214 &kmi1_device,
218 * RealView EB platform devices
220 static struct resource realview_eb_flash_resource = {
221 .start = REALVIEW_EB_FLASH_BASE,
222 .end = REALVIEW_EB_FLASH_BASE + REALVIEW_EB_FLASH_SIZE - 1,
223 .flags = IORESOURCE_MEM,
226 static struct resource realview_eb_eth_resources[] = {
227 [0] = {
228 .start = REALVIEW_EB_ETH_BASE,
229 .end = REALVIEW_EB_ETH_BASE + SZ_64K - 1,
230 .flags = IORESOURCE_MEM,
232 [1] = {
233 .start = IRQ_EB_ETH,
234 .end = IRQ_EB_ETH,
235 .flags = IORESOURCE_IRQ,
240 * Detect and register the correct Ethernet device. RealView/EB rev D
241 * platforms use the newer SMSC LAN9118 Ethernet chip
243 static int eth_device_register(void)
245 void __iomem *eth_addr = ioremap(REALVIEW_EB_ETH_BASE, SZ_4K);
246 const char *name = NULL;
247 u32 idrev;
249 if (!eth_addr)
250 return -ENOMEM;
252 idrev = readl(eth_addr + 0x50);
253 if ((idrev & 0xFFFF0000) != 0x01180000)
254 /* SMSC LAN9118 not present, use LAN91C111 instead */
255 name = "smc91x";
257 iounmap(eth_addr);
258 return realview_eth_register(name, realview_eb_eth_resources);
261 static struct resource realview_eb_isp1761_resources[] = {
262 [0] = {
263 .start = REALVIEW_EB_USB_BASE,
264 .end = REALVIEW_EB_USB_BASE + SZ_128K - 1,
265 .flags = IORESOURCE_MEM,
267 [1] = {
268 .start = IRQ_EB_USB,
269 .end = IRQ_EB_USB,
270 .flags = IORESOURCE_IRQ,
274 static struct resource pmu_resources[] = {
275 [0] = {
276 .start = IRQ_EB11MP_PMU_CPU0,
277 .end = IRQ_EB11MP_PMU_CPU0,
278 .flags = IORESOURCE_IRQ,
280 [1] = {
281 .start = IRQ_EB11MP_PMU_CPU1,
282 .end = IRQ_EB11MP_PMU_CPU1,
283 .flags = IORESOURCE_IRQ,
285 [2] = {
286 .start = IRQ_EB11MP_PMU_CPU2,
287 .end = IRQ_EB11MP_PMU_CPU2,
288 .flags = IORESOURCE_IRQ,
290 [3] = {
291 .start = IRQ_EB11MP_PMU_CPU3,
292 .end = IRQ_EB11MP_PMU_CPU3,
293 .flags = IORESOURCE_IRQ,
297 static struct platform_device pmu_device = {
298 .name = "arm-pmu",
299 .id = -1,
300 .num_resources = ARRAY_SIZE(pmu_resources),
301 .resource = pmu_resources,
304 static struct resource char_lcd_resources[] = {
306 .start = REALVIEW_CHAR_LCD_BASE,
307 .end = (REALVIEW_CHAR_LCD_BASE + SZ_4K - 1),
308 .flags = IORESOURCE_MEM,
311 .start = IRQ_EB_CHARLCD,
312 .end = IRQ_EB_CHARLCD,
313 .flags = IORESOURCE_IRQ,
317 static struct platform_device char_lcd_device = {
318 .name = "arm-charlcd",
319 .id = -1,
320 .num_resources = ARRAY_SIZE(char_lcd_resources),
321 .resource = char_lcd_resources,
324 static void __init gic_init_irq(void)
326 if (core_tile_eb11mp() || core_tile_a9mp()) {
327 unsigned int pldctrl;
329 /* new irq mode */
330 writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
331 pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
332 pldctrl |= 0x00800000;
333 writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
334 writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
336 /* core tile GIC, primary */
337 gic_init(0, 29, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE),
338 __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
340 #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
341 /* board GIC, secondary */
342 gic_init(1, 96, __io_address(REALVIEW_EB_GIC_DIST_BASE),
343 __io_address(REALVIEW_EB_GIC_CPU_BASE));
344 gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
345 #endif
346 } else {
347 /* board GIC, primary */
348 gic_init(0, 29, __io_address(REALVIEW_EB_GIC_DIST_BASE),
349 __io_address(REALVIEW_EB_GIC_CPU_BASE));
354 * Fix up the IRQ numbers for the RealView EB/ARM11MPCore tile
356 static void realview_eb11mp_fixup(void)
358 /* AMBA devices */
359 dmac_device.irq[0] = IRQ_EB11MP_DMA;
360 uart0_device.irq[0] = IRQ_EB11MP_UART0;
361 uart1_device.irq[0] = IRQ_EB11MP_UART1;
362 uart2_device.irq[0] = IRQ_EB11MP_UART2;
363 uart3_device.irq[0] = IRQ_EB11MP_UART3;
364 clcd_device.irq[0] = IRQ_EB11MP_CLCD;
365 wdog_device.irq[0] = IRQ_EB11MP_WDOG;
366 gpio0_device.irq[0] = IRQ_EB11MP_GPIO0;
367 gpio1_device.irq[0] = IRQ_EB11MP_GPIO1;
368 gpio2_device.irq[0] = IRQ_EB11MP_GPIO2;
369 rtc_device.irq[0] = IRQ_EB11MP_RTC;
370 sci0_device.irq[0] = IRQ_EB11MP_SCI;
371 ssp0_device.irq[0] = IRQ_EB11MP_SSP;
372 aaci_device.irq[0] = IRQ_EB11MP_AACI;
373 mmc0_device.irq[0] = IRQ_EB11MP_MMCI0A;
374 mmc0_device.irq[1] = IRQ_EB11MP_MMCI0B;
375 kmi0_device.irq[0] = IRQ_EB11MP_KMI0;
376 kmi1_device.irq[0] = IRQ_EB11MP_KMI1;
378 /* platform devices */
379 realview_eb_eth_resources[1].start = IRQ_EB11MP_ETH;
380 realview_eb_eth_resources[1].end = IRQ_EB11MP_ETH;
381 realview_eb_isp1761_resources[1].start = IRQ_EB11MP_USB;
382 realview_eb_isp1761_resources[1].end = IRQ_EB11MP_USB;
385 #ifdef CONFIG_HAVE_ARM_TWD
386 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
387 REALVIEW_EB11MP_TWD_BASE,
388 IRQ_LOCALTIMER);
390 static void __init realview_eb_twd_init(void)
392 if (core_tile_eb11mp() || core_tile_a9mp()) {
393 int err = twd_local_timer_register(&twd_local_timer);
394 if (err)
395 pr_err("twd_local_timer_register failed %d\n", err);
398 #else
399 #define realview_eb_twd_init() do { } while(0)
400 #endif
402 static void __init realview_eb_timer_init(void)
404 unsigned int timer_irq;
406 timer0_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE);
407 timer1_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE) + 0x20;
408 timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE);
409 timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20;
411 if (core_tile_eb11mp() || core_tile_a9mp())
412 timer_irq = IRQ_EB11MP_TIMER0_1;
413 else
414 timer_irq = IRQ_EB_TIMER0_1;
416 realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
417 realview_timer_init(timer_irq);
418 realview_eb_twd_init();
421 static struct sys_timer realview_eb_timer = {
422 .init = realview_eb_timer_init,
425 static void realview_eb_restart(char mode, const char *cmd)
427 void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
428 void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
431 * To reset, we hit the on-board reset register
432 * in the system FPGA
434 __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
435 if (core_tile_eb11mp())
436 __raw_writel(0x0008, reset_ctrl);
437 dsb();
440 static void __init realview_eb_init(void)
442 int i;
444 if (core_tile_eb11mp() || core_tile_a9mp()) {
445 realview_eb11mp_fixup();
447 #ifdef CONFIG_CACHE_L2X0
448 /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
449 * Bits: .... ...0 0111 1001 0000 .... .... .... */
450 l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
451 #endif
452 platform_device_register(&pmu_device);
455 realview_flash_register(&realview_eb_flash_resource, 1);
456 platform_device_register(&realview_i2c_device);
457 platform_device_register(&char_lcd_device);
458 eth_device_register();
459 realview_usb_register(realview_eb_isp1761_resources);
461 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
462 struct amba_device *d = amba_devs[i];
463 amba_device_register(d, &iomem_resource);
467 MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
468 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
469 .atag_offset = 0x100,
470 .smp = smp_ops(realview_smp_ops),
471 .fixup = realview_fixup,
472 .map_io = realview_eb_map_io,
473 .init_early = realview_init_early,
474 .init_irq = gic_init_irq,
475 .timer = &realview_eb_timer,
476 .handle_irq = gic_handle_irq,
477 .init_machine = realview_eb_init,
478 #ifdef CONFIG_ZONE_DMA
479 .dma_zone_size = SZ_256M,
480 #endif
481 .restart = realview_eb_restart,
482 MACHINE_END