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x86, efi: Set runtime_version to the EFI spec revision
[linux/fpc-iii.git] / arch / arm / mach-shmobile / intc-r8a7740.c
blob9a69a31918ba074d01501f210bfe162e0a216b56
1 /*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/io.h>
26 #include <linux/sh_intc.h>
27 #include <mach/intc.h>
28 #include <mach/irqs.h>
29 #include <asm/mach-types.h>
30 #include <asm/mach/arch.h>
31
32 /*
33 * INTCA
34 */
35 enum {
36 UNUSED_INTCA = 0,
37
38 /* interrupt sources INTCA */
39 DIRC,
40 ATAPI,
41 IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI,
42 AP_ARM_COMMTX, AP_ARM_COMMRX,
43 MFI, MFIS,
44 BBIF1, BBIF2,
45 USBHSDMAC,
46 USBF_OUL_SOF, USBF_IXL_INT,
47 SGX540,
48 CMT1_0, CMT1_1, CMT1_2, CMT1_3,
49 CMT2,
50 CMT3,
51 KEYSC,
52 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
53 MSIOF2, MSIOF1,
54 SCIFA4, SCIFA5, SCIFB,
55 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
56 SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3,
57 SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3,
58 AP_ARM_L2CINT,
59 IRDA,
60 TPU0,
61 SCIFA6, SCIFA7,
62 GbEther,
63 ICBS0,
64 DDM,
65 SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3,
66 RWDT0,
67 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
68 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
69 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
70 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
71 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
72 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
73 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
74 HDMI,
75 USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND,
76 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF,
77 SPU2_0, SPU2_1,
78 FSI, FMSI,
79 HDMI_SSS, HDMI_KEY,
80 IPMMU,
81 AP_ARM_CTIIRQ, AP_ARM_PMURQ,
82 MFIS2,
83 CPORTR2S,
84 CMT14, CMT15,
85 MMCIF_0, MMCIF_1, MMCIF_2,
86 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
87 STPRO_0, STPRO_1, STPRO_2, STPRO_3, STPRO_4,
88
89 /* interrupt groups INTCA */
90 DMAC1_1, DMAC1_2,
91 DMAC2_1, DMAC2_2,
92 DMAC3_1, DMAC3_2,
93 AP_ARM1, AP_ARM2,
94 SDHI0, SDHI1, SDHI2,
95 SHWYSTAT,
96 USBF, USBH1, USBH2,
97 RSPI, SPU2, FLCTL, IIC1,
98 };
99
100 static struct intc_vect intca_vectors[] __initdata = {
101 INTC_VECT(DIRC, 0x0560),
102 INTC_VECT(ATAPI, 0x05E0),
103 INTC_VECT(IIC1_ALI, 0x0780),
104 INTC_VECT(IIC1_TACKI, 0x07A0),
105 INTC_VECT(IIC1_WAITI, 0x07C0),
106 INTC_VECT(IIC1_DTEI, 0x07E0),
107 INTC_VECT(AP_ARM_COMMTX, 0x0840),
108 INTC_VECT(AP_ARM_COMMRX, 0x0860),
109 INTC_VECT(MFI, 0x0900),
110 INTC_VECT(MFIS, 0x0920),
111 INTC_VECT(BBIF1, 0x0940),
112 INTC_VECT(BBIF2, 0x0960),
113 INTC_VECT(USBHSDMAC, 0x0A00),
114 INTC_VECT(USBF_OUL_SOF, 0x0A20),
115 INTC_VECT(USBF_IXL_INT, 0x0A40),
116 INTC_VECT(SGX540, 0x0A60),
117 INTC_VECT(CMT1_0, 0x0B00),
118 INTC_VECT(CMT1_1, 0x0B20),
119 INTC_VECT(CMT1_2, 0x0B40),
120 INTC_VECT(CMT1_3, 0x0B60),
121 INTC_VECT(CMT2, 0x0B80),
122 INTC_VECT(CMT3, 0x0BA0),
123 INTC_VECT(KEYSC, 0x0BE0),
124 INTC_VECT(SCIFA0, 0x0C00),
125 INTC_VECT(SCIFA1, 0x0C20),
126 INTC_VECT(SCIFA2, 0x0C40),
127 INTC_VECT(SCIFA3, 0x0C60),
128 INTC_VECT(MSIOF2, 0x0C80),
129 INTC_VECT(MSIOF1, 0x0D00),
130 INTC_VECT(SCIFA4, 0x0D20),
131 INTC_VECT(SCIFA5, 0x0D40),
132 INTC_VECT(SCIFB, 0x0D60),
133 INTC_VECT(FLCTL_FLSTEI, 0x0D80),
134 INTC_VECT(FLCTL_FLTENDI, 0x0DA0),
135 INTC_VECT(FLCTL_FLTREQ0I, 0x0DC0),
136 INTC_VECT(FLCTL_FLTREQ1I, 0x0DE0),
137 INTC_VECT(SDHI0_0, 0x0E00),
138 INTC_VECT(SDHI0_1, 0x0E20),
139 INTC_VECT(SDHI0_2, 0x0E40),
140 INTC_VECT(SDHI0_3, 0x0E60),
141 INTC_VECT(SDHI1_0, 0x0E80),
142 INTC_VECT(SDHI1_1, 0x0EA0),
143 INTC_VECT(SDHI1_2, 0x0EC0),
144 INTC_VECT(SDHI1_3, 0x0EE0),
145 INTC_VECT(AP_ARM_L2CINT, 0x0FA0),
146 INTC_VECT(IRDA, 0x0480),
147 INTC_VECT(TPU0, 0x04A0),
148 INTC_VECT(SCIFA6, 0x04C0),
149 INTC_VECT(SCIFA7, 0x04E0),
150 INTC_VECT(GbEther, 0x0500),
151 INTC_VECT(ICBS0, 0x0540),
152 INTC_VECT(DDM, 0x1140),
153 INTC_VECT(SDHI2_0, 0x1200),
154 INTC_VECT(SDHI2_1, 0x1220),
155 INTC_VECT(SDHI2_2, 0x1240),
156 INTC_VECT(SDHI2_3, 0x1260),
157 INTC_VECT(RWDT0, 0x1280),
158 INTC_VECT(DMAC1_1_DEI0, 0x2000),
159 INTC_VECT(DMAC1_1_DEI1, 0x2020),
160 INTC_VECT(DMAC1_1_DEI2, 0x2040),
161 INTC_VECT(DMAC1_1_DEI3, 0x2060),
162 INTC_VECT(DMAC1_2_DEI4, 0x2080),
163 INTC_VECT(DMAC1_2_DEI5, 0x20A0),
164 INTC_VECT(DMAC1_2_DADERR, 0x20C0),
165 INTC_VECT(DMAC2_1_DEI0, 0x2100),
166 INTC_VECT(DMAC2_1_DEI1, 0x2120),
167 INTC_VECT(DMAC2_1_DEI2, 0x2140),
168 INTC_VECT(DMAC2_1_DEI3, 0x2160),
169 INTC_VECT(DMAC2_2_DEI4, 0x2180),
170 INTC_VECT(DMAC2_2_DEI5, 0x21A0),
171 INTC_VECT(DMAC2_2_DADERR, 0x21C0),
172 INTC_VECT(DMAC3_1_DEI0, 0x2200),
173 INTC_VECT(DMAC3_1_DEI1, 0x2220),
174 INTC_VECT(DMAC3_1_DEI2, 0x2240),
175 INTC_VECT(DMAC3_1_DEI3, 0x2260),
176 INTC_VECT(DMAC3_2_DEI4, 0x2280),
177 INTC_VECT(DMAC3_2_DEI5, 0x22A0),
178 INTC_VECT(DMAC3_2_DADERR, 0x22C0),
179 INTC_VECT(SHWYSTAT_RT, 0x1300),
180 INTC_VECT(SHWYSTAT_HS, 0x1320),
181 INTC_VECT(SHWYSTAT_COM, 0x1340),
182 INTC_VECT(USBH_INT, 0x1540),
183 INTC_VECT(USBH_OHCI, 0x1560),
184 INTC_VECT(USBH_EHCI, 0x1580),
185 INTC_VECT(USBH_PME, 0x15A0),
186 INTC_VECT(USBH_BIND, 0x15C0),
187 INTC_VECT(HDMI, 0x1700),
188 INTC_VECT(RSPI_OVRF, 0x1780),
189 INTC_VECT(RSPI_SPTEF, 0x17A0),
190 INTC_VECT(RSPI_SPRF, 0x17C0),
191 INTC_VECT(SPU2_0, 0x1800),
192 INTC_VECT(SPU2_1, 0x1820),
193 INTC_VECT(FSI, 0x1840),
194 INTC_VECT(FMSI, 0x1860),
195 INTC_VECT(HDMI_SSS, 0x18A0),
196 INTC_VECT(HDMI_KEY, 0x18C0),
197 INTC_VECT(IPMMU, 0x1920),
198 INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
199 INTC_VECT(AP_ARM_PMURQ, 0x19A0),
200 INTC_VECT(MFIS2, 0x1A00),
201 INTC_VECT(CPORTR2S, 0x1A20),
202 INTC_VECT(CMT14, 0x1A40),
203 INTC_VECT(CMT15, 0x1A60),
204 INTC_VECT(MMCIF_0, 0x1AA0),
205 INTC_VECT(MMCIF_1, 0x1AC0),
206 INTC_VECT(MMCIF_2, 0x1AE0),
207 INTC_VECT(SIM_ERI, 0x1C00),
208 INTC_VECT(SIM_RXI, 0x1C20),
209 INTC_VECT(SIM_TXI, 0x1C40),
210 INTC_VECT(SIM_TEI, 0x1C60),
211 INTC_VECT(STPRO_0, 0x1C80),
212 INTC_VECT(STPRO_1, 0x1CA0),
213 INTC_VECT(STPRO_2, 0x1CC0),
214 INTC_VECT(STPRO_3, 0x1CE0),
215 INTC_VECT(STPRO_4, 0x1D00),
216 };
217
218 static struct intc_group intca_groups[] __initdata = {
219 INTC_GROUP(DMAC1_1,
220 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
221 INTC_GROUP(DMAC1_2,
222 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR),
223 INTC_GROUP(DMAC2_1,
224 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
225 INTC_GROUP(DMAC2_2,
226 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR),
227 INTC_GROUP(DMAC3_1,
228 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
229 INTC_GROUP(DMAC3_2,
230 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR),
231 INTC_GROUP(AP_ARM1,
232 AP_ARM_COMMTX, AP_ARM_COMMRX),
233 INTC_GROUP(AP_ARM2,
234 AP_ARM_CTIIRQ, AP_ARM_PMURQ),
235 INTC_GROUP(USBF,
236 USBF_OUL_SOF, USBF_IXL_INT),
237 INTC_GROUP(SDHI0,
238 SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3),
239 INTC_GROUP(SDHI1,
240 SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3),
241 INTC_GROUP(SDHI2,
242 SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3),
243 INTC_GROUP(SHWYSTAT,
244 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
245 INTC_GROUP(USBH1, /* FIXME */
246 USBH_INT, USBH_OHCI),
247 INTC_GROUP(USBH2, /* FIXME */
248 USBH_EHCI,
249 USBH_PME, USBH_BIND),
250 INTC_GROUP(RSPI,
251 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF),
252 INTC_GROUP(SPU2,
253 SPU2_0, SPU2_1),
254 INTC_GROUP(FLCTL,
255 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
256 INTC_GROUP(IIC1,
257 IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI),
258 };
259
260 static struct intc_mask_reg intca_mask_registers[] __initdata = {
261 { /* IMR0A / IMCR0A */ 0xe6940080, 0xe69400c0, 8,
262 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
263 0, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
264 { /* IMR1A / IMCR1A */ 0xe6940084, 0xe69400c4, 8,
265 { ATAPI, 0, DIRC, 0,
266 DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
267 { /* IMR2A / IMCR2A */ 0xe6940088, 0xe69400c8, 8,
268 { 0, 0, 0, 0,
269 BBIF1, BBIF2, MFIS, MFI } },
270 { /* IMR3A / IMCR3A */ 0xe694008c, 0xe69400cc, 8,
271 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
272 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
273 { /* IMR4A / IMCR4A */ 0xe6940090, 0xe69400d0, 8,
274 { DDM, 0, 0, 0,
275 0, 0, 0, 0 } },
276 { /* IMR5A / IMCR5A */ 0xe6940094, 0xe69400d4, 8,
277 { KEYSC, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
278 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
279 { /* IMR6A / IMCR6A */ 0xe6940098, 0xe69400d8, 8,
280 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
281 0, 0, MSIOF2, 0 } },
282 { /* IMR7A / IMCR7A */ 0xe694009c, 0xe69400dc, 8,
283 { SDHI0_3, SDHI0_2, SDHI0_1, SDHI0_0,
284 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
285 { /* IMR8A / IMCR8A */ 0xe69400a0, 0xe69400e0, 8,
286 { SDHI1_3, SDHI1_2, SDHI1_1, SDHI1_0,
287 0, USBHSDMAC, 0, AP_ARM_L2CINT } },
288 { /* IMR9A / IMCR9A */ 0xe69400a4, 0xe69400e4, 8,
289 { CMT1_3, CMT1_2, CMT1_1, CMT1_0,
290 CMT2, USBF_IXL_INT, USBF_OUL_SOF, SGX540 } },
291 { /* IMR10A / IMCR10A */ 0xe69400a8, 0xe69400e8, 8,
292 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
293 0, 0, 0, 0 } },
294 { /* IMR11A / IMCR11A */ 0xe69400ac, 0xe69400ec, 8,
295 { IIC1_DTEI, IIC1_WAITI, IIC1_TACKI, IIC1_ALI,
296 ICBS0, 0, 0, 0 } },
297 { /* IMR12A / IMCR12A */ 0xe69400b0, 0xe69400f0, 8,
298 { 0, 0, TPU0, SCIFA6,
299 SCIFA7, GbEther, 0, 0 } },
300 { /* IMR13A / IMCR13A */ 0xe69400b4, 0xe69400f4, 8,
301 { SDHI2_3, SDHI2_2, SDHI2_1, SDHI2_0,
302 0, CMT3, 0, RWDT0 } },
303 { /* IMR0A3 / IMCR0A3 */ 0xe6950080, 0xe69500c0, 8,
304 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
305 0, 0, 0, 0 } },
306 /* IMR1A3 / IMCR1A3 */
307 { /* IMR2A3 / IMCR2A3 */ 0xe6950088, 0xe69500c8, 8,
308 { 0, 0, USBH_INT, USBH_OHCI,
309 USBH_EHCI, USBH_PME, USBH_BIND, 0 } },
310 /* IMR3A3 / IMCR3A3 */
311 { /* IMR4A3 / IMCR4A3 */ 0xe6950090, 0xe69500d0, 8,
312 { HDMI, 0, 0, 0,
313 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, 0 } },
314 { /* IMR5A3 / IMCR5A3 */ 0xe6950094, 0xe69500d4, 8,
315 { SPU2_0, SPU2_1, FSI, FMSI,
316 0, HDMI_SSS, HDMI_KEY, 0 } },
317 { /* IMR6A3 / IMCR6A3 */ 0xe6950098, 0xe69500d8, 8,
318 { 0, IPMMU, 0, 0,
319 AP_ARM_CTIIRQ, AP_ARM_PMURQ, 0, 0 } },
320 { /* IMR7A3 / IMCR7A3 */ 0xe695009c, 0xe69500dc, 8,
321 { MFIS2, CPORTR2S, CMT14, CMT15,
322 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
323 /* IMR8A3 / IMCR8A3 */
324 { /* IMR9A3 / IMCR9A3 */ 0xe69500a4, 0xe69500e4, 8,
325 { SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
326 STPRO_0, STPRO_1, STPRO_2, STPRO_3 } },
327 { /* IMR10A3 / IMCR10A3 */ 0xe69500a8, 0xe69500e8, 8,
328 { STPRO_4, 0, 0, 0,
329 0, 0, 0, 0 } },
330 };
331
332 static struct intc_prio_reg intca_prio_registers[] __initdata = {
333 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, ICBS0 } },
334 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
335 { 0xe6940008, 0, 16, 4, /* IPRCA */ { ATAPI, 0, CMT1_1, AP_ARM1 } },
336 { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, CMT1_2, 0 } },
337 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFIS, MFI, USBF } },
338 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC, DMAC1_2,
339 SGX540, CMT1_0 } },
340 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
341 SCIFA2, SCIFA3 } },
342 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC,
343 FLCTL, SDHI0 } },
344 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } },
345 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
346 AP_ARM_L2CINT, 0 } },
347 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_3, 0, SDHI1 } },
348 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, SCIFA6,
349 SCIFA7, GbEther } },
350 { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
351 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
352 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
353 { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
354 /* IPRBA3 */
355 /* IPRCA3 */
356 /* IPRDA3 */
357 { 0xe6950010, 0, 16, 4, /* IPREA3 */ { USBH1, 0, 0, 0 } },
358 { 0xe6950014, 0, 16, 4, /* IPRFA3 */ { USBH2, 0, 0, 0 } },
359 /* IPRGA3 */
360 /* IPRHA3 */
361 { 0xe6950020, 0, 16, 4, /* IPRIA3 */ { HDMI, 0, 0, 0 } },
362 { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { RSPI, 0, 0, 0 } },
363 { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
364 { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, HDMI_SSS, HDMI_KEY, 0 } },
365 { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU, 0, 0, 0 } },
366 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
367 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
368 CMT14, CMT15 } },
369 { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
370 /* IPRQA3 */
371 /* IPRRA3 */
372 { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { SIM_ERI, SIM_RXI,
373 SIM_TXI, SIM_TEI } },
374 { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { STPRO_0, STPRO_1,
375 STPRO_2, STPRO_3 } },
376 { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { STPRO_4, 0, 0, 0 } },
377 };
378
379 static DECLARE_INTC_DESC(intca_desc, "r8a7740-intca",
380 intca_vectors, intca_groups,
381 intca_mask_registers, intca_prio_registers,
382 NULL);
383
384 INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
385 INTC_VECT, "r8a7740-intca-irq-pins");
386
387
388 /*
389 * INTCS
390 */
391 enum {
392 UNUSED_INTCS = 0,
393
394 INTCS,
395
396 /* interrupt sources INTCS */
397
398 /* HUDI */
399 /* STPRO */
400 /* RTDMAC(1) */
401 VPU5HA2,
402 _2DG_TRAP, _2DG_GPM_INT, _2DG_CER_INT,
403 /* MFI */
404 /* BBIF2 */
405 VPU5F,
406 _2DG_BRK_INT,
407 /* SGX540 */
408 /* 2DDMAC */
409 /* IPMMU */
410 /* RTDMAC 2 */
411 /* KEYSC */
412 /* MSIOF */
413 IIC0_ALI, IIC0_TACKI, IIC0_WAITI, IIC0_DTEI,
414 TMU0_0, TMU0_1, TMU0_2,
415 CMT0,
416 /* CMT2 */
417 LMB,
418 CTI,
419 VOU,
420 /* RWDT0 */
421 ICB,
422 VIO6C,
423 CEU20, CEU21,
424 JPU,
425 LCDC0,
426 LCRC,
427 /* RTDMAC2(1) */
428 /* RTDMAC2(2) */
429 LCDC1,
430 /* SPU2 */
431 /* FSI */
432 /* FMSI */
433 TMU1_0, TMU1_1, TMU1_2,
434 CMT4,
435 DISP,
436 DSRV,
437 /* MFIS2 */
438 CPORTS2R,
439
440 /* interrupt groups INTCS */
441 _2DG1,
442 IIC0, TMU1,
443 };
444
445 static struct intc_vect intcs_vectors[] = {
446 /* HUDI */
447 /* STPRO */
448 /* RTDMAC(1) */
449 INTCS_VECT(VPU5HA2, 0x0880),
450 INTCS_VECT(_2DG_TRAP, 0x08A0),
451 INTCS_VECT(_2DG_GPM_INT, 0x08C0),
452 INTCS_VECT(_2DG_CER_INT, 0x08E0),
453 /* MFI */
454 /* BBIF2 */
455 INTCS_VECT(VPU5F, 0x0980),
456 INTCS_VECT(_2DG_BRK_INT, 0x09A0),
457 /* SGX540 */
458 /* 2DDMAC */
459 /* IPMMU */
460 /* RTDMAC(2) */
461 /* KEYSC */
462 /* MSIOF */
463 INTCS_VECT(IIC0_ALI, 0x0E00),
464 INTCS_VECT(IIC0_TACKI, 0x0E20),
465 INTCS_VECT(IIC0_WAITI, 0x0E40),
466 INTCS_VECT(IIC0_DTEI, 0x0E60),
467 INTCS_VECT(TMU0_0, 0x0E80),
468 INTCS_VECT(TMU0_1, 0x0EA0),
469 INTCS_VECT(TMU0_2, 0x0EC0),
470 INTCS_VECT(CMT0, 0x0F00),
471 /* CMT2 */
472 INTCS_VECT(LMB, 0x0F60),
473 INTCS_VECT(CTI, 0x0400),
474 INTCS_VECT(VOU, 0x0420),
475 /* RWDT0 */
476 INTCS_VECT(ICB, 0x0480),
477 INTCS_VECT(VIO6C, 0x04E0),
478 INTCS_VECT(CEU20, 0x0500),
479 INTCS_VECT(CEU21, 0x0520),
480 INTCS_VECT(JPU, 0x0560),
481 INTCS_VECT(LCDC0, 0x0580),
482 INTCS_VECT(LCRC, 0x05A0),
483 /* RTDMAC2(1) */
484 /* RTDMAC2(2) */
485 INTCS_VECT(LCDC1, 0x1780),
486 /* SPU2 */
487 /* FSI */
488 /* FMSI */
489 INTCS_VECT(TMU1_0, 0x1900),
490 INTCS_VECT(TMU1_1, 0x1920),
491 INTCS_VECT(TMU1_2, 0x1940),
492 INTCS_VECT(CMT4, 0x1980),
493 INTCS_VECT(DISP, 0x19A0),
494 INTCS_VECT(DSRV, 0x19C0),
495 /* MFIS2 */
496 INTCS_VECT(CPORTS2R, 0x1A20),
497
498 INTC_VECT(INTCS, 0xf80),
499 };
500
501 static struct intc_group intcs_groups[] __initdata = {
502 INTC_GROUP(_2DG1, /*FIXME*/
503 _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP),
504 INTC_GROUP(IIC0,
505 IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI),
506 INTC_GROUP(TMU1,
507 TMU1_0, TMU1_1, TMU1_2),
508 };
509
510 static struct intc_mask_reg intcs_mask_registers[] = {
511 /* IMR0SA / IMCR0SA */ /* all 0 */
512 { /* IMR1SA / IMCR1SA */ 0xffd20184, 0xffd201c4, 8,
513 { _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP, VPU5HA2,
514 0, 0, 0, 0 /*STPRO*/ } },
515 { /* IMR2SA / IMCR2SA */ 0xffd20188, 0xffd201c8, 8,
516 { 0/*STPRO*/, 0, CEU21, VPU5F,
517 0/*BBIF2*/, 0, 0, 0/*MFI*/ } },
518 { /* IMR3SA / IMCR3SA */ 0xffd2018c, 0xffd201cc, 8,
519 { 0, 0, 0, 0, /*2DDMAC*/
520 VIO6C, 0, 0, ICB } },
521 { /* IMR4SA / IMCR4SA */ 0xffd20190, 0xffd201d0, 8,
522 { 0, 0, VOU, CTI,
523 JPU, 0, LCRC, LCDC0 } },
524 /* IMR5SA / IMCR5SA */ /*KEYSC/RTDMAC2/RTDMAC1*/
525 /* IMR6SA / IMCR6SA */ /*MSIOF/SGX540*/
526 { /* IMR7SA / IMCR7SA */ 0xffd2019c, 0xffd201dc, 8,
527 { 0, TMU0_2, TMU0_1, TMU0_0,
528 0, 0, 0, 0 } },
529 { /* IMR8SA / IMCR8SA */ 0xffd201a0, 0xffd201e0, 8,
530 { 0, 0, 0, 0,
531 CEU20, 0, 0, 0 } },
532 { /* IMR9SA / IMCR9SA */ 0xffd201a4, 0xffd201e4, 8,
533 { 0, 0/*RWDT0*/, 0/*CMT2*/, CMT0,
534 0, 0, 0, 0 } },
535 /* IMR10SA / IMCR10SA */ /*IPMMU*/
536 { /* IMR11SA / IMCR11SA */ 0xffd201ac, 0xffd201ec, 8,
537 { IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI,
538 0, _2DG_BRK_INT, LMB, 0 } },
539 /* IMR12SA / IMCR12SA */
540 /* IMR13SA / IMCR13SA */
541 /* IMR0SA3 / IMCR0SA3 */ /*RTDMAC2(1)/RTDMAC2(2)*/
542 /* IMR1SA3 / IMCR1SA3 */
543 /* IMR2SA3 / IMCR2SA3 */
544 /* IMR3SA3 / IMCR3SA3 */
545 { /* IMR4SA3 / IMCR4SA3 */ 0xffd50190, 0xffd501d0, 8,
546 { 0, 0, 0, 0,
547 LCDC1, 0, 0, 0 } },
548 /* IMR5SA3 / IMCR5SA3 */ /* SPU2/FSI/FMSI */
549 { /* IMR6SA3 / IMCR6SA3 */ 0xffd50198, 0xffd501d8, 8,
550 { TMU1_0, TMU1_1, TMU1_2, 0,
551 CMT4, DISP, DSRV, 0 } },
552 { /* IMR7SA3 / IMCR7SA3 */ 0xffd5019c, 0xffd501dc, 8,
553 { 0/*MFIS2*/, CPORTS2R, 0, 0,
554 0, 0, 0, 0 } },
555 { /* INTAMASK */ 0xffd20104, 0, 16,
556 { 0, 0, 0, 0, 0, 0, 0, 0,
557 0, 0, 0, 0, 0, 0, 0, INTCS } },
558 };
559
560 /* Priority is needed for INTCA to receive the INTCS interrupt */
561 static struct intc_prio_reg intcs_prio_registers[] = {
562 { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, VOU, 0/*2DDMAC*/, ICB } },
563 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU, LCDC0, 0, LCRC } },
564 /* IPRCS */ /*BBIF2*/
565 /* IPRDS */
566 { 0xffd20010, 0, 16, 4, /* IPRES */ { 0/*RTDMAC(1)*/, VPU5HA2,
567 0/*MFI*/, VPU5F } },
568 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0/*KEYSC*/, 0/*RTDMAC(2)*/,
569 0/*CMT2*/, CMT0 } },
570 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_0, TMU0_1,
571 TMU0_2, _2DG1 } },
572 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0/*STPRO*/, 0/*STPRO*/,
573 _2DG_BRK_INT/*FIXME*/ } },
574 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, 0/*MSIOF*/, 0, IIC0 } },
575 { 0xffd20024, 0, 16, 4, /* IPRJS */ { CEU20, 0/*SGX540*/, 0, 0 } },
576 { 0xffd20028, 0, 16, 4, /* IPRKS */ { VIO6C, 0, LMB, 0 } },
577 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { 0/*IPMMU*/, 0, CEU21, 0 } },
578 /* IPRMS */ /*RWDT0*/
579 /* IPRAS3 */ /*RTDMAC2(1)*/
580 /* IPRBS3 */ /*RTDMAC2(2)*/
581 /* IPRCS3 */
582 /* IPRDS3 */
583 /* IPRES3 */
584 /* IPRFS3 */
585 /* IPRGS3 */
586 /* IPRHS3 */
587 /* IPRIS3 */
588 { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, 0, 0, 0 } },
589 /* IPRKS3 */ /*SPU2/FSI/FMSi*/
590 /* IPRLS3 */
591 { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
592 { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DISP, DSRV, 0 } },
593 { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0/*MFIS2*/, CPORTS2R, 0, 0 } },
594 /* IPRPS3 */
595 };
596
597 static struct resource intcs_resources[] __initdata = {
598 [0] = {
599 .start = 0xffd20000,
600 .end = 0xffd201ff,
601 .flags = IORESOURCE_MEM,
602 },
603 [1] = {
604 .start = 0xffd50000,
605 .end = 0xffd501ff,
606 .flags = IORESOURCE_MEM,
607 }
608 };
609
610 static struct intc_desc intcs_desc __initdata = {
611 .name = "r8a7740-intcs",
612 .resource = intcs_resources,
613 .num_resources = ARRAY_SIZE(intcs_resources),
614 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
615 intcs_prio_registers, NULL, NULL),
616 };
617
618 static void intcs_demux(unsigned int irq, struct irq_desc *desc)
619 {
620 void __iomem *reg = (void *)irq_get_handler_data(irq);
621 unsigned int evtcodeas = ioread32(reg);
622
623 generic_handle_irq(intcs_evt2irq(evtcodeas));
624 }
625
626 void __init r8a7740_init_irq(void)
627 {
628 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
629
630 register_intc_controller(&intca_desc);
631 register_intc_controller(&intca_irq_pins_desc);
632 register_intc_controller(&intcs_desc);
633
634 /* demux using INTEVTSA */
635 irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
636 irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
637 }
Linux with added FPC-III support